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CN106129041B - 具有面阵单元连接体的可堆叠模塑微电子封装 - Google Patents

具有面阵单元连接体的可堆叠模塑微电子封装 Download PDF

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Publication number
CN106129041B
CN106129041B CN201610583981.6A CN201610583981A CN106129041B CN 106129041 B CN106129041 B CN 106129041B CN 201610583981 A CN201610583981 A CN 201610583981A CN 106129041 B CN106129041 B CN 106129041B
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substrate
package
microelectronic
contacts
encapsulant
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CN106129041A (zh
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贝勒卡西姆·哈巴
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

本发明公开了一种微电子封装，具有基板和例如芯片这样的微电子元件，端子可具有与芯片的元件触点及基板的触点电连接的导电元件。导电元件可彼此绝缘以同时承载不同电位。密封剂可覆盖基板的第一表面及微电子元件远离基板的面的至少一部分，且密封剂可具有在微电子元件上方的主表面。复数个封装触点可位于微电子元件远离基板的面上。封装触点，如导电块，基本为刚性的柱，可与基板的端子通过导电元件而电连接。封装触点可具有至少部分地在密封剂的主表面暴露的顶面。

Description

具有面阵单元连接体的可堆叠模塑微电子封装
本申请为申请号201180043268.8的中国发明专利申请的分案申请，原申请的申请日为2011年07月18日，国际申请号为PCT/US2011/044342，发明名称为“具有面阵单元连接体的可堆叠模塑微电子封装”。本申请要求美国专利申请号为12/839,038，申请日为2010年7月19日的专利申请之申请日利益，其公开的内容通过援引加入本文。
技术领域
本申请主题涉及微电子封装，尤其是可堆叠模塑微电子封装，如可在微电子元件上方及下方的表面上具有封装触点。
背景技术
微电子元件，如半导体芯片，通常设置在封装内，封装提供对半导体芯片或其他微电子元件的物理方面及化学方面的保护。这种封装通常包括封装基板或芯片载体，封装基板或芯片载体可包括其上具有电连接端子的介电材料板。芯片安装在封装基板上且与封装基板的端子电连接。通常，芯片和部分基板被密封剂或外壳覆盖，使得只有承载端子的基板外表面仍保持暴露。这种封装可以方便地运输、贮存及处理。该封装可安装至电路板上，如采用标准安装技术的电路板，最通常地，标准安装技术为表面安装技术。为使这种封装更小，使得封装芯片占据电路板上较小的面积，在本领域内已投入相当大的努力。例如，被称为芯片级封装的封装，占据的电路板面积与芯片自身的面积相等，或仅稍大于芯片自身的面积。但是，即使应用芯片级封装，数个封装芯片所占据的总面积也会大于或等于单个芯片的总面积。
某些多芯片封装可被称为“裸片堆叠封装”，其中复数个芯片以一个在另一个之上的方式安装在具有外部接口的共同封装内。这种共同封装可安装在电路板的一个区域内，该区域的面积可等于或仅稍大于包含单个芯片的单个封装安装通常所需的面积。裸片堆叠封装方式节省电路板上的空间。功能彼此相关的芯片或其他元件，可设置在一个共同的堆叠封装内。封装可包括这些元件之间的互连。因此，安装封装的电路板无需包括这些互连所需的导电体及其他元件。这反过来，允许应用更简单的电路板，且在某些情况下，允许使用具有较少金属连接层的电路板，从而显著地降低电路板的成本。此外，与在电路板上安装的单个封装之间相对应的互连相比，裸片堆叠封装内的互连通常可制作为具有更低的电阻抗及更短的信号传播延迟时间。这反过来，能增加堆叠封装内的微电子元件的工作速度，例如，在信号传输中允许在这些元件之间应用较高的时钟速度。
迄今为止已推出的一种芯片封装方式，有时被称为“球堆叠”("ball stack")。球堆叠封装包括两个或更多个单独的单元。每个单元包括，与单独封装的封装基板类似的单元基板，及一个或多个安装至单元基板上且与单元基板的端子连接的微电子元件。各单独单元以一个在另一个之上方式堆叠，每个单独的单元基板上的端子与另一个单元基板上的端子通过导电元件如焊料球或引脚而连接。底部单元基板上的端子可构成封装的端子，或替代地，可在封装的底部安装附加基板，且附加基板可具有与各单元基板的端子连接的端子。例如，球堆叠封装在美国专利公开号为2003/0107118和2004/0031972的专利申请的某些优选实施例中已描述，其公开的内容通过援引加入本文。
另一种类型的堆叠封装有时被称为折叠堆叠封装，两个或更多个芯片或其他微电子元件安装至单个基板上。这种单个基板通常具有沿基板延伸的导电体，以使安装在基板上各微电子元件相互连接。在同一基板上还具有导电端子，导电端子与安装在基板上的一个微电子元件连接或与各微电子元件都连接。基板折叠于其自身之上，使得一个部分上的微电子元件位于另一部分上的微电子元件的上方，并使得封装基板的端子暴露在折叠封装的底部，以把封装安装至电路板上。在折叠封装的某些变例中，在基板已折叠至其最终布局后，附接一个或多个微电子元件至基板。折叠堆叠的示例在以下专利文献的某些优选实施例中示出。专利号为6121676的美国专利；专利申请号为10/077388的美国专利申请；专利申请号为10/655952的美国专利申请；临时专利申请号为60/403939的美国临时专利申请；临时专利申请号为60/408664的美国临时专利申请；及临时专利申请号为60/408644的美国临时专利申请。折叠堆叠已经应用于各种用途，但已发现在封装芯片必须相互联系时的特别应用，例如，在移动电话内的包括基带信号处理芯片和射频功率放大器（“RFPA”）芯片的组件形成时，从而形成紧凑的、完备的组件。
尽管在本领域中已进行了这些努力，但仍需要进一步地改善。
发明内容
根据本发明实施例的微电子封装可包括基板，基板具有第一表面、远离第一表面的第二表面、复数个基板触点、及复数个与基板触点电互连且在第二表面暴露的端子。封装包括具有第一面、远离第一面的第二面、及在第一面暴露的元件触点的微电子元件，第一面或第二面中的一个与基板的第一表面并置（juxtaposed）。复数个导电元件在第一表面上突出，且与元件触点及基板触点电连接。至少一些导电元件彼此电绝缘，且适于同时承载不同的电位。密封剂覆盖基板的第一表面、导电元件及微电子元件远离基板的面的至少一部分。密封剂可限定主表面。复数个封装触点可位于微电子元件远离基板的面上，且从基板上突出高于元件触点的高度。封装触点可与基板的端子，如通过导电元件而电互连。封装触点可包括导电结合(conductive bond)材料块或基本为刚性的导电柱中的至少一种。封装触点的顶面可至少部分地在密封剂的主表面暴露。
在一个实施例中，密封剂的主表面可至少朝着基板的外围边缘延伸到微电子元件的外围边缘之外。在特定实施例中，封装触点可主要由导电结合材料组成。可选择地，封装触点包括基本为刚性的柱。
在特定实施例中，至少一些导电柱的顶面的至少一部分在从密封剂主表面向下延伸的开口内暴露。密封剂可与该至少一些柱的边缘表面的至少一部分接触。该至少一些柱的边缘表面可至少部分地在密封剂的相应开口内暴露。
在一个示例中，密封剂可与至少一些柱的顶面的至少一部分接触，从而该至少一些柱的顶面只部分地在开口内暴露。在特定的示例中，至少一些柱的边缘表面可全部被密封剂覆盖。
在一个示例中，导电柱的顶面可与密封剂的主表面共面。在这种示例中，在一种情况下，至少一些柱的边缘表面可部分地或全部地被密封剂覆盖。
在一个实施例中，基板可为第一基板，封装可进一步包括覆盖微电子元件的远离第一基板的面的第二基板。第二基板可使至少一些封装触点与微电子元件分离。第一基板和第二基板可通过导电元件电连接。导电元件可为第一导电元件，微电子封装可进一步包括至少一个与参考电位连接的第二导电元件，从而与至少一个第一导电元件形成受控阻抗传输线路。
在一个示例中，无论封装包括一个或两个基板，至少一些导电元件可与微电子元件直接连接。
在特定示例中，微电子元件的元件触点可面向第一基板。在另一示例中，微电子元件的元件触点可背向第一基板且与第一基板电互连。
在之前的或者是之后的任一个示例中，微电子元件可为第一微电子元件，封装可进一步包括位于第一微电子元件与第二基板之间的第二微电子元件，第二微电子元件与第一基板和第二基板中的至少一个电互连。
在一个示例中，为导电结构、导热结构或间隔体中至少一个的第二基本为刚性的结构，可从至少第一表面突出到至少第二基板。在一个示例中，第二基板可包括介电元件。
封装触点可包括复数个从第二基板表面向外突出的基本为刚性的导电柱。
在一个示例中，第二基板可包括第二介电元件，且封装触点可从第二介电元件的表面向外突出。第二基板可包括复数个开口，至少一些导电元件可延伸穿过第二基板的开口。
在一个实施例中，第二基本为刚性的导电柱可从第一基板向外延伸，且第二导电柱可与第一基板电连接。第二导电柱可在密封剂的相应开口内暴露于密封剂的主表面。
根据本发明的一个实施例，提供了一种制造微电子封装的方法。在这种方法中，可提供包括基板的微电子组件，基板具有基板触点、第一表面、远离第一表面的第二表面、及复数个暴露在第二表面的端子。该组件可包括微电子元件，微电子元件具有正面、暴露在正面的元件触点、及远离其的背面，正面或背面与第一表面并置。微电子组件可进一步包括在第一表面上突出且与元件触点及基板触点电连接的复数个导电元件。复数个封装触点可位于微电子元件的面上，该面远离微电子元件的与基板第一表面并置的面。封装触点可与导电元件电互连。在特定示例中，封装触点可包括导电结合材料块或基本为刚性的导电柱中的至少一种，导电结合材料块或基本为刚性的导电柱延伸至高于微电子元件的元件触点的高度。
然后密封剂可形成为覆盖基板的第一表面、导电元件及微电子元件远离基板的面的至少一部分。密封剂可限定主表面，且封装触点的顶面的至少一部分可在密封剂的主表面暴露。
在一个实施例中，顶面的至少一部分可与密封剂的主表面平齐。
根据本发明的一个实施例，最初时封装触点可未在密封剂的主表面暴露。在这种情况下，密封剂主表面可覆盖第二导电元件，且密封剂主表面内可形成有开口，以使第二导电元件至少部分地暴露。在特定的实施例中，第二导电元件可用作微电子封装的封装触点。在另一示例中，在密封剂层内形成开口后，可形成与第二导电元件电气通信的封装触点。
在一个示例中，形成封装触点的步骤可包括在开口内的第二导电元件上沉积导电结合材料块的步骤。在特定的示例中，形成封装触点的步骤可包括，在暴露于开口内的第二导电元件上电镀导电柱的步骤。在特定的实施例中，导电元件可包括微电子元件的元件触点。
在一个示例中，封装触点可包括至少一个基本为刚性的导电柱或导电块，封装触点可从基板的第一表面延伸至高于元件触点的高度。
导电柱可具有远离基板第一表面的顶面，及从顶面向外延伸的边缘表面。形成开口的步骤中可至少部分地暴露边缘表面。
在一个实施例中，本文的制造方法可应用于制造第一微电子封装和第二微电子封装中的每一个，然后第二微电子封装可在第一微电子封装顶上堆叠。第一微电子封装与第二微电子封装可通过第一微电子封装的封装触点及第二微电子封装的端子而电连接。替代地，第一微电子封装和第二微电子封装可通过第一微电子封装及第二微电子封装的封装触点而电互连，或通过第一微电子封装及第二微电子封装的端子而电互连。
附图说明
图1是说明根据本发明实施例基板制造方法中一个阶段的剖视图。
图2是说明根据本发明实施例基板制造方法中图1所示阶段随后的阶段的剖视图。
图3是说明根据本发明实施例基板制造方法中图1所示阶段随后的阶段的剖视图。
图4是说明根据本发明实施例基板制造方法中图1所示阶段随后的阶段的剖面图。
图5是说明根据本发明实施例的方法中应用的基板的剖视图。
图6是说明根据本发明实施例的变例的方法中应用的基板的剖视图。
图7是说明根据本发明实施例的方法中图5或图6所示阶段随后的制造阶段的剖视图。
图8是说明根据本发明实施例的方法中图7所示阶段随后的制造阶段的剖视图。
图9是说明根据本发明实施例的方法中图8所示阶段随后的制造阶段的剖视图。
图9A是说明根据图8和图9中所示本发明实施例的变例的方法中图7所示阶段随后的制造阶段的剖视图。
图10是说明根据本发明实施例的方法中图9或图9A所示阶段随后的制造阶段的剖视图。
图11是说明根据图10所示阶段随后的制造阶段的剖视图。
图12是说明根据本发明实施例微电子封装的剖视图。
图13是说明根据本发明实施例微电子封装沿图14中的线13-13进行剖切时的剖视图。
图14是说明面向图13中所示的根据本发明实施例微电子封装的上基板观看时的俯视图。
图15是说明根据本发明实施例微电子封装制造方法的一个阶段的剖视图。
图16A是说明根据本发明实施例微电子封装制造方法中图15所示阶段随后的阶段的剖视图。
图16B是说明图16A所示方法的变例中图15所示阶段随后的阶段的剖视图。
图17是说明根据本发明实施例微电子封装制造方法中一个阶段的剖视图。
图18是说明根据本发明实施例微电子封装制造方法中图17所示阶段随后的阶段的剖视图。
图19是说明根据本发明实施例微电子封装制造方法中图18所示阶段随后的阶段的剖视图。
图20是说明根据本发明实施例微电子封装的剖视图。
图20A是说明根据图20所示本发明实施例的变例的微电子封装的剖视图。
图20B是说明根据图20所示本发明实施例的另一变例的微电子封装的剖视图。
图21是说明根据本发明实施例堆叠微电子组件制造方法中一个阶段的剖视图。
图22是说明根据本发明实施例微电子封装的剖视图。
图23是说明根据本发明实施例微电子封装的剖视图。
图24是说明根据本发明实施例微电子封装的剖视图。
图25是说明根据本发明实施例微电子封装的剖视图。
图26是说明根据本发明实施例微电子封装的剖视图。
图27是说明根据本发明实施例微电子封装的剖视图。
图27A是说明根据本发明实施例微电子封装的剖视图。
图28是说明根据本发明实施例微电子封装的剖视图。
图29是说明根据本发明实施例微电子封装的剖视图。
图30是说明根据本发明实施例微电子封装的剖视图。
图31是说明根据本发明实施例微电子封装的剖视图。
图32是说明根据本发明实施例微电子封装的剖视图。
图33是说明根据本发明实施例微电子组件的剖视图。
具体实施方式
制造微电子封装的方法将根据本发明实施例进行描述。参照图1，在一个实施例中，封装基板或互连基板可应用介电元件104上的层状金属结构102而制造，该层状金属结构具有第一金属层110、第二金属层112、及在第一金属层与第二金属层之间的导电蚀刻隔离层114。
在本文中应用的术语如“上”“下”“向上”及“向下”，及类似的指示方向的术语，参考的是各部件自身的参照系，而不是重力参照系。在该部件以附图所示的方向沿重力参照系定向时，在重力参照系中图中的顶部为上且图中的底部为下，上基板在重力参照系中确实位于下基板的上方。但是，当该部件反转，在重力参照系中图中顶部面向下时，上基板在重力参照系中位于下基板的下方。
平行于基板主表面105的方向本文称为“水平”方向或“横向”方向；而垂直于主表面的方向本文称为向上或向下的方向，在本文还被称为“竖直”方向。声明一个特征与另一特征相比，位于“表面上方”较高的高度，意味着这两个特征都以同一正交方向偏离该表面，但沿该同一正交方向该一个特征比该另一个特征距该表面的距离更远。相反地，声明，一个特征与另一个特征相比，位于“表面上方”较低高度，意味着这两个特征都以同一正交方向偏离该表面，但沿该同一正交方向该一个特征比该另一个特征距该表面的距离更近。
在一个示例中，第一金属层与第二金属层包括或主要由铜组成，蚀刻隔离层包括一种不被用于使第一金属层及第二金属层形成图案的蚀刻剂腐蚀的金属。例如，当第一金属层和第二金属层由铜组成时，蚀刻隔离层可由镍、铬、或镍与铬的合金组成。在一个示例中，第一金属层的厚度比第二金属层的厚度更大。在一个示例中，第一金属层可具有50微米至300微米之间的厚度，第二金属层可具有几微米至小于50微米的厚度，且在任何情况下第二金属层的厚度都小于第一金属层的厚度。第二金属层的厚度的典型范围为约6微米至约30微米之间。
从图1中可以看出，在这个阶段，层状金属结构可由介电元件104支撑，在特定示例中，介电元件104可包括复数个开口106，第二金属层112的部分通过开口106暴露。如在本文应用的，声明导电结构“暴露在”介电结构的表面，指的是导电结构可跟一理论点接触，该理论点以垂直于该介电结构表面的方向从介电结构外部该介电结构表面移动。因此，暴露在介电结构表面上的端子或其他导电结构可从该表面突出；可与该表面平齐；或可相对该表面凹陷，并通过介电结构上的孔或凹坑暴露。
介电元件104可包括单层的介电材料，或可为包括数个子层的层压板。介电元件可主要由聚合物电介质如聚酰亚胺、BT树脂、环氧树脂等或其他电介质聚合物制成，在一些示例中，可包括强化纤维，例如玻璃纤维。介电元件104可为柔性的或刚性的。在特定示例中，介电元件可为聚合物带材料如聚酰亚胺材料，例如通常在卷带自动结合（“TAB”, tapeautomated bonding）中应用的聚酰亚胺材料。
从图2中可以看出，掩模层或其他图案化的牺牲层116在第一金属层上形成。掩模层由耐蚀金属或其他材料制成，如通过照相平版印刷或其他图案化技术制成，仅举几例如模版印刷（stenciling）、丝网印刷、或激光烧蚀。然后，在图3中可以看出，第一金属层可被图案化，如通过以方向118朝层状金属结构102引入蚀刻剂流体而进行。这个图案化过程去除了第一金属层上没有被掩模层116保护的部分，从而形成了复数个蚀刻固态金属柱120。因为蚀刻隔离层114不被用于第一金属层图案化的蚀刻剂腐蚀，柱突出于蚀刻隔离层114的暴露表面112上方。金属柱可在蚀刻隔离层上相互分离，从而提供了一系列的单个导体。在图4中可以看出，当柱通过蚀刻形成时，它们可具有截头圆锥的形状，每个柱具有比其顶端127宽的基底128，柱通常具有相对竖直方向以一角度延伸的边缘表面。
图4示出了过程的随后阶段，其中蚀刻隔离金属层的暴露部分被去除，且第二金属层112被图案化，以形成垫124及通常还具有的沿介电元件104所在平面方向延伸的迹线（未示出），垫及迹线与柱120电连接。第二金属层的迹线可使至少一些垫与至少一些固态金属柱电连接。作为图案化的结果，介电元件104中的开口现在变为贯穿结构126的厚度而延伸的贯通开口。
在上述实施例（图1至图4）的变例中，包括柱、垫及迹线的类似结构126，可通过在介电层104的一个或多个表面上电镀而形成、或通过电镀与蚀刻步骤的组合而形成。在电镀的结构中，柱120通常具有垂直于介电元件的表面105的边缘表面，柱从该表面105突出。
结构126已被确定，图5示出了包括介电元件132的基板130，介电元件132上具有复数个连接元件134及端子140，及与触点134及端子140电连接的金属或其他导电元件142。基板130通常以连续或半连续带或薄板的形式，具有大量的区域131。如将在下文说明的，在过程结束时每个区域131都将构成单独封装的一部分，且每个区域131都包括如下文所述的将形成单个封装一部分的特征。与基板104相似，基板130可为柔性的或刚性的，且可由一种或多种与基板104相同的材料构成，其介电元件132可包括单层的介电材料，或可为包括数个子层的层压板，可主要由聚合物电介质如聚酰亚胺、BT树脂、环氧树脂等或其他电介质聚合物制成，在一些示例中，可包括强化纤维，例如玻璃纤维。与基板104中的介电元件相似，介电元件可为聚合物带材料如聚酰亚胺材料，如通常在卷带自动结合（“TAB”）中应用的聚酰亚胺材料。
特别地如图5所示，端子140形成在与连接元件134分离的层内，这些金属层通过介电元件132相互分离，且通过导电元件如延伸穿过介电元件的通路32而彼此电连接。这样的布置通常称为“双金属”结构。替代地，如图6所描述的，基板150可由单一金属结构制成，单一金属层既构成暴露在基板第一表面152的导电连接元件154，又构成暴露在基板第二表面158的开口内的端子160，其中第二表面158远离第一表面。替代地，在图6所示实施例的变例中，基板150可应用相反的布置，其中端子位于基板的第二表面158，而导电连接元件暴露在开口内，其中开口从第一表面154开始并延伸穿过介电元件。在又一进一步的变例中，构建导电安装元件、端子或二者的一个或多个金属层，可位于介电层的厚度范围内，且通过孔在适当的表面暴露。
从图7中可以看出，微电子元件170安装在第一基板130的第一表面或“上”表面136上。每个区域131具有一个或多个安装于其上的微电子元件。在特定实施例中示出，下基板的每个区域131承载一个微电子元件。所示的微电子元件为以面向下的方向安装的半导体芯片，芯片的例如结合垫（未示出）这样的触点与基板的导电连接元件134连接，例如通过应用如焊料这样的结合材料171而使触点与导电安装元件结合。但是，也可应用其他技术。例如，每个微电子元件170可为封装的微电子元件，包括其上具有封装端子的封装基板（未示出），这些封装端子与第一基板上的导电连接元件134连接。在又一其他变例中，可应用如各向异性的导电粘接剂的技术。基板130的每个区域131内的微电子元件170，可通过该区域131的导电连接元件134与同一区域的至少一些安装端子140连接，或与该区域的至少一些层间连接端子138连接，或与二者都连接。微电子元件170可应用常规技术安装在下基板上，或者作为本文描述的组装过程的一部分，或者在用于准备下基板130的单独操作中。
在微电子元件170安装至基板130后，微电子元件与基板之间通过结合材料171和连接元件134而电连接，可在基板130与微电子元件的触点承载面172之间注入底充胶174（图8），从而方便增加对电连接中热应力及机械应力的阻力。然后，基板100可例如通过粘接剂178安装至微电子元件170的背面176。在一个实施例中，例如，当基板包括聚合介电材料时，粘接剂可为柔性的。但在另一实施例中，当基板100具有与微电子元件170相同或接近的热膨胀系数时，粘接剂则无需为柔性的，甚至可为刚性材料。基板100安装至微电子元件170，使得导电柱120从远离微电子元件170的基板表面108向外突出。
从图8中进一步可以看出，当基板和微电子元件接合以形成组件180时，第二基板的开口106与第一基板的层间连接元件138对齐。这允许将要形成的导电元件182（图9）使第一基板上的层间连接元件138与第二基板的垫124接合，从而形成组件184。例如，引线结合(wirebonding)工具的顶端可穿过第二基板的开口106，以形成具有附接至层间连接元件138的第一端及附接至垫124的第二端的结合引线(wire bond)。然后，组件184可沿线186切割以把组件分离成单独的微电子组件188（图10），每个微电子组件188都包含第一基板和第二基板中每个的区域，及在两个基板区域之间且与每个基板区域都电连接的微电子元件170。
在上述过程的变例中（图9A），复数个单独的基板126’中，每个都具有从其上突出的柱120及导电元件，如其上的垫124，基板126’可附接至相应的微电子元件170上，且经由结合引线182’与基板130电连接。在基板130的复数个区域以连续基板或半连续基板的形式保持连接在一起时，可进行这个过程。在这种情况下，结合引线182’可设置为超出每个基板126’的外围边缘107。
如图11所示，可应用模具190，以形成围绕组件188的结构的模塑密封区域。例如，在从图9A中可以看到的结构中，在切割基板130之前，可把模板192靠在第一基板区域131的表面136上而放置。然后，密封剂通过入口（未示出）注入模具内，以环绕结合引线182，并通常充满单个柱120之间的所有空间，及微电子元件170的边缘198与结合引线182之间的所有空间。然后组件可从模具取出，并可选择地处理以使密封剂201至少部分地固化，如在图12所表示的。基板130还将被切割，以便在当时形成单独的单元188。导电柱120暴露在覆盖微电子元件170的密封剂的暴露主表面200上。导电柱在覆盖微电子元件170的密封剂的开口202内延伸。通常，在从模具190取出具有密封区域的微电子组件188后，焊料凸点204或焊料球可与端子140接合，以形成从图12中可以看出的微电子封装210。
图13示出了根据特定实施例的微电子封装290，其中所附的端子240可为垫、或为具有附接于其上的例如焊料球这样的结合材料球242的垫，每个端子240可分别与暴露在密封剂远离端子的表面200上的导电柱220竖直对齐。封装290的端子和柱的这种布置，方便在如图21所示的堆叠组件内，复数个微电子封装290的相互堆叠及连接。
在图13至图14中进一步说明，在微电子封装290中，柱220形成位于上基板100的表面221的面阵（area array）222。在第二基板100的表面221暴露的垫224可与在下基板表面暴露的垫238电连接，例如通过结合引线282而连接。进一步如图14所示，可布置封装290内的结合引线，以提供具有所需阻抗或受控阻抗的传输线路。特别地，下基板上的一些垫可被用来与参考电位如地面、电源电压、或其他电位连接，相对于其他柱220上存在的信号变化的典型速度，参考电位可只缓慢地变化，或可极缓慢地变化，或只在窄的范围内变化。例如，垫238A可为用于与地面电连接的接地垫，通过设置在基板230的表面244上的电连接件240、242而与地面电连接。参考结合引线284A在基板的这些接地垫224A、238A之间延伸，其走向(run)邻近信号结合引线282的走向。在这种情况下，在沿基板100的表面221的一个或多个横向方向292上，参考结合引线的走向与信号结合引线的走向基本上均匀地间隔开。替代地，或附加地，封装290可包括延伸至参考垫238B以与参考电位连接的参考结合引线284B，且相对基板100的第一表面221，这些参考结合引线284B的走向，可延伸至在竖直方向294（图13）上基本对齐的信号结合引线282B的走向的上方或下方。任意或所有这些特定设置，可选择地设置在同一微电子封装290内。
在上述方法（图1至图12）的变例中，组件从模具内取出时，导电垫无需暴露。替代地，从图15中可以看出，密封剂可覆盖顶面121，即柱远离基板100的端部。在这种情况下，顶面121被密封剂覆盖，从而它们被埋在密封剂主表面300之下。然后，如图16A所示，可在密封剂内形成复数个部分地暴露柱的顶面121的开口301，使顶面的其他部分303仍被密封剂覆盖。在这种情况下，柱的边缘表面123可保持为被密封剂覆盖。
在图16A中实施例的一个变例中，密封剂主表面的开口302（图16B）至少部分地暴露至少一些柱的顶面121，并至少部分地暴露同一柱的边缘表面123。柱的边缘表面123可只部分地在开口内暴露，如图16B所示，或可暴露至基板的表面105。参照图21在下文进一步描述，如在微电子封装接合的堆叠组件内，密封剂201在相邻柱120之间的部分304可作为各柱之间的绝缘体，及用于限制结合材料的流动而保留，可与柱120连接的结合材料如，锡、焊料、导电胶等。
在一个实施例中，可在主表面的一个这样的开口内暴露一个柱120的顶面的至少一部分以及边缘表面的至少一部分，任一其他柱120的表面都不在同一开口内暴露。替代地，两个或更多个柱120中的每个柱的顶面的至少一部分以及边缘表面的至少一部分可暴露在形成于密封剂主表面的单个开口内。在另一情况下，两个或更多个柱的顶面的至少一部分以及边缘表面的至少一部分可在形成于密封剂主表面的单个开口内暴露。
在特定实施例中，一排柱中的两个或更多个柱，或替代地，一个或多个整排的柱，可具有顶面的至少一部分及边缘表面的至少一部分在密封剂主表面的单个开口内暴露。在一些情况下，只有小于整个顶面的部分顶面在特定开口内暴露。在一些情况下，整个的顶面可在特定开口内暴露。在特定情况下，边缘表面只有部分可在特定开口内暴露，在一些情况下，边缘表面可暴露至基板的表面105，或暴露至与柱接触的导电元件的表面。在特定实施例中，复数个柱中每个柱的整个顶面及部分边缘表面，即小于整个边缘表面的部分边缘表面，可在密封剂主表面的单个开口内暴露。
图17示出了上述实施例（图12；或图13至图14）的一个变例，其中密封剂201形成在暴露于基板400朝外的表面421的导电垫402的顶上。以这种方式，垫402被埋在密封剂的暴露表面404之下，在一个示例中，暴露表面404可为密封剂的主表面。与上述实施例（图12至图13）中的导电柱220相似，垫402可经由迹线（未示出）或其他导电体（未示出）与第一基板400的结合垫(bond pad)124电连接，以同时承载信号及在不同电位的其他电压。在密封剂至少部分固化后，在密封剂内形成开口406（图18），开口从暴露表面404延伸，并至少部分地暴露相应的垫402。随后，导电结合材料，如锡、焊料、或其他导电胶等，可设置在每个开口内以形成在表面404暴露的导电块408（图19）。在封装（图19）的一个变例中，金属如铜、金或其组合物可电镀至开口内的垫上，以形成固态金属柱而取代在表面404暴露的块408。在柱形成后，组件可平面化，使得以这种方式电镀的柱的表面为平的且可与表面404平齐。
在另一变例（图20）中，导电块410，如焊料球，可在施加密封剂之前与导电垫402接合。在模塑时，模具的盖板192（图11）与导电块的表面接触，且导电块410可被模具压缩，从而使导电块与盖板接触的表面平面化。从而，当封装490从模具内取出时，导电块具有暴露于主表面404的相对宽的平表面412。
在一个变例中，从图20A可以看出，密封剂可形成为具有在高度H1的主表面405，高度H1大于例如焊料球这样的导电块410在上基板400上方延伸的高度H2。在密封剂层形成后，可应用激光烧蚀、机械球磨或其他方式，以形成分别暴露一个导电块的开口411。
在上述实施例（图15至图20A）的变例中，两个或更多个导电柱或导电块可暴露在密封剂层的单个开口内。在图20A所示实施例的一个变例中，各导电块410可与每个导电柱的顶面427及边缘表面428接触，导电块部分地暴露在开口411内。
图21示出了堆叠组件500的形成过程，堆叠组件500包括复数个微电子封装290A、290B、290C，每个微电子封装都如上所述。第一微电子封装的焊料球242A可与电路板502的端子504接合，电路板如柔性的或刚性的电路板或卡、母板等。以这种方式，用于承载信号及其他电压的电连接可设置在电路板502与微电子元件170A及封装290A的层间导电元件138A之间。向电路板的垫504及从电路板的垫504，经由垫124、结合引线282、及层间导电元件138A所形成的电连接，导电柱120A也可承载信号及其他电压，其中层间导电元件138A具有与端子240A及焊料球242A的电连接（未示出）。
在使微电子封装290A与电路板502接合后，微电子封装290B的焊料球242B可与微电子封装290A的导电柱120A接合。图21进一步示出了已定位的微电子封装290C，使得微电子封装290C的焊料球242C与微电子封装290B的导电柱120B对齐，之后微电子封装290C与微电子封装290B接合。在一个变例中，包括微电子封装290A、290B、290C的组件可通过使组件内一个封装上的焊料球分别与组件内另一个封装的导电柱接合而形成，之后焊料球242A暴露在这种组件的底部，且可与电路板上相对应的垫504接合。
参照简化的附图，另外的变例已示出并在下文描述，附图中不是所有存在的元件都具体示出或引用。同时，在下文所描述的每个变例中，每个附图中所示的元件不是都必须存在或需要的。对于本文描述的实施例，“上基板”或“下基板”无需遵从重力参照系。在图22至图32中，称为 “上基板”或“下基板”的每个元件可为单独的基板，或可为从更大的如连续或半连续基板上切割的部分。另外，每个微电子封装或组件内的上基板及下基板的相对位置是可以反转的，从而下基板位于在每个相应的图中所示的上基板的位置，而上基板位于每个图中下基板的位置。
因此，在图22中可以看出的实施例中，参考结合引线584可具有以竖直方向延伸的走向，邻近且至少基本平行于信号结合引线582的走向，参考结合引线与暴露在密封剂主表面504的参考导电柱520电连接。参考导电柱可用来与如地面或电源电压的参考电位连接，例如，参考导电柱与参考结合引线584一起应用，以控制信号结合引线的阻抗。从图22可以进一步看出，在一个特定实施例中，第一基板550可具有复数个金属层552，其中至少一个金属层可埋在介电元件的厚度范围内。
图23示出实施例（图22）的一个变例，其中附加导电柱522与导电元件538电连接，导电元件538如在下基板550的第一表面554上突出的迹线、垫等。例如在设置了一个或多个参考电位时，导电柱522可与一个或多个参考柱520或参考导电体电连接，参考电位如电源电压或地面。在一个示例中，柱520具有与柱522的对应相邻表面523冶金接合或一体的基底521。在特定实施例中，可用如间隔体等的结构取代柱522，以保持上基板与下基板之间的适当间隔。替代地，可用散热片或其他热导体取代导电柱522，或导电柱522也可具有间隔体的作用或具有热传导的作用。
图24示出了实施例（图22）的进一步的变例，其中上基板或第二基板600为引线框架（lead frame），其柱620与从柱延伸的迹线622为一体形成的，如在制造引线框架时通过冲压或压印金属箔而一体形成，在一些情况下，可在其上电镀金属。然后这种引线框架600可与微电子元件670的背面672结合，然后所得的组件可放置在模具内，然后如上文参照图11 所描述的方法形成密封剂。替代地，不是通过冲压或压印金属箔，上基板可从层状金属结构图案化，如上文参照图1至图4所描述的那样，不同之处在于图案化的层状金属结构可通过粘接剂与芯片670的面粘接，即，在微电子封装内无需另外的介电元件，如支撑柱及触点的介电基板。
如在图22中，一个或多个参考柱620A与一个或多个参考结合引线，可承载如电源或地面的参考电位。图25示出进一步的变例，其中可省略图24中的一个或多个参考柱620A。
图26示出实施例（图13至图14）的一个变例，其中微电子元件770的触点承载面771面向上，即远离下基板700。触点772，如微电子元件770的结合垫，可邻近微电子元件的外围边缘774而设置，使得触点可在上基板730的相邻外围边缘732外暴露。第一结合引线740可使微电子元件的触点772与下基板上的相对应的垫744连接。第二结合引线742可使触点772与上基板的相对应的垫（未示出）电连接。在一个实施例中， 一根或多根结合引线可将上基板及下基板的垫直接相连接。
在图27中可以看到进一步的变例，第一微电子元件870和第二微电子元件880可每个都面向上安装，即承载触点的面背向下基板800。各微电子元件可经由结合引线882而连接在一起，结合引线882在每个微电子元件的触点之间延伸。附加的结合引线884、886可使微电子元件与上基板830及下基板800电连接。在进一步的变例中，可安装第三微电子元件、第四微电子元件、或甚至更多数量的微电子元件，且在微电子封装内以相似的方式电连接。
图27A示出了图27所示实施例的一个变例，其中两个微电子元件970、980的每一个都以倒装芯片的方式分别安装至基板800、900上。微电子元件的背面可如图所示背靠背结合(back-bonded)在一起。从图27A中可以进一步看出，微电子封装内至少一些结合引线984可具有受控阻抗。亦即，从图27可以看出，在承载元件间，如上基板800和下基板900之间的信号的结合引线984，可与其他具有竖直走向的结合引线986侧向连接，该结合引线986与信号结合引线984的竖直走向平行，且具有基本均匀的间距。其他结合引线986可与参考电位电连接，参考电位如地面、电源电压、或替代地，与信号结合引线承载的信号变化速度相比，只缓慢变化的电压。这些参考结合引线986通过在上基板800与下基板900中每个上设置的触点，与参考电位电连接。
在图27A所示实施例的变例中，一个或多个微电子元件可以倒装芯片的方式安装至基板800、900中相应的一个上，其他微电子元件可相对其中一个基板以面向上的方式安装，微电子元件与基板通过一根或多根结合引线（未示出）电连接。在图27所示实施例的特定变例中，微电子元件（未示出）可以倒装芯片的方式安装至基板800，微电子元件870可与以倒装芯片方式安装的微电子元件的背面背靠背结合。如图27所示，该微电子元件870可与基板800电连接，另一微电子元件880可与下基板800、上基板830、或微电子元件870如图27所示及参照图27在上文所述而电连接。
图28示出了实施例（图26）的进一步的变例，与图20中实施例类似，焊料球940与例如上基板上的垫（未示出）这样的导电元件在形成密封剂之前接合。
图29示出了图26中实施例的变例，也与图19实施例类似，导电块1008可在形成密封剂之后形成。
图30示出又一变例，其中微电子元件1170以触点承载面1172背向基板1100的方式安装至基板1100。在这个实施例中省略了上基板。导电柱1120可具有例如50微米至300微米的高度，可如关于上面的实施例（图1至图14）所描述。柱可从微电子元件的面1172向外延伸，且在密封剂的表面1102暴露。在一个实施例中，导电柱可如以下专利文献所描述的方式形成。专利申请号为12/317707、12/462208、12/286102、12/832376的共同拥有的美国专利申请，或专利号为7911805的美国专利(TIMI 3.0-100, TIMI 3.0-101, TESSERA 3.0-585,TESSERA 3.0-609 或 TESSERA 3.0-565)，其公开的内容通过援引加入本文。柱1120可用来使微电子元件1170与另一封装或元件电连接，也可用来与焊料球，如基板1100的球栅阵列（BGA）接口1140，经由垫1174、结合引线1176及导电元件1178而电连接，导电元件1178沿表面1172延伸，并使柱1120与结合引线1176连接。
图31示出实施例（图30）的进一步变例，其中设置例如焊料球这样的导电块1220以代替在图30所看到的导电柱1120。
图32示出了上述实施例（图26）的变例，其具有一个或多个在下基板与密封剂1300的表面1302之间延伸的附加导电柱1320。该导电柱可与一个或多个焊料球1340电连接。在一个实施例中，附加导电柱可以脊、环或其部分的形式沿微电子元件1370的外围边缘1374延伸，即，以图32中进入及穿出纸面的方向来设置。在一个实施例中，该一个或多个附加导电柱可承载时变信号（time-varying signals）。替代地，该一个或多个附加导电柱1320可承载参考电位，如地面或电源电压。
图33示出了根据进一步实施例的堆叠组件，其中上封装的端子1440B与例如下微电子封装1490A的导电柱1420A这样的连接体接合，下微电子封装1490A具有如图26所示及参照图26在上文所述的结构。图33示出了微电子封装1490A上的连接体1420A的间距、数量、及接触面积可被标准化，使得与另一封装1490B的相对应的BGA接口匹配，且另一封装无需具有与封装1490A相同的结构。
先前优选实施例的描述是旨在说明而不是限制本发明。制造微电子封装及其内结构的特定方法，可进一步如Belgacem Haba共同拥有的专利申请号为12/838974、名称为“可堆叠模塑微电子封装”、申请日为2010年7月19日的美国专利申请中所描述的，其公开的内容通过援引加入本文。
在不偏离权利要求所限定的本发明的情况下，可利用上述的这些变例及其他变例及特征的组合，先前对于优选实施例的描述，应当认为是权利要求限定的本发明的示例方式，而不是对本发明的限制。

Claims (26)

1.微电子封装，包括：
第一基板，具有第一表面、远离所述第一表面的第二表面、在所述第一表面暴露的复数个第一基板触点、与所述第一基板触点电互连且在所述第二表面暴露的复数个端子；
远离所述第一基板的第二基板，所述第二基板具有第一表面、第二表面、在所述第二基板的第二表面暴露的复数个第二基板触点，其中所述第二基板的第一表面朝向所述第一基板的第一表面，所述第二基板的第二表面远离所述第二基板的第一表面；
设置在所述第一基板的第一表面与所述第二基板的第一表面之间的微电子元件，所述微电子元件具有第一面、远离该第一面的第二面、在所述第一面暴露的元件触点，所述第一面或所述第二面中的一个朝向所述第一基板的第一表面，所述第一面或所述第二面中的另一个朝向所述第二基板的第一表面；
复数个结合引线，将所述第一基板和所述第二基板的每一个之上的导电元件电连接；
连续的密封剂，覆盖所述第一基板的所述第一表面、所述复数个结合引线及所述第二基板的第二表面的至少一部分，所述连续的密封剂限定了主表面以及从所述主表面向下延伸的开口；及
复数个封装触点，在所述密封剂的主表面暴露并置于所述第二基板的第二表面之上，至少部分地在所述密封剂的开口内，所述封装触点突出高于所述第二基板触点的高度，所述封装触点与所述微电子元件的所述元件触点至少通过所述复数个结合引线电互连，所述封装触点包括了从所述第二基板的第二表面向上突出的截头圆锥形状的铜的固态金属柱，其中至少所述封装触点的顶面至少部分地在所述密封剂的所述主表面的下方暴露，
其中，由所述开口形成的所述密封剂的部分构造成限制待连接到所述柱的结合材料的流动。
2.根据权利要求1所述的封装，其中所述微电子元件的至少一部分以平行于所述第二基板的所述第一表面的方向延伸到所述第二基板的外围边缘之外。
3.根据权利要求1所述的封装，其中所述密封剂的所述主表面至少朝着所述第一基板的外围边缘延伸到所述微电子元件的外围边缘之外。
4.根据权利要求3所述的封装，其中至少一些所述柱的顶面仅延伸至所述密封剂的所述主表面的开口的一部分高度，所述密封剂与所述至少一些柱的边缘表面的至少一部分接触。
5.根据权利要求4所述的封装，其中所述至少一些柱的所述边缘表面至少部分地在所述密封剂的相应开口内暴露。
6.根据权利要求4所述的封装，其中所述至少一些柱的边缘表面全部被所述密封剂覆盖。
7.根据权利要求3所述的封装，其中所述至少一些柱的边缘表面全部被所述密封剂覆盖。
8.根据权利要求1所述的封装，其中所述复数个结合引线从所述第一基板的所述第一表面上方伸出并且在所述第一基板触点与所述第二基板触点之间延伸，至少一些所述结合引线彼此电绝缘并适于同时承载不同的电位。
9.根据权利要求8所述的封装，其中所述结合引线包括多个第一结合引线以及至少一个第二结合引线，所述至少一个第二结合引线与所述第一基板触点连接以便将所述至少一个第二结合引线与参考电位电连接，从而所述至少一个第二结合引线与至少一个所述第一结合引线形成受控阻抗传输线路。
10.根据权利要求8所述的封装，还包括与所述微电子元件直接电连接的第二结合引线以及位于所述第二基板的第二表面上的触点，其中所述密封剂的所述主表面覆盖所述第二结合引线。
11.根据权利要求1所述的封装，其中所述微电子元件为第一微电子元件，所述封装进一步包括位于所述第一微电子元件与所述第二基板之间的第二微电子元件，所述第二微电子元件与所述第一基板和所述第二基板中的至少一个电互连。
12.根据权利要求1所述的封装，其中所述第二基板的所述第一表面附接至所述微电子元件。
13.根据权利要求1所述的封装，其中所述固态金属柱暴露于所述密封剂的主表面。
14.根据权利要求1所述的封装，其中所述封装触点配置为同时承载不同的电位。
15.微电子封装，包括：
第一基板，具有第一表面、远离所述第一表面的第二表面、在所述第一表面暴露的复数个第一基板触点、与所述第一基板触点电互连且在所述第二表面暴露的复数个端子；
远离所述第一基板的第二基板，所述第二基板具有第一表面、远离该第一表面的第二表面、在所述第二基板的第二表面暴露的复数个第二基板触点；
设置在所述第一基板的第一表面与所述第二基板的第一表面之间的微电子元件，所述微电子元件具有第一面、远离第一面的第二面、在所述第一面暴露的元件触点，所述第一面或所述第二面中的一个与所述第一基板的所述第一表面并置；
复数个结合引线，将所述第一基板和所述第二基板的每一个之上的导电元件电连接；
连续的密封剂，覆盖所述第一基板的所述第一表面、所述复数个结合引线及所述第二基板的第二表面的至少一部分，所述连续的密封剂限定了主表面以及从所述主表面向下延伸的开口；及
复数个封装触点，在所述密封剂的主表面暴露并置于所述第二基板的第二表面之上，所述封装触点至少部分位于所述密封剂的开口内并与所述微电子元件的所述元件触点通过所述复数个结合引线电互连，所述开口从所述密封剂的主表面朝暴露在所述第二基板的第二表面上的第二基板触点连续地变小，所述第二基板触点包括连接到从所述第二基板的第二表面延伸的柱的导电结合材料块。
16.根据权利要求15所述的封装，其中至少一些封装触点的顶面的至少一部分在所述开口内暴露，所述密封剂与所述第二基板的所述至少一些封装触点的所述顶面的至少一部分接触，其中第一组最外侧相对边缘在所述第一基板的第一表面和第二表面之间延伸，其中第二组最外侧相对边缘在所述第二基板的第一表面和第二表面之间延伸并与第一组所述相对边缘对齐，基板开口在所述第一表面和第二表面之间延伸并与所述第一基板的至少一些基板触点对齐，其中所述复数个结合引线延伸穿过所述第二基板的所述基板开口。
17.根据权利要求15所述的封装，其中至少一些封装触点的边缘表面全部被所述密封剂覆盖。
18.根据权利要求15所述的封装，其中所述复数个结合引线从所述第一基板的所述第一表面上方伸出并且在所述第一基板触点与所述第二基板触点之间延伸，至少一些所述结合引线彼此电绝缘并适于同时承载不同的电位。
19.制造微电子封装的方法，包括：
提供包括第一基板和微电子元件的第一微电子子组件，所述第一基板具有基板触点、第一表面、远离所述第一表面的第二表面、及复数个暴露在所述第二表面的端子，所述微电子元件具有正面、暴露在所述正面的元件触点、及远离其的背面，所述正面与所述第一表面并置；所述第一微电子子组件进一步包括复数个导电元件，所述导电元件在所述第一表面上突出，且与所述元件触点及所述基板触点电连接，仅在所述微电子元件的所述正面与所述第一基板的所述第一表面之间设置底充胶，以便增加对所述微电子元件与所述第一基板之间的电连接中的热应力及机械应力的阻力；
提供第二子组件，其包括在第二基板的表面上方延伸的基本上刚性的导电柱；
将所述第二子组件连接到所述微电子元件的所述背面，使得所述基本上刚性的导电柱与所述导电元件电互连，并且延伸至高于所述微电子元件的所述元件触点的高度；
然后形成密封剂，其覆盖已连接的所述第一微电子子组件和所述第二子组件的至少一部分，所述密封剂覆盖所述第一表面、所述导电元件及所述微电子元件远离所述第一基板的面的至少一部分，所述密封剂限定了主表面，其中所述基本上刚性的导电柱的顶面的至少一部分通过所述密封剂的所述主表面内的开口而暴露，所述基本上刚性的导电柱的顶面的至少一部分位于所述密封剂的所述主表面的下方。
20.制造微电子封装的方法，包括：
提供包括第一基板和微电子元件的第一微电子子组件，所述第一基板具有基板触点、第一表面、远离所述第一表面的第二表面、及复数个暴露在所述第二表面的端子，所述微电子元件具有正面、暴露在所述正面的元件触点、及远离其的背面，所述正面与所述第一表面并置；所述第一微电子子组件进一步包括复数个导电元件，所述导电元件在所述第一表面上突出，且与所述元件触点及所述基板触点电连接，
提供第二子组件，其包括具有第一表面和第二表面的第二基板和设置在所述第二基板的所述第一表面上的导电柱；
将所述第二子组件连接到所述微电子元件的所述背面，使得所述导电柱与所述导电元件电互连；
然后形成密封剂，其覆盖所述第一表面、所述导电元件、所述导电柱的顶面及所述微电子元件远离所述第一基板的面的至少一部分，所述密封剂限定了主表面；及
然后在所述密封剂形成开口，以至少部分地暴露所述导电柱的所述顶面，并使得由所述开口形成的所述密封剂的部分能够限制待连接到所述柱的结合材料的流动。
21.根据权利要求20所述的方法，其中所述导电柱用作所述微电子封装的封装触点。
22.根据权利要求20所述的方法，进一步包括形成与所述导电柱电气通信的封装触点。
23.根据权利要求22所述的方法，其中所述形成封装触点的步骤包括在所述开口内的所述导电柱上沉积导电结合材料块的步骤。
24.根据权利要求21所述的方法，其中所述封装触点从所述第二基板的所述第一表面延伸至高于所述元件触点的高度。
25.根据权利要求20所述的方法，其中所述导电柱具有远离所述第二基板的所述第一表面的顶面以及从所述顶面向外延伸的边缘表面，其中所述形成开口的步骤中至少部分地暴露所述边缘表面。
26.根据权利要求20或21所述的方法，其中所述方法应用于制造第一微电子封装和第二微电子封装中的每一个，所述方法进一步包括在所述第一微电子封装顶上堆叠所述第二微电子封装的步骤，及通过所述第一微电子封装的所述端子及所述第二微电子封装的所述端子而使所述第一微电子封装与所述第二微电子封装电互连的步骤。
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US8906743B2 (en) 2013-01-11 2014-12-09 Micron Technology, Inc. Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
TWI557865B (zh) * 2014-01-29 2016-11-11 矽品精密工業股份有限公司 堆疊組及其製法與基板結構
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9741692B2 (en) * 2014-09-15 2017-08-22 Intel Corporation Methods to form high density through-mold interconnections
KR102289985B1 (ko) 2014-12-08 2021-08-17 삼성디스플레이 주식회사 표시 장치
CN104538368A (zh) * 2014-12-30 2015-04-22 华天科技（西安）有限公司 一种基于二次塑封技术的三维堆叠封装结构及其制备方法
TWI550805B (zh) * 2015-04-20 2016-09-21 南茂科技股份有限公司 晶片堆疊封裝結構
CN106486453A (zh) * 2015-08-25 2017-03-08 力成科技股份有限公司 一种柱顶互连型态半导体封装构造及其制造方法
US9842820B1 (en) * 2015-12-04 2017-12-12 Altera Corporation Wafer-level fan-out wirebond packages
KR102711053B1 (ko) 2016-10-04 2024-09-30 스카이워크스 솔루션즈, 인코포레이티드 오버몰드 구조체를 갖는 양면 라디오-주파수 패키지
US20180114786A1 (en) * 2016-10-21 2018-04-26 Powertech Technology Inc. Method of forming package-on-package structure
FR3060846B1 (fr) * 2016-12-19 2019-05-24 Institut Vedecom Procede d’integration de puces de puissance et de bus barres formant dissipateurs thermiques
TWI675441B (zh) * 2018-05-14 2019-10-21 欣興電子股份有限公司 封裝載板結構及其製造方法
CN109801894A (zh) * 2018-12-28 2019-05-24 华进半导体封装先导技术研发中心有限公司 芯片封装结构和封装方法
KR102574414B1 (ko) 2019-05-21 2023-09-04 삼성전기주식회사 전자 부품 모듈
JP2021041375A (ja) * 2019-09-13 2021-03-18 株式会社東芝 導電性流体用吐出ヘッド
US11410902B2 (en) 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US12136588B2 (en) * 2021-07-19 2024-11-05 Texas Instruments Incorporated Heat slug attached to a die pad for semiconductor package
CN114743963A (zh) * 2022-04-15 2022-07-12 江苏芯德半导体科技有限公司 一种多层芯片封装结构及其封装工艺

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020066952A1 (en) * 2000-12-04 2002-06-06 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
CN1877824A (zh) * 2005-06-10 2006-12-13 夏普株式会社 半导体器件、层叠式半导体器件和半导体器件的制造方法
JP2007208159A (ja) * 2006-02-06 2007-08-16 Hitachi Ltd 半導体装置
JP2009506553A (ja) * 2005-08-31 2009-02-12 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
CN101385140A (zh) * 2005-12-23 2009-03-11 泰塞拉公司 具有极细间距堆叠的微电子组件
US20090206461A1 (en) * 2008-02-15 2009-08-20 Qimonda Ag Integrated circuit and method
US20090236753A1 (en) * 2008-03-21 2009-09-24 Moon Dongsoo Integrated circuit package system for stackable devices
US20100032822A1 (en) * 2008-08-07 2010-02-11 Advanced Semiconductor Engineering, Inc. Chip package structure
US20100078789A1 (en) * 2008-09-26 2010-04-01 Daesik Choi Semiconductor package system with through silicon via interposer
WO2010041630A1 (ja) * 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
US20100224975A1 (en) * 2009-03-05 2010-09-09 Shin Hangil Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof

Family Cites Families (472)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1439262B2 (de) 1963-07-23 1972-03-30 Siemens AG, 1000 Berlin u. 8000 München Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression
US3358897A (en) 1964-03-31 1967-12-19 Tempress Res Co Electric lead wire bonding tools
US3623649A (en) 1969-06-09 1971-11-30 Gen Motors Corp Wedge bonding tool for the attachment of semiconductor leads
DE2119567C2 (de) 1970-05-05 1983-07-14 International Computers Ltd., London Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung
DE2228703A1 (de) 1972-06-13 1974-01-10 Licentia Gmbh Verfahren zum herstellen einer vorgegebenen lotschichtstaerke bei der fertigung von halbleiterbauelementen
US4327860A (en) 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections
US4422568A (en) 1981-01-12 1983-12-27 Kulicke And Soffa Industries, Inc. Method of making constant bonding wire tail lengths
US4437604A (en) 1982-03-15 1984-03-20 Kulicke & Soffa Industries, Inc. Method of making fine wire interconnections
JPS59189069U (ja) 1983-06-02 1984-12-14 昭和アルミニウム株式会社 冷却装置
JPS61125062A (ja) 1984-11-22 1986-06-12 Hitachi Ltd ピン取付け方法およびピン取付け装置
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
JP2608701B2 (ja) 1985-09-19 1997-05-14 三菱電機株式会社 保護装置の点検回路
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
JPS62158338A (ja) 1985-12-28 1987-07-14 Tanaka Denshi Kogyo Kk 半導体装置
US4793814A (en) 1986-07-21 1988-12-27 Rogers Corporation Electrical circuit board interconnect
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS62226307A (ja) 1986-03-28 1987-10-05 Toshiba Corp ロボツト装置
US4771930A (en) 1986-06-30 1988-09-20 Kulicke And Soffa Industries Inc. Apparatus for supplying uniform tail lengths
JPS6397941A (ja) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd 感光材料
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
JP2642359B2 (ja) 1987-09-11 1997-08-20 株式会社日立製作所 半導体装置
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
US4845354A (en) 1988-03-08 1989-07-04 International Business Machines Corporation Process control for laser wire bonding
US4998885A (en) 1989-10-27 1991-03-12 International Business Machines Corporation Elastomeric area array interposer
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
US5095187A (en) 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
AU645283B2 (en) 1990-01-23 1994-01-13 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
CA2034700A1 (en) 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US4999472A (en) 1990-03-12 1991-03-12 Neinast James E Electric arc system for ablating a surface coating
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5067382A (en) 1990-11-02 1991-11-26 Cray Computer Corporation Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
JPH04346436A (ja) 1991-05-24 1992-12-02 Fujitsu Ltd バンプ製造方法とバンプ製造装置
WO1993004375A1 (en) 1991-08-23 1993-03-04 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US5220489A (en) 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
JP2931936B2 (ja) 1992-01-17 1999-08-09 株式会社日立製作所 半導体装置用リードフレームの製造方法及び半導体装置用リードフレーム並びに樹脂封止型半導体装置
US5831836A (en) 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5494667A (en) 1992-06-04 1996-02-27 Kabushiki Kaisha Hayahibara Topically applied hair restorer containing pine extract
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
AU4782293A (en) 1992-07-24 1994-02-14 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US6295729B1 (en) 1992-10-19 2001-10-02 International Business Machines Corporation Angled flying lead wire bonding process
US20050062492A1 (en) 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JPH06268101A (ja) 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US7368924B2 (en) 1993-04-30 2008-05-06 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US20030048108A1 (en) 1993-04-30 2003-03-13 Beaman Brian Samuel Structural design and processes to control probe position accuracy in a wafer test probe assembly
JP2981385B2 (ja) 1993-09-06 1999-11-22 シャープ株式会社 チップ部品型ｌｅｄの構造及びその製造方法
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
EP1213756A3 (en) 1994-03-18 2005-05-25 Hitachi Chemical Co., Ltd. Fabrication process of semiconductor package and semiconductor package
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
JPH07335783A (ja) 1994-06-13 1995-12-22 Fujitsu Ltd 半導体装置及び半導体装置ユニット
US5468995A (en) 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US6117694A (en) 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5541567A (en) 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5495667A (en) 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
US5736074A (en) 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US5971253A (en) 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JPH09134934A (ja) 1995-11-07 1997-05-20 Sumitomo Metal Ind Ltd 半導体パッケージ及び半導体装置
JP3332308B2 (ja) 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
US5718361A (en) 1995-11-21 1998-02-17 International Business Machines Corporation Apparatus and method for forming mold for metallic material
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
US6000126A (en) 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
DE19618227A1 (de) 1996-05-07 1997-11-13 Herbert Streckfus Gmbh Verfahren und Vorrichtung zum Verlöten von elektronischen Bauelementen auf einer Leiterplatte
KR100186333B1 (ko) 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
JPH10135220A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
JPH10135221A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US5976913A (en) 1996-12-12 1999-11-02 Tessera, Inc. Microelectronic mounting with multiple lead deformation using restraining straps
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
JP3400279B2 (ja) 1997-01-13 2003-04-28 株式会社新川 バンプ形成方法
US5898991A (en) 1997-01-16 1999-05-04 International Business Machines Corporation Methods of fabrication of coaxial vias and magnetic devices
US5839191A (en) 1997-01-24 1998-11-24 Unisys Corporation Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package
WO1999009595A1 (en) 1997-08-19 1999-02-25 Hitachi, Ltd. Multichip module structure and method for manufacturing the same
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JP3859318B2 (ja) 1997-08-29 2006-12-20 シチズン電子株式会社 電子回路のパッケージ方法
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JP3393800B2 (ja) 1997-11-05 2003-04-07 新光電気工業株式会社 半導体装置の製造方法
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
US6124546A (en) 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
JPH11220082A (ja) 1998-02-03 1999-08-10 Oki Electric Ind Co Ltd 半導体装置
JP3536650B2 (ja) 1998-02-27 2004-06-14 富士ゼロックス株式会社 バンプ形成方法および装置
JPH11260856A (ja) 1998-03-11 1999-09-24 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体装置の実装構造
KR100260997B1 (ko) 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
US6180881B1 (en) 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
KR100265563B1 (ko) 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6164523A (en) 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000091383A (ja) 1998-09-07 2000-03-31 Ngk Spark Plug Co Ltd 配線基板
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6158647A (en) 1998-09-29 2000-12-12 Micron Technology, Inc. Concave face wire bond capillary
US6684007B2 (en) 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
JP2000311915A (ja) 1998-10-14 2000-11-07 Texas Instr Inc <Ti> 半導体デバイス及びボンディング方法
JP3407275B2 (ja) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
US6206273B1 (en) 1999-02-17 2001-03-27 International Business Machines Corporation Structures and processes to create a desired probetip contact geometry on a wafer test probe
KR100319609B1 (ko) 1999-03-09 2002-01-05 김영환 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
JP3398721B2 (ja) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6228687B1 (en) 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
TW417839U (en) 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
JP4526651B2 (ja) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
JP5333337B2 (ja) 1999-08-12 2013-11-06 富士通セミコンダクター株式会社 半導体装置の製造方法
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
US6724638B1 (en) 1999-09-02 2004-04-20 Ibiden Co., Ltd. Printed wiring board and method of producing the same
US6867499B1 (en) 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
JP3513444B2 (ja) 1999-10-20 2004-03-31 株式会社新川 ピン状ワイヤ等の形成方法
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
JP3619410B2 (ja) 1999-11-18 2005-02-09 株式会社ルネサステクノロジ バンプ形成方法およびそのシステム
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP3566156B2 (ja) 1999-12-02 2004-09-15 株式会社新川 ピン状ワイヤ等の形成方法
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP3980807B2 (ja) 2000-03-27 2007-09-26 株式会社東芝 半導体装置及び半導体モジュール
JP2001274196A (ja) 2000-03-28 2001-10-05 Rohm Co Ltd 半導体装置
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6531335B1 (en) 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP2001326236A (ja) 2000-05-12 2001-11-22 Nec Kyushu Ltd 半導体装置の製造方法
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6476583B2 (en) 2000-07-21 2002-11-05 Jomahip, Llc Automatic battery charging system for a battery back-up DC power supply
SE517086C2 (sv) 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6507104B2 (en) 2000-09-07 2003-01-14 Siliconware Precision Industries Co., Ltd. Semiconductor package with embedded heat-dissipating device
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR100393102B1 (ko) 2000-12-29 2003-07-31 앰코 테크놀로지 코리아 주식회사 스택형 반도체패키지
AUPR244801A0 (en) 2001-01-10 2001-02-01 Silverbrook Research Pty Ltd A method and apparatus (WSM01)
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
JP2002280414A (ja) 2001-03-22 2002-09-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002289769A (ja) 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
TW544826B (en) 2001-05-18 2003-08-01 Nec Electronics Corp Flip-chip-type semiconductor device and manufacturing method thereof
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6754407B2 (en) 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
WO2003019654A1 (en) 2001-08-22 2003-03-06 Tessera, Inc. Stacked chip assembly with stiffening layer
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US20030057544A1 (en) 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
JP2005506690A (ja) 2001-10-09 2005-03-03 テッセラ，インコーポレイテッド 積層パッケージ
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP2003122611A (ja) 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd データ提供方法及びサーバ装置
JP4257771B2 (ja) 2001-10-16 2009-04-22 シンジーテック株式会社 導電性ブレード
US20030094666A1 (en) 2001-11-16 2003-05-22 R-Tec Corporation Interposer
JP3875077B2 (ja) 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
JP2003174124A (ja) 2001-12-04 2003-06-20 Sainekkusu:Kk 半導体装置の外部電極形成方法
JP3507059B2 (ja) 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
JP2003197669A (ja) 2001-12-28 2003-07-11 Seiko Epson Corp ボンディング方法及びボンディング装置
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
JP3935370B2 (ja) 2002-02-19 2007-06-20 セイコーエプソン株式会社 バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
KR100452819B1 (ko) 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6979230B2 (en) 2002-03-20 2005-12-27 Gabe Cherian Light socket
US7323767B2 (en) 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
JP2004047702A (ja) 2002-07-11 2004-02-12 Toshiba Corp 半導体装置積層モジュール
US6756252B2 (en) 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
TW549592U (en) 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
US7053485B2 (en) 2002-08-16 2006-05-30 Tessera, Inc. Microelectronic packages with self-aligning features
US6740546B2 (en) 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
US7246431B2 (en) 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7294928B2 (en) 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7071547B2 (en) 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US7229906B2 (en) 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
WO2004032186A2 (en) 2002-09-30 2004-04-15 Advanced Interconnect Technologies Limited Thermal enhanced package for block mold assembly
US7045884B2 (en) 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
WO2004034433A2 (en) 2002-10-08 2004-04-22 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP2004172157A (ja) * 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
JP2004172477A (ja) 2002-11-21 2004-06-17 Kaijo Corp ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置
JP4464041B2 (ja) 2002-12-13 2010-05-19 キヤノン株式会社 柱状構造体、柱状構造体を有する電極、及びこれらの作製方法
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
JP2004221257A (ja) 2003-01-14 2004-08-05 Seiko Epson Corp ワイヤボンディング方法及びワイヤボンディング装置
JP2006518944A (ja) 2003-02-25 2006-08-17 テッセラ，インコーポレイテッド バンプを有するボールグリッドアレー
US20040217471A1 (en) 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
JP3885747B2 (ja) 2003-03-13 2007-02-28 株式会社デンソー ワイヤボンディング方法
JP2004343030A (ja) 2003-03-31 2004-12-02 North:Kk 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2004319892A (ja) * 2003-04-18 2004-11-11 Renesas Technology Corp 半導体装置の製造方法
JP4199588B2 (ja) 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
JP4145730B2 (ja) 2003-06-17 2008-09-03 松下電器産業株式会社 半導体内蔵モジュール
KR100604821B1 (ko) 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
US20040262728A1 (en) 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
US7227095B2 (en) 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
KR100546374B1 (ko) 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7061096B2 (en) 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
WO2005031861A1 (en) 2003-09-26 2005-04-07 Tessera, Inc. Structure and method of making capped chips including a flowable conductive medium
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
JP4272968B2 (ja) 2003-10-16 2009-06-03 エルピーダメモリ株式会社 半導体装置および半導体チップ制御方法
JP4167965B2 (ja) 2003-11-07 2008-10-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路用部材の製造方法
KR100564585B1 (ko) 2003-11-13 2006-03-28 삼성전자주식회사 이중 스택된 ｂｇａ 패키지 및 다중 스택된 ｂｇａ 패키지
TWI227555B (en) 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005183923A (ja) 2003-11-28 2005-07-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
JP2005175019A (ja) 2003-12-08 2005-06-30 Sharp Corp 半導体装置及び積層型半導体装置
WO2005059967A2 (en) * 2003-12-17 2005-06-30 Chippac, Inc. Multiple chip package module having inverted package stacked over die
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
JP4334996B2 (ja) 2003-12-24 2009-09-30 株式会社フジクラ 多層配線板用基材、両面配線板およびそれらの製造方法
US7495644B2 (en) 2003-12-26 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing display device
US6900530B1 (en) 2003-12-29 2005-05-31 Ramtek Technology, Inc. Stacked IC
US6917098B1 (en) 2003-12-29 2005-07-12 Texas Instruments Incorporated Three-level leadframe for no-lead packages
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
WO2005065207A2 (en) 2003-12-30 2005-07-21 Tessera, Inc. Microelectronic packages and methods therefor
JP2005203497A (ja) 2004-01-14 2005-07-28 Toshiba Corp 半導体装置およびその製造方法
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
JP4484035B2 (ja) 2004-04-06 2010-06-16 セイコーエプソン株式会社 半導体装置の製造方法
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US6962864B1 (en) 2004-05-26 2005-11-08 National Chung Cheng University Wire-bonding method for chips with copper interconnects by introducing a thin layer
US7233057B2 (en) 2004-05-28 2007-06-19 Nokia Corporation Integrated circuit package with optimized mold shape
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
JP4385329B2 (ja) 2004-10-08 2009-12-16 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
EP2014406A3 (de) 2004-11-02 2010-06-02 HID Global GmbH Verlegevorrichtung, Kontaktiervorrichtung, Zustellsystem, Verlege- und Kontaktiereinheit Herstellungsanlage, Verfahren zur herstellung und eine Transpondereinheit
WO2006052616A1 (en) 2004-11-03 2006-05-18 Tessera, Inc. Stacked packaging improvements
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
US7440722B2 (en) 2004-11-30 2008-10-21 Palo Alto Research Center Incorporated Xerography methods and systems employing addressable fusing of unfused toner image
KR100674926B1 (ko) 2004-12-08 2007-01-26 삼성전자주식회사 메모리 카드 및 그 제조 방법
JP4504798B2 (ja) 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
JP2006186086A (ja) 2004-12-27 2006-07-13 Itoo:Kk プリント基板のはんだ付け方法およびブリッジ防止用ガイド板
DE102005006333B4 (de) 2005-02-10 2007-10-18 Infineon Technologies Ag Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben
DE102005006995B4 (de) 2005-02-15 2008-01-24 Infineon Technologies Ag Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben
KR100630741B1 (ko) 2005-03-04 2006-10-02 삼성전자주식회사 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
TWI284394B (en) 2005-05-12 2007-07-21 Advanced Semiconductor Eng Lid used in package structure and the package structure of having the same
JP2006324553A (ja) 2005-05-20 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
US7216794B2 (en) 2005-06-09 2007-05-15 Texas Instruments Incorporated Bond capillary design for ribbon wire bonding
JP2009500821A (ja) 2005-07-01 2009-01-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電子素子
US7476608B2 (en) 2005-07-14 2009-01-13 Hewlett-Packard Development Company, L.P. Electrically connecting substrate with electrical device
TWI263313B (en) 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
SG130055A1 (en) * 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
US7504716B2 (en) 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
EP1946364A1 (en) 2005-11-01 2008-07-23 Koninklijke Philips Electronics N.V. Methods of packaging a semiconductor die and package formed by the methods
JP4530975B2 (ja) 2005-11-14 2010-08-25 株式会社新川 ワイヤボンディング方法
JP2007142042A (ja) 2005-11-16 2007-06-07 Sharp Corp 半導体パッケージとその製造方法，半導体モジュール，および電子機器
US7344917B2 (en) 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
JP2007234845A (ja) 2006-03-01 2007-09-13 Nec Corp 半導体装置
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7780064B2 (en) 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
JP4961848B2 (ja) 2006-06-12 2012-06-27 日本電気株式会社 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法
US20070290325A1 (en) 2006-06-16 2007-12-20 Lite-On Semiconductor Corporation Surface mounting structure and packaging method thereof
US7967062B2 (en) 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
CN101449375B (zh) 2006-06-29 2012-01-18 英特尔公司 用于集成电路封装中的无导线连接的设备、系统和方法
KR100792352B1 (ko) 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
KR100800478B1 (ko) 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
JP5132101B2 (ja) * 2006-07-27 2013-01-30 新光電気工業株式会社 スタックパッケージ構造体及びその製造に用いる単体パッケージと、それらの製造方法
US8048479B2 (en) 2006-08-01 2011-11-01 Qimonda Ag Method for placing material onto a target board by means of a transfer board
JP2008039502A (ja) 2006-08-03 2008-02-21 Alps Electric Co Ltd 接触子およびその製造方法
US7486525B2 (en) 2006-08-04 2009-02-03 International Business Machines Corporation Temporary chip attach carrier
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
KR20080020069A (ko) 2006-08-30 2008-03-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR100891516B1 (ko) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
KR100770934B1 (ko) 2006-09-26 2007-10-26 삼성전자주식회사 반도체 패키지와 그를 이용한 반도체 시스템 패키지
TWI336502B (en) 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
TWI312561B (en) 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
KR100817073B1 (ko) 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
WO2008065896A1 (fr) 2006-11-28 2008-06-05 Kyushu Institute Of Technology Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé
JP2008166439A (ja) 2006-12-27 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US8598717B2 (en) 2006-12-27 2013-12-03 Spansion Llc Semiconductor device and method for manufacturing the same
KR100757345B1 (ko) 2006-12-29 2007-09-10 삼성전자주식회사 플립 칩 패키지 및 그의 제조 방법
US20080156518A1 (en) 2007-01-03 2008-07-03 Tessera, Inc. Alignment and cutting of microelectronic substrates
TWI332702B (en) 2007-01-09 2010-11-01 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
JP5347222B2 (ja) 2007-01-10 2013-11-20 富士通株式会社 半導体装置の製造方法
US7719122B2 (en) 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
JP4823089B2 (ja) 2007-01-31 2011-11-24 株式会社東芝 積層型半導体装置の製造方法
KR101057368B1 (ko) 2007-01-31 2011-08-18 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
US8685792B2 (en) 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
EP2135280A2 (en) 2007-03-05 2009-12-23 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
CN101636830B (zh) 2007-03-23 2012-07-11 三洋电机株式会社 半导体装置及其制造方法
JP4926787B2 (ja) 2007-03-30 2012-05-09 アオイ電子株式会社 半導体装置の製造方法
JPWO2008120755A1 (ja) 2007-03-30 2010-07-15 日本電気株式会社 機能素子内蔵回路基板及びその製造方法、並びに電子機器
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
KR20080094251A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP5601751B2 (ja) 2007-04-26 2014-10-08 スパンション エルエルシー 半導体装置
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
JP5179787B2 (ja) 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US7911805B2 (en) 2007-06-29 2011-03-22 Tessera, Inc. Multilayer wiring element having pin interface
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR20090007120A (ko) 2007-07-13 2009-01-16 삼성전자주식회사 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
JP2009044110A (ja) 2007-08-13 2009-02-26 Elpida Memory Inc 半導体装置及びその製造方法
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
CN101874296B (zh) 2007-09-28 2015-08-26 泰塞拉公司 利用成对凸柱进行倒装芯片互连
JP2009088254A (ja) 2007-09-28 2009-04-23 Toshiba Corp 電子部品パッケージ及び電子部品パッケージの製造方法
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
KR20090033605A (ko) 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US20090091009A1 (en) 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US8008183B2 (en) 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI389220B (zh) 2007-10-22 2013-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
KR100886100B1 (ko) 2007-11-29 2009-02-27 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7964956B1 (en) 2007-12-10 2011-06-21 Oracle America, Inc. Circuit packaging and connectivity
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
KR20090123680A (ko) 2008-05-28 2009-12-02 주식회사 하이닉스반도체 적층 반도체 패키지
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
US7859033B2 (en) 2008-07-09 2010-12-28 Eastman Kodak Company Wafer level processing for backside illuminated sensors
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
SG10201505279RA (en) 2008-07-18 2015-10-29 Utac Headquarters Pte Ltd Packaging structural member
US8004093B2 (en) 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
KR100997793B1 (ko) 2008-09-01 2010-12-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
KR20100033012A (ko) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 반도체 패키지 및 이를 갖는 적층 반도체 패키지
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
JP5185062B2 (ja) 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101461630B1 (ko) 2008-11-06 2014-11-20 삼성전자주식회사 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
JP2010199528A (ja) 2009-01-27 2010-09-09 Tatsuta System Electronics Kk ボンディングワイヤ
JP2010177597A (ja) 2009-01-30 2010-08-12 Sanyo Electric Co Ltd 半導体モジュールおよび携帯機器
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
JP2010206007A (ja) 2009-03-04 2010-09-16 Nec Corp 半導体装置及びその製造方法
JP5471605B2 (ja) 2009-03-04 2014-04-16 日本電気株式会社 半導体装置及びその製造方法
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US20100244276A1 (en) 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US20100289142A1 (en) 2009-05-15 2010-11-18 Il Kwon Shim Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof
US8020290B2 (en) 2009-06-14 2011-09-20 Jayna Sheats Processes for IC fabrication
TWI379367B (en) 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5214554B2 (ja) 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8264091B2 (en) 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
TWI392066B (zh) 2009-12-28 2013-04-01 矽品精密工業股份有限公司 封裝結構及其製法
US9496152B2 (en) 2010-03-12 2016-11-15 STATS ChipPAC Pte. Ltd. Carrier system with multi-tier conductive posts and method of manufacture thereof
US7928552B1 (en) 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8564141B2 (en) 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
KR20120007839A (ko) 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101683814B1 (ko) 2010-07-26 2016-12-08 삼성전자주식회사 관통 전극을 구비하는 반도체 장치
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US20120063090A1 (en) 2010-09-09 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling mechanism for stacked die package and method of manufacturing the same
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8697492B2 (en) 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US20120184116A1 (en) 2011-01-18 2012-07-19 Tyco Electronics Corporation Interposer
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
US8487421B2 (en) 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
KR101800440B1 (ko) 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
US8680684B2 (en) 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9082763B2 (en) 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8828860B2 (en) 2012-08-30 2014-09-09 International Business Machines Corporation Double solder bumps on substrates for low temperature flip chip bonding
KR101419597B1 (ko) 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020066952A1 (en) * 2000-12-04 2002-06-06 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
CN1877824A (zh) * 2005-06-10 2006-12-13 夏普株式会社 半导体器件、层叠式半导体器件和半导体器件的制造方法
JP2009506553A (ja) * 2005-08-31 2009-02-12 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
CN101385140A (zh) * 2005-12-23 2009-03-11 泰塞拉公司 具有极细间距堆叠的微电子组件
JP2007208159A (ja) * 2006-02-06 2007-08-16 Hitachi Ltd 半導体装置
US20090206461A1 (en) * 2008-02-15 2009-08-20 Qimonda Ag Integrated circuit and method
US20090236753A1 (en) * 2008-03-21 2009-09-24 Moon Dongsoo Integrated circuit package system for stackable devices
US20100032822A1 (en) * 2008-08-07 2010-02-11 Advanced Semiconductor Engineering, Inc. Chip package structure
US20100078789A1 (en) * 2008-09-26 2010-04-01 Daesik Choi Semiconductor package system with through silicon via interposer
WO2010041630A1 (ja) * 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
US20100224975A1 (en) * 2009-03-05 2010-09-09 Shin Hangil Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof

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KR101895019B1 (ko) 2018-09-04
TWI460845B (zh) 2014-11-11
WO2012012321A3 (en) 2012-06-21
US9159708B2 (en) 2015-10-13
CN103201836B (zh) 2016-08-17
CN103201836A (zh) 2013-07-10
JP2017038075A (ja) 2017-02-16
KR101734882B1 (ko) 2017-05-12
WO2012012321A2 (en) 2012-01-26
TW201209991A (en) 2012-03-01
EP2596530A2 (en) 2013-05-29
KR20170051546A (ko) 2017-05-11
KR20130086347A (ko) 2013-08-01
US20160086922A1 (en) 2016-03-24
CN106129041A (zh) 2016-11-16
US20120013001A1 (en) 2012-01-19
JP2013535825A (ja) 2013-09-12
US9553076B2 (en) 2017-01-24
JP6027966B2 (ja) 2016-11-16

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