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CN1877824A - 半导体器件、层叠式半导体器件和半导体器件的制造方法 - Google Patents

半导体器件、层叠式半导体器件和半导体器件的制造方法 Download PDF

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Publication number
CN1877824A
CN1877824A CNA200610094536XA CN200610094536A CN1877824A CN 1877824 A CN1877824 A CN 1877824A CN A200610094536X A CNA200610094536X A CN A200610094536XA CN 200610094536 A CN200610094536 A CN 200610094536A CN 1877824 A CN1877824 A CN 1877824A
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semiconductor device
mentioned
external connection
connection terminals
semiconductor chip
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CNA200610094536XA
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CN100463147C (zh
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矢野祐司
石原诚治
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Sharp Corp
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Sharp Corp
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Abstract

本发明提供一种半导体器件、层叠式半导体器件和半导体器件的制造方法。半导体器件具有：基板；半导体芯片，通过粘结层搭载于上述基板上；树脂层，覆盖上述半导体芯片的至少一部分；以及外部连接端子，通过配线层与上述基板电连接。外部连接端子从树脂层露出，并且，其露出面和树脂层的表面形成相同的平面。因此，本发明能够提供一种在半导体器件彼此层叠时，即使搭载于上层的半导体器件的连接端子的高度较低，与上层之间的接合的可靠性也会比较高、并且可易于制造的下层的半导体器件和层叠式半导体器件。

Description

半导体器件、层叠式半导体器件和半导体器件的制造方法
技术领域
本发明涉及一种搭载了半导体芯片的半导体器件、层叠多个半导体器件而构成的层叠式半导体器件和半导体器件的制造方法。
背景技术
近年来，随着电子设备不断趋于小型化、轻型化、多功能化，就要求能够实现半导体器件的高密度安装。为了顺应这种要求，例如，在日本国专利申请公开特开平10-135267号公报(公开：1998年5月22日)、日本国专利申请公开特开2004-172157号公报(公开日：2004年6月17日)中，就提出了通过层叠半导体器件来寻求实现半导体器件的高密度安装的方法。
根据现有技术的结构，在层叠半导体器件时，上层半导体器件的连接端子的高度与下层半导体器件的树脂密封的高度之间的关系很重要。
下面，参照图15至17对此进行说明。图15是表示层叠现有技术的两个半导体器件的状态的剖面图。
在图15中，半导体器件200被层叠在半导体器件100上。其中，半导体器件100具有：基板101；被搭载于该基板101上的半导体芯片103；被设置于该基板101的下面的外部连接端子107；以及被设置于该基板101的上面的外部连接端子108。半导体芯片103与基板101通过金属丝104进行电连接。另外，半导体芯片103和金属丝104被树脂层106覆盖。另一方面，基板101上的设有外部连接端子108的区域露出，该区域未被树脂层106覆盖。
在半导体器件200中，不仅仅是形成有半导体芯片103和金属丝104的区域被树脂层106覆盖，而且，基板101上的所有的区域都被树脂层106所覆盖。除此之外，半导体器件200的结构与半导体器件100相同。
例如，在层叠图15所示的半导体器件100和半导体器件200时，如果半导体器件200的外部连接端子107的高度s低于半导体器件100的树脂层106的高度t，那么，就会在半导体器件200的外部连接端子107与半导体器件100的外部连接端子108之间产生空隙，从而导致半导体器件100与半导体器件200不能进行连接。因此，为了连接半导体器件100与半导体器件200，必须满足下述关系，即，“半导体器件200的外部连接端子107的高度s＞半导体器件100的树脂层106的高度t”。
所以，如果降低半导体器件200的外部连接端子107的高度s，也就需要降低半导体器件100的树脂层106的高度t。但是，存在下述的问题，即：要降低半导体器件100的树脂层106的高度t，就要求具备能够使半导体器件100实现薄型化的技术，例如，半导体芯片103的薄型化、金属丝104的低引线环(Loop)化等等，这将增加半导体器件100制造上的技术难度。在层叠图16所示的半导体器件时也会面临同样的问题。
图16是表示层叠现有技术的两个半导体器件的状态的剖面图。在图16中，半导体器件400被层叠在半导体器件300上。在半导体器件300中，外部连接端子108被形成在半导体芯片103上，形成有外部连接端子108的区域露出，该区域未被树脂层106覆盖。除此之外，半导体器件300的结构与上述半导体器件100相同。另外，半导体器件400的结构和上述半导体器件200相同。
图17是表示现有技术的半导体器件制造工艺中的树脂密封工序的剖面图。在制造上述半导体器件300时，在树脂密封工序中会出现下述问题。即：如果不用树脂106对形成有半导体芯片103的外部连接端子108的区域进行覆盖，而只是要覆盖除此之外的区域，例如，在利用转移成型技术(Transfer Molding)进行树脂密封的情况下，如图17所示，模具50将直接按压配线层108，其中，该配线层108被形成在半导体芯片103上并由导电层x和绝缘层y构成。配线层108比较薄，其厚度一般为50um左右，而且，其材质容易变形，所以，配线层108不能完全吸收由模具50所施加的应力。因此，在半导体芯片103上被施加较大的应力，从而有可能对半导体芯片103造成损害。
发明内容
本发明是鉴于上述问题而进行的，其目的之一在于提供一种在半导体器件彼此层叠时，即使搭载于上层的半导体器件的连接端子的高度较低，与上层之间的接合可靠性也会比较高、并且可易于制造的下层的半导体器件和层叠式半导体器件，从而为半导体器件的高密度安装做出贡献。
本发明的其他目的为，在具有外部连接端子从树脂层露出的构造的半导体器件中，用简单的方法来减轻对半导体芯片的损害。
为了解决上述课题，本发明的半导体器件的特征为，具有：基板；半导体芯片，与上述基板电连接；树脂层，覆盖上述半导体芯片的至少一部分；以及第1外部连接端子，与上述基板电连接，其中，上述第1外部连接端子从上述树脂层露出，并且，其露出面和上述树脂层的表面形成相同的平面。
根据上述结构，第1外部连接端子从树脂层露出，并且，其露出面和树脂层的表面形成相同的平面，因此，当在本发明的半导体器件上层叠半导体器件时，即使上层的半导体器件的外部连接端子的高度较低，也能够确保第1外部连接端子和上层的半导体器件的外部连接端子之间的连接。也就是说，如果以窄间距排列上层半导体器件的外部连接端子，外部连接端子的高度就会降低，但即使在这种情况下，也不会发生因被树脂层阻挡而不能到达第1外部连接端子这样的问题。因此，无需为确保连接而将树脂层的高度形成得较低。所以，本发明的半导体器件与上层的半导体器件的接合的可靠性较高，并且，不需要诸如半导体芯片的薄型化、金属丝的低引线环化等半导体器件的薄型化技术，因此，能够简单地制造出本发明的半导体器件。
另外，如果采用上述第1外部连接端子，来取代为了实现与上层半导体器件之间的连接而露出被形成在半导体芯片表面的配线层，那么，即使在利用诸如转移成型技术对半导体器件进行树脂密封时，也能够减轻对半导体芯片的损害。
为了解决上述课题，本发明的半导体器件的制造方法是这样一种半导体器件的制造方法，即，具有：基板；半导体芯片，与上述基板电连接；树脂层，覆盖上述半导体芯片的至少一部分；以及第1外部连接端子，与上述基板电连接，该制造方法的特征在于，包括：封入工序，在该工序中封入树脂，使得第1外部连接端子从上述树脂层露出，并且，其露出面和树脂层的表面形成相同的平面。
根据上述方法，能够制造这样一种半导体器件，即，第1外部连接端子从树脂层露出且其露出面和树脂层的表面形成相同的平面的半导体器件。因此，当在该半导体器件上层叠半导体器件时，即使上层的半导体器件的外部连接端子的高度较低，也能够确保外部连接端子之间的连接。也就是说，如果以窄间距排列上层半导体器件的外部连接端子，外部连接端子的高度就会降低，但即使在这种情况下，也不会发生不能到达由本发明的制造方法所得到的半导体器件的外部连接端子这样的问题。因此，根据本发明的半导体器件的制造方法，无需为确保与上层半导体器件的连接而将树脂层的高度形成得较低。所以，能够简单地制造出与上层半导体器件之间的接合的可靠性较高的半导体器件，而无需诸如半导体芯片的薄型化、金属丝的低引线环化等半导体器件的薄型化技术。
另外，如上所述，如果形成外部连接端子，使其变形后进行树脂密封，来取代为了实现与上层半导体器件之间的连接而露出被形成在半导体芯片表面的配线层，那么，就能够减轻对半导体芯片的损害。
此外，为了解决上述课题，本发明的半导体器件的制造方法的特征在于，上述封入工序包括：按压模具，使得上述第1外部连接端子的表面平坦化的步骤；封入树脂，使得上述已平坦化的第1外部连接端子从树脂层露出且其露出面和树脂层的表面形成相同的平面的步骤。
根据上述结构，通过按压模具使外部连接端子发生变形后封入树脂这样简单的步骤，就能够使外部连接端子从树脂层露出并且其露出面和树脂层的表面形成相同的平面，因此，可以较容易地制造出半导体器件。
本发明的其他目的、特征和优点在以下的描述中会变得十分明了。此外，以下参照附图来明确本发明的优点。
附图说明
图1是表示本发明的实施方式的半导体器件的结构的剖面图。
图2是表示从上方观察图1的半导体器件时的状态的平面图。
图3(a)是表示本发明的实施方式的半导体器件的制造工序的剖面图。
图3(b)是表示本发明的实施方式的半导体器件的制造工序的剖面图。
图3(c)是表示本发明的实施方式的半导体器件的制造工序的剖面图。
图4是表示本发明的实施方式的变形例1的半导体器件的结构的剖面图。
图5是表示本发明的实施方式的变形例2的半导体器件的结构的剖面图。
图6是表示本发明的实施方式的变形例3的半导体器件的结构的剖面图。
图7是表示本发明的实施方式的变形例4的半导体器件的结构的剖面图。
图8是表示本发明的实施方式的变形例5的半导体器件的结构的剖面图。
图9是表示本发明的实施方式的变形例6的半导体器件的结构的剖面图。
图10是表示本发明的实施方式的变形例7的半导体器件的结构的剖面图。
图11是表示本发明的实施方式的变形例8的半导体器件的结构的剖面图。
图12是表示本发明的实施方式的变形例9的半导体器件的结构的剖面图。
图13是表示本发明的实施方式的变形例10的半导体器件的结构的剖面图。
图14是表示本发明的实施方式的层叠式半导体器件的结构的剖面图。
图15是表示层叠现有技术的两个半导体器件的状态的剖面图。
图16是表示层叠现有技术的两个半导体器件的状态的剖面图。
图17是表示现有技术的半导体器件制造工艺中的树脂密封工序的剖面图。
具体实施方式
下面，根据图1至图14来说明本发明的一个实施方式。另外，在下面的说明中，以附图中的上、下为基准，采用“上面”、“下面”、“上方”和“下方”的表述。但这只是为了便于进行说明所使用的表述，其并非用于限定某一面在上(或者，某一面在下)。
图1是表示本实施方式的半导体器件的结构的剖面图。图2是表示从上方观察该半导体器件时的状态的平面图。
如图1所示，本实施方式的半导体器件20具有：基板1；半导体芯片3，通过粘结层2搭载于该基板1上；以及外部连接端子(第2外部连接端子)7，被设置于基板1的下面。基板1和半导体芯片3通过金属丝4进行电连接。
在半导体芯片3的上面形成有配线层9。在配线层9上形成有作为导电性突起物的外部连接端子(第1外部连接端子)8。如图2所示，面阵列(Area-Array)状地排列该外部连接端子8。配线层9和基板1通过金属丝4进行电连接。
半导体器件20被树脂层6密封。具体而言，树脂层6覆盖基板1的上面、粘结层2、半导体芯片3、金属丝4和配线层9。作为树脂层6的材料，例如，可以使用环氧树脂、硅树脂等，但不限于此。
本实施方式的半导体器件20的特征为：外部连接端子8在和树脂层6的表面相同的面上从树脂层6露出。换言之，外部连接端子8的表面(露出面)和树脂层6的表面形成相同的平面。此外，还可以说：外部连接端子8的表面和树脂层6的表面处于相同的高度。
这里，“相同的面”并非是必须完全相同的面，为了获得下述的效果，只要是大致相同的面即可。
使外部连接端子8的表面如上所述地从树脂层6露出，从而在半导体器件8的表面形成外部连接端子8。因此，在半导体器件20上层叠了半导体器件的情况下，即使上层的半导体器件的外部连接端子的高度较低，也能够确保半导体器件20的外部连接端子8和上层的半导体器件的外部连接端子之间的连接。也就是说，即使是为了进行更高密度的集成而将上层的半导体器件的外部连接端子的高度形成得较低，也不会发生因被树脂层6阻挡而不能到达外部连接端子8这样的问题。因此，无需为确保连接而将树脂层6的高度形成得较低，所以，本实施方式的半导体器件20与上层的半导体器件的接合的可靠性较高，并且，不需要诸如半导体芯片3的薄型化、金属丝4的低引线环化等半导体器件20的薄型化技术，因此，能够简单地制造出本实施方式的半导体器件20。
另外，根据本实施方式的半导体器件20，形成于半导体芯片3的表面的配线层9未从树脂层6露出(被树脂层6覆盖)。因此，在进行树脂密封时，无需借助于模具来堵塞被形成于半导体芯片3的表面的配线层9。所以，可以减少在树脂密封时对半导体芯片的损害。
此外，在本实施方式的半导体器件20中，外部连接端子8通过配线层9与基板1进行电连接，因此，能够容易地确保半导体器件20与上层的半导体器件之间的电连接。
另外，在本实施方式的半导体器件20中，配线层9被形成于半导体芯片3的上面，所以，可望实现半导体器件20的薄型化。
接着，说明本实施方式的半导体器件20的制造方法。图3(a)～3(c)是表示本实施方式的半导体器件20的制造工序的剖面图。
首先，如图3(a)所示，在基板1上，通过粘结层2来搭载预先形成了配线层9和外部连接端子8的半导体芯片3。另外，也可以在基板1上搭载预先形成了配线层9的半导体芯片3之后搭载外部连接端子8。其后，通过金属丝4对半导体芯片3和基板1进行电连接，同样地，也通过金属丝4对配线层9和基板1进行电连接。
接着，封入树脂，使得外部连接端子8从树脂层6露出，并且，其露出面和树脂层6的表面形成相同的平面(封入工序)。这里，如图3(b)所示，按压模具50，以使得外部连接端子8发生变形。即，按压模具50，从而使外部连接端子8的上面变得平坦，其中，模具50与外部连接端子8接触的面是平坦的面。为了使该步骤易于实施，外部连接端子8优选由易变形的材料构成。作为易变形的材料，例如，可以举出焊锡、铜等。
在外部连接端子8的材料采用焊锡的情况下，当模具温度超过焊锡的熔点时，焊锡就会在封入树脂时熔化并流动。树脂密封时的模具温度一般在150℃～200℃之间。因此，优选采用熔点高于或等于200℃的焊锡。
然后，如图3(c)所示，封入树脂，使得外部连接端子8从树脂层6露出，并且，其露出面和树脂层6的表面形成相同的平面。
最后，在基板1的下面形成外部连接端子7。另外，关于外部连接端子7，并不限于在树脂密封之后才形成，也可以在树脂密封之前形成。
如上所述，本实施方式的半导体器件20的制造方法包括封入工序，该封入工序是利用模具50来实施的。根据上述制造方法，能够较容易地使半导体器件20的外部连接端子8从树脂层露出且其露出面和树脂层6的表面形成相同的平面，因此，可以较容易地制造出半导体器件20。另外，在上述的说明中，采用了模具50。但是，如果外部连接端子8从树脂层6露出(即，如果在半导体器件20的表面形成有外部连接端子8)，上述制造方法并不限于采用模具50。
以下，对本实施方式的半导体器件20的变形例进行说明。另外，对具有与上述构件相同的功能的构件赋予相同的标号，并省略其说明。
(变形例1)
图4是表示变形例1的半导体器件20a的结构的剖面图。如图4所示，在半导体器件20a中，取代金属丝4的连接，利用倒装芯片连接(Flip-Chip Bond)技术对半导体芯片3和基板1进行连接，该倒装芯片连接是通过凸缘(Bump)10来实现的。
除此之外，半导体器件20a具有与上述半导体器件20相同的结构。
如上所述，在本变形例的半导体器件20a中，通过采用倒装芯片连接技术，将半导体芯片3更高密度地安装至基板1。
除了利用倒装芯片连接技术对半导体芯片3和基板1进行连接这一点之外，能够通过与上述半导体器件20的制造方法相同的方法来制造本变形例的半导体器件20a。
(变形例2)
图5是表示变形例2的半导体器件20b的结构的剖面图。在上述的半导体器件20、半导体器件20a中，配线层9被直接形成在半导体芯片3上。但是，在半导体器件20b中，如图5所示，配线层9被形成于支持体11上，并通过粘结层12搭载于半导体芯片3上。在支持体11上形成配线层9，并且，通过粘结层12将配线层9搭载于半导体芯片3上，从而可借助于支持体11和粘结层12来减轻被施加在半导体芯片3上的应力，因此，可进一步减少对半导体芯片3的损害。支持体11和粘结层12为绝缘体，如果采用弹性率较低的材料，就能够更好地吸收应力，从而进一步减小对半导体芯片3的损害。
支持体11、以及支持体11上的配线层9的形成区域可以具有比半导体芯片更大的面积。换言之，配线层9的尺寸可以大于半导体芯片3的尺寸。如果在比半导体芯片3更大的区域中形成配线层9，即使上层半导体器件的外部连接端子排列面积比下层半导体芯片要大，也能够对上层半导体器件和下层半导体器件进行层叠。
半导体芯片3和基板1通过金属丝4来连接。另一方面，配线层9和基板1通过金属丝5来连接。
在半导体芯片3和粘结层12之间，没有足够的用于设置金属丝4的空间，因此，对金属丝4进行设置以使得其通过粘结层12的内部。换言之，金属丝4被包入粘结层12。由于金属丝4被包入粘结层12，所以，具有能够抑制树脂密封时的金属丝变形这样的优点。
除此之外，半导体器件20b具有与上述半导体器件20相同的结构。因此，作为形成、变形外部连接端子8、进行树脂密封的方法，可以采用与上述半导体器件20的制造方法相同的方法。
(变形例3)
图6是表示变形例3的半导体器件20c的结构的剖面图。半导体器件20c的结构和变形例2的半导体器件20b大致相同，两者的不同之处为，如图6所示，在半导体器件20c中，隔层(Spacer Layer)13通过粘结层18设置在半导体芯片3上。
通过设置隔层13，从而能够在半导体芯片3与粘结层12之间确保足够的用于设置金属丝4的空间。因此，在本变形例的半导体器件20c中，金属丝4不通过粘结层12的内部，从而提高半导体芯片3和金属丝4之间的连接的可靠性。进而，支持体11和隔层13可采用导电性材料，从而提高散热性。
关于本变形例的半导体器件20c，作为形成、变形外部连接端子8、进行树脂密封的方法，也可以采用与上述半导体器件20的制造方法相同的方法。
(变形例4)
图7是表示变形例4的半导体器件20d的结构的剖面图。如图7所示，本变形例的半导体器件20d与变形例2的半导体器件20b的不同之处为：在半导体器件20d中，利用倒装芯片连接技术对半导体芯片3和基板1进行连接，该倒装芯片连接是通过凸缘10来实现的。除此之外，和变形例2的半导体器件20b相同。
如上所述，在本变形例的半导体器件20d中，通过采用倒装芯片连接技术，将半导体芯片3更高密度地安装至基板1。即，无需象变形例2那样地使粘结层12变厚，或者，象变形例3那样地设置隔层13，从而，能够实现半导体器件的薄型化。
关于本变形例的半导体器件20d，除了利用倒装芯片连接技术对半导体芯片3和基板1进行连接这一点之外，能够通过与上述半导体器件20的制造方法相同的方法来制造本变形例的半导体器件20d。
(变形例5)
图8是表示变形例5的半导体器件20e的结构的剖面图。在上述半导体器件20、半导体器件20a、半导体器件20b、半导体器件20c和半导体器件20d中，在半导体芯片3上，间隔着配线层9地设置外部连接端子8。对此，在半导体器件20e中，如图8所示，外部连接端子8被直接设置于基板1上并进行电连接。
除此之外，半导体器件20e具有与上述半导体器件20相同的结构。
如上所述，在本变形例的半导体器件20e中，外部连接端子8不是被形成在半导体芯片3的上方，而是形成在基板1上。因此，在进行树脂密封时，由模具施加给外部连接端子8的应力不会到达半导体芯片3。所以，能够进一步减小对半导体芯片3的损害。此外，还具有能够降低半导体器件的高度这样的优点。
关于本变形例的半导体器件20e，作为形成、变形外部连接端子8、进行树脂密封的方法，也可以采用与上述半导体器件20的制造方法相同的方法。
(变形例6)
图9是表示变形例6的半导体器件20f的结构的剖面图。在半导体器件20f中，与变形例5的半导体器件20e同样地，外部连接端子8被直接设置于基板1上并进行电连接。
如图9所示，半导体器件20f与半导体器件20e的不同之处为，在半导体器件20f中，(1)半导体芯片3被设置于基板1的开口部16；(2)层叠了2个半导体芯片3，分别通过金属丝4、配线层9与基板1进行电连接。
除此之外，半导体器件20f具有与变形例5的半导体器件20e相同的结构。
如上所述，在本变形例的半导体器件20f中，半导体芯片3被设置于基板1的开口部16，因此，与在基板1上设置半导体芯片3的情况相比较而言，本变形例的半导体器件20f能够更高密度地安装半导体芯片3。
另外，在本变形例中，层叠了2个半导体芯片3，但是，所搭载的半导体芯片3的数量并不限于2个。在搭载1个半导体芯片3的情况下，较之于在基板1上设置半导体芯片3的情况，能够实现半导体器件的薄型化，因此，可实现高密度化。此外，在层叠3个或3个以上的半导体芯片3的情况下，较之于在基板1上设置相同数量的半导体芯片3的情况，能够更高密度地安装半导体芯片3。
关于本变形例的半导体器件20f，作为形成、变形外部连接端子8、进行树脂密封的方法，也可以采用与上述半导体器件20的制造方法相同的方法。
(变形例7)
图10是表示变形例7的半导体器件20g的结构的剖面图。在半导体器件20g中，与变形例5的半导体器件20e同样地，外部连接端子8被直接设置于基板1上并进行电连接。
如图10所示，半导体器件20g与半导体器件20e的不同之处为，在半导体器件20g中，(1)半导体芯片3被设置于基板1的凹部17；(2)层叠了2个半导体芯片3，分别通过金属丝4与基板1进行电连接。在本变形例中，下层的半导体芯片3和基板1不通过配线层9而直接由金属丝4进行电连接，但也可以通过配线层9。此外，上层的半导体芯片3和基板1通过配线层9由金属丝4进行电连接，但也可以不通过配线层9而直接进行电连接。
除此之外，半导体器件20g具有与变形例5的半导体器件20e相同的结构。
如上所述，在本变形例的半导体器件20g中，半导体芯片3被设置于基板1的凹部17，因此，与在凹部17之外的基板1上设置半导体芯片3的情况相比较而言，本变形例的半导体器件20g能够更高密度地安装半导体芯片3。
此外，较之于在基板1上设置开口部16的变形例6的结构，在基板1上设置凹部17的结构的半导体器件的机械强度降低的幅度比较小。
关于本变形例的半导体器件20g，作为形成、变形外部连接端子8、进行树脂密封的方法，也可以采用与上述半导体器件20的制造方法相同的方法。
(变形例8)
图11是表示变形例8的半导体器件20h的结构的剖面图。如图11所示，在半导体器件20h中，树脂层6的表面不平坦，设有外部连接端子8的区域14的树脂层6的表面要比其他区域、即区域15的树脂层6的表面低(也就是说，向基板1侧凹陷)。除此之外，半导体器件20h的结构和半导体器件20相同。
如上所述，通过使设有外部连接端子8的区域的树脂层6的表面凹陷，能够在半导体器件20h上层叠半导体器件时将上层的半导体器件的外部连接端子的一部分收容在上述凹陷部分，从而可以实现更高密度的安装。
关于本变形例的半导体器件20h，作为形成、变形外部连接端子8、进行树脂密封的方法，也可以采用与上述半导体器件20的制造方法相同的方法。但是，作为模具50，例如，采用如图17所示的模具，即，与树脂层6的表面凹陷对应的部分突出的模具。
(变形例9)
图12是表示变形例9的半导体器件20i的结构的剖面图。如图12所示，在半导体器件20i中，与变形例8的半导体器件20h同样地，设有外部连接端子8的区域14的树脂层6的表面也要比其他区域、即区域15的树脂层6的表面低(也就是说，向基板1侧凹陷)。
在半导体器件20i中，外部连接端子8直接设置于基板1上并进行电连接。由此，在半导体器件20h中，在设有外部连接端子8的区域14的两侧设置其他区域、即区域15，但是，在半导体器件20i中，设有外部连接端子8的区域14被设置在其他区域、即区域15的两侧。
除此之外，半导体器件20i具有与变形例8的半导体器件20h相同的结构。
如上所述，外部连接端子8不是形成在半导体芯片3的上方，而是形成在基板1上，由此，在进行树脂密封时，可以防止由模具施加给外部连接端子8的应力被施加到半导体芯片3，所以，能够进一步减小对半导体芯片3的损害。
此外，通过使设有外部连接端子8的区域的树脂层6的表面凹陷，能够在半导体器件20i上层叠半导体器件时将上层的半导体器件的外部连接端子的一部分收容在上述凹陷部分，从而可以实现更高密度的安装。
关于本变形例的半导体器件20i，作为形成、变形外部连接端子8、进行树脂密封的方法，也可以采用与上述半导体器件20的制造方法相同的方法。但是，作为模具50，采用与树脂层6的表面凹陷对应的部分突出的模具。
(变形例10)
图13是表示变形例10的半导体器件20j的结构的剖面图。如图13所示，半导体器件20j具有：基板1；3个半导体芯片3a～3c，被层叠于上述基板1上；以及外部连接端子(第2外部连接端子)7，被设置于上述基板1的下面。
下层的半导体芯片3a，通过粘结层设置于基板1上，通过倒装芯片连接来实现与基板1的电连接，该倒装芯片连接是借助于凸缘10来实现的。
中间层的半导体芯片3b，通过粘结层设置于下层的半导体芯片3a上，通过金属丝4来实现与基板1的电连接。连接中间层的半导体芯片3b和基板1的金属丝4通过被设置在中间层的半导体芯片3b上的粘结层的内部。
上层的半导体芯片3c，通过粘结层设置于中间层的半导体芯片3b上，通过金属丝4来实现与基板1的电连接。隔层13通过粘结层设置于上层的半导体芯片3c上，所以，连接上层的半导体芯片3c和基板1的金属丝4不通过粘结层的内部。
支持体11通过粘结层设置于隔层13上。在该支持体11上，间隔着配线层9地形成有作为导电性突起物的外部连接端子(第1外部连接端子)8。与图2所示同样地，面阵列状地排列该外部连接端子8。配线层9和基板1通过金属丝5来实现电连接。
另外，半导体器件20j被树脂层6密封。具体而言，树脂层6覆盖了在基板1的上面侧所形成的构件中除外部连接端子8之外的所有构件。
在半导体器件20j中，与上述半导体器件20同样地，外部连接端子8在和树脂层6的表面相同的面上从树脂层6露出。换言之，外部连接端子8的表面和树脂层6的表面形成相同的平面。此外，还可以说：外部连接端子8的表面和树脂层6的表面处于相同的高度。这里，“和树脂层6的表面相同的面”并非必须完全相同，只要是大致相同的面即可。
如上所述，在本变形例的半导体器件20j中，搭载了3个半导体芯片3a～3c，因此，能够进一步实现更高密度的安装。
另外，在本变形例中，层叠了3个半导体芯片3，但是，所层叠的半导体芯片3的数量并不限于3个，可以是2个，也可以是4个或4个以上。此外，关于半导体芯片3的安装方式，对此并不作特别的限定。
关于本变形例的半导体器件20j，作为形成、变形外部连接端子8、进行树脂密封的方法，也可以采用与上述半导体器件20的制造方法相同的方法。
接着，说明层叠式半导体器件。图14是表示本实施方式的层叠式半导体器件40的结构的剖面图。
如图14所示，在层叠式半导体器件40中，在上述半导体器件20上层叠上述半导体器件20i，进而，在上述半导体器件20i上层叠另一半导体器件30。
半导体器件20的外部连接端子8与半导体器件20i的外部连接端子7接合，由此，半导体器件20和半导体器件20i实现电连接。
半导体器件30的下面具有外部连接端子7。半导体器件20i的外部连接端子8与半导体器件30的外部连接端子7接合，由此，半导体器件20i和半导体器件30实现电连接。
如上所述，半导体器件20的外部连接端子8从树脂层6露出，并且，其露出面和树脂层6的表面形成相同的平面。因此，即使是上层的半导体器件20i的外部连接端子7的高度较低，也能够确保半导体器件20的外部连接端子8与半导体器件20i的外部连接端子7之间的连接。同样地，半导体器件20i的外部连接端子8也从树脂层6露出，并且，其露出面和树脂层6的表面形成相同的平面。因此，即使是上层的半导体器件30的外部连接端子7的高度较低，也能够确保半导体器件20i的外部连接端子8与半导体器件30的外部连接端子7之间的连接。
因此，如果按照上述那样层叠半导体器件20、20i、30并使之相互电连接从而构成层叠式半导体器件40，就能够降低外部连接端子7的高度而不会损害连接的稳定性，所以，可以实现半导体器件的高密度化。
另外，在上述的说明中，所层叠的半导体器件的数量为3个，但并不限于此，可以是2个，也可以是4个或4个以上。
此外，在上述的说明中，层叠了半导体器件20、20i、30。但是，可以在选自半导体器件20、20a～20j的1个或多个半导体器件上层叠半导体器件30，也可以使选自半导体器件20、20a～20j的多个半导体器件彼此层叠。
本发明并不限于上述实施方式，可以在权利要求所示的范围内进行各种变更。即，通过组合在权利要求所示范围内进行了适当变更的技术手段所得到的实施方式，也被包括在本发明的技术范围内。
如上所述，本发明的半导体器件的特征在于，具有：基板；半导体芯片，与上述基板电连接；树脂层，覆盖上述半导体芯片的至少一部分；以及第1外部连接端子，与上述基板电连接，上述第1外部连接端子从上述树脂层露出，并且，其露出面和上述树脂层的表面形成相同的平面。
根据上述结构，第1外部连接端子从树脂层露出，并且，其露出面和树脂层的表面形成相同的平面，因此，当在本发明的半导体器件上层叠半导体器件时，即使上层的半导体器件的外部连接端子的高度较低，也能够确保第1外部连接端子和上层的半导体器件的外部连接端子之间的连接。也就是说，如果以窄间距排列上层半导体器件的外部连接端子，外部连接端子的高度就会降低，但即使在这种情况下，也不会发生因被树脂层阻挡而不能到达第1外部连接端子这样的问题。因此，无需为确保连接而将树脂层的高度形成得较低。所以，本发明的半导体器件与上层的半导体器件的连接的可靠性较高，并且，不需要诸如半导体芯片的薄型化、金属丝的低引线环化等半导体器件的薄型化技术，因此，能够简单地制造出本发明的半导体器件。
另外，如果采用上述第1外部连接端子，来取代为了实现与上层半导体器件之间的连接而露出被形成在半导体芯片表面的配线层，即使在借助于诸如转移成型技术对半导体器件进行树脂密封时，也能够减轻对半导体芯片的损害。
在本发明的半导体器件中，上述第1外部连接端子可以通过配线层与上述基板电连接。
如上所述，使第1外部连接端子通过配线层与基板电连接，由此，能够容易地确保本发明的半导体器件与上层的半导体器件之间的电连接。
在本发明的半导体器件中，上述配线层可以形成在上述半导体芯片的上述第1外部连接端子侧的面上。
通过直接将配线层形成在半导体芯片的第1外部连接端子侧的面上，较之于后述的间隔着支持体、粘结层的构造，可望实现半导体器件的薄型化。
另外，在本发明的半导体器件中，上述配线层可以形成在支持体上，并搭载于上述半导体芯片上。
在支持体上形成配线层，通过粘结层将其搭载于上述半导体芯片，由此，可以借助于支持体和粘结层来减轻被施加在半导体芯片上的应力，因此，能够进一步减轻对半导体芯片的损害。
此外，在本发明的半导体器件中，设有上述配线层的区域的面积可以比半导体芯片的面积大。换言之，上述配线层的尺寸可以大于上述半导体芯片的尺寸。
如上所述，在比半导体芯片更大的区域中形成配线层，由此，即使上层半导体器件的外部连接端子排列面积比下层半导体芯片要大，也能够对上层半导体器件和下层半导体器件进行层叠。
此外，在本发明的半导体器件中，上述第1外部连接端子可以形成在基板上。
第1外部连接端子不是被形成在半导体芯片的上方，而是形成在基板上，由此，在进行树脂密封时，能够防止由模具施加给第1外部连接端子的应力被施加到半导体芯片，所以，能够进一步减轻对半导体芯片的损害。此外，还具有能够降低半导体器件的高度这样的优点。
另外，在本发明的半导体器件中，上述半导体芯片可以被设置于上述基板的开口部。
如上所述，半导体芯片被设置于基板的开口部，由此，与在基板上设置半导体芯片的情况相比较而言，能够更高密度地安装半导体芯片。
此外，在本发明的半导体器件中，上述半导体芯片可以被设置于上述基板的凹部。
如上所述，半导体芯片被设置于基板的凹部，由此，与在基板上设置半导体芯片的情况相比较而言，能够更高密度地安装半导体芯片。
另外，在本发明的半导体器件中，相对于其他区域的树脂层的表面，设有上述第1外部连接端子的区域的树脂层的表面向基板侧凹陷。换言之，排列了上述第1外部连接端子的区域的树脂面可以比其他区域的树脂面低。
如上所述，通过使设有第1外部连接端子的区域的树脂层的表面凹陷，能够在本发明的半导体器件上层叠半导体器件时将上层的半导体器件的外部连接端子的一部分收容在上述凹陷部分，从而可以进一步实现高密度化。
此外，在本发明的半导体器件中，上述第1外部连接端子可以由焊锡构成。
通过由容易发生变形的材料焊锡构成第1外部连接端子，能够容易地使第1外部连接端子发生变形，从而使其在和树脂层的表面相同的面上更容易从树脂层露出。
另外，在本发明的半导体器件中，上述焊锡的熔点温度优选高于或等于200℃。
由于树脂密封时的模具温度一般在150℃～200℃之间，因此，如果上述焊锡的熔点温度高于或等于200℃，就可以减小当模具温度超过焊锡的熔点时焊锡熔化并流动的危险性。
此外，在本发明的半导体器件中，上述第1外部连接端子可以由铜构成。
通过由容易发生变形的材料铜来构成第1外部连接端子，能够容易地使第1外部连接端子发生变形，从而使其在和树脂层的表面相同的面上更容易从树脂层露出。
另外，本发明的半导体器件可以构成为：具有多个上述半导体芯片，各半导体芯片与基板电连接。
通过在树脂层内搭载多个半导体芯片，可望进一步实现高密度化。
此外，如上所述，本发明的层叠式半导体器件的特征在于：在上述任一半导体器件上，层叠进一步具有第2外部连接端子的上述任一半导体器件，这些半导体器件借助于第1外部连接端子和第2外部连接端子的接合来实现电连接。
根据上述结构，借助于第1外部连接端子和第2外部连接端子的接合，使半导体器件彼此电连接，由此，能够进一步实现高密度化。
另外，如上所述，本发明的层叠式半导体器件的特征在于：在上述任一半导体器件上，层叠具有第2外部连接端子的其他半导体器件，这些半导体器件借助于第1外部连接端子和第2外部连接端子的接合来实现电连接。
根据上述结构，借助于第1外部连接端子和第2外部连接端子的接合，使半导体器件彼此电连接，由此，能够进一步实现高密度化。
如上所述，本发明的半导体器件的制造方法是这样一种半导体器件的制造方法，即，具有：基板；半导体芯片，与上述基板电连接；树脂层，覆盖上述半导体芯片的至少一部分；以及第1外部连接端子，与上述基板电连接，该方法的特征在于，包括：封入工序，在该工序中封入树脂，使得第1外部连接端子从上述树脂层露出且其露出面和树脂层的表面形成相同的平面。
根据上述方法，能够制造这样一种半导体器件，即，第1外部连接端子从树脂层露出且其露出面和树脂层的表面形成相同的平面的半导体器件。因此，当在该半导体器件上层叠半导体器件时，即使上层的半导体器件的外部连接端子的高度较低，也能够确保外部连接端子之间的连接。也就是说，如果以窄间距排列上层半导体器件的外部连接端子，外部连接端子的高度就会降低，但即使在这种情况下，也不会发生不能到达由本发明的制造方法所得到的半导体器件的外部连接端子这样的问题。因此，根据本发明的半导体器件的制造方法，无需为确保与上层半导体器件的连接而将树脂层的高度形成得较低。所以，能够简单地制造出与上层半导体器件之间的连接的可靠性较高的半导体器件，而无需诸如半导体芯片的薄型化、金属丝的低引线环化等半导体器件的薄型化技术。
另外，如上所述，如果形成外部连接端子，使其变形后进行树脂密封，来取代为了实现与上层半导体器件之间的连接而露出被形成在半导体芯片表面的配线层，那么，就能够减轻对半导体芯片的损害。
此外，如上所述，本发明的半导体器件的制造方法的特征在于，上述封入工序包括：按压模具，使得上述第1外部连接端子的表面平坦化的步骤；封入树脂，使得上述已平坦化的第1外部连接端子从树脂层露出且其露出面和树脂层的表面形成相同的平面的步骤。
根据上述结构，通过按压模具使外部连接端子发生变形后封入树脂这样简单的步骤，能够使外部连接端子从树脂层露出且其露出面和树脂层的表面形成相同的平面，因此，可以较容易地制造出半导体器件。
另外，本发明的半导体器件的制造方法还可以包括下述工序，即，对上述模具进行加热，使其温度低于或等于上述外部连接端子的熔点温度。
通过对上述模具进行加热，使其温度低于或等于上述外部连接端子的熔点温度，就可以减小当模具温度超过焊锡的熔点时焊锡熔化并流动的危险性。
如上所述，根据本发明的半导体器件，第1外部连接端子从树脂层露出，并且，其露出面和树脂层的表面形成相同的平面，因此，当在本发明的半导体器件上层叠半导体器件时，即使上层的半导体器件的外部连接端子的高度较低，也能够确保第1外部连接端子和上层的半导体器件的外部连接端子之间的连接。所以，无需为确保连接而将树脂层的高度形成得较低。基于此，本发明的半导体器件可以取得这样的效果，即：与上层的半导体器件的连接的可靠性较高，并且，无需诸如半导体芯片的薄型化、金属丝的低引线环化等半导体器件的薄型化技术就能够简单地制造出本发明的半导体器件。
另外，如果采用上述第1外部连接端子，来取代为了实现与上层半导体器件之间的连接而露出被形成在半导体芯片表面的配线层，就能够取得这样的效果，即：即使在借助于诸如转移成型技术进行树脂密封时，也能够减轻对半导体芯片的损害。
以上，对本发明进行了详细的说明，上述具体实施方式或实施例仅仅是揭示本发明的技术内容的示例，本发明并不限于上述具体示例，不应对本发明进行狭义的解释，可在本发明的精神和权利要求的范围内进行各种变更来实施之。

Claims (18)

1.一种半导体器件(20)，具有：基板(1)；半导体芯片(3)，与上述基板(1)电连接；树脂层(6)，覆盖上述半导体芯片(3)的至少一部分；以及第1外部连接端子，与上述基板(1)电连接，其特征在于：
上述第1外部连接端子从上述树脂层(6)露出，并且，其露出面和上述树脂层(6)的表面形成相同的平面。
2.根据权利要求1所述的半导体器件(20)，其特征在于：
上述第1外部连接端子通过配线层(9)与上述基板(1)电连接。
3.根据权利要求2所述的半导体器件(20)，其特征在于：
上述配线层(9)形成在上述半导体芯片(3)的上述第1外部连接端子侧的面上。
4.根据权利要求2所述的半导体器件(20)，其特征在于：
上述配线层(9)形成在支持体(11)上，并搭载于上述半导体芯片(3)上。
5.根据权利要求4所述的半导体器件(20)，其特征在于：
设有上述配线层(9)的区域的面积比上述半导体芯片(3)的面积大。
6.根据权利要求1所述的半导体器件(20)，其特征在于：
上述第1外部连接端子形成在上述基板(1)上。
7.根据权利要求6所述的半导体器件(20)，其特征在于：
上述半导体芯片(3)被设置于上述基板(1)的开口部(16)。
8.根据权利要求6所述的半导体器件(20)，其特征在于：
上述半导体芯片(3)被设置于上述基板(1)的凹部(17)。
9.根据权利要求1至8中的任一项所述的半导体器件(20)，其特征在于：
设有上述第1外部连接端子的区域的上述树脂层(6)的表面相对于其他区域的树脂层(6)的表面向基板侧(1)凹陷。
10.根据权利要求1至8中的任一项所述的半导体器件(20)，其特征在于：
上述第1外部连接端子由焊锡构成。
11.根据权利要求10所述的半导体器件(20)，其特征在于：
上述焊锡的熔点高于或等于200℃。
12.根据权利要求1至8中的任一项所述的半导体器件(20)，其特征在于：
上述第1外部连接端子由铜构成。
13.根据权利要求1至8中的任一项所述的半导体器件(20)，其特征在于：
具有多个上述半导体芯片(3)，各半导体芯片(3)与上述基板(1)电连接。
14.一种层叠式半导体器件(40)，其特征在于：
在权利要求1所述的半导体器件(20)上，层叠还具有第2外部连接端子的半导体器件；
上述层叠的半导体器件(20)和还具有第2外部连接端子的半导体器件，借助于第1外部连接端子与第2外部连接端子的接合而相互电连接。
15.一种层叠式半导体器件(40)，其特征在于：
在权利要求1所述的半导体器件(20)上，层叠具有第2外部连接端子的其他的半导体器件；
上述层叠的半导体器件(20)和具有第2外部连接端子的其他的半导体器件，借助于第1外部连接端子与第2外部连接端子的接合而相互电连接。
16.一种半导体器件(20)的制造方法，该半导体器件(20)具有：基板(1)；半导体芯片(3)，与上述基板(1)电连接；树脂层(6)，覆盖上述半导体芯片(3)的至少一部分；以及第1外部连接端子，与上述基板(1)电连接，该制造方法的特征在于，包括：
封入工序，在该工序中封入树脂，使上述第1外部连接端子从上述树脂层(6)露出，并且，其露出面和上述树脂层(6)的表面形成相同的平面。
17.根据权利要求16所述的半导体器件(20)的制造方法，其特征在于，上述封入工序包括：
按压模具(50)，使得上述第1外部连接端子的表面平坦化的步骤；以及
封入树脂，使得上述已平坦化的第1外部连接端子从上述树脂层(6)露出，并且，其露出面和上述树脂层(6)的表面形成相同的平面的步骤。
18.根据权利要求17所述的半导体器件(20)的制造方法，其特征在于，还包括：
加热工序，对上述模具(50)进行加热，使其温度低于或等于上述第1外部连接端子的熔点。
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KR100878169B1 (ko) 2009-01-12
CN100463147C (zh) 2009-02-18
TW200721399A (en) 2007-06-01
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US20060278970A1 (en) 2006-12-14
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