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KR100770934B1 - 반도체 패키지와 그를 이용한 반도체 시스템 패키지 - Google Patents

반도체 패키지와 그를 이용한 반도체 시스템 패키지 Download PDF

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Publication number
KR100770934B1
KR100770934B1 KR1020060093433A KR20060093433A KR100770934B1 KR 100770934 B1 KR100770934 B1 KR 100770934B1 KR 1020060093433 A KR1020060093433 A KR 1020060093433A KR 20060093433 A KR20060093433 A KR 20060093433A KR 100770934 B1 KR100770934 B1 KR 100770934B1
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South Korea
Prior art keywords
semiconductor
package
printed circuit
circuit board
semiconductor die
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KR1020060093433A
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English (en)
Inventor
서호성
조시연
이영민
김상현
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삼성전자주식회사
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Priority to KR1020060093433A priority Critical patent/KR100770934B1/ko
Priority to US11/894,338 priority patent/US7902652B2/en
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Publication of KR100770934B1 publication Critical patent/KR100770934B1/ko
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Abstract

본 발명의 제1 측면에 따른 반도체 패키지는 인쇄회로 기판과; 상기 인쇄회로 기판 상에 안착되며 그 상면에 도전 포스트들이 형성된 반도체 다이와; 상기 인쇄회로 기판 상에 상기 반도체 다이를 덮도록 형성된 몰딩을 포함하며, 상기 도전 포스트들은 일면이 상기 몰딩의 상부 면 상에 노출된다.
본 발명의 제2 측면에 따른 반도체 시스템 패키지는 도전 포스트들이 형성된 반도체 다이와, 상기 도전 포스트들의 상면이 노출되도록 형성된 몰딩을 포함하는 제1 반도체 패키지와; 상기 제1 반도체 패키지 상에 상기 도전 포스트들과 전기적으로 연결되게 안착되는 제2 반도체 패키지를 포함한다.
패키지 온 패키지, 반도체 다이, 와이어 본딩

Description

반도체 패키지와 그를 이용한 반도체 시스템 패키지{SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR SYSTEM IN PACKAGE}
도 1은 종래의 패키지 온 패키지 형태로 집적된 반도체 시스템 패키지의 단면을 도시한 도면,
도 2a는 본 발명의 제1 실시 예에 따른 반도체 시스템 패키지의 단면을 도시한 도면,
도 2b는 도 2a에 도시된 반도체 다이의 단면을 도시한 도면,
도 3a 내지 도 3d는 도 2a 도시된 반도체 시스템 패키지의 제조 단계별 단면을 도시한 도면,
도 4는 본 발명의 제2 실시 예에 따른 반도체 시스템 패키지의 단면을 도시한 도면.
본 발명은 반도체 다이를 실장하는 반도체 패키지에 관한 발명으로서, 특히 반도체 패키지들이 전기적으로 연결된 시스템 패키지에 관한 발명이다.
시스템 패키지(System In Package; SIP)는 반도체 다이(Semiconductor die)와 같은 고밀도 집적 회로들을 모듈화하기 위한 패키지로서, 실장 공간의 확보가 어려운 휴대용 단말기 등에 응용되고 있으나, 근래에는 다양하게 응용되고 있다.
상술한 시스템 패키지는 크게 반도체 다이를 적층하여 와이어 본딩으로 접속하는 와이어 본딩(Wire bonding) 형과, 박형화된 패키지를 적층하는 패키지 온 패키지(Package on package) 형과, 실리콘 칩에 관통 비아(Via)를 형성해서 접속하는 관통 비아형과, 웨이퍼 레벨(Wafer level)의 CSP(Chip size package)를 수지 기판 내부에 내장하는 기판 내장형 등으로 구분할 수 있다.
상술한 시스템 패키지는 메모리의 역할을 수행할 수 있는 반도체 다이와 로직(Logic)의 역할을 수행할 수 있는 반도체 다이 또는 메모리의 기능을 수행할 수 있는 반도체 다이와 마이콘(Micon)과 같이 메모리의 조합이 주체인 구성에 사용되고 있다. 근래의 시스템 패키지는 다양한 기능의 반도체 다이의 구성에도 사용되고 있다.
도 1은 종래 패키지 온 패키지 형태의 시스템 패키지의 단면 구조를 도시한 도면이다. 도 1을 참조하면, 종래의 시스템 패키지(100)는 제1 및 제2 반도체 패키지(110,120)를 구비하며, 상기 제1 및 제2 반도체 패키지(110,120)는 상하로 적층된 구조로서, 상기 제1 및 제2 반도체 패키지(110,120) 사이에 개재된 복수의 솔더 볼들(130)에 의해 연결된 구조를 갖는다.
상기 제1 및 제2 패키지(110,120)는 다층 적층 구조의 인쇄회로 기판(111,121)과, 상기 인쇄회로 기판(111,121) 상에 위치된 반도체 다이(112,122) 와, 상기 반도체 다이(112,122)와 인쇄회로 기판(111,121)을 전기적으로 연결시키기 위한 와이어(114,124)와, 상기 인쇄회로 기판(111,121) 상에 상기 반도체 다이들(112,122)을 덮도록 형성된 몰딩(molding; 113,123)을 포함한다.
상기 각 인쇄회로 기판(111,121)은 그 상면에 각각의 전기 패턴들이 형성되고 상기 각 반도체 다이(112,122)와 전기적 패턴들 중 일부가 와이어 본딩(wire bonding)에 의해 전기적으로 연결된다. 와이어 본딩 되지 않은 나머지 전기 패턴들 중 일부는 상기 솔더 볼들(130)에 의해서 타 측의 패키지(110 또는 120)와 전기적으로 연결된다.
그러나, 패키지 온 패키지(Package on Package) 형태의 시스템 패키지(system in package)는 제1 및 제2 반도체 패키지 사이의 전기적 연결이 많아질 경우에 삽입되는 솔더 볼의 공간이 많이 요구되는 문제가 있다.
또한, 종래의 시스템 패키지는 각 패키지의 크기에 비해서 접촉되는 면적이 작으므로, 기계적 강도 및 신뢰성이 저하되는 문제가 있다.
본 발명은 상술한 종래 기술의 문제를 해결하기 위한 발명으로서, 부피를 최소화시킬 수 있는 시스템 패키지를 제공하는 데 목적이 있다.
본 발명의 제1 측면에 따른 반도체 패키지는,
인쇄회로 기판과;
상기 인쇄회로 기판 상에 안착되며 그 상면에 도전 포스트들이 형성된 반도 체 다이와;
상기 인쇄회로 기판 상에 상기 반도체 다이를 덮도록 형성된 몰딩을 포함하며,
상기 도전 포스트들은 일면이 상기 몰딩의 상부 면 상에 노출된다.
본 발명의 제2 측면에 따른 반도체 시스템 패키지는,
도전 포스트들이 형성된 반도체 다이와, 상기 도전 포스트들의 상면이 노출되도록 형성된 몰딩을 포함하는 제1 반도체 패키지와;
상기 제1 반도체 패키지 상에 상기 도전 포스트들과 전기적으로 연결되게 안착되는 제2 반도체 패키지를 포함한다.
이하에서는 첨부도면들을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다. 본 발명을 설명함에 있어서, 관련된 공지기능, 혹은 구성에 대한 구체적인 설명은 본 발명의 요지를 모호하지 않게 하기 위하여 생략한다.
도 2a는 본 발명의 제1 실시 예에 따른 시스템 패키지의 단면을 도시한 도면이고, 도 3a 내지 도 3d는 도 2a 도시된 시스템 패키지의 제조 단계별 단면을 도시한 도면이다. 도 2a 및 2b와 도 3a 내지 도 3d를 참조하면, 본 실시 예에 따른 반도체 시스템 패키지(200)는 제1 및 제2 반도체 패키지(220,210)를 포함한다. 상기 제1 반도체 패키지(220) 상에 상기 제2 반도체 패키지(210)가 안착된다.
상기 제1 반도체 패키지(220)는 재배선들(225)이 형성된 반도체 다이(222) 와, 상기 재배선들(225)의 상면이 노출되도록 형성된 몰딩(223)과, 상기 반도체 다이(222)가 안착되는 인쇄회로 기판(221)을 포함하며, 상기 몰딩(223)은 상기 인쇄회로 기판(221) 상에 상기 반도체 다이(222)를 덮도록 형성된다. 상기 반도체 다이(222)는 상기 인쇄회로 기판(221)과 와이어 본딩(224)에 의해 연결된다.
도 2b는 도 2a에 도시된 제1 반도체 패키지(220)에 실장되는 반도체 다이의 단면을 도시한 도면이고, 도 3a는 상기 반도체 다이(222)의 단면을 도시한 도면이다. 도 2b와 도 3a를 참조하면, 상기 반도체 다이(222)는 상호 대향된 상부 및 하부 면을 구비하며 상기 하부 면은 상기 인쇄회로 기판(221)에 접하게 안착된다.
상기 반도체 다이(222)는 상부 면 상에 형성된 본딩 패드들(222a)과, 상기 본딩 패드들(222a)의 상면이 노출되게 상기 반도체 다이(222)의 상부 면 상에 형성된 절연 층(222b)을 포함한다. 상기 재배선(225)는 상기 절연 층(222b) 상에 노출된 본딩 패드들(222b) 중 일부에 형성된 범핑 패드(225a)와, 상기 범핑 패드(225a)상에 형성된 도전 포스트들(225b)을 포함한다.
상기 반도체 다이(222)는 그 상면에 회로 패턴들(미도시)이 형성되며, 상기 회로 패턴들 중 외부와 전기적으로 연결되는 단자의 상면에는 상기 본딩 패드들(222a)이 형성된다. 상기 절연 층(222b)은 상기 본딩 패드들(222a)을 덮도록 상기 반도체 다이(222) 상에 형성되나, 상기 본딩 패드들(222a)의 상면이 노출될 수 있게 상기 반도체 다이(222) 상에 형성된다.
상기 범핑 패드들(225a)은 상기 본딩 패드들(222a) 중에서 와이어 본딩에 의해 인쇄회로 기판과 연결되지 않는 본딩 패드(222a) 상면에 형성되고, 상기 도전 포스트(225b)는 구리 등과 같은 금속성 재질이 사용될 수 있으며 상기 범핑 패드(225a)에 리플로우(reflow) 등에 의해 결합될 수 있다.
상기 몰딩(223)은 상기 도전 포스트(225b)의 상면이 노출되도록 상기 인쇄회로 기판(221) 상에 상기 반도체 다이(222)를 덮도록 형성된다. 상기 몰딩(223)은 도 3b에 도시된 바와 같이 상기 도전 포스트(225b)를 포함해서 상기 반도체 다이(222)를 완전하게 덮도록 형성되며, 상기 몰딩(223)은 도 3c에 도시된 바와 같이 상기 도전 포스트들(225b)이 상면이 노출될 수 있도록 그 상부의 일 부분이 식각 또는 연마된다.
상기 제2 반도체 패키지(210)는 상기 제1 반도체 패키지(220) 상에 패키지 온 패키지(Package on Package)의 형태로 안착되는 인쇄회로 기판(211)과, 상기 인쇄회로 기판(211) 상에 안착된 적어도 하나의 반도체 다이들(212)을 포함한다. 상기 반도체 다이들(212)은 적층형으로서, 와이어 본딩(214)에 의해 상기 제2 반도체 패키지()210의 인쇄회로 기판(211)과 전기적으로 연결된다. 상기 인쇄회로 기판(211) 상에는 몰딩(213)이 형성된다.
상기 제1 및 제2 반도체 패키지(220,210)의 인쇄회로 기판(221,211)은 적층형 인쇄회로 기판(embeded)이 사용될 수 있으며, 상기 제2 반도체 패키지(210)의 인쇄회로 기판(211)은 상기 제1 반도체 패키지(220)의 몰딩(223) 상에 노출된 도전 포스트(225b)와 전기적으로 연결된다.
상기 제1 및 제2 반도체 패키지(220,210)의 사이에는 도 3d에 도시된 바와 같이 도전성 접착 패드(230)가 삽입될 수 있으며, 상기 도전성 접착 패드(230)에 의해서 상기 제1 및 제2 반도체 패키지(220,210)가 전기적으로 연결될 수 있다. 상기 도전성 접착 패드(230)는 접착 물질 내에 금속과 같은 도전 물질들이 알갱이 상태로 내재 되며, 상기 제1 및 제2 반도체 패키지(220,210)의 사이에 가해지는 압력에 의해서 상하의 수직 방향으로 전기적으로 연결될 수 있다.
도 4는 본 발명의 제2 실시 예에 따른 시스템 패키지의 단면을 도시한 도면이다. 도 4를 참조하면, 본 실시 예에 따른 반도체 시스템 패키지(300)는 제1 및 제2 반도체 패키지(320,310)를 포함한다. 상기 제1 반도체 패키지(320) 상에 상기 제2 반도체 패키지(310)가 안착되며, 본 실시 예에 따른 반도체 시스템 패키지(300)는 상기 제1 반도체 패키지(320)보다 길이가 긴 제2 반도체 패키지(310)가 적용된다.
상기 제1 및 제2 반도체 패키지(320,310)는 인쇄회로 기판(321,311)과, 상기 각 인쇄회로 기판(321,311) 상에 위치된 반도체 다이들(322,312)과, 상기 반도체 다이들(322,312)을 포함해서 해당 인쇄회로 기판(321,311)을 덮도록 형성된 몰딩(323,313)을 포함하며, 상기 각 반도체 다이들(322,312)은 와이어 본딩(324,314)에 의해서 해당 인쇄회로 기판(321,311)과 전기적으로 연결될 수 있다.
상기 제1 반도체 패키지(320)의 반도체 다이(322)는 그 상면에 도전 포스트들(325)이 형성되고, 상기 도전 포스트들(325)에 의해서 상기 제1 반도체 패키지(320)의 반도체 다이(322)와 상기 제2 반도체 패키지(310)가 전기적으로 연결될 수 있다. 상기 제1 및 제2 반도체 패키지(320,310)는 그 사이에 개재된 인터포저(Interposer) 등에 의해 연결될 수 있다.
본 발명은 기존 패키지 온 패키지 방식의 반도체 패키지에 비해서, 반도체 패키지의 고밀도 집적이 가능하고, 반도체 패키지 간의 접촉 면적이 넓으므로 안정적인 기계적 강도와 신뢰성 확보가 용이하다.

Claims (8)

  1. 반도체 패키지에 있어서,
    인쇄회로 기판과;
    상기 인쇄회로 기판 상에 안착되며 그 상면에 도전 포스트들이 형성된 반도체 다이와;
    상기 인쇄회로 기판 상에 상기 반도체 다이를 덮도록 형성된 몰딩을 포함하며,
    상기 도전 포스트들은 일면이 상기 몰딩의 상부 면 상에 노출됨을 특징으로 하는 반도체 패키지.
  2. 제1 항에 있어서, 상기 반도체 다이는,
    상호 대향된 상부 및 하부 면을 구비하며, 상기 하부 면은 상기 인쇄회로 기판에 접하게 안착됨을 특징으로 하는 반도체 패키지.
  3. 제2 항에 있어서, 상기 반도체 다이는,
    상기 상부 면 상에 형성된 회로 패턴 및 본딩 패드와;
    상기 회로 패턴과 상기 본딩 패드가 노출되게 상기 상부 면 상에 형성된 절 연 층과;
    상기 절연 층 상에 노출된 회로 패턴들 상에 형성된 범핑 패드와;
    상기 범핑 패드 상에 형성된 도전 포스트를 포함함을 특징으로 하는 반도체 패키지.
  4. 반도체 시스템 패키지에 있어서,
    도전 포스트들이 형성된 반도체 다이와, 상기 도전 포스트들의 상면이 노출되도록 형성된 몰딩을 포함하는 제1 반도체 패키지와;
    상기 제1 반도체 패키지 상에 상기 도전 포스트들과 전기적으로 연결되게 안착되는 제2 반도체 패키지를 포함함을 특징으로 하는 반도체 시스템 패키지.
  5. 제4 항에 있어서, 제1 반도체 패키지는,
    상기 반도체 다이가 안착되는 인쇄회로 기판을 더 포함하며,
    상기 몰딩은 상기 인쇄회로 기판 상에 상기 반도체 다이를 덮도록 형성됨을 특징으로 하는 반도체 시스템 패키지.
  6. 제5 항에 있어서, 상기 반도체 다이는,
    상호 대향된 상부 및 하부 면을 구비하며, 상기 하부 면은 상기 인쇄회로 기판에 접하게 안착됨을 특징으로 하는 반도체 시스템 패키지.
  7. 제6 항에 있어서, 상기 반도체 다이는,
    상기 상부 면 상에 형성된 본딩 패드들과;
    상기 본딩 패드들이 노출되게 상기 상부 면 상에 형성된 절연 층과;
    상기 절연 층 상에 노출된 본딩 패드들 상에 형성된 범핑 패드와;
    상기 범핑 패드 상에 형성된 도전 포스트를 포함함을 특징으로 하는 반도체 시스템 패키지.
  8. 제4 항에 있어서, 제2 반도체 패키지는,
    상기 제1 반도체 패키지 상에 패키지 온 패키지의 형태로 안착되는 인쇄회로 기판과;
    상기 인쇄회로 기판 상에 안착된 적어도 하나의 반도체 다이들을 포함함을 특징으로 하는 반도체 시스템 패키지.
KR1020060093433A 2006-09-26 2006-09-26 반도체 패키지와 그를 이용한 반도체 시스템 패키지 Expired - Fee Related KR100770934B1 (ko)

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