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JP2716336B2 - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JP2716336B2
JP2716336B2 JP5049172A JP4917293A JP2716336B2 JP 2716336 B2 JP2716336 B2 JP 2716336B2 JP 5049172 A JP5049172 A JP 5049172A JP 4917293 A JP4917293 A JP 4917293A JP 2716336 B2 JP2716336 B2 JP 2716336B2
Authority
JP
Japan
Prior art keywords
solder
semiconductor substrate
integrated circuit
substrate
micro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5049172A
Other languages
English (en)
Other versions
JPH06268015A (ja
Inventor
研二 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5049172A priority Critical patent/JP2716336B2/ja
Priority to EP94103427A priority patent/EP0615283B1/en
Priority to DE69428819T priority patent/DE69428819T2/de
Priority to CA002118649A priority patent/CA2118649C/en
Priority to AU57713/94A priority patent/AU675273B2/en
Priority to KR1019940004651A priority patent/KR0153212B1/ko
Publication of JPH06268015A publication Critical patent/JPH06268015A/ja
Priority to US08/642,410 priority patent/US5640052A/en
Application granted granted Critical
Publication of JP2716336B2 publication Critical patent/JP2716336B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体集積回路のパッ
ケージ構造体に係り、特に、集積回路の半導体基体とパ
ッケージ用基板との電気的、機械的結合にはんだの微小
柱状体を用いた集積回路装置に関する。
【０００２】
【従来の技術】集積回路装置を完成させるためには、集
積回路が形成された半導体基体をパッケージ用基板に取
り付け、かつ、これらの間での電気的な接続を行なう必
要がある。
【０００３】このような取付けと接続のための技法とし
ては、従来、種々の方法が提案され、実用に供されてい
るが、その中ではんだの微小柱状体を用い、半導体基体
とパッケージ用基板との電気的な結合と機械的な結合と
を同時に得るようにした方法がある。
【０００４】この方法は、例えば図２に示す様に、半導
体基体１とパッケージ用基板２の相互に接続すべき端子
部５，６のうちの一方、例えば半導体基体１側の端子部
５に、あらかじめ約５〜４０重量％の錫と９５〜６０重
量％の鉛を成分とするはんだ組成物を形成しておく。そ
して、半導体基体１とパッケージ用基板２とを所定の間
隔を隔てて面対向させた状態で加熱し、上記はんだ組成
物を溶融（リフロー）せしめ、双方の端子部間にはんだ
の微小柱状体３を形成せしめることにより端子部５，６
間での電気的接続と、半導体基体１とパッケージ用基板
２との間での機械的結合とが得られる。
【０００５】このようなはんだの微小柱状体による結合
方法によれば、電気的に接続すべき端子部が複数あって
も、これと無関係に、ただ一度の溶融処理で全て同時に
接続処理が完了し、かつ機械的な結合も同時に得られ
る。このため、接続端子数の多い集積回路装置に、近
年、この方法が広く採用されるようになってきた。
【０００６】これとは別に、集積回路の集積度も増加の
一途をたどり、特にＬＳＩと呼ばれるものでは端子引出
数は数百本にも達するようになってきた。ところが、こ
のような端子引出数の多い半導体基体とパッケージ用基
板との接続に、上記のはんだ微小柱状体による方法を適
用すると、集積回路装置に故障が発生し易いという問題
点が生じるようになってきた。この故障は、主としては
んだ微小柱状体によって電気的に接続した半導体基体と
パッケージ用基板のそれぞれの端子部間での導通不良の
発生という形で現われる。これは、半導体基体とパッケ
ージ用基板との間での熱膨張係数の差に起因して、はん
だ微小柱状体に与えられる繰り返し応力の結果、この部
分が熱疲労により破壊し、電気的な断線に至るためであ
る。そこで、このような問題点の解決のため、従来、以
下に示すようないくつかの提案がなされている。
【０００７】第１の方法は、ＩＣチップ等の電気部品の
はんだバンプ形成面もしくは基板の導体面のいずれか一
方の面のはんだバンプとは干渉しない個所に、融点がは
んだ端子よりも高いペーストはんだをはんだ端子の高さ
よりも低く、かつ、１個のはんだバンプよりも多い量を
塗布しておく。そして、実装時には、はんだバンプのリ
フローに続いて上記ペーストはんだを融点以上に加熱し
て融解させた後、はんだ端子を硬化させることにより、
はんだバンプを引き延ばし、つづみ状に成形させる。こ
の第１の方法は、特公平２−２０６１３８号公報に示さ
れている。
【０００８】第２の方法は、特公昭６１−１５６７４５
公報に示されており、この方法では、ＩＣチップ裏面に
磁性体からなる部分を形成し、はんだリフローの際にＩ
Ｃチップを磁石により上方に吸引することにより、基板
に対するチップの高さを高くするようにしている。ま
た、特公昭６２−０１３８１７公報に示された第３の方
法では、ＩＣ基板に設けられた電極部以外をマスクする
厚い絶縁体を形成し、電気メッキ、あるいは蒸着等によ
り、上記電極部にはんだバンプを形成し、ＩＣ基板側の
電極とセラミック基板側の電極とをはんだの融解により
接続した後、上記絶縁体を除去することにより、はんだ
バンプを細長く形成するようにしている。
【０００９】
【発明が解決しようとする課題】しかしながら、これら
の従来の技術では、半導体基体内の素子の集積度の向上
にともなって、チップが大型化され、熱膨張差の影響が
大きく現れる場合には熱疲労によるはんだ微小柱状体で
の断線故障を防止するには不十分であり、充分な長寿命
を得ることができないという問題点があった。
【００１０】本発明の課題は上記の問題点を解消して長
寿命を得ることのできる集積回路装置を提供することに
ある。
【００１１】
【課題を解決するための手段】本発明は、集積回路の半
導体基体とパッケージ用基板との間にはんだの微小柱状
体を配置し、上記微小柱状体の溶着により上記半導体基
体と上記パッケージ用基板との電気的接続と機械的結合
を得るフリップチップ実装構造の集積回路装置におい
て、上記半導体基体と上記パッケージ用基板のいずれか
一方に、上記微小柱状体の内部に含まれるように金属製
の芯がはんだ付け接続されており、上記微小柱状体の側
面形状を内側にくぼんだつづみ形状としたことを特徴と
する。
【００１２】
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例を示す断面図である。図１
において、１は半導体基体、２はパッケージ用基板、３
ははんだの微小柱状体、４は金属製の芯、５，６はそれ
ぞれ、半導体基体１、パッケージ用基板２の対向端面に
形成された端子部である。
【００１３】半導体基体１は、例えば十数ｍｍ角の大き
さのシリコン基板に大型電子計算機用プロセッサを構成
する固体回路を形成してなるＬＳＩチップで、その一方
の面に多数の端子部５がマトリクス状に配列してある。
【００１４】パッケージ用基板２は、例えばアルミナを
母材として、表面に有機絶縁層８をもつ多層配線基板で
あり、半導体基体１に対向する面には、端子部５に対応
して相互に向い合う位置に端子部６がマトリクス状に配
列してある。
【００１５】端子部５は半導体基体１の面に形成した積
層金属層で、金属製の芯４との結合界面として機能す
る。同様に、端子部６は、パッケージ用基板２の表面に
形成した積層金属層で、はんだの微小柱状体３との結合
界面として機能する。
【００１６】金属製の芯４は端子部５との間に供給され
た高融点はんだ７を加熱溶融させることにより電気的な
接続と機械的な結合とを行なう。
【００１７】はんだの微小柱状体３は端子部５，６の間
に、内部に金属製の芯４を有した状態で配置された上で
加熱溶融され、金属製の芯４と、端子部６との結合界面
で合金化したあとで常温に戻される。これにより、半導
体基体１とパッケージ用基板２との間での電気的な接続
と機械的な結合とを行なう。
【００１８】ここで、半導体基体１の端子部５と端子部
６と金属製の芯４は共に平面形状が円形をなし、それら
が数１００μｍの均一なピッチで相互に対応する位置に
配列されている。
【００１９】一方、はんだの微小柱状体３は、以下の様
にして形成される。まず、半導体基体１側の端子部５に
接続された金属製の芯４にあらかじめめっき法、蒸着法
などの周知の方法と、それに続く加熱、冷却処理によ
り、側面投影形状が内側にくぼんだつづみ形状になる様
なある一定の体積のはんだ量を供給して、はんだバンプ
を形成させる。その後、この半導体基体１をあらかじめ
水平に保ってあるパッケージ用基板２の上に載置し、端
子部５と６と金属製の芯４の互いに対応するものが正確
に向い合った状態で空気中でのフラックスを用いた加熱
処理、或いは水素、窒素、アルゴンなどの制御された雰
囲気中でのフラックスを用いない加熱処理によりはんだ
バンプの溶融と、それに続く常温への復帰処理が行なわ
れ、結合界面での合金化により金属製の芯４と端子部６
との間にはんだの微小柱状体３を形成する。
【００２０】図３は本発明の有効性を検証するために有
限要素法により応力シミュレーションを行った際のシミ
ュレーションモデルを示し、シミュレーションの結果、
図４に示すような結果が得られた。シミュレーションモ
デルにおいては、最外周バンプのみをモデル化し、シミ
ュレーションの条件としては、２３℃で応力０、１２５
℃に温度上昇した時の応力を求めた。図中Max で示す箇
所は応力最大の箇所を示し、図２のような従来の場合の
応力を１とすると、本発明のようなはんだの微小柱状体
の側面投影形状（つづみ状）で芯無しの場合、０．６２
となり、金属製の芯のみの場合、０．６３であり、本発
明では０．５１という値が得られた。
【００２１】
【発明の効果】以上説明したように本発明は、半導体基
体とパッケージ用基板との間に設けられるはんだの微小
柱状体の内部に金属製の芯を有し、内側にくぼんだつづ
み状の側面投影形状になるようにしたので、単にはんだ
微小柱状体のみで半導体基体とパッケージ用基板とを接
続し、その側面投影形状を内側にくぼんだ側面投影形状
にした場合よりも、接続部に加わる応力が低減される。
また、半導体基体とパッケージ用基板との間を金属製の
芯のみで接続した場合よりも応力を低減させることがで
きる。よって、本発明によれば従来のものよりも寿命特
性を充分に改善することができる。
【図面の簡単な説明】
【図１】本発明による集積回路装置の断面図である。
【図２】従来技術による集積回路装置の断面図である。
【図３】本発明の有効性を検証するためのシミュレーシ
ョンモデルを示した図である。
【図４】図３に示したシミュレーションモデルによるシ
ミュレーション結果を、従来例の場合と共に示した図で
ある。
【符号の説明】
１ 半導体基体 ２ パッケージ用基板 ３ はんだの微小柱状体 ４ 金属製の芯 ５，６ 端子部 ７ 高融点はんだ ８ 有機絶縁層

Claims (1)

    (57)【特許請求の範囲】
  1. 【請求項１】 集積回路の半導体基体とパッケージ用基
    板との間にはんだの微小柱状体を配置し、上記微小柱状
    体の溶着により上記半導体基体と上記パッケージ用基板
    との電気的接続と機械的結合を得るフリップチップ実装
    構造の集積回路装置において、上記半導体基体と上記パ
    ッケージ用基板のいずれか一方に、上記微小柱状体の内
    部に含まれるように金属製の芯がはんだ付け接続されて
    おり、上記微小柱状体の側面形状を内側にくぼんだつづ
    み形状としたことを特徴とする集積回路装置。
JP5049172A 1993-03-10 1993-03-10 集積回路装置 Expired - Lifetime JP2716336B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP5049172A JP2716336B2 (ja) 1993-03-10 1993-03-10 集積回路装置
DE69428819T DE69428819T2 (de) 1993-03-10 1994-03-07 Verbindungsstruktur für elektronische Bauteile, welche Lötperlen mit Metallseelen enthalten
EP94103427A EP0615283B1 (en) 1993-03-10 1994-03-07 Interconnection structure of electronic parts comprising solder bumps with metal core members
AU57713/94A AU675273B2 (en) 1993-03-10 1994-03-09 Interconnection structure of electronic parts
CA002118649A CA2118649C (en) 1993-03-10 1994-03-09 Interconnection structure of electronic parts
KR1019940004651A KR0153212B1 (ko) 1993-03-10 1994-03-10 반도체 장치의 상호 접속 구조 및 상호 접속 방법
US08/642,410 US5640052A (en) 1993-03-10 1996-05-03 Interconnection structure of electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5049172A JP2716336B2 (ja) 1993-03-10 1993-03-10 集積回路装置

Publications (2)

Publication Number Publication Date
JPH06268015A JPH06268015A (ja) 1994-09-22
JP2716336B2 true JP2716336B2 (ja) 1998-02-18

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EP (1) EP0615283B1 (ja)
JP (1) JP2716336B2 (ja)
KR (1) KR0153212B1 (ja)
AU (1) AU675273B2 (ja)
CA (1) CA2118649C (ja)
DE (1) DE69428819T2 (ja)

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KR940022765A (ko) 1994-10-21
DE69428819T2 (de) 2002-06-20
AU675273B2 (en) 1997-01-30
JPH06268015A (ja) 1994-09-22
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US5640052A (en) 1997-06-17
CA2118649A1 (en) 1994-09-11
CA2118649C (en) 2000-05-02

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