[go: up one dir, main page]

KR100265563B1 - 볼 그리드 어레이 패키지 및 그의 제조 방법 - Google Patents

볼 그리드 어레이 패키지 및 그의 제조 방법 Download PDF

Info

Publication number
KR100265563B1
KR100265563B1 KR1019980025015A KR19980025015A KR100265563B1 KR 100265563 B1 KR100265563 B1 KR 100265563B1 KR 1019980025015 A KR1019980025015 A KR 1019980025015A KR 19980025015 A KR19980025015 A KR 19980025015A KR 100265563 B1 KR100265563 B1 KR 100265563B1
Authority
KR
South Korea
Prior art keywords
metal wire
groove
semiconductor chip
encapsulant
attached
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980025015A
Other languages
English (en)
Other versions
KR20000003743A (ko
Inventor
박상욱
김지연
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019980025015A priority Critical patent/KR100265563B1/ko
Priority to TW088110395A priority patent/TW419761B/zh
Priority to US09/339,094 priority patent/US6211461B1/en
Priority to CNB991088646A priority patent/CN1211854C/zh
Priority to JP18393299A priority patent/JP4400898B2/ja
Priority to GB9915229A priority patent/GB2339334B/en
Publication of KR20000003743A publication Critical patent/KR20000003743A/ko
Application granted granted Critical
Publication of KR100265563B1 publication Critical patent/KR100265563B1/ko
Priority to US09/782,699 priority patent/US6519846B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02233—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body not in direct contact with the bonding area
    • H01L2224/02235—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02233—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body not in direct contact with the bonding area
    • H01L2224/02255—Shape of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02317—Manufacturing methods of the redistribution layers by local deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02319—Manufacturing methods of the redistribution layers by using a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02321—Reworking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02335—Free-standing redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/031—Manufacture and pre-treatment of the bonding area preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0333—Manufacturing methods by local deposition of the material of the bonding area in solid form
    • H01L2224/03334—Manufacturing methods by local deposition of the material of the bonding area in solid form using a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0106—Neodymium [Nd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 볼 그리드 어레이 패키지 및 그의 제조 방법을 개시한다. 개시된 본 발명은, 회로가 구성된 반도체 칩(10)에 U자 형상의 홈부(11)가 형성되고, 홈부(11)의 저면 중앙과 양측에 한 쌍의 본딩 패드(20)와 절연 패드(30)가 형성된다. 각 패드(20,30)는 금속 와이어(40)에 의해 연결되고, 봉지제(50)가 홈부(11)내를 몰딩하게 된다. 이때, 금속 와이어(40)의 중간부가 봉지제(50)에서 돌출되고, 이 돌출된 금속 와이어(40) 부분에 범프(60)가 부착되며, 기판에 실장되는 솔더 볼(70)이 범프(60)에 부착된다. 따라서, 봉지제(50)가 반도체 칩(10)에서 돌출되지 않으므로, 반도체 칩(10)의 두께가 바로 패키지의 두께가 되어, 패키지의 경박화가 실현된다.

Description

볼 그리드 어레이 패키지 및 그의 제조 방법
본 발명은 볼 그리드 어레이 패키지 및 그의 제조 방법에 관한 것으로서, 보다 구체적으로는 소정의 회로 패턴을 갖는 기판에 반도체 칩이 탑재되어 전기적으로 연결되고, 기판의 하면에 실장을 위한 다수의 솔더 볼이 부착되어 구성된 볼 그리드 어레이 패키지 및 그의 제조 방법에 관한 것이다.
패키지의 한 예로서, 가장 범용으로 사용되고 있는 에스오제이(SOJ:Small Outline J-lead) 타입이 있고, 특수한 경우에 사용하는 지프(ZIP: Zigzag Inline Package) 타입이 있으며, 또 규격화되고 있는 메모리 카드(memory card)에 적합하도록 구성된 티에스오피(TSOP: Thin Small Outline Package) 타입 등이 있다.
이러한 패키지 제조 방법을 개략적으로 설명하면 다음과 같다.
먼저, 웨이퍼를 스크라이빙 라인을 따라 절단하는 소잉(sawing) 공정을 진행하여 개개의 반도체 칩으로 분리한 다음, 리드 프레임의 인너 리드를 각 반도체 칩에 부착하는 다이 어태치 공정을 진행한다.
이후 일정 온도에서 일정시간 동안 큐어링(curing)을 실시한 후, 반도체 칩의 패드와 리드 프레임의 인너 리드를 금속 와이어로 상호 연결시켜 전기적으로 연결시키는 와이어 본딩 공정을 수행한다.
와이어 본딩이 끝나면, 봉지제를 사용하여 반도체 칩을 몰딩하는 몰딩 공정을 수행한다. 이와 같이 반도체 칩을 몰딩해야만, 외부의 열적, 기계적 충격으로 부터 반도체 칩을 보호할 수가 있는 것이다.
상기와 같은 몰딩 공정이 완료된 후에는 아우터 리드을 도금하는 플래팅 공정, 아우터 리드를 지지하고 있는 댐바를 절단하는 트림 공정, 및 기판에 실장이 용이하도록 아우터 리드를 소정 형태로 절곡 형성하는 포밍 공정을 진행하여, 패키지를 제조한다.
이러한 공정으로 제작되는 일반적인 패키지에 대해, 패키지의 경박화를 위해 제시된 볼 그리드 어레이 패키지는 상기 일반적인 패키지에서 사용되는 리드 프레임 대신에 탭 테이프가 사용되고, 기판에 실장하기 위해서 수 개의 솔더 볼이 어레이식으로 배열된다.
종래의 볼 그리드 어레이 패키지는 도 1에 나타낸 바와 같이, 반도체 칩(1)의 패드에 범프(2)가 형성되어 있고, 구리 재질의 금속 패턴이 형성된 탭 테이프(3:TAB tape)가 범프(2)에 열압착에 의해 부착되어 전기적으로 연결된다. 전체가 봉지제(4)로 몰딩되고, 탭 테이프(3)의 밑면에 형성된 볼 랜드에 솔더 볼(5)이 부착된 구조로 이루어져 있다.
그러나, 상기한 바와 같은 종래의 패키지의 두께는 반도체 칩(1)에 탭 테이프(3)와 봉지제(4)의 두께가 합산되기 때문에, 경박화되는 패키지 발전 추세에 비추어보면 개선의 요지가 되어 왔다.
그리고, 범프(2)와 탭 테이프(3)를 열압착할 때, 기계적 충격으로 범프(2) 또는 탭 테이프(3)에 균열이 발생되는 문제점이 있었다.
또한, 볼 랜드의 금속면과 솔더 볼(5)이 반응하여, 계면에서 금속 화합물이 발생되는 문제점도 있었다.
특히, 탭 테이프(3) 자체에는 이온 또는 수분이 잔존할 소지가 많아서, 패키지가 오동작을 일으키는 경우가 많았다. 또한, 탭 테이프(3)내의 금속 패턴을 절연시키는 절연 필름이 손상되면, 쇼트가 발생된다. 그리고, 패드의 위치나 솔더 볼간의 피치나 위치가 변경될 때마다, 탭 테이프(3)를 새로 설계해야만 하는 문제점도 있었다.
상기와 같은 문제점을 해소하기 위해 안출된 본 발명은, 반도체 칩의 두께가 패키지의 두께가 되도록 하여, 패키지의 경박화를 실현할 수 있는 획기적인 구조의 볼 그리드 어레이 패키지 및 그의 제조 방법을 제공하는데 목적이 있다.
다른 목적은, 범프를 사용하지 않고 금속 와이어로 대체하여, 기계적 충격에 의한 패드의 파괴를 방지할 수 있는 볼 그리드 어레이 패키지 및 그의 제조 방법을 제공하는데 목적이 있다.
또 다른 목적은, 솔더 볼의 부착 방식을 변경하여 솔더 볼과 볼 랜드 사이에 금속 반응이 일어나지 않도록 하는데 있다.
또한, 탭 테이프를 사용하지 않으므로써, 탭 테이프로 인한 제반 문제점들을 해소시키는데 목적이 있다.
도 1은 종래의 볼 그리드 어레이 패키지를 나타낸 단면도
도 2 내지 도 10은 본 발명의 실시예 1에 따른 패키지의 제조 과정을 순차적으로 나타낸 단면도
도 11 및 도 12는 본 발명의 실시예 2에 따른 패키지 제조 과정을 나타낸 단면도
도 13 및 도 14는 본 발명의 실시예 3에 따른 패키지 제조 과정을 나타낸 단면도
도 15 내지 도 19는 본 발명의 실시예4에 따른 패키지 제조 과정을 순차적으로 나타낸 단면도
- 도면의 주요 부분에 대한 부호의 설명 -
10 - 반도체 칩 11 - 홈부
20 - 본딩 패드 30 - 절연 패드
40 - 금속 와이어 50 - 봉지제
60 - 범프 70 - 솔더 볼
100 - 세라믹 캡 101 - 인출홈
상기와 같은 목적을 달성하기 위한 본 발명에 따른 패키지는 다음과 같은 구성으로 이루어진다.
회로가 형성될 반도체 칩의 상부 밑면에 홈부가 형성되고, 홈부의 저면 중앙에 본딩 패드가 형성된다. 본딩 패드의 양측으로 절연 패드가 부착되고, 절연 패드와 패드가 금속 와이어로 연결된다. 특히, 금속 와이어의 중간부는 반도체 칩의 양측 상단에서 약간 돌출되게 굴곡진 형상을 이룬다. 홈부 전체가 봉지제에 의해 몰딩되는데, 이때 금속 와이어의 돌출부가 봉지제에서 약간 돌출된다. 금속 와이어의 돌출부에 범프가 형성되고, 이 범프에 솔더 볼이 부착된다.
다른 방안으로서, 절연 패드 대신에, 더미(dummy) 패드가 반도체 칩의 양측 상단에 형성되고, 본딩 패드와 더미 패드가 금속 와이어로 연결된다. 홈부 전체가 봉지제에 의해 몰딩되고, 반도체 칩의 양측 상단면을 기준으로 그라인딩되어, 더미 패드와 금속 와이어의 상단이 제거된다. 따라서, 금속 와이어의 절단된 상단은 봉지제에서 노출되고, 이 노출된 금속 와이어에 범프가 형성되어서, 솔더 볼이 부착된다.
또 다른 방안으로서, 여러 개가 연결된 반도체 칩 각각에 홈부가 형성되고, 홈부 저면 중앙에 한 쌍의 본딩 패드가 형성된다. 금속 와이어가 인접하는 반도체 칩들 사이를 넘어서, 그의 양단이 각 홈부에 형성된 본딩 패드에 연결된다. 각 홈부가 봉지제로 몰딩되고, 각 반도체 칩이 절단되어 개개의 칩으로 분리된다. 따라서, 절단된 금속 와이어의 상단이 봉지제에서 노출되어지고, 이 부분에 범프가 형성되어 솔더 볼이 부착된다.
상기 3가지 방안과는 완전히 다른 방안으로서, 홈부를 봉지제로 몰딩하지 않고, 반도체 칩의 상부에 세라믹 재질의 캡이 설치된다. 금속 와이어는 첫 번째 방안과 같이, 양단이 본딩 패드와 절연 패드에 연결된다. 캡에는 금속 와이어의 중간부가 인출되는 인출홈이 형성되어서, 인출홈을 통해 노출된 금속 와이어 부분에 범프가 형성되어 솔더 볼이 부착된다.
상기된 본 발명의 구성에 의하면, 반도체 칩에 형성된 홈부내에서 와이어 본딩이 이루어지고, 따라서 봉지제도 홈부내만 몰딩하면 되므로, 반도체 칩의 두께가 거의 패키지의 두께가 되므로써, 패키지의 경박화가 실현된다.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.
먼저, 본 실시예들을 상술하기 전에, 첨부된 도면들에서 반도체 칩은 180。로 뒤집어진 상태이다. 이는, 본 발명에 따라 패키지를 제조할 때, 반도체 칩의 밑면에 각종 공정이 실시되므로, 첨부도면에서는 패키지를 180。로 뒤집어진 상태로 도시하였다.
＜실시예 1＞
먼저, 본 실시예 1에 따른 최종 완성품인 볼 그리드 어레이 패키지의 구조를 도 10을 참고로 하여 설명하면 다음과 같다.
도시된 바와 같이, 뒤집어진 상태의 반도체 칩(10)의 상부, 즉 회로가 형성된 부분에 U자 형상의 홈부(11)가 형성된다. 홈부(11)의 저면 중앙에 한 쌍의 본딩 패드(20)가 형성되고, 양측으로는 한 쌍의 절연 패드(30)가 형성된다. 각 패드(20,30)가 금속 와이어(40)로 연결되는데, 특히 금속 와이어(40)의 중간부는 반도체 칩(10)의 양측 상단에서 약간 돌출되게 굴곡진 형상으로 이루어진다.
봉지제(50)가 홈부(11)내에만 도포되어, 홈부(11) 전체를 몰딩하게 된다. 따라서, 봉지제(50)의 높이는 반도체 칩(10)의 양측 상단 높이와 동일하게 되고, 특히 금속 와이어(40)의 중간부가 봉지제(50)에서 약간 돌출되어진다. 금 재질의 범프(60)가 돌출된 금속 와이어(40) 부분에 형성되고, 이 범프(60)에 솔더 볼(70)이 부착된다. 따라서, 상기와 같은 구조의 패키지의 두께는 반도체 칩(10)의 두께와 동일하게 된다.
이하, 상기와 같은 구조의 패키지의 제조 과정을 첨부도면을 참고로 하여 순차적으로 설명한다.
먼저, 도 2에서와 같이, 회로가 형성될 부위인 반도체 칩(10)의 상부면에 U자 형상의 홈부(11)를 식각하여 형성한다. 이때, 홈부(11)의 폭은 200 내지 400 ㎛로, 깊이는 250 내지 400㎛인 것이 바람직하다. 그런 다음, 도 3과 같이, 홈부(11)의 저면 중앙에 한 쌍의 본딩 패드(20)를 형성하고, 양측으로는 절연 패드(30)를 부착한다.
절연 패드(30)는 도 4에 도시된 바와 같이, 접착층(31) 상부에 U자 형상의 홈부가 형성되고, 이 홈부내에 홈부의 깊이와 동일 두께를 갖는 금속층(32)이 수용되며, 금속층(32)의 상부에 와이어 본딩이 용이하도록 금속박막(33)이 코팅된 구조로 이루어진다. 여기서, 접착층(31)의 재질은 폴리머 계열의 폴리이미드이고, 금속층(32)의 재질은 알루미늄(Al), 동(Cu), 니켈(Ni), 금(Au), 은(Ag), 크롬(Cr), 코발트(Co), 또는 주석(Sn)이거나 이들의 합금이고, 금속박막(33)의 재질은 이후에 실시될 금속 와이어와의 열압착시 접착력이 우수한 금(Au), 은(Ag), 또는 크롬인 것이 바람직하다. 한편, 접착층(31)의 두께는 10 내지 100 ㎛이고, 절연 패드(30)의 두께는 1 내지 4 mil인 것이 바람직하다.
이어서, 도 5와 같이, 금속 와이어(40)로 본딩 패드(20)와 절연 패드(30), 즉 금속박막(33)을 열압착으로 연결한다. 이때, 금속 와이어(40)의 굴곡진 중간부가 반도체 칩(10)의 양측 상단보다 높게 위치하도록 한다.
그런 다음, 디스펜서(80)를 사용하여, 도 6과 같이, 홈부(11)내에 봉지제(50)를 도포하여 몰딩한다. 특히, 봉지제(50)의 높이가 반도체 칩(10)의 양측 상단 높이와 동일하게 몰딩한다.
이때, 금속 와이어(40)는 반도체 칩(10)의 양측 상단보다 높게 위치하고 있지만, 봉지제(50) 도포시, 봉지제(50)내로 함몰되어 노출되지 않게 될 우려가 있으므로, 도 7과 같이, 봉지제(50)의 표면에 노즐(9)을 통해서 연마제를 분사하여, 금속 와이어(40)를 봉지제(50)에서 돌출시킨다. 연마제 대신에 연마 페이퍼를 사용하여 그라인딩을 하여도 무방하다.
이어서, 도 8과 같이, 봉지제(50)에서 돌출된 금속 와이어(40) 부분에 금 재질의 범프(60)를 형성하고, 도 9와 같이 서로 연결되어 있는 수 개의 반도체 칩(10)을 절단하여 개개의 칩으로 분리한다.
최종적으로, 도 10과 같이, 솔더 볼(70)을 범프(60)에 부착하면, 본 실시예 1에 따른 볼 그리드 어레이 패키지가 완성된다. 즉, 도 10에 도시된 패키지를 180。로 뒤집으면, 솔더 볼(70)이 하부에 위치하게 되므로, 솔더 볼(70)을 기판에 실장할 수가 있게 된다.
＜실시예 2＞
본 실시예 2는 실시예 1에서 사용된 절연 패드를 사용하지 않는 방식이다.
즉, 도 11에 도시된 바와 같이, U자 형상의 홈부(11)가 형성된 반도체 칩(10)의 양측 상단에 더미 패드(34)가 형성되어서, 더미 패드(34)와 본딩 패드(20)가 금속 와이어(44)로 연결된다. 따라서, 더미 패드(34)측 금속 와이어(44) 부분은 자연적으로 반도체 칩(10)의 양측 상단보다 높게 돌출되어진다.
이어서, 홈부(11)내를 봉지제(50)로 몰딩한 후, 반도체 칩(10)의 양측 상단을 기준으로 그라인딩하면, 더미 패드(34)와 이에 연결된 금속 와이어(44)의 상단이 절단되어 제거된다. 그러므로, 절단된 금속 와이어(44)의 상단이 봉지제(50)에서 노출되고, 이 노출된 금속 와이어(44)에 범프(60)가 형성된다. 범프(60)에 솔더 볼(70)을 부착하면, 도 12와 같이 본 실시예 2에 따른 패키지가 완성된다.
＜실시예 3＞
본 실시예 3은 상기 실시예 1 및 2에서 사용되는 절연 패드나 더미 패드를 전혀 사용하지 않은 방식이다.
즉, 도 13에 도시된 바와 같이, 개개의 칩으로 분리되기 전 상태로서 서로 연결된 수 개의 반도체 칩(10) 각각에 홈부(11)가 형성된다. 각 홈부(11)의 저면 중앙에는 본딩 패드(20)가 형성된다. 금속 와이어(45)가 서로 이웃하는 반도체 칩(10)의 측벽을 넘어서 그의 양단이 각 홈부(11)의 본딩 패드(20)를 연결하게 된다.
봉지제(50)가 홈부(11)를 몰딩하게 되고, 절단 공정에 의해 반도체 칩(10)을 개개의 칩으로 분리한다. 이때, 금속 와이어(45)도 절단되어 분리된다. 이어서, 봉지제(50)가 측벽 높이를 기준으로 그라인딩되는데, 이때 절단된 금속 와이어(45) 부분이 봉지제(50)에서 노출된다. 따라서, 도 14와 같이, 노출된 각 금속 와이어(45) 부분에 범프(60)를 형성하고, 솔더 볼(70)을 범프(60)에 부착하면, 본 실시예 3에 따른 패키지가 완성된다.
＜실시예 4＞
본 실시예 4에서는 실시예 1에서의 와이어 본딩 방식은 동일하지만, 봉지제가 사용되지 않고 세라믹 캡이 대신 사용된다.
즉, 도 15에 도시된 바와 같이, 반도체 칩(10)의 홈부(11)에 형성된 본딩 패드(20)와 절연 패드(30)가 금속 와이어(40)로 연결된다. 홈부(11)가 봉지제로 몰딩되는 대신에, 반도체 칩(10) 상부에 세라믹 캡(100)이 씌워진다. 세라믹 캡(100)은 반도체 칩(10)에 접착제(110)로 부착된다. 세라믹 캡(100)에는 도 16에 도시된 바와 같이, 인출홈(101)이 형성되어서, 이 인출홈(101)을 통해 금속 와이어(40)가 인출된다. 인출된 금속 와이어(40)가 인출홈(101)으로 빠지지 않도록 하기 위해서, 펀치로 금속 와이어(40)를 압착하여, 인출홈(101)의 저면에 고정시킨다.
그런 다음, 도 17과 같이, 금속 와이어(40)에 범프(60)를 부착하고, 솔더 볼(70)을 범프(60)에 부착하면, 도 18과 같이 본 실시예 4에 따른 패키지가 완성된다.
한편, 도 18과 같은 구조의 패키지가 여러 개로 구성된 것을, 기판(220)에 실장한 후, 전체 상부에 접착제(210)를 사용해서 세라믹 캡슐(200)을 씌우면, 최종적인 패키지가 완성된다.
이상에서 설명한 바와 같이, 봉지제가 반도체 칩에 형성된 홈부내에만 도포되므로, 반도체 칩의 두께가 바로 패키지의 두께가 되므로써, 패키지의 경박화가 실현된다.
종래에 사용되던 탭 테이프 대신에 금속 와이어를 사용하므로써, 패드나 솔더 볼 위치 변경에 즉각적인 대응이 가능하다. 즉, 설계 변경이 매우 간단해진다.
이상에서는 본 발명에 의한 패키지를 실시하기 위한 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.

Claims (7)

  1. 회로가 구성되는 상부면에 홈부가 형성되고, 상기 홈부의 저면 중앙에 한 쌍의 본딩 패드가 배치된 반도체 칩;
    일측이 상기 본딩 패드에 연결된 금속 와이어;
    상기 금속 와이어의 타측이 돌출되도록, 상기 홈부내를 몰딩하는 봉지제;
    상기 봉지제에서 돌출된 금속 와이어에 부착되는 범프; 및
    상기 범프에 부착된 솔더 볼을 포함하는 볼 그리드 어레이 패키지.
  2. 제 1 항에 있어서, 상기 홈부의 저면 양측에 절연 패드가 부착되고, 상기 절연 패드에 금속 와이어의 타측이 연결되며, 상기 금속 와이어의 중간부가 봉지제에서 돌출된 것을 특징으로 하는 볼 그리드 어레이 패키지.
  3. 제 2 항에 있어서, 상기 절연 패드는 반도체 칩에 부착되고, 상부면에 홈부가 형성된 접착층과; 상기 접착층의 홈부내에 형성되어, 상기 금속 와이어가 연결된 금속층을 포함하는 것을 특징으로 하는 볼 그리드 어레이 패키지.
  4. 제 3 항에 있어서, 상기 금속층의 표면은 접착층의 양측 상단과 동일 평면이고, 상기 금속층의 표면에 금속 와이어가 연결되는 금속박막이 형성된 것을 특징으로 하는 볼 그리드 어레이 패키지.
  5. 제 3 항 또는 제 4 항에 있어서, 상기 접착층의 재질은 폴리머 계열의 폴리이미드이고, 상기 금속층의 재질은 알루미늄, 동, 니켈, 금, 은, 코발트, 또는 주석 중 하나이거나 이들 중 수 개로 이루어진 합금이며, 상기 금속박막의 재질은 은, 금 또는 크롬 중 하나인 것을 특징으로 하는 볼 그리드 어레이 패키지.
  6. 회로가 구성되는 상부면에 홈부가 형성된 반도체 칩;
    상기 반도체 칩의 홈부 저면 중앙에 형성된 한 쌍의 본딩 패드;
    상기 반도체 칩의 홈부 저면 양측에 부착된 한 쌍의 절연 패드;
    상기 절연 패드와 본딩 패드를 연결하는 금속 와이어;
    상기 반도체 칩의 양측 상단에 부착되고, 상기 금속 와이어의 중간부가 인출되는 인출홈이 형성된 캡;
    상기 캡의 인출홈을 통해 노출된 금속 와이어에 부착되는 범프; 및
    상기 범프에 부착된 솔더 볼을 포함하는 볼 그리드 어레이 패키지.
  7. 서로의 측면이 연결된 상태인 각 반도체 칩의 상부면에 홈부를 형성하는 단계;
    상기 각 홈부의 저면에 한 쌍의 본딩 패드를 형성하는 단계;
    금속 와이어로 어느 한 홈부의 본딩 패드와 이웃하는 홈부의 본딩 패드를 연결하는 단계;
    상기 각 반도체 칩의 홈부를 봉지제로 몰딩하는 단계;
    상기 각 반도체 칩을 절단하여 개개의 칩으로 분리함과 동시에 상기 금속 와이어의 중간부를 절단하는 단계;
    상기 반도체 칩의 양측 상단 높이를 기준으로 봉지제를 그라인딩하여, 상기 금속 와이어의 절단된 부분을 봉지제에서 돌출시키는 단계;
    상기 봉지제에서 돌출된 금속 와이어 부분에 범프를 부착하는 단계; 및
    상기 범프에 솔더 볼을 부착하는 단계를 포함하는 볼 그리드 어레이 패키지 제조 방법.
KR1019980025015A 1998-06-29 1998-06-29 볼 그리드 어레이 패키지 및 그의 제조 방법 Expired - Fee Related KR100265563B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019980025015A KR100265563B1 (ko) 1998-06-29 1998-06-29 볼 그리드 어레이 패키지 및 그의 제조 방법
TW088110395A TW419761B (en) 1998-06-29 1999-06-22 Chip size package and method of fabricating the same
US09/339,094 US6211461B1 (en) 1998-06-29 1999-06-23 Chip size package and method of fabricating the same
CNB991088646A CN1211854C (zh) 1998-06-29 1999-06-28 芯片尺寸封装及其制造方法
JP18393299A JP4400898B2 (ja) 1998-06-29 1999-06-29 チップサイズパッケージ及びその製造方法
GB9915229A GB2339334B (en) 1998-06-29 1999-06-29 Chip size package and method of fabricating the same
US09/782,699 US6519846B2 (en) 1998-06-29 2001-02-13 Chip size package and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980025015A KR100265563B1 (ko) 1998-06-29 1998-06-29 볼 그리드 어레이 패키지 및 그의 제조 방법

Publications (2)

Publication Number Publication Date
KR20000003743A KR20000003743A (ko) 2000-01-25
KR100265563B1 true KR100265563B1 (ko) 2000-09-15

Family

ID=19541527

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980025015A Expired - Fee Related KR100265563B1 (ko) 1998-06-29 1998-06-29 볼 그리드 어레이 패키지 및 그의 제조 방법

Country Status (6)

Country Link
US (2) US6211461B1 (ko)
JP (1) JP4400898B2 (ko)
KR (1) KR100265563B1 (ko)
CN (1) CN1211854C (ko)
GB (1) GB2339334B (ko)
TW (1) TW419761B (ko)

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW452873B (en) * 2000-06-21 2001-09-01 Advanced Semiconductor Eng Manufacturing method of wafer scale semiconductor package structure
KR100649443B1 (ko) * 2001-01-10 2006-11-24 삼성전자주식회사 노출된 와이어를 갖는 반도체 칩 패키지와 그 반도체 칩패키지가 기판에 부착된 구조
KR100422346B1 (ko) * 2001-06-12 2004-03-12 주식회사 하이닉스반도체 칩크기 패키지 구조 및 그 제조방법
DE10209922A1 (de) * 2002-03-07 2003-10-02 Infineon Technologies Ag Elektronisches Modul, Nutzen mit zu vereinzelnden elektronischen Modulen und Verfahren zu deren Herstellung
US7262074B2 (en) * 2002-07-08 2007-08-28 Micron Technology, Inc. Methods of fabricating underfilled, encapsulated semiconductor die assemblies
US6650016B1 (en) * 2002-10-01 2003-11-18 International Business Machines Corporation Selective C4 connection in IC packaging
US20040075170A1 (en) * 2002-10-21 2004-04-22 Yinon Degani High frequency integrated circuits
CN101408688B (zh) * 2003-03-31 2011-10-12 德塞拉互连材料股份有限公司 布线电路基板、布线电路基板的制造方法和电路模块
US6890836B2 (en) * 2003-05-23 2005-05-10 Texas Instruments Incorporated Scribe street width reduction by deep trench and shallow saw cut
US7173231B2 (en) * 2003-09-16 2007-02-06 Wen Ching Chen Chip scale package structure for an image sensor
US20060216868A1 (en) * 2005-03-25 2006-09-28 Advanced Semiconductor Engineering Inc. Package structure and fabrication thereof
KR100713928B1 (ko) 2006-02-08 2007-05-07 주식회사 하이닉스반도체 반도체 칩 패키지
SG148901A1 (en) * 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
DE102008046188B4 (de) * 2008-09-06 2011-06-01 Qimonda Ag Chip-Leiterplatten-Anordnung und Verfahren zum Herstellen einer Chip-Leiterplatten-Anordnung
MY149251A (en) * 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
TWI417973B (zh) * 2011-07-11 2013-12-01 矽品精密工業股份有限公司 具微機電元件之封裝結構之製法
CN102569232A (zh) * 2012-01-13 2012-07-11 中国科学院上海微系统与信息技术研究所 圆片级芯片尺寸封装应力缓冲结构
KR101629273B1 (ko) * 2014-12-24 2016-06-14 주식회사 에스에프에이반도체 반도체 연결패드 상의 범프 구조물 및 이의 형성방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987000686A1 (en) 1985-07-16 1987-01-29 Nippon Telegraph And Telephone Corporation Connection terminals between substrates and method of producing the same
US4939316A (en) * 1988-10-05 1990-07-03 Olin Corporation Aluminum alloy semiconductor packages
US5134539A (en) * 1990-12-17 1992-07-28 Nchip, Inc. Multichip module having integral decoupling capacitor
US5214844A (en) * 1990-12-17 1993-06-01 Nchip, Inc. Method of assembling integrated circuits to a silicon board
US5490324A (en) 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
US5388327A (en) 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5772451A (en) * 1993-11-16 1998-06-30 Form Factor, Inc. Sockets for electronic components and methods of connecting to electronic components
KR970000214B1 (ko) 1993-11-18 1997-01-06 삼성전자 주식회사 반도체 장치 및 그 제조방법
US5796589A (en) * 1995-12-20 1998-08-18 Intel Corporation Ball grid array integrated circuit package that has vias located within the solder pads of a package
WO1998028955A2 (en) * 1996-12-13 1998-07-02 Tessera, Inc. Microelectric assembly fabrication with terminal formation
US5990565A (en) * 1998-10-28 1999-11-23 Chang; Meilien Flip chip package

Cited By (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8531020B2 (en) 2004-11-03 2013-09-10 Tessera, Inc. Stacked packaging improvements
US8927337B2 (en) 2004-11-03 2015-01-06 Tessera, Inc. Stacked packaging improvements
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9123664B2 (en) 2010-07-19 2015-09-01 Tessera, Inc. Stackable molded microelectronic packages
US8907466B2 (en) 2010-07-19 2014-12-09 Tessera, Inc. Stackable molded microelectronic packages
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8659164B2 (en) 2010-11-15 2014-02-25 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8957527B2 (en) 2010-11-15 2015-02-17 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8637991B2 (en) 2010-11-15 2014-01-28 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11424211B2 (en) 2011-05-03 2022-08-23 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
US9041227B2 (en) 2011-10-17 2015-05-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9252122B2 (en) 2011-10-17 2016-02-02 Invensas Corporation Package-on-package assembly with wire bond vias
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US11189595B2 (en) 2011-10-17 2021-11-30 Invensas Corporation Package-on-package assembly with wire bond vias
US11735563B2 (en) 2011-10-17 2023-08-22 Invensas Llc Package-on-package assembly with wire bond vias
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10510659B2 (en) 2012-05-22 2019-12-17 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9917073B2 (en) 2012-07-31 2018-03-13 Invensas Corporation Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9095074B2 (en) 2012-12-20 2015-07-28 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9633979B2 (en) 2013-07-15 2017-04-25 Invensas Corporation Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9893033B2 (en) 2013-11-12 2018-02-13 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10629567B2 (en) 2013-11-22 2020-04-21 Invensas Corporation Multiple plated via arrays of different wire heights on same substrate
USRE49987E1 (en) 2013-11-22 2024-05-28 Invensas Llc Multiple plated via arrays of different wire heights on a same substrate
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9837330B2 (en) 2014-01-17 2017-12-05 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US11404338B2 (en) 2014-01-17 2022-08-02 Invensas Corporation Fine pitch bva using reconstituted wafer with area array accessible for testing
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US11990382B2 (en) 2014-01-17 2024-05-21 Adeia Semiconductor Technologies Llc Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9356006B2 (en) 2014-03-31 2016-05-31 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9812433B2 (en) 2014-03-31 2017-11-07 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10032647B2 (en) 2014-05-29 2018-07-24 Invensas Corporation Low CTE component with wire bond interconnects
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US10475726B2 (en) 2014-05-29 2019-11-12 Invensas Corporation Low CTE component with wire bond interconnects
US9947641B2 (en) 2014-05-30 2018-04-17 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US10806036B2 (en) 2015-03-05 2020-10-13 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10559537B2 (en) 2015-10-12 2020-02-11 Invensas Corporation Wire bond wires for interference shielding
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US11462483B2 (en) 2015-10-12 2022-10-04 Invensas Llc Wire bond wires for interference shielding
US10115678B2 (en) 2015-10-12 2018-10-30 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10658302B2 (en) 2016-07-29 2020-05-19 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor

Also Published As

Publication number Publication date
GB9915229D0 (en) 1999-09-01
JP2000036549A (ja) 2000-02-02
US20010035294A1 (en) 2001-11-01
KR20000003743A (ko) 2000-01-25
CN1211854C (zh) 2005-07-20
US6211461B1 (en) 2001-04-03
TW419761B (en) 2001-01-21
JP4400898B2 (ja) 2010-01-20
CN1241815A (zh) 2000-01-19
US6519846B2 (en) 2003-02-18
GB2339334B (en) 2003-05-07
GB2339334A (en) 2000-01-19

Similar Documents

Publication Publication Date Title
KR100265563B1 (ko) 볼 그리드 어레이 패키지 및 그의 제조 방법
KR100381837B1 (ko) 플라스틱 집적회로 장치 패키지와 마이크로 리드프레임 및
US8102037B2 (en) Leadframe for semiconductor package
US5953589A (en) Ball grid array semiconductor package with solder balls fused on printed circuit board and method for fabricating the same
US8278150B2 (en) Stackable packages for three-dimensional packaging of semiconductor dice
US6525406B1 (en) Semiconductor device having increased moisture path and increased solder joint strength
US7808084B1 (en) Semiconductor package with half-etched locking features
US8823152B1 (en) Semiconductor device with increased I/O leadframe
US6677219B2 (en) Method of forming a ball grid array package
KR100299384B1 (ko) 볼 그리드 어레이 패키지
US8299602B1 (en) Semiconductor device including leadframe with increased I/O
KR20060121823A (ko) 가역 리드리스 패키지, 및 이를 제조 및 사용하기 위한방법
US8089145B1 (en) Semiconductor device including increased capacity leadframe
US20040238923A1 (en) Surface-mount-enhanced lead frame and method for fabricating semiconductor package with the same
US7495255B2 (en) Test pads on flash memory cards
US20020003308A1 (en) Semiconductor chip package and method for fabricating the same
US6984877B2 (en) Bumped chip carrier package using lead frame and method for manufacturing the same
KR100587033B1 (ko) 칩 사이즈 패키지의 제조 방법
KR100575859B1 (ko) 볼 그리드 어레이 패키지
KR100247641B1 (ko) 적층형 볼 그리드 어레이 패키지 및 그의 제조방법
KR20010004610A (ko) 트랜스퍼 몰드형 칩 사이즈 패키지 및 그의 제조 방법
KR20010004527A (ko) 칩 스캐일 패키지
KR20000013555U (ko) 볼 그리드 어레이 패키지
KR100290783B1 (ko) 반도체 패키지
KR20010063610A (ko) 칩 스캐일 패키지

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19980629

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19980629

Comment text: Request for Examination of Application

PG1501 Laying open of application
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20000517

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20000615

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20000616

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20030520

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20040331

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20050523

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20060522

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20070518

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20080527

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20090526

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20100524

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20110526

Start annual number: 12

End annual number: 12

FPAY Annual fee payment

Payment date: 20120524

Year of fee payment: 13

PR1001 Payment of annual fee

Payment date: 20120524

Start annual number: 13

End annual number: 13

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee