[go: up one dir, main page]

WO2023005648A1 - 像素电路及其驱动方法、阵列基板和显示装置 - Google Patents

像素电路及其驱动方法、阵列基板和显示装置 Download PDF

Info

Publication number
WO2023005648A1
WO2023005648A1 PCT/CN2022/104828 CN2022104828W WO2023005648A1 WO 2023005648 A1 WO2023005648 A1 WO 2023005648A1 CN 2022104828 W CN2022104828 W CN 2022104828W WO 2023005648 A1 WO2023005648 A1 WO 2023005648A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
transistor
terminal
initialization
control
Prior art date
Application number
PCT/CN2022/104828
Other languages
English (en)
French (fr)
Inventor
冯宇
刘利宾
董甜
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/273,695 priority Critical patent/US12118939B2/en
Publication of WO2023005648A1 publication Critical patent/WO2023005648A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, an array substrate and a display device.
  • Organic light emitting diode Organic Light Emitting Diode, OLED
  • OLED Organic Light Emitting Diode
  • Pixel circuits in OLED display devices generally adopt a matrix driving method, which is divided into active matrix (Active Matrix, AM) driving and passive matrix (Passive Matrix, PM) driving according to whether switching components are introduced into each pixel unit.
  • PMOLED has a simple process and low cost, it cannot meet the needs of high-resolution and large-size displays due to shortcomings such as crosstalk, high power consumption, and low lifespan.
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. Through the driving control of the thin film transistors and storage capacitors, the control of the current flowing through the OLED is realized, so that the OLED glow.
  • AMOLED Compared with PMOLED, AMOLED requires less driving current, lower power consumption, and longer life, which can meet the needs of large-size display with high resolution and multiple gray scales. At the same time, AMOLED has obvious advantages in terms of viewing angle, color reproduction, power consumption, and response time, and is suitable for display devices with high information content and high resolution.
  • At least one embodiment of the present disclosure provides a pixel circuit, including: a drive circuit, a data writing circuit, a first light emission control circuit, a second light emission control circuit, a first initialization circuit, a second initialization circuit, and an energy storage circuit.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light;
  • the data writing circuit is It is configured to write a data signal into the control terminal of the driving circuit under the control of the first scanning signal;
  • the first light emission control circuit is configured to write the first power supply of the first power supply terminal A voltage is applied to the first end of the drive circuit;
  • the second light emission control circuit is configured to apply the drive current from the second end of the drive circuit to the light emission control circuit under the control of a second light emission control signal element;
  • the first initialization circuit is configured to apply a first initialization voltage to the control terminal of the drive circuit under the control of a first reset control signal;
  • the second initialization circuit is configured to Applying a second initialization voltage to the second terminal of the drive circuit under the control of the drive circuit;
  • the storage circuit is configured to store the data signal written to the control terminal of the drive circuit, and the
  • the semiconductor material of the first active layer of the first transistor is the same as the semiconductor material of the second active layer of the second transistor.
  • the semiconductor material of the first active layer of the first transistor is an oxide semiconductor; the semiconductor material of the third active layer of the third transistor is polysilicon.
  • the oxide semiconductor is an indium oxide semiconductor material
  • the polysilicon semiconductor material is a low temperature polysilicon semiconductor material.
  • the first light emission control circuit, the second light emission control circuit, and the second initialization circuit respectively include the semiconductor material of the active layer of the transistor and the The semiconductor material of the third active layer of the third transistor is the same and arranged in the same layer.
  • the energy storage circuit includes a first capacitor and a second capacitor, and the first capacitor is electrically connected to the control terminal of the driving circuit and the second capacitor of the driving circuit.
  • the second sub-capacitor is electrically connected between the first end of the driving circuit and the first power supply voltage end, and the first capacitor is electrically connected to the first end of the driving circuit
  • the electrodes of the second capacitor are electrically connected to the electrodes electrically connected to the first end of the drive circuit.
  • the reset circuit is configured to couple the change of the first light emission control signal to the first terminal of the driving circuit.
  • the reset circuit includes a third capacitor, and the third capacitor is electrically connected between the control terminal of the first light emission control circuit and the first terminal of the driving circuit. between.
  • the third capacitor includes a first capacitor electrode and a second capacitor electrode that are opposite to each other and located on different layers, and the first capacitor electrode is connected to the third active electrode of the third transistor.
  • the layer is integrally arranged, or the first capacitor electrode is electrically connected to the third active layer of the third transistor through a hole, and the second capacitor electrode is integrally arranged with the control terminal of the first light emission control circuit.
  • the first initialization voltage and the second initialization voltage are different from each other.
  • At least one embodiment of the present disclosure further provides an array substrate, including a plurality of pixel units arranged in an array, and each pixel unit includes the pixel circuit provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device, including the array substrate provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method for driving a pixel circuit, the method includes a first operation period, and the first operation period includes a reset phase, a sampling phase, a writing phase, and a light emitting phase, wherein, in the In the reset phase, the first initialization circuit is turned on under the control of the first reset control signal, and the first initialization voltage is applied to the control terminal of the driving circuit, so that the second initialization circuit is Under the control of the second reset control signal, the second initialization voltage is applied to the second terminal of the driving circuit; in the sampling phase, the first light-emitting control circuit and the second light-emitting The control circuit is turned off, and the first initialization circuit is kept on under the control of the first reset control signal, and the first initialization voltage is applied to the control terminal of the driving circuit, so that the second initialization circuit The circuit remains turned on under the control of the second reset control signal, and the second initialization voltage is applied to the second terminal of the driving circuit; in the writing phase, the first initialization circuit, the
  • the driving method provided by an embodiment of the present disclosure further includes: a second operation period, the second operation period is immediately after the first operation period in time, the first lighting control signal, the The second lighting control signal and the second reset control signal have a first frequency, the first reset control signal and the first scan signal have a second frequency, the first frequency is greater than the second frequency, and Compared with the first operation period, in the second operation period, the first light emission control signal, the second light emission control signal and the second reset control signal enter different periods, and the first The reset control signal and the first scanning signal are still in the same cycle.
  • the first frequency is greater than 30 Hz
  • the second frequency is 1 Hz ⁇ 10 Hz.
  • the first light emission control circuit in the reset phase, is also turned on under the control of the first light emission control signal, and the first The power supply voltage is applied to the first end of the driving circuit, and the second light emission control circuit is turned on under the control of the second light emission control signal, and the second initialization signal from the second initialization circuit A voltage is applied to the light emitting element.
  • the second initialization voltage prevents the light emitting element from being turned on.
  • FIG. 1 is a schematic block diagram of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 1;
  • FIG. 3 is a flowchart of a method for driving a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 4A is a timing diagram of a driving method of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 4B is a timing comparison diagram of a high-frequency drive and a low-frequency drive provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic block diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 5;
  • FIG. 7A is an exemplary partial layout of the pixel circuit shown in FIG. 2 provided by an embodiment of the present disclosure
  • FIG. 7B is a schematic stacked view of the pixel circuit shown in FIG. 7A;
  • FIG. 7C is a schematic layout of the first active layer in the layout shown in FIG. 7A;
  • FIG. 7D is a schematic layout of the first conductive layer in the layout shown in FIG. 7A;
  • FIG. 7E is a schematic layout of the second conductive layer in the layout shown in FIG. 7A;
  • FIG. 7F is a schematic layout of the third conductive layer in the layout shown in FIG. 7A;
  • FIG. 7G and FIG. 7H are exemplary partial layouts of a pixel circuit shown in FIG. 6 provided by an embodiment of the present disclosure
  • FIG. 7I is a stacked schematic diagram of the pixel circuit shown in FIG. 7H;
  • FIG. 7J is another schematic diagram of stacking of the pixel circuit shown in FIG. 7H;
  • FIG. 7K is another exemplary partial layout of the pixel circuit shown in FIG. 6 provided by an embodiment of the present disclosure.
  • FIG. 7L is an exemplary laminated schematic diagram of the pixel circuit shown in FIG. 7K;
  • FIG. 7M is another exemplary partial layout of the pixel circuit shown in FIG. 6 provided by an embodiment of the present disclosure.
  • FIG. 7N is an exemplary stacked structure of the pixel circuit shown in FIG. 7M.
  • FIG. 8 is a schematic diagram of an array substrate and a display device provided by an embodiment of the present disclosure.
  • An OLED display device usually includes a plurality of pixel units arranged in an array, and each pixel unit can realize the basic function of driving OLED to emit light through a pixel circuit.
  • the basic pixel circuit used in an AMOLED display device is usually a 2T1C pixel circuit, that is, two TFTs (Thin-film transistor, thin film transistor) and a storage capacitor Cs are used to realize the basic function of driving OLED to emit light.
  • AMOLED pixel circuits are not limited to the above pixel circuits, and may also be pixel circuits of other structures, such as 4T1C, 4T2C, 6T1C or 8T2C pixel circuits.
  • low-frequency signals can be used to drive the pixel circuit.
  • use of the pixel circuit in order to reduce the power consumption of OLED, low-frequency signals can be used to drive the pixel circuit.
  • At least one embodiment of the present disclosure provides a pixel circuit, including a driving circuit, a data writing circuit, a first light emission control circuit, a second light emission control circuit, a first initialization circuit, a second initialization circuit and an energy storage circuit.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving the light emitting element to emit light.
  • the data writing circuit is configured to write the data signal into the control terminal of the driving circuit under the control of the first scan signal.
  • the first light emission control circuit is configured to apply the first power supply voltage of the first power supply terminal to the first terminal of the driving circuit under the control of the first light emission control signal.
  • the second light emission control circuit is configured to apply the driving current from the second terminal of the driving circuit to the light emitting element under the control of the second light emission control signal.
  • the first initialization circuit is configured to apply the first initialization voltage to the control terminal of the driving circuit under the control of the first reset control signal.
  • the second initialization circuit is configured to apply a second initialization voltage to the second terminal of the driving circuit under the control of the second reset control signal.
  • the storage circuit is configured to store the data signal written to the control terminal of the driving circuit.
  • the first initialization circuit includes a first transistor, the data writing circuit includes a second transistor, and the drive circuit includes a third transistor, and the leakage current characteristic of the semiconductor material of the first active layer of the first transistor is smaller than that of the third active layer of the third transistor.
  • the leakage current characteristic of the semiconductor material of the source layer; the leakage current characteristic of the semiconductor material of the second active layer of the second transistor is smaller than the leakage current characteristic of the semiconductor material of the third active layer of the third transistor.
  • At least one embodiment of the present disclosure further provides a driving method corresponding to the above pixel circuit, an array substrate and a display device.
  • the leakage current characteristics of the semiconductor material of the first active layer of the first transistor and the leakage current characteristics of the semiconductor material of the second active layer of the second transistor are respectively smaller than the first transistor.
  • the leakage current characteristics of the semiconductor material of the third active layer of the three transistors so the leakage current on the leakage path of the energy storage circuit is lower, and the voltage retention rate of the control terminal of the driving circuit is improved, so that low-frequency driving can be realized. That is, the pixel circuit can at least partly avoid the flickering phenomenon under low-frequency driving.
  • an example of an embodiment of the present disclosure provides a pixel circuit 10 , for example, the pixel circuit 10 is used for a sub-pixel of an OLED display device.
  • the pixel circuit 10 includes a drive circuit 100, a data writing circuit 200, a first light emission control circuit 300, a second light emission control circuit 400, a first initialization circuit 500, a second initialization circuit 600 and an energy storage circuit. 700.
  • the pixel circuit 10 controls, for example, the light emitting element 800 to emit light.
  • the driving circuit 100 includes a first terminal 110, a second terminal 120 and a control terminal 130, and the driving circuit 100 is configured to control the driving current flowing through the first terminal 110 and the second terminal 120 for driving the light emitting element 800 to emit light.
  • the control terminal 130 of the driving circuit 100 is connected to the first node N1
  • the first terminal 110 of the driving circuit 100 is connected to the second node N2
  • the second terminal 120 of the driving circuit 100 is connected to the third node N3.
  • the driving circuit 100 can provide a driving current to the light-emitting element 800 to drive the light-emitting element 800 to emit light, and the driving current can be changed according to the written data signal (described in detail below), so that the "gray degree" glow.
  • the light emitting element 800 may adopt an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), an inorganic light emitting diode, etc., and embodiments of the present disclosure include but are not limited thereto.
  • the light-emitting element is configured such that one terminal is connected to the second voltage terminal VSS (for example, providing a low level, such as grounding), and embodiments of the present disclosure include but are not limited to this situation.
  • the data writing circuit 200 is configured to write the data signal Vdata into the control terminal 130 of the driving circuit 100 under the control of the first scanning signal Gate_N.
  • the data writing circuit 200 is connected to the control terminal 130 of the driving circuit 100 , the first scan line (the first scan signal terminal Gate_N) and the data line (the data signal terminal Vdata).
  • the first scan signal from the first scan signal terminal Gate_N is applied to the data writing circuit 200 to control whether the data writing circuit 200 is turned on.
  • the data writing circuit 200 is turned on, the data signal Vdata from the data line The data is written into the control terminal 130 of the driving circuit 100 via the data writing circuit 200 .
  • the first light emission control circuit 300 is configured to apply the first power supply voltage VDD of the first power supply terminal to the first terminal 110 of the driving circuit 100 under the control of the first light emission control signal EM1 .
  • the first lighting control circuit 300 is connected to the first terminal 110 of the driving circuit 100 , the energy storage circuit 700 and the first power supply terminal VDD.
  • the first light emission control signal EM1 is applied to the first light emission control circuit 300 to control whether the first light emission control circuit 300 is turned on.
  • the first power supply voltage VDD at the first power supply terminal is applied to the first terminal 110 of the driving circuit 100 .
  • the first light-emitting control circuit 300 can be turned on in response to the first light-emitting control signal EM1, so that the first power supply voltage VDD can be applied to the first terminal 110 of the driving circuit 100, when the driving circuit 100 is turned on , the driving current flowing through the driving circuit 100 is generated in the pixel circuit.
  • the first power supply voltage VDD may be a driving voltage, such as a high voltage (higher than the second voltage VSS).
  • the second light emission control circuit 400 is configured to apply the driving current from the second terminal 120 of the driving circuit 100 to the light emitting element 800 under the control of the second light emission control signal EM2 .
  • the second light emission control circuit 400 is connected with the second terminal 120 of the driving circuit 100 and the light emitting element 800 .
  • the second light emission control signal EM2 is applied to the second light emission control circuit 400 to control whether the second light emission control circuit 400 is turned on or not.
  • the second light-emitting control circuit 400 can be turned on in response to the second light-emitting control signal EM2, so that the driving current from the driving circuit 100 can be applied to the light-emitting element 800 to provide a driving voltage, thereby driving the light-emitting element to emit light.
  • the first initialization circuit 500 is configured to apply the first initialization voltage Vinit1 to the control terminal 130 of the driving circuit 100 under the control of the first reset control signal Re_N.
  • the first initialization circuit 500 is connected to the first node N1 to be connected to the control terminal 130 of the drive circuit 100, and is connected to the first reset control signal line (the first reset control signal terminal Re_N) and the first initialization voltage line (the first reset control signal terminal Re_N).
  • An initialization voltage terminal Vinit1) is connected.
  • the first initialization circuit 500 can be turned on in response to the first reset control signal Re_N, so that the first initialization voltage Vinit1 can be applied to the first node to reset the control terminal of the driving circuit 100, thereby eliminating For example, the influence of the data signal of the control terminal applied to the driving circuit 100 during the display process of the previous frame in the OLED display panel or display device.
  • the second initialization circuit 600 is configured to apply the second initialization voltage Vinit2 to the second terminal 120 of the driving circuit 100 under the control of the second reset control signal Re_P.
  • the second initialization circuit 600 is connected to the third node N3 to be connected to the second terminal 120 of the driving circuit 100, and is connected to the second reset control signal line (the first reset control signal terminal Re_P) and the second initialization voltage line ( The first initialization voltage terminal Vinit2) is connected.
  • the second initialization circuit 600 in the reset phase, can be turned on in response to the second reset control signal Re_P, so that the second initialization voltage Vinit2 can be applied to the second node, thereby resetting the second terminal 120 of the driving circuit 100 .
  • the storage circuit 700 is configured to store the data signal Vdata written to the control terminal 130 of the driving circuit 100 .
  • the energy storage circuit 700 is connected to the first node N1 and the first power supply terminal VDD.
  • the first initialization circuit includes a first transistor
  • the data writing circuit includes a second transistor
  • the driving circuit includes a third transistor
  • the leakage current characteristic of the semiconductor material of the first active layer of the first transistor is smaller than that of the first transistor.
  • the leakage current characteristic of the semiconductive material of the third active layer of the three transistors, the leakage current characteristic of the semiconductive material of the second active layer of the second transistor is smaller than the drain of the semiconductive material of the third active layer of the third transistor current characteristics.
  • the data signal stored in the energy storage circuit It can be maintained for a longer time, so that the magnitude of the driving current controlled by the driving circuit is more stable, and thus the display panel or display device using the pixel circuit can achieve better display quality.
  • the frequency of refreshing the pixel circuit during the display process can be reduced, thereby reducing the power consumption of the display panel or display device.
  • the leakage current characteristic of the semiconductor material of the active layer of the first transistor and the second transistor is smaller than the leakage current characteristic of the semiconductor material of the active layer of the third transistor, and the leakage current characteristic of the active layer of the first transistor and the second transistor
  • the leakage current characteristic of the semiconductor material is also smaller than that of the semiconductor material of the active layer of the transistor included in any one of the second initialization circuit, the first light emission control transistor, and the second light emission control transistor.
  • the leakage current characteristics of the semiconductor material of the active layer of the first transistor and the second transistor are not compared with the leakage current characteristics of the semiconductor material of the active layer of the third transistor (for example, both substantially equal, or the former is greater than the latter), but make the leakage current characteristics of the semiconductor material of the active layer of the first transistor and the second transistor smaller than any of the second initialization circuit, the first light emission control transistor, and the second light emission control transistor A leakage current characteristic of the semiconducting material comprising the active layer of the transistor.
  • leakage current characteristic refers to the transistor's effective leakage current when the transistors involved have the same size (including channel width-to-length ratio) and the same voltage (including gate voltage, source voltage, and drain voltage) is applied. The magnitude of the leakage current generated in the source layer.
  • the first node N1, the second node N2 and the third node N3 do not represent actual components, but represent the confluence of related circuit connections in the circuit diagram.
  • the symbol Vdata can represent both the data signal terminal and the level of the data signal.
  • the symbols Vinit1 and Vinit2 can represent both the reset voltage terminal and the reset voltage
  • the symbol VDD can represent both the first power supply voltage terminal and the first power supply voltage
  • the symbol VSS can represent both the second voltage terminal and the second voltage.
  • the first power supply voltage terminal VDD for example, maintains the input of a DC high level signal
  • the DC high level is called the first power supply voltage
  • the second voltage terminal VSS for example, maintains the input of a DC low level signal.
  • level signal, the DC low level is referred to as a second voltage, which is lower than the first power supply voltage.
  • the semiconductor material of the first active layer of the first transistor is the same as the semiconductor material of the second active layer of the second transistor, and the leakage current characteristic of the semiconductor material is smaller than that of the first transistor. Leakage current characteristics of the semiconductor material of the third active layer of the three-transistor.
  • the semiconductor material of the first active layer of the first transistor and the semiconductor material of the second active layer of the second transistor may also be different, but the semiconductor material of the first active layer Both the leakage current characteristics of the material and the leakage current characteristics of the semiconductor material of the second active layer are smaller than the leakage current characteristics of the semiconductor material of the third active layer.
  • the semiconductor material of the first active layer of the first transistor and the semiconductor material of the second active layer of the second transistor are both oxide semiconductors
  • the semiconductor material of the third active layer of the third transistor is polysilicon.
  • the leakage current characteristic of the oxide semiconductor is smaller than that of the polysilicon semiconductor material, which can reduce the leakage current on the leakage current path, thereby at least partly avoiding the occurrence of the flicker screen.
  • the oxide semiconductor is an indium oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) or doped IGZO;
  • the polysilicon semiconductor material is a low-temperature polysilicon semiconductor material or a high-temperature polysilicon semiconductor material, usually in the In the process of crystallizing amorphous silicon to obtain polysilicon, if the operating temperature is lower than 600 degrees Celsius, the obtained polysilicon is called low-temperature polysilicon, otherwise it is called high-temperature polysilicon.
  • the pixel circuit 10 may include both N-type transistors and P-type transistors.
  • the first transistor and the second transistor may be N-type transistors
  • the third transistor may be a P-type transistor.
  • the pixel circuit 10 only uses N-type transistors, and the resolution of the display panel or display device can be increased due to the small size of the N-type transistors.
  • the first transistor and the second transistor are N-type transistors
  • the third transistor is an N-type transistor, but the semiconductor material (such as an oxide semiconductor material) of the active layer of the first transistor and the second transistor is different from that of the third transistor.
  • the semiconductor material of the active layer (such as polysilicon semiconductor material).
  • the leakage current of the N-type transistors corresponding to the first transistor and the second transistor is small, it can overcome the problem when the pixel circuit is used for low-frequency driving. Flicker phenomenon; on the other hand, since the leakage current of the N-type transistor corresponding to the first transistor and the second transistor is relatively small, the aging problem of the transistor is alleviated during the use of the display panel or display device.
  • the first light emission control circuit, the second light emission control circuit, and the second initialization circuit respectively include the semiconductor material of the active layer of the transistor and the semiconductor material of the third active layer of the third transistor.
  • the materials are the same and set in the same layer.
  • the semiconducting material of the active layer of the transistor and the semiconducting material of the third active layer of the third transistor included in the first light emitting control circuit, the second light emitting control circuit and the second initialization circuit are all low temperature polysilicon semiconductor materials , such as N-type or P-type low-temperature polysilicon semiconductor materials.
  • the semiconductor materials of the active layers of the first transistor and the second transistor are N-type oxide semiconductor materials and are arranged in the same layer. In this way, the manufacturing process of the pixel circuit can be simplified and the manufacturing cost can be reduced.
  • the pixel circuit 10 shown in FIG. 1 may be the pixel circuit shown in FIG. 2 .
  • the pixel circuit 10 includes first to sixth transistors T1 , T2 , T3 , T4 , T5 , T6 and includes a first capacitor C1 and a second capacitor C2 .
  • the third transistor T3 is used as a driving transistor, and the other first, second, and fourth to sixth transistors are used as switching transistors.
  • the light-emitting element L1 can be various types of OLEDs, such as top emission, bottom emission, double-side emission, etc., and can emit red, green, blue, or white light, which is not limited by embodiments of the present disclosure.
  • the first reset control circuit 500 may be implemented as a first transistor T1.
  • the gate of the first transistor T1 is connected to the first reset control signal terminal Re_N to receive the first reset control signal Re_N.
  • the first electrode of the first transistor T1 is connected to the first initialization voltage terminal Vinit1 to receive the first initialization voltage Vinit1 .
  • the second pole of the first transistor T1 is connected to the control terminal 130 (the first node N1 ) of the driving circuit 100 .
  • the first transistor T1 is an N-type transistor, for example, the semiconductor material of the first active layer is an oxide semiconductor.
  • the N-type transistor is turned on in response to a high-level signal, and the following embodiments are the same and will not be repeated here.
  • the data writing circuit 200 may be implemented as a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan signal terminal Gate_N to receive the first scan signal Gate_N.
  • the first electrode of the second transistor T2 is connected to the data signal terminal Vdata to receive the data signal Vdata.
  • the second pole of the second transistor T2 is connected to the control terminal 130 (the first node N1 ) of the driving circuit 100 .
  • the second transistor T2 is an N-type transistor, for example, the semiconductor material of the second active layer is an oxide semiconductor.
  • the driving circuit 100 can be realized as a third transistor T3.
  • the gate of the third transistor T3 serves as the control terminal 130 of the drive circuit 100 and is connected to the first node N1; the first pole of the first transistor T1 serves as the first terminal 110 of the drive circuit 100 and is connected to the second node N2;
  • the second pole of the transistor T1 serves as the second terminal 120 of the driving circuit 100 and is connected to the third node N3.
  • the third transistor T3 is a P-type transistor, for example, the semiconductor material of the third active layer is a low temperature polysilicon semiconductor material.
  • the P-type transistor is turned on in response to a low-level signal, and the following embodiments are the same and will not be repeated here.
  • the second reset control circuit 600 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the second reset control signal terminal Re_P to receive the second reset control signal Re_P.
  • the first electrode of the fourth transistor T4 is connected to the second initialization voltage terminal Vinit2 to receive the second initialization voltage Vinit2.
  • the second pole of the fourth transistor T4 is connected to the second terminal 120 (third node N3 ) of the driving circuit 100 .
  • the fourth transistor T4 is a P-type transistor, for example, the semiconductor material of the active layer of the fourth transistor T4 is a low temperature polysilicon semiconductor material.
  • the first light emission control circuit 300 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the first light emission control signal terminal EM1 to receive the first light emission control signal EM1 .
  • the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD to receive the first power supply voltage VDD from the first voltage terminal, and the first pole of the fifth transistor T5 is connected to the energy storage circuit 700 .
  • the second pole of the fifth transistor T5 is connected to the first terminal 110 (the second node N2 ) of the driving circuit 100 .
  • the fifth transistor T5 is a P-type transistor, for example, the semiconductor material of the active layer of the fifth transistor T5 is a low temperature polysilicon semiconductor material.
  • the second light emission control circuit 400 may be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the second light emission control signal terminal EM2 to receive the second light emission control signal EM2 .
  • the first electrode of the sixth transistor T6 is connected to the light emitting element L1.
  • the second pole of the sixth transistor T6 is connected to the second terminal 120 (the third node N3 ) of the driving circuit 100 .
  • the sixth transistor T6 is a P-type transistor, for example, the semiconductor material of the active layer of the sixth transistor T6 is a low temperature polysilicon semiconductor material.
  • the connection between the first end (here, the anode) of the light emitting element L1 and the first pole of the sixth transistor T6 is configured to receive a driving current from the second end 120 of the driving circuit 100 through the second light emitting control circuit 400, and the second end of the light emitting element L1
  • the terminal (cathode here) is configured to be connected to the second voltage terminal VSS to receive the second voltage.
  • the second voltage terminal can be grounded, that is, VSS can be 0V.
  • the energy storage circuit 700 includes a first capacitor C1 and a second capacitor C2.
  • the first capacitor C1 is electrically connected between the control terminal 130 of the driving circuit 100 and the first terminal 110 of the driving circuit 100
  • the second capacitor C2 is electrically connected between the first terminal 110 of the driving circuit 100 and the first power supply voltage terminal VDD
  • the electrode of the first capacitor C1 electrically connected to the first end 110 of the driving circuit 100 is electrically connected to the electrode of the second capacitor C2 electrically connected to the first end 110 of the driving circuit 100 .
  • the first capacitor C1 is electrically connected between the gate of the third transistor T3 and the first electrode of the third transistor.
  • the second capacitor C2 is electrically connected between the first pole of the third transistor T3 and the first power supply voltage terminal VDD, and the electrode of the first capacitor C1 electrically connected to the first pole of the third transistor T3 is connected to the electrode of the second capacitor C2
  • the electrode electrically connected to the first electrode of the third transistor T3 is electrically connected, for example, the first capacitor C1 and the second capacitor C2 may share the same electrode, and the electrode electrically connected to the two is integrally formed.
  • the capacitance of the first capacitor C1 and the second capacitor C2 are set for the compensation operation, and the capacitance of the second capacitor C2 is used to adjust the data range, which will be described later.
  • the pixel circuit can be driven by low frequency signal.
  • the low-frequency drive will produce phenomena such as flicker, which limits the use of the pixel circuit.
  • the pixel circuit uses transistors with different leakage current characteristics, for example, compared with the third transistor, the first transistor T1 and the second transistor T2 use transistors with lower leakage current characteristics. Since the leakage current of the first transistor T1 and the second transistor T2 in the leakage path is small, the flickering phenomenon can be overcome when the pixel circuit is used for low-frequency driving.
  • the first transistor T1 and the second transistor T2 adopt transistors with lower leakage current characteristics.
  • the first transistor T1 and the second transistor T2 adopt a lower leakage current characteristic transistor.
  • the method includes a first period of operation.
  • the first operation period includes a reset phase, a sampling phase, a writing phase and a light emitting phase.
  • the first operation period will be described below in conjunction with Fig. 3 .
  • FIG. 3 is a flowchart of a method for driving a pixel circuit provided by an embodiment of the present disclosure.
  • the method for driving the pixel circuit shown in FIG. 1 or FIG. 2 includes four stages, which are reset stage 301 , sampling stage 302 , writing stage 303 and light emitting stage 304 .
  • the first initialization circuit is turned on under the control of the first reset control signal, the first initialization voltage is applied to the control terminal of the drive circuit, and the second initialization circuit is controlled by the second reset control signal is turned on, and the second initialization voltage is applied to the second terminal of the driving circuit.
  • the first initialization circuit 500 is turned on under the control of the first reset control signal Re_N, the first initialization voltage Vinit1 is applied to the control terminal 130 of the driving circuit 100, and the The second initialization circuit 600 is turned on under the control of the second reset control signal Re_P, and applies the second initial voltage Vinit2 to the second terminal 120 of the driving circuit 100 .
  • the first transistor T1 is turned on under the control of the first reset control signal Re_N, the first initialization voltage Vinit1 is applied to the gate of the third transistor, and the fourth transistor T4 is turned on at the second reset Under the control of the control signal Re_P, the second initial voltage Vinit2 is applied to the second terminal 120 of the third transistor T3.
  • the first light emission control circuit 300 may also be turned on under the control of the first light emission control signal EM1, and the first power supply voltage VDD of the first power supply terminal is applied to the driving circuit.
  • the first end of 100 also makes the second light emission control circuit 400 conduct under the control of the second light emission control signal EM2, and applies the second initialization voltage Vinit2 from the second initialization circuit 600 to the light emitting element.
  • the fifth transistor T5 is turned on under the control of the first light emission control signal EM1, and the first power supply voltage VDD of the first power supply terminal is applied to the first pole of the third transistor (that is, the second node N2 ), and turn on the sixth transistor T6 under the control of the second light emission control signal EM2 , and apply the second initial voltage Vinit2 to the light emitting element L1 .
  • the second initialization voltage Vinit2 prevents the light emitting element from being turned on. That is, when the fourth transistor T4 applies the second initial voltage Vinit2 to the light emitting element L1, the value of the second initializing voltage Vinit2 is set to be, for example, less than or equal to the value of the second power supply voltage VSS, so that both ends of the light emitting element L1 There is no voltage difference or is biased, so that the light-emitting element L1 can be prevented from being turned on and eg emitting light at this stage.
  • the first initialization voltage and the second initialization voltage are different from each other. That is, the first initialization voltage Vinit1 and the second initialization voltage Vinit2 are connected to different voltage terminals so as to be separately set so as to be different from each other.
  • the second initial voltage Vinit2 is smaller than the first initialization voltage Vinit1 .
  • the first initialization voltage Vinit1 can be a DC voltage
  • the voltage value of the first initialization voltage Vinit1 can be greater than or equal to -7V and less than or equal to 0V; for example, the voltage value of the first initialization voltage Vinit1 can be -6V, -5V , -4V, -3V or -2V, but not limited to.
  • the second initialization voltage Vinit2 can be a DC voltage, and the voltage value of the second initialization voltage Vinit2 can be greater than or equal to -7V and less than or equal to 0V; for example, the voltage value of the second initialization voltage Vinit2 can be -6V, -5V , -4V, -3V or -2V, but not limited to.
  • the first light-emitting control circuit and the second light-emitting control circuit are turned off, and the first initialization circuit is kept on under the control of the first reset control signal, and the first initialization voltage is applied to the control terminal of the driving circuit , so that the second initialization circuit remains turned on under the control of the second reset control signal, and the second initialization voltage is applied to the second terminal of the driving circuit.
  • the threshold voltage of the driving circuit can be written at the second terminal of the driving circuit for the compensation operation of the pixel circuit.
  • the first light emission control circuit 300 and the second light emission control circuit 400 are turned off, and the first initialization circuit 500 is kept on under the control of the first reset control signal Re_N,
  • the first initialization voltage Vinit1 is applied to the control terminal 130 of the driving circuit 100, so that the second initialization circuit 600 remains turned on under the control of the second reset control signal Re_P, and the second initialization voltage Vinit2 is applied to the second End 120.
  • the fifth transistor T5 and the sixth transistor T6 are turned off, the first transistor T1 is kept on under the control of the first reset control signal Re_N, and the first initialization voltage Vinit1 is applied to the gate of the third transistor T3.
  • the second node N2 (the first The voltage of the first terminal of the third transistor T2 is adjusted so as to write the threshold voltage of the third transistor T2 for the compensation operation of the pixel circuit, which will be described in detail later in conjunction with the signal.
  • the first initialization circuit, the second initialization circuit, the first light emission control circuit and the second light emission control circuit are turned off, so that the data writing circuit writes the received data signal into To the control terminal of the drive circuit, the data signal is stored in the energy storage circuit through the energy storage circuit.
  • the first initialization circuit 500, the second initialization circuit 600, the first light emission control circuit 300 and the second light emission control circuit 400 are turned off, so that the data writing circuit 200 is in the first scan Under the control of the signal Gate_N, the received data signal Vdata is written into the control terminal 130 of the driving circuit 100 , and the data signal is stored in the energy storage circuit 700 through the energy storage circuit 700 .
  • the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off, so that the second transistor writes the received data signal Vdata under the control of the first scanning signal Gate_N.
  • the voltage of the second node N2 is also adjusted by the action of the third transistor T3 for compensation operation.
  • the first initialization circuit and the second initialization circuit are turned off, and the first light-emitting control circuit is turned on under the control of the first light-emitting control signal, and the first power supply voltage of the first power supply terminal is applied to the drive circuit.
  • the first end makes the second light emitting control circuit conduct under the control of the second light emitting control signal, and applies the driving current from the second end of the driving circuit to the light emitting element to drive the light emitting element.
  • the first initialization circuit 500 and the second initialization circuit 600 are turned off, and the first light emission control circuit 300 is turned on under the control of the first light emission control signal EM1, the first The first power supply voltage VDD at the voltage terminal is applied to the first terminal 110 of the drive circuit 100, so that the second light emission control circuit 400 is turned on under the control of the second light emission control signal EM2, and the drive from the second terminal 120 of the drive circuit 100 Current is applied to the light emitting element 800 to drive the light emitting element 800 to emit light.
  • the first transistor T1 and the fourth transistor T4 are turned off, and the fifth transistor T5 is turned on under the control of the first light emission control signal EM1, and the first power supply voltage VDD of the first voltage terminal is applied to
  • the first pole of the third transistor T3 makes the sixth transistor T6 turn on under the control of the second light emission control signal EM2, and applies the driving current from the second pole of the third transistor T3 to the light emitting element L1 to drive the light emitting element L1 glows.
  • the display process of each frame of image includes four stages, which are reset stage t1, sampling stage t2, writing stage t3 and light emitting stage t4, and the timing of each signal in each stage is shown in the figure waveform.
  • the first reset control signal and the second reset control signal are input to turn on the first initialization circuit 500 and the second initialization circuit 600, the first initialization voltage Vinit1 is applied to the control terminal 130 of the drive circuit 100, and the second The initial voltage Vinit2 is applied to the second terminal 120 of the driving circuit 100 .
  • the first transistor T1 is an N-type transistor
  • the first transistor T1 is turned on by the high level of the first reset control signal Re_N, and the first initial voltage Vinit1 is passed through the first transistor.
  • T1 is written into the first node N1.
  • the fourth transistor T4 is a P-type transistor.
  • the fourth transistor T4 is turned on by the low level of the second reset control signal Re_P, and the second initial voltage Vinit2 is written into the third node N3 through the fourth transistor T4.
  • the second transistor T2 is an N-type transistor, which is turned off by the low level of the first scan signal Gate_N.
  • the first light emission control signal EM1 and the second light emission control signal EM2 are the same. As shown in FIG. 4A , both the first light emission control signal EM1 and the second light emission control signal EM2 are the same light emission control signal EM.
  • the light emission control signal EM is low level, that is, the first light emission control signal EM1 and the second light emission control signal EM2 are low level, so the fifth transistor T5 and the sixth transistor T5 Transistor T6 is turned on.
  • the voltage of the second node N2 is set to the VDD potential, and the voltage of the first terminal of the light emitting element L1 is set to the second initial voltage Vinit2.
  • the potential of the first node N1 is the first initial voltage Vinit1
  • the potential of the second node N2 is the first power supply voltage VDD
  • the potential of the third node N3 and the first end of the light-emitting element L1 is the second initial voltage Vinit2.
  • the second initializing voltage Vinit2 prevents the light emitting element L1 from being turned on.
  • the second initialization voltage Vinit2 is at a lower level than the second power supply voltage VSS, so as to prevent the light emitting element L1 from being turned on.
  • the value of the first initial voltage Vinit1 can be selected so that the third transistor T3 is in a state of being in an off state but having a leakage current, or can be in a state of generating a weak current.
  • the light emitting control signal EM is at high level, that is, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at high level, so the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third transistor T3 has a leakage current or is in a state capable of generating a weak current
  • the potential of the source of the third transistor T3 is (ie, the potential of the second node N2 ) is discharged to Vinit1 - Vth, which is the threshold voltage of the third transistor, so that the third transistor is turned off. Therefore, at this stage, the voltage VGS of the gate (that is, the first node N1) and the source (that is, the second node N2) of the third transistor T3 can satisfy:
  • the threshold voltage of the third transistor ie, the driving transistor
  • the first transistor T1 is turned off by the low level of the first reset control signal Re_N, and the fourth transistor T4 is turned off by the high level of the second reset control signal Re_P.
  • the second transistor T2 is turned on under the action of the high level of the first scanning signal Gate_N, and at this time, the data signal Vdata is applied to the data line, so that the data signal Vdata is written through the second transistor T2, so that the first A node N1 is written with Vdata potential.
  • the light emitting control signal EM is at a high level, that is, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at a high level, so the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the potential of the second node N2 changes as C1/(C1+C2)(Vdata-Vinit1)+Vinit1-Vth due to the coupling effect of the first capacitor C1 (and the second capacitor C2).
  • the light-emitting control signal EM is at low level, that is, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at low level, so the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the potential of the second node N2 returns to the first power supply voltage VDD, and the pixel circuit generates a driving current, which is applied to the light emitting element L1 to drive the light emitting element L1 to emit light.
  • the potential of the first node N1 is coupled to C2/(C1+C2)(Vdata-Vinti1)+Vdd+Vth.
  • the third transistor T3 is in a saturated state, so the driving current for driving the light emitting element L1 is calculated according to the following formula.
  • I OLED 1/2*K*(C2/(C1+C2)(Vdata-Vinti1)) 2 .
  • Vth represents the threshold voltage of the third transistor T3
  • K is a constant value related to the driving transistor itself. It can be seen from the above calculation formula of I OLED that the driving current I OLED flowing through the light-emitting element L1 is no longer related to the threshold voltage Vth of the third transistor T3, thus the compensation of the pixel circuit can be realized, and the problem of the driving transistor ( In the embodiment of the present disclosure, the third transistor T3) has the problem of threshold voltage drift caused by the process and long-term operation, and its influence on the driving current I OLED can be eliminated, so that the display effect of the display device using it can be improved.
  • the OLED display panel or display device can work at different frequencies, the refresh rate for normal display is higher, and a lower refresh rate can be selected to save power consumption.
  • the above-mentioned method for driving a pixel circuit may further include a second operation period in addition to the first operation period, and the second operation period is immediately after the first operation period in time.
  • the first light emission control signal EM1 , the second light emission control signal EM2 and the second reset control signal Re_P have a first frequency
  • the first reset control signal Re_N and the first scanning signal Gate_N have a second frequency
  • the first frequency is greater than the second frequency.
  • the display panel or display device employing the above-described pixel circuit operates at a low refresh rate compared to normal display operation.
  • FIG. 4B is a timing comparison diagram of high-frequency driving and low-frequency driving provided by an embodiment of the present disclosure.
  • the pixel circuit 10 may be driven in a high-frequency driving manner, as shown in the high-frequency timing diagram in FIG. 4B .
  • the pixel circuit 10 may be driven in a low-frequency driving manner, as shown in the low-frequency timing diagram in FIG. 4B .
  • each driving cycle is the same as that in FIG. 4A . Therefore, in each cycle (operation period), the emission control signal EM (namely, the first emission control signal EM1, the second emission control signal EM2), the second reset control signal Re_P, the first scan signal Gate_N, and the first reset control signal
  • the signal Re_N corresponds to different cycles, and four stages of reset, sampling, data writing, and light emission are performed in each cycle, and details will not be repeated here.
  • the method of driving the pixel circuit may further include, for example, at least one second operation period on the basis of including the first operation period, and the second operation period is immediately after the first operation period in time. after the period.
  • the first operation period is the same as that shown in FIG. 4A , and the four stages of reset, sampling, data writing, and light emission are carried out, and details will not be repeated; in the second operation period, the first light emission control signal EM1, the second light emission control signal The signal EM2 and the second reset control signal Re_P have a first frequency, the first reset control signal Re_N and the first scan signal Gate_N have a second frequency, and the first frequency is greater than the second frequency.
  • the first frequency is greater than 30 Hz
  • the second frequency is 1 Hz ⁇ 10 Hz.
  • the data signal written in the first operation period will be stored and retained by the energy storage circuit (such as a storage capacitor), so as to continue to control the driving circuit, so that the first light emission control signal EM1 can
  • the energy storage circuit such as a storage capacitor
  • the duration of the second operation period is the same as the duration of the first operation period.
  • the number of the second operation periods is not limited to one but may be multiple, for example, at least two second operation periods are shown in FIG. 4B , and of course the embodiments of the present disclosure are not limited thereto.
  • the number of second operating periods is generally based on the frequency at low frequency driving, the lower the frequency is relative to the frequency at high frequency driving, the greater the number of second operating periods.
  • the first light emission control signal EM1 , the second light emission control signal EM2 , and the second reset control signal Re_P enter different periods, and the first reset control signal and the first The scan signal is still in the same cycle.
  • FIG. 5 is a schematic block diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit 20 further includes a reset circuit 900 on the basis of the pixel circuit 10 .
  • the reset circuit is the same as those in the pixel circuit 10 , and will not be repeated here.
  • the reset circuit is configured to write a reset voltage into the first terminal of the driving circuit 100 to provide a bias voltage for the driving transistor in the driving circuit.
  • the reset circuit 900 is configured to couple the change of the first light emission control signal EM1 to the first terminal of the driving circuit 100 .
  • the first scanning signal Gate_N makes the data writing circuit 200 cut off, and the second node N2 can be driven upward by EM1 through the reset circuit 900, and the second node is still allowed in the absence of the reset phase t1.
  • N2 has a certain degree of high-frequency reset characteristics, which can reduce the occurrence of splash screens. That is to say, through the reset circuit 900 , the voltage of the second node N2 can be periodically adjusted at high frequency, and a part of low frequency components can be changed into high frequency components, thereby reducing the occurrence of flickering screens.
  • FIG. 6 is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 5 .
  • the reset circuit 900 includes a third capacitor C3 , and the third capacitor C3 is electrically connected between the control terminal of the first lighting control circuit 300 and the first terminal of the driving circuit 100 . That is to say, the third capacitor C3 is electrically connected between the control terminal of the fifth transistor T5 and the first electrode of the third transistor T3.
  • the capacitance of the third capacitor C3 is generally set to be much smaller than the capacitance of the second capacitor C2 , thereby substantially not affecting the data signal stored in the second capacitor C2 .
  • the capacitance of the third capacitor C3 is one tenth, or one hundredth, or less than the capacitance of the second capacitor C2.
  • the third capacitor C3 includes a first capacitor electrode and a second capacitor electrode opposite to each other and located on different layers.
  • the first capacitor electrode is integrally provided with the third active layer of the third transistor T3, or the first capacitor electrode is electrically connected to the third active layer of the third transistor through a hole.
  • the second capacitive electrode is integrated with or electrically connected to the control terminal of the first light emission control circuit 300 .
  • the driving method of the pixel circuit 20 shown in FIGS. 5 and 6 is similar to the driving method of the pixel circuit 10 described above.
  • the driving method of driving the pixel circuit 20 includes a first operation period.
  • the first operation period includes a reset phase, a sampling phase, a writing phase and a light emitting phase.
  • the first transistor T1 is turned off by the low level of the first reset control signal Re_N, and the fourth transistor T4 is turned off by the high level of the second reset control signal Re_P.
  • the second transistor T2 is turned on under the action of the high level of the first scan signal Gate_N, and the first node N1 is written into the potential of Vdata.
  • the light emitting control signal EM is at a high level, that is, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at a high level, so the fifth transistor T5 and the sixth transistor T6 are turned off. Due to the coupling effect of C1, the potential of the second node N2 changes as follows:
  • the light-emitting control signal EM is at low level, that is, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at low level, so the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the second node N2 returns to the VDD potential, and the light emitting element L1 emits light.
  • the potential of the first node N1 is coupled to C2/(C1+C2+C3)(Vdata-Vinti1)+Vdd+Vth. Therefore, the driving current of the light emitting element L1 is calculated according to the following formula.
  • I OLED 1/2*K*(C2/(C1+C2+C3)(Vdata-Vinti1)) 2 .
  • the driving current I OLED flowing through the light-emitting element L1 is no longer related to the threshold voltage Vth of the third transistor T3, thereby realizing compensation for the pixel circuit and solving the problem of
  • the drive transistor (the third transistor T3 in the embodiment of the present disclosure) has the problem of threshold voltage drift caused by the process and long-term operation, and its influence on the drive current I OLED can be eliminated, thereby improving the performance of the display device using it. display effect.
  • FIGS. 7A ⁇ 7N The layout and stacked structure of multiple embodiments of the present disclosure will be described below with reference to FIGS. 7A ⁇ 7N . It should be noted that FIGS. 7A to 7N only show the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the first Embodiments of the present disclosure are not limited to the specific position, size, pattern, etc. of the stacked positional relationship between the source-drain metal layer and the second source-drain metal layer.
  • FIG. 7A is an exemplary partial layout of the pixel circuit shown in FIG. 2 provided by an embodiment of the present disclosure.
  • FIG. 7B is a schematic stacked view of the pixel circuit shown in FIG. 7A .
  • the display substrate includes a base substrate 710 and a laminate formed on the base substrate 710, the laminate may include a first active layer 701, a first conductive layer 702, a second The conductive layer 703, the second active layer (not shown), the third conductive layer 704, the first source-drain metal layer 706, the second source-drain metal layer (not shown), etc. These layers are sequentially stacked on the base substrate starting from the base substrate.
  • the first active layer is located between the base substrate and the first conductive layer
  • the first conductive layer is located between the first active layer and the second conductive layer
  • the second conductive layer The layer is located between the first conductive layer and the second active layer
  • the second active layer is located between the second conductive layer and the third conductive layer
  • the third conductive layer is located between the second active layer and the first source and drain metal
  • the first source-drain metal layer is located between the third conductive layer and the second source-drain metal layer
  • the second source-drain metal layer can be used for electrical connection with the light-emitting element and the like.
  • the stack schematic diagram shown in FIG. 7B takes the third transistor T3 as an example, that is, the first active layer 701 and the first conductive layer 702 shown in the figure are respectively corresponding to the active layer and the gate of the transistor.
  • the first active layer is, for example, a low-temperature polysilicon semiconductor layer, which is used to form an active layer of a transistor in a pixel circuit such as a driver circuit, and can also be used to form a first active layer in a pixel circuit, for example.
  • the second active layer is, for example, an oxide semiconductor layer, which is used to form the active layer of the transistor (first transistor) of the first initialization circuit and the transistor (second transistor) of the data writing circuit in the pixel circuit.
  • FIG. 7C shows a schematic layout of the first active layer 701 in an exemplary partial layout.
  • the first active layer 701 is in the shape of an "H" as a whole, and is used to form the respective active layers of the third transistor T3, the fifth transistor T5 and the sixth transistor T6. , the active layers of these three transistors are respectively different parts of the first active layer 701 .
  • the portion forming the active layer of the third transistor T3 is in the shape of a "face”.
  • the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned on, it is necessary to form a conduction path from the first power supply terminal VDD to the light-emitting element, so the third transistor T3, Parts of the respective active layers of the fifth transistor T5 and the sixth transistor T6 may be respectively doped to be conductive so as to have a lower resistivity to reduce losses.
  • These conductorized portions of the first active layer may be referred to as conductorized layers.
  • the layout of the pixel circuits of adjacent pixels may be distributed in a mirror image.
  • each layer (the first active layer 701, the first conductive layer 702, the second conductive layer 703, the second active layer, the third conductive layer 704, the first source and drain metal) in the pixel circuit of the adjacent pixel layer 706, the second source-drain metal layer, etc.) are all mirror images.
  • the first conductive layer 702 is used to form the gate of the third transistor T3 and the first capacitor electrode of the first capacitor C1; the second conductive layer 703 forms the second capacitor electrode of the first capacitor C1 and the first capacitor of the second capacitor C2 The electrodes, that is, the first capacitor C1 and the second capacitor C2 share one capacitor electrode; the third conductive layer 704 is used to form the second capacitor electrode of the second capacitor C2.
  • the first capacitor electrode of the second capacitor C2 is formed through the second conductive layer 703
  • the second capacitor electrode of the second capacitor C2 is formed through the third conductive layer 704 .
  • the first conductive layer 702 also includes a portion for the light emission control line EM, which simultaneously forms the gates of the fifth transistor T5 and the sixth transistor T6 (not shown in FIG. 7B ). As shown in FIG. 7B , the conductive part 705 is electrically connected to the first capacitor electrode of the second capacitor C2 through the via hole 7051 and the transition electrode formed in the first source-drain electrode layer 706 .
  • the local shape of the first conductive layer 702 in FIG. 7A is, for example, any one of the shapes shown in FIG. 7D . As shown in FIG. 7D , the first conductive layer 702 in the pixel circuits of adjacent pixels may be mirrored.
  • the partial shape of the second conductive layer 703 used to form the second capacitor electrode of the first capacitor C1 and the first capacitor electrode of the second capacitor C2 in FIG. 7A is, for example, as shown in FIG. 7E .
  • the second conductive layer 703 in the pixel circuits of adjacent pixels may be distributed in a mirror image.
  • the partial shape of the third conductive layer 704 used to form the second capacitor electrode of the second capacitor C2 in FIG. 7A is, for example, as shown in FIG. 7F .
  • the partial shape of the third conductive layer 704 used to form the second capacitor electrode of the second capacitor C2 may be similar to a rectangle.
  • the third conductive layers of two adjacent pixels may be integrally formed.
  • FIG. 7G and 7H are exemplary partial layouts of the pixel circuit shown in FIG. 6 provided by an embodiment of the present disclosure.
  • FIG. 7G is a layout of pixel circuits of two adjacent pixels
  • FIG. 7H is an exemplary partial layout of a pixel circuit.
  • an exemplary partial layout diagram 7H of a pixel circuit is taken as an example for illustration.
  • FIG. 7I is an exemplary stacked structure of the pixel circuit shown in FIG. 7H ;
  • FIG. 7J is another exemplary stacked structure of the pixel circuit shown in FIG. 7H .
  • the pixel circuit 20 shown in FIG. 6 includes a third capacitor C3.
  • FIG. 7G , FIG. 7H , FIG. 7I and FIG. 7J except for the structure for forming the third capacitor C3 , the other parts are the same as those in FIG. 7A to FIG. 7F , and will not be repeated here.
  • the stacked schematic diagrams shown in FIG. 7I and FIG. 7J take the third transistor T3 as an example, that is, the first active layer 701 and the first conductive layer 702 shown in the figure are the active layer and the first conductive layer respectively corresponding to the transistor. grid.
  • the conductive portion 705 and the first conductive layer 702 that are directly electrically connected to the drain of the third transistor constitute the third capacitor C3 .
  • the part of the first conductive layer 702 forming the gate of the fifth transistor T5 is modified to form an extension part 7021, which is integrally formed with the gate of the fifth transistor T5, and at the same time, it is connected with the conductive Portions 705 overlap each other in a direction perpendicular to the base substrate.
  • the part of the first conductive layer 702 forming the gate of the fifth transistor T5 is modified to form an extension part 7021, which is integrally formed with the gate of the fifth transistor T5, and at the same time, it is connected with the conductive Portions 705 overlap each other in a direction perpendicular to the base substrate.
  • the third capacitor C3 includes two parts connected in parallel with each other, that is, a first part formed between the conductorization layer 705 and the extension part, and a first part formed between the extension part and the first electrode of the second capacitor C2 the second part of .
  • FIG. 7K is another exemplary partial layout of the pixel circuit shown in FIG. 6 provided by an embodiment of the present disclosure.
  • FIG. 7L is an exemplary stacked structure of the pixel circuit shown in FIG. 7K.
  • the stack diagram shown in FIG. 7L takes the third transistor T3 as an example, that is, the first active layer 701 and the first conductive layer 702 shown in the figure are respectively corresponding to the active layer and the gate of the transistor.
  • the other parts are the same as those in FIG. 7A to FIG. 7F , and will not be repeated here.
  • the conductive portion 705 directly electrically connected to the drain of the third transistor, the first conductive layer 702 and the second conductive layer 703 form a third capacitor C3 .
  • a part of the second conductive layer 703 (for example, the part forming the first electrode of the second capacitor C2) is electrically connected to the conductive part 705 through the via hole 7051 and the connection electrode in the first source-drain electrode layer 706, and this part serves as the second
  • the first capacitor electrode of the third capacitor C3; the part of the first conductive layer used to form the gate of the fifth transistor T5 is used as the second capacitor electrode of the third capacitor C3 (the extension portion 7021 is not present in this embodiment).
  • the first capacitor electrode and the second capacitor electrode of the third capacitor C3 overlap each other in a direction perpendicular to the base substrate 710 , thereby forming the third capacitor C3 .
  • FIG. 7M is another exemplary partial layout of the pixel circuit shown in FIG. 6 provided by an embodiment of the present disclosure.
  • FIG. 7N is an exemplary stacked structure of the pixel circuit shown in FIG. 7M.
  • the stack schematic diagram shown in FIG. 7N takes the third transistor T3 as an example, that is, the first active layer 701 and the first conductive layer 702 shown in the figure are respectively corresponding to the active layer and the gate of the transistor.
  • FIG. 7M and FIG. 7N except for the structure for forming the third capacitor C3 , other parts are the same as those in FIG. 7A to FIG. 7F , which will not be repeated here.
  • the second conductive layer 703 can be widened along the Y direction to obtain the protruding portion 7031 of the second conductive layer in the Y direction.
  • the protruding part 7031 in the second conductive layer 703 can be used as the first capacitor electrode of the third capacitor C3, and the part of the first conductive layer 702 used to form the first light emission control signal line EM 7022 serves as the second capacitor electrode of the third capacitor C3.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the embodiments of the present disclosure in order to distinguish the two poles of the transistor except the gate, it is directly described that one pole is the first pole and the other pole is the second pole.
  • At least one embodiment of the present disclosure further provides an array substrate, including a plurality of pixel units arranged in an array, and each pixel unit includes the pixel circuit provided by any embodiment of the present disclosure.
  • FIG. 8 is a schematic block diagram of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 8 , the array substrate 11 is disposed in the display device 1 and is electrically connected to the gate driver 12 , the timing controller 13 and the data driver 14 .
  • the array substrate 11 includes a pixel unit P defined by intersections of a plurality of scan lines GL and a plurality of data lines DL; a gate driver 12 is used to drive a plurality of scan lines GL; a data driver 14 is used to drive a plurality of data lines DL; The controller 13 is used for processing the image data RGB input from the outside of the display device 1, providing the processed image data RGB to the data driver 14, and outputting the scan control signal GCS and the data control signal DCS to the gate driver 12 and the data driver 14, so as to control The gate driver 12 and the data driver 14 perform control.
  • the array substrate 11 includes a plurality of pixel units P, and the pixel units P include any pixel circuit 10 provided in the above-mentioned embodiments.
  • the pixel circuit 20 shown in FIG. 6 is included.
  • the array substrate 11 further includes a plurality of scan lines GL and a plurality of data lines DL.
  • the multiple scan lines are correspondingly connected to the data writing circuit 200 in the pixel circuit 10 of each row of pixel units to provide the first scan signal.
  • the pixel unit P is disposed at the intersection area of the scan line GL and the data line DL.
  • each pixel unit P is connected to five scan lines GL (respectively providing the first scan signal Gate_N, the first reset control signal Re_N, the second reset control signal Re_P, the first light emission control signal EM1 and the second scan line GL).
  • FIG. 10 Only part of the pixel unit P, the scan line GL, and the data line DL are shown in FIG. 10 .
  • the plurality of pixel units P are arranged in multiple rows, the first initialization circuit 500 of the pixel circuit of each row of pixel units P is connected to the same scanning line GL, and the second initialization circuit 600 of the pixel circuit of each row of pixel units P is connected to To another scan line GL, the data writing circuit 200 of the pixel circuit of each row of pixel units P is connected to another scan line GL to receive the first scan signal.
  • the data line DL of each column is connected to the data writing circuit 200 in the pixel circuit 10 of this column to provide a data signal.
  • a plurality of pixel units are arranged in multiple rows, the first light emission control circuit 300 of the pixel circuit of the pixel unit in the nth row (n is an integer greater than 1) is connected to the same light emission control line, and the pixel circuit of the pixel unit in the nth row
  • the second light emission control circuit 400 is connected to another light emission control line.
  • the gate driver 12 supplies a plurality of gate signals to a plurality of scan lines GL according to a plurality of scan control signals GCS from the timing controller 13 .
  • the plurality of gating signals include a first scan signal, a second scan signal, a first light emission control signal, a second light emission control signal, and a reset signal (i.e., a second scan signal). These signals are supplied to each pixel unit P through a plurality of scan lines GL.
  • the data driver 14 converts digital image data RGB input from the timing controller 13 into data signals according to a plurality of data control signals DCS from the timing controller 13 using a reference gamma voltage.
  • the data driver 14 supplies converted data signals to a plurality of data lines DL.
  • the timing controller 13 processes externally input image data RGB to match the size and resolution of the array substrate 11 , and then provides the processed image data to the data driver 14 .
  • the timing controller 13 generates a plurality of scanning control signals GCS and a plurality of data control signals DCS using synchronous signals (such as dot clock DCLK, data enable signal DE, horizontal synchronous signal Hsync, and vertical synchronous signal Vsync) input from the display device.
  • the timing controller 13 provides the generated scan control signal GCS and data control signal DCS to the gate driver 12 and the data driver 14 respectively for controlling the gate driver 12 and the data driver 14 .
  • the data driver 14 can be connected to a plurality of data lines DL to provide a data signal Vdata; meanwhile, it can also be connected to a plurality of first voltage lines, a plurality of second voltage lines and a plurality of reset voltage lines to provide a first voltage, a second voltage and a reset voltage.
  • the gate driver 12 and the data driver 14 may be implemented as semiconductor chips.
  • the display device 1 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may be existing conventional components, and will not be described in detail here.
  • the array substrate 11 provided in this embodiment can be applied to any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.
  • a display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素电路及其驱动方法、阵列基板和显示装置。像素电路包括驱动电路(100)、数据写入电路(200)、第一发光控制电路(300)、第二发光控制电路(400)、第一初始化电路(500)、第二初始化电路(600)。驱动电路(100)配置为控制驱动电流；数据写入电路(200)配置为将数据信号写入驱动电路(100)的控制端；第一初始化电路(500)配置为将第一初始化电压施加至驱动电路(100)的控制端；第一初始化电路(500)包括第一晶体管，数据写入电路(200)包括第二晶体管，驱动电路(100)包括第三晶体管，第一晶体管的第一有源层的半导体材料的漏电流特性小于第三晶体管的第三有源层的半导体材料的漏电流特性，第二晶体管的第二有源层的半导体材料的漏电流特性小于第三晶体管的第三有源层的半导体材料的漏电流特性。像素电路可以实现低频驱动。

Description

像素电路及其驱动方法、阵列基板和显示装置
相关交叉引用
本申请要求于2021年7月30日递交的PCT专利申请PCT/CN2021/109890号的优先权以及2021年8月5日递交的中国专利申请202110898678.6的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、阵列基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。由于上述特点，有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。PMOLED虽然工艺简单、成本较低，但因存在交叉串扰、高功耗、低寿命等缺点，不能满足高分辨率大尺寸显示的需求。相比之下，AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。相比PMOLED，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
发明内容
本公开至少一实施例提供一种像素电路，包括：驱动电路、数据写入电路、第一发光控制电路、第二发光控制电路、第一初始化电路、第二初始化电路和储能电路，所述驱动电路包括控制端、第一端和第二端，且配置为控制流经所述第一端和所述第二端的用于驱动所述发光元件发光的驱动电流；所述数据写入电路被配置为在第一扫描信号的控制下将数据信号写入所述驱动电路的控制端；所述第一发光控制电路被配置为在第一发光控制信号的控制下将第一电源端的第一电源电压施加至所述驱动电路的第一端；所述第二发光控制电路被配置为在第二发光控制信号的控制下将来自所述驱动电路的第二端的所述驱动电流施加至所述发光元件；所述第一初始化电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至所述驱动电路的控制端；所述第二初始化电路被配置为在第二复位控制信号 的控制下将第二初始化电压施加至所述驱动电路的第二端；所述储能电路被配置为存储写入到所述驱动电路的控制端的所述数据信号，第一初始化电路包括第一晶体管，所述数据写入电路包括第二晶体管，所述驱动电路包括第三晶体管，第一晶体管的第一有源层的半导材料的漏电流特性小于所述第三晶体管的第三有源层的半导材料的漏电流特性；所述第二晶体管的第二有源层的半导材料的漏电流特性小于所述第三晶体管的第三有源层的半导材料的漏电流特性。
例如，本公开一实施例提供的像素电路，所述第一晶体管的第一有源层的半导材料和所述第二晶体管第二有源层的半导材料相同。
例如，本公开一实施例提供的像素电路，所述第一晶体管的第一有源层的半导材料为氧化物半导体；所述第三晶体管的第三有源层的多晶硅半导材料。
例如，在本公开一实施例提供的像素电路中，所述氧化物半导体为氧化铟半导体材料；所述多晶硅半导材料为低温多晶硅半导体材料。
例如，在本公开一实施例提供的像素电路中，所述第一发光控制电路、所述第二发光控制电路，所述第二初始化电路分别包括的晶体管的有源层的半导材料与所述第三晶体管的第三有源层的半导材料相同且同层设置。
例如，在本公开一实施例提供的像素电路中，所述储能电路包括第一电容和第二电容，所述第一电容电连接在所述驱动电路的控制端和所述驱动电路的第一端之间，所述第二子电容电连接在所述驱动电路的第一端与所述第一电源电压端之间，且所述第一电容与所述驱动电路的第一端电连接的电极和所述第二电容与所述驱动电路的第一端电连接的电极电连接。
例如，在本公开一实施例提供的像素电路中，复位电路被配置为将所述第一发光控制信号的变化耦合至所述驱动电路的第一端。
例如，在本公开一实施例提供的像素电路中，所述复位电路包括第三电容，所述第三电容电连接在所述第一发光控制电路的控制端与所述驱动电路的第一端之间。
例如，在本公开一实施例提供的像素电路中，第三电容包括彼此相对且位于不同层的第一电容电极和第二电容电极，第一电容电极与所述第三晶体管的第三有源层一体设置，或者所述第一电容电极经过孔与所述第三晶体管的第三有源层电连接，第二电容电极与所述第一发光控制电路的控制端一体设置。
例如，在本公开一实施例提供的像素电路中，第一初始化电压和所述第二初始化电压彼此不同。
本公开至少一实施例还提供一种阵列基板，包括阵列排布的多个像素单元，每个像素单元包括本公开任一实施例提供的像素电路。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的阵列基板。
本公开至少一实施例还提供一种驱动像素电路的方法，所述方法包括第一操作时段，所述第一操作时段包括复位阶段、采样阶段、写入阶段和发光阶段，其中，在所述复位阶段， 使得所述第一初始化电路在所述第一复位控制信号的控制下导通，将所述第一初始化电压施加至所述驱动电路的控制端，使得所述第二初始化电路在所述第二复位控制信号的控制下导通，将所述第二初始化电压施加至所述驱动电路的第二端；在所述采样阶段，使得所述第一发光控制电路和所述第二发光控制电路截止，且使得所述第一初始化电路在所述第一复位控制信号的控制下保持导通，将所述第一初始化电压施加至所述驱动电路的控制端，使得所述第二初始化电路在所述第二复位控制信号的控制下保持导通，将所述第二初始化电压施加至所述驱动电路的第二端；在所述写入阶段，使得所述第一初始化电路、所述第二初始化电路、所述第一发光控制电路和所述第二发光控制电路截止，使得所述数据写入电路在所述第一扫描信号的控制下将接收的所述数据信号写入到所述驱动电路的控制端，通过所述储能电路将所述数据信号存储在所述储能电路之中；在所述发光阶段，使得所述第一初始化电路和所述第二初始化电路截止，且使得所述第一发光控制电路在所述第一发光控制信号的控制下导通，将所述第一电源端的第一电源电压施加至所述驱动电路的第一端，使得所述第二发光控制电路在所述第二发光控制信号的控制下导通，将来自所述驱动电路的第二端的所述驱动电流施加至所述发光元件，以驱动所述发光元件。
例如，本公开一实施例提供的驱动方法，还包括：第二操作时段，所述第二操作时段在时间上紧接在所述第一操作时段之后，所述第一发光控制信号、所述第二发光控制信号以及所述第二复位控制信号具有第一频率，所述第一复位控制信号和所述第一扫描信号具有第二频率，所述第一频率大于所述第二频率，与所述第一操作时段相比，在所述第二操作时段中，所述第一发光控制信号、所述第二发光控制信号以及所述第二复位控制信号进入不同的周期，所述第一复位控制信号和所述第一扫描信号仍然在同一周期。
例如，本公开一实施例提供的驱动方法，第一频率大于30Hz，所述第二频率为1Hz～10Hz。
例如，本公开一实施例提供的驱动方法，在所述复位阶段，还使得所述第一发光控制电路在所述第一发光控制信号的控制下导通，将所述第一电源端的第一电源电压施加至所述驱动电路的第一端，还使得所述第二发光控制电路在所述第二发光控制信号的控制下导通，将来自所述第二初始化电路的所述第二初始化电压施加至发光元件。
例如，本公开一实施例提供的驱动方法，在所述第二初始化电路将所述第二初始化电压施加至发光元件的情况下，使得所述第二初始化电压避免发光元件导通。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种像素电路的示意框图；
图2为图1中所示的像素电路的一种具体实现示例的电路图；
图3为本公开一实施例提供的一种驱动像素电路的方法的流程图；
图4A为本公开一实施例提供的一种像素电路的驱动方法的时序图；
图4B为本公开一实施例提供的一种高频驱动和低频驱动的时序对比图；
图5为本公开一实施例提供的另一种像素电路的示意框图；
图6为图5中所示的像素电路的一种具体实现示例的电路图；
图7A为本公开一实施例提供的图2所示的像素电路的示例性部分版图；
图7B为图7A所示的像素电路的叠层示意图；
图7C为图7A所示的版图中第一有源层的示意性版图；
图7D为图7A所示的版图中第一导电层的示意性版图；
图7E为图7A所示的版图中第二导电层的示意性版图；
图7F为图7A所示的版图中第三导电层的示意性版图；
图7G和图7H为本公开一实施例提供的图6所示的一种像素电路的示例性部分版图；
图7I为图7H所示的像素电路的一种叠层示意图；
图7J为图7H所示的像素电路的另一种叠层示意图；
图7K为本公开一实施例提供的图6所示的像素电路的另一种示例性部分版图；
图7L为图7K所示的像素电路的一种示例性叠层示意图；
图7M为本公开一实施例提供的图6所示的像素电路的另一种示例性部分版图；
图7N为图7M所示的像素电路的一种示例性叠层结构；以及
图8为本公开一实施例提供的一种阵列基板和显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面，将参照附图详细描述根据本公开的各个实施例。需要注意的是，在附图中，将相同的附图标记赋予基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
OLED显示装置通常包括多个按阵列排布的像素单元，每个像素单元可以通过像素电路来实现驱动OLED发光的基本功能。AMOLED显示装置中使用的基础像素电路通常为2T1C像素电路，即利用两个TFT(Thin-film transistor，薄膜晶体管)和一个存储电容Cs来实现驱动OLED发光的基本功能。AMOLED的像素电路不限于上述像素电路，还可以是其他结构的像素电路，例如4T1C、4T2C、6T1C或8T2C的像素电路等。
在一些视频图像的显示过程中，为了降低OLED的功耗，可以采用低频信号对像素电路进行驱动，然而由于晶体管的漏电流的影响，采用低频驱动会产生闪屏(Flicker)等现象，从而限制了该像素电路的使用。
本公开至少一实施例提供一种像素电路，包括驱动电路、数据写入电路、第一发光控制电路、第二发光控制电路、第一初始化电路、第二初始化电路和储能电路。该驱动电路包括控制端、第一端和第二端，且配置为控制流经第一端和第二端的用于驱动发光元件发光的驱动电流。数据写入电路被配置为在第一扫描信号的控制下将数据信号写入驱动电路的控制端。第一发光控制电路被配置为在第一发光控制信号的控制下将第一电源端的第一电源电压施加至驱动电路的第一端。第二发光控制电路被配置为在第二发光控制信号的控制下将来自驱动电路的第二端的驱动电流施加至发光元件。第一初始化电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至驱动电路的控制端。第二初始化电路被配置为在第二复位控制信号的控制下将第二初始化电压施加至驱动电路的第二端。储能电路被配置为存储写入到驱动电路的控制端的数据信号。第一初始化电路包括第一晶体管，数据写入电路包括第二晶体管，驱动电路包括第三晶体管，第一晶体管的第一有源层的半导材料的漏电流特性小于第三晶体管的第三有源层的半导材料的漏电流特性；第二晶体管的第二有源层的半导材料的漏电流特性小于第三晶体管的第三有源层的半导材料的漏电流特性。
本公开至少一实施例还提供了一种对应于上述像素电路的驱动方法、阵列基板和显示装置。
在本公开至少一实施例提供的像素电路中，第一晶体管的第一有源层的半导材料的漏电流特征和第二晶体管的第二有源层半导材料的漏电流特性分别小于第三晶体管的第三有源层的半导材料的漏电流特性，因此在储能电路的漏电通路上的漏电流更低，提高了驱动电路的控制端的电压保持率，从而可以实现低频驱动，也即，该像素电路可以至少部分地避免低频驱动下闪屏等现象的产生。
下面结合附图对本公开的实施例进行详细说明。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开实施例的一个示例提供一种像素电路10，该像素电路10例如用于OLED显示装置的子像素。如图1所示，该像素电路10包括驱动电路100、数据写入电路200、第一发光控制电路300、第二发光控制电路400、第一初始化电路500、第二初始化电路600和储能电路700。该像素电路10例如控制发光元件800发光。
例如，驱动电路100包括第一端110、第二端120和控制端130，并且驱动电路100配 置为控制流经第一端110和第二端120的用于驱动发光元件800发光的驱动电流。例如，驱动电路100的控制端130和第一节点N1连接，驱动电路100的第一端110和第二节点N2连接，驱动电路100的第二端120和第三节点N3连接。例如，在发光阶段，驱动电路100可以向发光元件800提供驱动电流以驱动发光元件800进行发光，并且驱动电流可以根据写入的数据信号(下面详细描述)而改变，从而可以根据需要的“灰度”发光。例如，发光元件800可以采用有机发光二极管(OLED)、量子点发光二极管(QLED)、无机发光二极管等，本公开的实施例包括但不限于此。该发光元件配置为一端和第二电压端VSS(例如，提供低电平，例如接地)连接，本公开的实施例包括但不限于此情形。
例如，数据写入电路200被配置为在第一扫描信号Gate_N的控制下将数据信号Vdata写入驱动电路100的控制端130。例如，数据写入电路200与驱动电路100的控制端130、第一扫描线(第一扫描信号端Gate_N)和数据线(数据信号端Vdata)连接。例如，来自第一扫描信号端Gate_N的第一扫描信号被施加至数据写入电路200以控制数据写入电路200是否开启，在数据写入电路200开启的情况下，来自数据线的数据信号Vdata经数据写入电路200被写入到驱动电路100的控制端130。
例如，第一发光控制电路300被配置为在第一发光控制信号EM1的控制下将第一电源端的第一电源电压VDD施加至驱动电路100的第一端110。例如，第一发光控制电路300与驱动电路100的第一端110、储能电路700和第一电源端VDD连接。例如，第一发光控制信号EM1被施加至第一发光控制电路300以控制第一发光控制电路300是否开启，在第一发光控制电路300开启的情况下，第一电源端的第一电源电压VDD被施加至驱动电路100的第一端110。
例如，在发光阶段，第一发光控制电路300可以响应于第一发光控制信号EM1而开启，从而可以将第一电源电压VDD施加至驱动电路100的第一端110，在驱动电路100导通时，像素电路中产生流经驱动电路100的驱动电流。例如，第一电源电压VDD可以是驱动电压，例如高电压(高于第二电压VSS)。
例如，第二发光控制电路400被配置为在第二发光控制信号EM2的控制下将来自驱动电路100的第二端120的驱动电流施加至发光元件800。例如，第二发光控制电路400与驱动电路100的第二端120和发光元件800连接。例如，第二发光控制信号EM2被施加至第二发光控制电路400以控制第二发光控制电路400是否开启。例如，在发光阶段，第二发光控制电路400可以响应于第二发光控制信号EM2而开启，从而可以将来自驱动电路100的驱动电流施加至发光元件800以提供驱动电压，从而驱动发光元件发光。
例如，第一初始化电路500被配置为在第一复位控制信号Re_N的控制下将第一初始化电压Vinit1施加至驱动电路100的控制端130。例如，第一初始化电路500连接至第一节点N1，以与驱动电路100的控制端130连接，并且与第一复位控制信号线(第一复位控制信号端Re_N)和第一初始化电压线(第一初始化电压端Vinit1)连接。例如，在复位阶段，第一初始化电路500可以响应于第一复位控制信号Re_N而开启，从而可以将第一初始化电 压Vinit1施加至第一节点，以对驱动电路100的控制端进行复位，从而消除例如在OLED显示面板或显示装置中前一帧显示过程中施加至驱动电路100的控制端数据信号的影响。
例如，第二初始化电路600被配置为在第二复位控制信号Re_P的控制下将第二初始化电压Vinit2施加至驱动电路100的第二端120。例如，第二初始化电路600连接至第三节点N3，以与驱动电路100的第二端120连接，并且与第二复位控制信号线(第一复位控制信号端Re_P)和第二初始化电压线(第一初始化电压端Vinit2)连接。例如，在复位阶段，第二初始化电路600可以响应于第二复位控制信号Re_P而开启，从而可以将第二初始化电压Vinit2施加至第二节点，从而对驱动电路100的第二端120进行复位。
例如，储能电路700被配置为存储写入到驱动电路100的控制端130的数据信号Vdata。例如，储能电路700与第一节点N1和第一电源端VDD连接。
在像素电路10中，第一初始化电路包括第一晶体管，数据写入电路包括第二晶体管，驱动电路包括第三晶体管，第一晶体管的第一有源层的半导材料的漏电流特性小于第三晶体管的第三有源层的半导材料的漏电流特性，第二晶体管的第二有源层的半导材料的漏电流特性小于第三晶体管的第三有源层的半导材料的漏电流特性。由于第一初始化电路包括的第一晶体管和数据写入电路包括的第二晶体管具有更小的漏电流特性，从而在工作过程中导致更小的漏电流，从而在储能电路中存储的数据信号得以更长时间保持，从而使得驱动电路控制的驱动电流的大小更稳定，由此采用该像素电路的显示面板或显示装置可以实现更好的显示品质。而且，由于储能电路中存储的数据信号得以更长时间保持，因此在显示过程中刷新像素电路的频率可以降低，从而可以降低显示面板或显示装置的功耗。
或者，第一晶体管以及第二晶体管的有源层的半导材料的漏电流特性小于第三晶体管的有源层的半导体材料的漏电流特性，而且第一晶体管以及第二晶体管的有源层的半导材料的漏电流特性也小于第二初始化电路、第一发光控制晶体管、第二发光控制晶体管中任一所包括的晶体管的有源层的半导材料的漏电流特性。
又或者，在另一个实施例中，第一晶体管以及第二晶体管的有源层的半导材料的漏电流特性不与第三晶体管的有源层的半导体材料的漏电流特性比较(例如二者基本相等，或者前者大于后者)，但是使得第一晶体管以及第二晶体管的有源层的半导材料的漏电流特性小于第二初始化电路、第一发光控制晶体管、第二发光控制晶体管中任一所包括的晶体管的有源层的半导材料的漏电流特性。
在本公开中，“漏电流特性”指所涉及晶体管具有相同尺寸(包括沟道的宽长比)以及施加相同电压(包括栅极电压、源极电压和漏极电压)情况下在晶体管的有源层中产生的漏电流的大小。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2和第三节点N3并非表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vdata既可以表示数据信号端又可以表示数据信号的电平，同样地，符号Vinit1和Vinit2既可以表示复位电压端又可以表示复 位电压，符号VDD既可以表示第一电源电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电压。以下各实施例与此相同，不再赘述。
需要说明的是，本公开的实施例中的第一电源电压端VDD例如保持输入直流高电平信号，将该直流高电平称为第一电源电压；第二电压端VSS例如保持输入直流低电平信号，将该直流低电平称为第二电压，低于第一电源电压。以下各实施例与此相同，不再赘述。
例如，在本公开的一些实施例中，第一晶体管的第一有源层的半导材料和第二晶体管的第二有源层的半导材料相同，该半导材料的漏电流特性小于第三晶体管的第三有源层的半导体材料的漏电流特性。
在本公开的另一些实施例中，第一晶体管的第一有源层的半导材料和第二晶体管第二有源层的半导材料也可以不相同，但第一有源层的半导材料的漏电流特性和第二有源层的半导材料的漏电流特性都小于第三有源层的半导体材料的漏电流特性。
例如，第一晶体管的第一有源层的半导材料和第二晶体管的第二有源层的半导材料均为氧化物半导体，第三晶体管的第三有源层的多晶硅半导材料。氧化物半导体的漏电流特性小于多晶硅半导材料的漏电流特性，这样可以降低漏电流通路上的漏电流，从而至少部分地避免闪屏的发生。
例如，氧化物半导体为氧化铟半导体材料，例如可以为IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)或掺杂的IGZO；多晶硅半导材料为低温多晶硅半导体材料或高温多晶硅半导体材料，通常在将非晶硅结晶以得到多晶硅的过程中，操作温度低于600摄氏度的，所得到的多晶硅被称为低温多晶硅，反之则称为高温多晶硅。
在本公开的一些实施例中，该像素电路10可以同时包括N型晶体管和P型晶体管。例如，第一晶体管和第二晶体管可以是N型晶体管，第三晶体管可以是P型晶体管。
在本公开的一些实施例中，该像素电路10仅使用N型晶体管，由于N型晶体管的尺寸较小，从而可以增加显示面板或显示装置的分辨。例如，第一晶体管和第二晶体管是N型晶体管，而第三晶体管是N型晶体管，但是第一晶体管和第二晶体管的有源层的半导体材料(例如氧化物半导体材料)不同于第三晶体管的有源层的半导体材料(例如多晶硅半导体材料)。相比与其他仅使用N晶体管的像素电路，本公开实施例中，由于第一晶体管和第二晶体管对应的N型晶体管的漏电流较小，因此可以在该像素电路用于低频率驱动时克服闪屏现象；另一方面，由于该第一晶体管和第二晶体管对应的N型晶体管的漏电流较小，所以在显示面板或显示装置使用过程中晶体管的老化问题得到缓解。
在本公开的一些实施例中，第一发光控制电路、第二发光控制电路，第二初始化电路分别包括的晶体管的有源层的半导材料与第三晶体管的第三有源层的半导材料相同且同层设置。例如，第一发光控制电路、第二发光控制电路，第二初始化电路分别包括的晶体管的有源层的半导材料与第三晶体管的第三有源层的半导材料都是低温多晶硅半导体材料，例如N型或P型低温多晶硅半导体材料。在这些实施例中，第一晶体管和第二晶体管的有源层的半导材料为N型氧化物半导体材料且同层设置。这样可以简化该像素电路的制备工艺， 降低制造成本。
例如，图1中所示的像素电路10的一个具体示例可以为图2所示的像素电路。如图2所示，该像素电路10包括第一晶体管至第六晶体管T1、T2、T3、T4、T5、T6以及包括第一电容C1和第二电容C2。
例如，第三晶体管T3被用作驱动晶体管，其他的第一晶体管、第二晶体管以及第四晶体管至第六晶体管被用作开关晶体管。例如，发光元件L1可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图2所示，第一复位控制电路500可以实现为第一晶体管T1。第一晶体管T1的栅极和第一复位控制信号端Re_N连接以接收第一复位控制信号Re_N。第一晶体管T1的第一极和第一初始化电压端Vinit1连接以接收第一初始化电压Vinit1。第一晶体管T1的第二极和驱动电路100的控制端130(第一节点N1)连接。例如，该第一晶体管T1为N型晶体管，例如第一有源层的半导材料为氧化物半导体。例如，N型晶体管响应于高电平信号开启，以下实施例与此相同，不再赘述。
例如，如图2所示，数据写入电路200可以实现为第二晶体管T2。第二晶体管T2的栅极和第一扫描信号端Gate_N连接以接收第一扫描信号Gate_N。第二晶体管T2的第一极和数据信号端Vdata连接以接收数据信号Vdata。第二晶体管T2的第二极和驱动电路100的控制端130(第一节点N1)连接。例如，该第二晶体管T2为N型晶体管，例如第二有源层的半导材料为氧化物半导体。
例如，如图2所示，驱动电路100可以实现为第三晶体管T3。第三晶体管T3的栅极作为驱动电路100的控制端130，和第一节点N1连接；第一晶体管T1的第一极作为驱动电路100的第一端110，和第二节点N2连接；第一晶体管T1的第二极作为驱动电路100的第二端120，和第三节点N3连接。例如，该第三晶体管T3为P型晶体管，例如第三有源层的半导材料为低温多晶硅半导体材料。例如，P型晶体管响应于低电平信号开启，以下实施例与此相同，不再赘述。
例如，如图2所示，第二复位控制电路600可以实现为第四晶体管T4。第四晶体管T4的栅极和第二复位控制信号端Re_P连接以接收第二复位控制信号Re_P。第四晶体管T4的第一极和第二初始化电压端Vinit2连接以接收第二初始化电压Vinit2。第四晶体管T4的第二极和驱动电路100的第二端120(第三节点N3)连接。例如，该第四晶体管T4为P型晶体管，例如第四晶体管T4的有源层的半导材料为低温多晶硅半导体材料。
例如，如图2所示，第一发光控制电路300可以实现为第五晶体管T5。第五晶体管T5的栅极和第一发光控制信号端EM1连接以接收第一发光控制信号EM1。第五晶体管T5的第一极和第一电源端VDD连接以接收来自第一电压端的第一电源电压VDD，并且第五晶体管T5的第一极和储能电路700连接。第五晶体管T5的第二极和驱动电路100的第一端110(第二节点N2)连接。例如，该第五晶体管T5为P型晶体管，例如第五晶体管T5的 有源层的半导材料为低温多晶硅半导体材料。
例如，如图2所示，第二发光控制电路400可以实现为第六晶体管T6。第六晶体管T6的栅极和第二发光控制信号端EM2连接以接收第二发光控制信号EM2。第六晶体管T6的第一极和发光元件L1连接。第六晶体管T6的第二极和驱动电路100的第二端120(第三节点N3)连接。例如，该第六晶体管T6为P型晶体管，例如第六晶体管T6的有源层的半导材料为低温多晶硅半导体材料。
发光元件L1的第一端(这里为阳极)和第六晶体管T6的第一极连接配置为通过第二发光控制电路400从驱动电路100的第二端120接收驱动电流，发光元件L1的第二端(这里为阴极)配置为和第二电压端VSS连接以接收第二电压。例如第二电压端可以接地，即VSS可以为0V。
例如，在本公开的一些实施例中，储能电路700包括第一电容C1和第二电容C2。第一电容C1电连接在驱动电路100的控制端130和驱动电路100的第一端110之间，第二电容C2电连接在驱动电路100的第一端110与第一电源电压端VDD之间，且第一电容C1与驱动电路100的第一端110电连接的电极与第二电容C2与驱动电路100的第一端110电连接的电极电连接。
例如，如图2所示，第一电容C1电连接在第三晶体管T3的栅极和第三晶体管的第一极之间。第二电容C2电连接在第三晶体管T3的第一极和第一电源电压端VDD之间，且第一电容C1中与第三晶体管T3的第一极电连接的电极和第二电容C2中与第三晶体管T3的第一极电连接的电极电连接，例如，第一电容C1和第二电容C2可以共用同一电极，而二者电连接的电极一体形成。第一电容C1的电容值和第二电容C2的电容值被设定以用于补偿操作，且第二电容C2的电容值被用于调节数据范围(data range)，对此后续将进行说明。
在一些视频图像的显示过程中，为了降低OLED的功耗，可以采用低频信号对像素电路进行驱动，然而在像素电路采用漏电流特性较高的晶体管实现时，由于晶体管的漏电流比较大，采用低频驱动会产生闪屏(Flicker)等现象，从而限制了该像素电路的使用。在本公开实施例中，该像素电路采用具有不同漏电流特性的晶体管，例如，相对于第三晶体管而言，第一晶体管T1和第二晶体管T2采用漏电流特性较低的晶体管。由于漏电通路中的第一晶体管T1和第二晶体管T2的漏电流较小，因此可以在该像素电路用于低频率驱动时克服闪屏现象。
可选地，同样地，相对于第四晶体管、第五晶体管或第六晶体管而言，第一晶体管T1和第二晶体管T2采用漏电流特性更低的晶体管。
又或者，在不考虑第三晶体管T3的漏电流特性的情况下，相对于第四晶体管、第五晶体管或第六晶体管而言，第一晶体管T1和第二晶体管T2采用漏电流特性更低的晶体管。
本公开的另一方面提供了一种驱动像素电路的方法。该方法包括第一操作时段。第一操作时段包括复位阶段、采样阶段、写入阶段和发光阶段。下面结合图3对第一操作时段进行 说明。
图3为本公开一实施例提供的一种驱动像素电路的方法的流程图。
如图3所示，驱动上述图1或者图2所示的像素电路的方法包括4个阶段，分别为复位阶段301、采样阶段302、写入阶段303和发光阶段304。
在复位阶段301，使得第一初始化电路在第一复位控制信号的控制下导通，将第一初始化电压施加至驱动电路的控制端，并且使得第二初始化电路在第二复位控制信号的控制下导通，将第二初始化电压施加至驱动电路的第二端。
例如，在图1所示的像素电路10中，使得第一初始化电路500在第一复位控制信号Re_N的控制下导通，将第一初始化电压Vinit1施加至驱动电路100的控制端130，以及使得第二初始化电路600在第二复位控制信号Re_P的控制下导通，将第二初始电压Vinit2施加至驱动电路100的第二端120。
例如，在图2中，使得第一晶体管T1在第一复位控制信号Re_N的控制下导通，将第一初始化电压Vinit1施加至第三晶体管的栅极，以及使得第四晶体管T4在第二复位控制信号Re_P的控制下导通，将第二初始电压Vinit2施加至第三晶体管T3的第二端120。
在本公开的一些实施例中，在复位阶段301，还可以使得第一发光控制电路300在第一发光控制信号EM1的控制下导通，将第一电源端的第一电源电压VDD施加至驱动电路100的第一端，还使得第二发光控制电路400在第二发光控制信号EM2的控制下导通，将来自第二初始化电路600的第二初始化电压Vinit2施加至发光元件。
例如，在图2中，使得第五晶体管T5在第一发光控制信号EM1的控制下导通，将第一电源端的第一电源电压VDD施加至第三晶体管的第一极(即，第二节点N2)，以及使得第六晶体管T6在第二发光控制信号EM2的控制下导通，将第二初始电压Vinit2施加至发光元件L1。
在本公开的一些实施例中，在第二初始化电路600将第二初始化电压Vinit2施加至发光元件800的情况下，使得第二初始化电压Vinit2避免发光元件导通。也即，在第四晶体管T4将第二初始电压Vinit2施加至发光元件L1的情况下，设定第二初始化电压Vinit2的值例如小于等于第二电源电压VSS的值，由此发光元件L1两端无电压差或被偏置，从而可以避免发光元件L1在此阶段导通而例如发光。
在本公开的一些实施例中，第一初始化电压和第二初始化电压彼此不同。也即，第一初始化电压Vinit1和第二初始化电压Vinit2连接到不同的电压端，从而可以分开设置从而彼此不相同。例如，第二初始电压Vinit2小于第一初始化电压Vinit1。例如，第一初始化电压Vinit1可以为直流电压，第一初始化电压Vinit1的电压值可以在大于或等于-7V而小于或等于0V；例如，第一初始化电压Vinit1的电压值可以为-6V、-5V、-4V、-3V或-2V，但不限于此。
例如，第二初始化电压Vinit2可以为直流电压，第二初始化电压Vinit2的电压值可以在大于或等于-7V而小于或等于0V；例如，第二初始化电压Vinit2的电压值可以为-6V、- 5V、-4V、-3V或-2V，但不限于此。在采样阶段302，使得第一发光控制电路和第二发光控制电路截止，且使得第一初始化电路在第一复位控制信号的控制下保持导通，将第一初始化电压施加至驱动电路的控制端，使得第二初始化电路在第二复位控制信号的控制下保持导通，将第二初始化电压施加至驱动电路的第二端。由此，可以在驱动电路的第二端写入驱动电路的阈值电压以用于像素电路的补偿操作。
例如，在图1所示的像素电路10中，使得第一发光控制电路300和第二发光控制电路400截止，且使得第一初始化电路500在第一复位控制信号Re_N的控制下保持导通，将第一初始化电压Vinit1施加至驱动电路100的控制端130，使得第二初始化电路600在第二复位控制信号Re_P的控制下保持导通，将第二初始化电压Vinit2施加至驱动电路100的第二端120。例如，在图2中，第五晶体管T5和第六晶体管T6截止，第一晶体管T1在第一复位控制信号Re_N的控制下保持导通，将第一初始化电压Vinit1施加至第三晶体管T3的栅极，以及使得第四晶体管T4在第二复位控制信号Re_P的控制下保持导通，将第二初始化电压Vinit2施加至第三晶体管的第二端120，在此阶段可以对第二节点N2(第三晶体管T2的第一端)的电压进行调整从而写入第三晶体管T2的阈值电压，以用于像素电路的补偿操作，后面将结合信号具体描述。
在写入阶段303，使得第一初始化电路、第二初始化电路、第一发光控制电路和第二发光控制电路截止，使得数据写入电路在第一扫描信号的控制下将接收的数据信号写入到驱动电路的控制端，通过储能电路将数据信号存储在储能电路之中。
例如，在图1所示的像素电路中，使得第一初始化电路500、第二初始化电路600、第一发光控制电路300和第二发光控制电路400截止，使得数据写入电路200在第一扫描信号Gate_N的控制下将接收的数据信号Vdata写入到驱动电路100的控制端130，通过储能电路700将数据信号存储在储能电路700之中。例如，在图2中，使得第一晶体管T1、第四晶体管T4、第五晶体管T5和第六晶体管T6截止，使得第二晶体管在第一扫描信号Gate_N的控制下将接收的数据信号Vdata写入到第三晶体管300的栅极，同时也通过第三晶体管T3的作用对第二节点N2的电压进行调整，以用于补偿操作。
在发光阶段304，使得第一初始化电路和第二初始化电路截止，且使得第一发光控制电路在第一发光控制信号的控制下导通，将第一电源端的第一电源电压施加至驱动电路的第一端，使得第二发光控制电路在第二发光控制信号的控制下导通，将来自驱动电路的第二端的驱动电流施加至发光元件，以驱动发光元件。
例如，在图1所示的像素电路中，使得第一初始化电路500、第二初始化电路600截止，且使得第一发光控制电路300在第一发光控制信号EM1的控制下导通，将第一电压端的第一电源电压VDD施加至驱动电路100的第一端110，使得第二发光控制电路400在第二发光控制信号EM2的控制下导通，将来自驱动电路100的第二端120的驱动电流施加至发光元件800，以驱动发光元件800发光。
例如，在图2中，使得第一晶体管T1、第四晶体管T4截止，且使得第五晶体管T5在 第一发光控制信号EM1的控制下导通，将第一电压端的第一电源电压VDD施加至第三晶体管T3的第一极，使得第六晶体管T6在第二发光控制信号EM2的控制下导通，将来自第三晶体管T3的第二极的驱动电流施加至发光元件L1，以驱动发光元件L1发光。
下面结合图2和图4A所示的信号时序图，对图3所示的驱动像素电路的方法作进一步说明。
如图4A所示，每一帧图像的显示过程包括四个阶段，分别为复位阶段t1、采样阶段t2、写入阶段t3和发光阶段t4，图中示出了每个阶段中各个信号的时序波形。
在复位阶段t1，输入第一复位控制信号和第二复位控制信号以开启第一初始化电路500和第二初始化电路600，将第一初始化电压Vinit1施加至驱动电路100的控制端130，将第二初始电压Vinit2施加至驱动电路100的第二端120。
如图2和图4A示，在复位阶段t1，由于第一晶体管T1是N型晶体管，第一晶体管T1被第一复位控制信号Re_N的高电平导通，第一初始电压Vinit1经第一晶体管T1写入第一节点N1。第四晶体管T4是P型晶体管，第四晶体管T4被第二复位控制信号Re_P的低电平导通，第二初始电压Vinit2经第四晶体管T4写入第三节点N3。同时，第二晶体管T2为N型晶体管，被第一扫描信号Gate_N的低电平截止。
在本公开的一些实施例中，第一发光控制信号EM1和第二发光控制信号EM2相同。如图4A所示，第一发光控制信号EM1和第二发光控制信号EM2都为同一发光控制信号EM。
如图2和图4A所示，在复位阶段t1，发光控制信号EM为低电平，即第一发光控制信号EM1和第二发光控制信号EM2为低电平，因此第五晶体管T5和第六晶体管T6导通。此时，第二节点N2的电压被设置为VDD电位，而发光元件L1的第一端的电压被设置为第二初始电压Vinit2。
所以，经过复位阶段t1后第一节点N1电位为第一初始电压Vinit1，第二节点N2电位为第一电源电压VDD，第三节点N3和发光元件L1的第一端的电位为第二初始电压Vinit2。
在本公开的一些实施例中，在第四晶体管T4将第二初始电压Vinit2施加至发光元件L1的情况下，使得第二初始化电压Vinit2避免发光元件L1导通。例如，第二初始化电压Vinit2与第二电源电压VSS相比为更低的电平，从而使得避免发光元件L1导通。
并且，可以选择第一初始电压Vinit1的值使得第三晶体管T3处于在截止状态但具有漏电流的状态，或者能处于产生微弱电流的状态。
在采样阶段t2，发光控制信号EM为高电平，即第一发光控制信号EM1和第二发光控制信号EM2为高电平，因此第五晶体管T5和第六晶体管T6截止。
如上所述，根据第三晶体管T3自身的特性，虽然第一节点N1处于第一初始电压Vinit1，第三晶体管T3具有漏电流或处于能产生微弱电流的状态，第三晶体管T3的源极的电位(即，第二节点N2的电位)被放电至Vinit1-Vth从而第三晶体管被截止，Vth为第三晶体管的阈值电压。从而在此阶段，可以使第三晶体管T3的栅极(即第一节点N1)和源极(即第二节 点N2)的电压VGS满足：|VGS|＝|Vth|。由此，在第二节点N2记录了第三晶体管(即驱动晶体管)的阈值电压。
在写入阶段t3，第一晶体管T1在第一复位控制信号Re_N的低电平在作用下截止，第四晶体管T4在第二复位控制信号Re_P的高电平在作用下截止。第二晶体管T2在第一扫描信号Gate_N的高电平的作用下导通，并且此时在数据线上施加了数据信号Vdata，由此该数据信号Vdata经第二晶体管T2被写入，使得第一节点N1被写入Vdata电位。发光控制信号EM为高电平，即第一发光控制信号EM1和第二发光控制信号EM2为高电平，因此第五晶体管T5和第六晶体管T6截止。第二节点N2的电位由于第一电容C1(以及第二电容C2)的耦合作用，变化为C1/(C1+C2)(Vdata-Vinit1)+Vinit1-Vth。
在发光阶段t4，发光控制信号EM为低电平，即第一发光控制信号EM1和第二发光控制信号EM2为低电平，因此第五晶体管T5和第六晶体管T6导通。此时，第二节点N2的电位回到第一电源电压VDD，像素电路产生驱动电流，该驱动电流被施加到发光元件L1以驱动发光元件L1发光。在该阶段，第一节点N1的电位被耦合至C2/(C1+C2)(Vdata-Vinti1)+Vdd+Vth。第三晶体管T3处于饱和状态，因此驱动发光元件L1的驱动电流按照如下的公式计算。
I OLED＝1/2*K*(Vgs-Vth) 2，其中，K＝W*C OX*U/L。
将如下值：
Vg＝V N1＝C2/(C1+C2)(Vdata-Vinti1)+Vdd+V TH,
Vs＝V N2＝Vdd，
Vgs＝Vg-Vs＝C2/(C1+C2)(Vdata-Vinti1)+V TH,
代入上述公式可以得到：
I OLED＝1/2*K*(C2/(C1+C2)(Vdata-Vinti1)) 2。
在上述公式中，Vth表示第三晶体管T3的阈值电压，K为与驱动晶体管本身相关的一常数值。从上述I OLED的计算公式可以看出，流经发光元件L1的驱动电流I OLED不再与第三晶体管T3的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为第三晶体管T3)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流I OLED的影响，从而可以改善采用其的显示装置的显示效果。
并且由上述公式I OLED＝1/2*K*(C2/(C1+C2)(Vdata-Vinti1)) 2中可以看出，可以通过设置C1/C2之间的比值来设定同一Vdata产生的驱动电流的大小，设定像素单元显示的灰阶范围以及分辨率。
如上所述，OLED显示面板或显示装置可以工作在不同的频率下，正常显示的刷新频率较高，另外可以选择较低的刷新频率以节省功耗。例如，在本公开的一些实施例中，上述驱动像素电路的方法在包括第一操作时段的基础上还可以包括第二操作时段，第二操作时段在时间上紧接在第一操作时段之后。第一发光控制信号EM1、第二发光控制信号EM2以及第二复位控制信号Re_P具有第一频率，第一复位控制信号Re_N和第一扫描信号Gate_N 具有第二频率，第一频率大于第二频率。与第一操作时段相比，在第二操作时段中，第一发光控制信号EM1、第二发光控制信号EM2以及所述第二复位控制信号Re_P进入不同的周期，所述第一复位控制信号和所述第一扫描信号仍然在同一周期。在这种情况下，相比正常显示操作，采用上述像素电路的显示面板或显示装置工作在低刷新频率下。
图4B为本公开一实施例提供的一种高频驱动和低频驱动的时序对比图。
如图4B所示，在本公开的一些实施例中，可以按照高频驱动的方式驱动像素电路10，如图4B中的高频时序图。
在本公开的另一些实施例中，可以按照低频驱动的方式驱动像素电路10，如图4B中的低频时序图。
如图4B所示，在高频时序图中，其每个驱动周期与图4A相同。因此，在每个周期(操作时段)中，发光控制信号EM(即第一发光控制信号EM1、第二发光控制信号EM2)、第二复位控制信号Re_P、第一扫描信号Gate_N和第一复位控制信号Re_N分别对应不同的周期，每个周期内都会进行复位、采样、数据写入以及发光这四个阶段，具体不再赘述。
如图4B所示，在低频时序图中，驱动像素电路的方法在包括第一操作时段的基础上还可以包括例如至少一个第二操作时段，第二操作时段在时间上紧接在第一操作时段之后。第一操作时段与图4A所示相同，进行了复位、采样、数据写入以及发光这四个阶段，具体不再赘述；在第二操作时段中，第一发光控制信号EM1、第二发光控制信号EM2以及第二复位控制信号Re_P具有第一频率，第一复位控制信号Re_N和第一扫描信号Gate_N具有第二频率，第一频率大于第二频率。例如，第一频率大于30Hz，第二频率为1Hz～10Hz。而且，在第二操作时段中，在第一操作时段中写入的数据信号将被储能电路(例如存储电容)存储从而保留，从而继续控制驱动电路，由此可以在第一发光控制信号EM1、第二发光控制信号EM2分别开启第一发光控制电路、第二发光控制电路时，仍然在像素电路中产生驱动电流以驱动发光元件L1发光。
例如，第二操作时段的时长与第一操作时段的时长相同。第二操作时段的数量不限于一个可以是多个，例如在图4B中示出至少2个第二操作时段，当然本公开的实施例不限于此。第二操作时段的数量通常根据低频驱动时的频率，该频率相对于高频驱动时的频率越低，则第二操作时段的数量越大。
例如，与第一操作时段相比，在第二操作时段中，第一发光控制信号EM1、第二发光控制信号EM2以及第二复位控制信号Re_P进入不同的周期，第一复位控制信号和第一扫描信号仍然在同一周期。
通过降低第一复位控制信号Re_N和第一扫描信号Gate_N的频率，可以节省功耗，并且由于第一晶体管T1和第二晶体管T2的漏电流特性较小，储能电路中存储的数据信号得以更长时间被保留，因此，在节省功耗的同时，可以降低闪屏的发生。
图5为本公开一实施例提供的另一种像素电路的示意框图。
如图5所示，像素电路20在像素电路10的基础上还包括复位电路900。在像素电路20 中，除复位电路之外的其他电路结构与像素电路10中的电路结构相同，在此不再赘述。
复位电路被配置为，将复位电压写入驱动电路100的第一端，以对驱动电路中的驱动晶体管提供偏压。
具体地，在一实施例中，复位电路900被配置为将第一发光控制信号EM1的变化耦合至驱动电路100的第一端。
当低频驱动的保持帧时，第一扫描信号Gate_N使得数据写入电路200截止，可通过复位电路900由EM1带动第二节点N2向上跳变，在没有复位阶段t1的情况下仍让第二节点N2存在高频的一定程度的复位特性，从而可以降低闪屏的发生。也就是说，通过复位电路900可以将第二节点N2的电压进行高频周期性调节，可以将一部分低频分量变为高频分量，从而降低了闪屏的发生。
图6为图5中所示的像素电路的一种具体实现示例的电路图。
如图6和图5所示，复位电路900包括第三电容C3，第三电容C3电连接在第一发光控制电路300的控制端与驱动电路100的第一端之间。也就是说，第三电容C3电连接在第五晶体管T5的控制端与第三晶体管T3的第一极之间。该第三电容C3的电容值通常设定为远小于第二电容C2的电容值，由此基本上不影响第二电容C2所存储数据信号。例如，第三电容C3的电容值是为第二电容C2的电容值的十分之一，或者是百分之一，或更小。
在本公开的一些实施例中，第三电容C3包括彼此相对且位于不同层的第一电容电极和第二电容电极。例如，该第一电容电极与第三晶体管T3的第三有源层一体设置，或者第一电容电极经过孔与第三晶体管的第三有源层电连接。另外，第二电容电极与第一发光控制电路300的控制端一体设置或与之电连接。
图5和图6所示的像素电路20的驱动方法与上文中驱动像素电路10的驱动方法类似。例如，驱动像素电路20的驱动方法包括第一操作时段。第一操作时段包括复位阶段、采样阶段、写入阶段和发光阶段。
对于复位阶段和采样阶段，与驱动像素电路10的方法类似，在此不再赘述。
在写入阶段t3，第一晶体管T1在第一复位控制信号Re_N的低电平在作用下截止，第四晶体管T4在第二复位控制信号Re_P的高电平在作用下截止。第二晶体管T2在第一扫描信号Gate_N的高电平的作用下导通，第一节点N1被写入Vdata电位。发光控制信号EM为高电平，即第一发光控制信号EM1和第二发光控制信号EM2为高电平，因此第五晶体管T5和第六晶体管T6截止。第二节点N2由于C1的耦合作用，电位变化为：
C1/(C1+C2+C3)(Vdata-Vinit1)+Vinit1-Vth。
在发光阶段t4，发光控制信号EM为低电平，即第一发光控制信号EM1和第二发光控制信号EM2为低电平，因此第五晶体管T5和第六晶体管T6导通。此时，第二节点N2回到VDD电位，发光元件L1发光。第一节点N1的电位耦合至C2/(C1+C2+C3)(Vdata-Vinti1)+Vdd+Vth。因此，发光元件L1的驱动电流按照如下的公式计算。
I OLED＝1/2*K*(Vgs-Vth) 2，其中，K＝W*C OX*U/L。
将如下值：
Vg＝V N1＝C2/(C1+C2+C3)(Vdata-Vinti1)+Vdd+V TH,，
Vs＝V N2＝Vdd，
Vgs＝Vg-Vs＝C2/(C1+C2+C3)(Vdata-Vinti1)+V TH,
代入上述公式可以得到：
I OLED＝1/2*K*(C2/(C1+C2+C3)(Vdata-Vinti1)) 2。
同样地，从上述I OLED的计算公式可以看出，流经发光元件L1的驱动电流I OLED不再与第三晶体管T3的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为第三晶体管T3)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流I OLED的影响，从而可以改善采用其的显示装置的显示效果。
并且，由上述公式I OLED＝1/2*K*(C2/(C1+C2+C3)(Vdata-Vinti1)) 2中可以看出，由于第三电容的电容值C3很小，因此可以通过设置C1/C2之间的比值来设定同一Vdata产生的驱动电流的大小，设定像素单元显示的灰阶范围以及分辨率。
下面将结合图7A～7N说明本公开多个实施例的版图以及叠层结构。需要说明的是，图7A～图7N仅示出了示例性的像素电路中的第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第一源漏极金属层、第二源漏极金属层之间的层叠位置关系，本公开的实施例不限于所示出的具体位置、尺寸、图形等。
图7A为本公开一实施例提供的一种图2所示的像素电路的示例性部分版图。图7B为图7A所示的像素电路的叠层示意图。
在根据本公开的至少一个实施例中，显示基板包括衬底基板710以及形成在衬底基板710上的叠层，该叠层可以包括第一有源层701、第一导电层702、第二导电层703、第二有源层(未示出)、第三导电层704、第一源漏极金属层706、第二源漏极金属层(未示出)等。这些层从衬底基板开始依次层叠在衬底基板上。例如，在垂直于衬底基板的方向上，第一有源层位于衬底基板与第一导电层之间，第一导电层位于第一有源层和第二导电层之间，第二导电层位于第一导电层和第二有源层之间，第二有源层位于第二导电层和第三导电层之间，第三导电层位于第二有源层和第一源漏极金属层之间，第一源漏极金属层位于第三导电层和第二源漏极金属层之间，第二源漏极金属层可以用于与发光元件电连接等。图7B所示的叠层示意图例如以第三晶体管T3为例，也即图中所示的第一有源层701、第一导电层702为分别对应于该晶体管的有源层和栅极。
在该实施例的至少一个示例中，第一有源层例如为低温多晶硅半导体层，用于形成像素电路中例如驱动电路的晶体管的有源层，并且例如还可以用于形成像素电路中第一发光控制电路的晶体管、第二发光控制电路的晶体管、第二初始化电路的晶体管的有源层。根据各个晶体管的类型(N型或P型)，对于第一有源层中对应于不同晶体管的不同部分的源漏区进行掺杂或对沟道区进行掺杂。对应地，第二有源层例如为氧化物半导体层，用于形成像素电路中第一初始化电路的晶体管(第一晶体管)和数据写入电路的晶体管(第二晶体管)的 有源层。
图7C示出了示例性部分版图中第一有源层701的示意性版图。
如图7A和7C所示，在该部分版图中，第一有源层701整体上呈“H”形，用于形成第三晶体管T3、第五晶体管T5和第六晶体管T6各自的有源层，这三个晶体管的有源层分别为第一有源层701的不同部分。例如，形成第三晶体管T3的有源层的部分呈“几”字形。并且，当第三晶体管T3、第五晶体管T5和第六晶体管T6导通时，需要形成从第一电源端VDD到发光元件的导电通路，因此第一有源层中除形成第三晶体管T3、第五晶体管T5和第六晶体管T6各自的有源层的部分可以分别掺杂以导体化，从而具有较低的电阻率，以将降低损耗。第一有源层中这些被导体化的部分可以称为导体化层。例如，在第三晶体管T3和第五晶体管T5之间具有导体化部分705。如图7A～图7G所示，对于相邻像素的像素电路的版图可以是呈镜像分布。例如，相邻像素的像素电路中的各层(第一有源层701、第一导电层702、第二导电层703、第二有源层、第三导电层704、第一源漏极金属层706、第二源漏极金属层等)都是镜像分布的。
第一导电层702用于形成第三晶体管T3的栅极以及第一电容C1的第一电容电极；第二导电层703形成第一电容C1的第二电容电极以及第二电容C2的第一电容电极，也即第一电容C1和第二电容C2公用一个电容电极；第三导电层704用于形成第二电容C2的第二电容电极。第二电容C2的第一电容电极是通过第二导电层703形成的，第二电容C2的第二电容电极是通过第三导电层704形成的。另外，第一导电层702还包括用于发光控制线EM的部分，该部分同时形成第五晶体管T5和第六晶体管T6的栅极(图7B中未示出)。如图7B所示，导体化部分705通过过孔7051以及形成在第一源漏电极层706中的过渡电极与第二电容C2的第一电容电极电连接。
图7A中的第一导电层702的局部形状例如为图7D所示的任意一种形状。如图7D所示，相邻像素的像素电路中的第一导电层702可以是镜像分布的。
图7A中用于形成第一电容C1的第二电容电极以及第二电容C2的第一电容电极的第二导电层703局部形状例如为图7E所示。如图7E所示，相邻像素的像素电路中的第二导电层703可以是镜像分布的。
图7A中用于形成第二电容C2的第二电容电极的第三导电层704的局部形状例如为图7F所示。如图7F所示，用于形成第二电容C2的第二电容电极的第三导电层704的局部形状可以类似于矩形。例如，两个相邻像素的第三导电层可以是一体形成的。
图7G和图7H为本公开一实施例提供的一种图6所示的像素电路的示例性部分版图。图7G为两个相邻像素的像素电路的版图，图7H为一个像素电路的示例性部分版图。下面以一个像素电路的示例性部分版图图7H为例进行说明。图7I为图7H所示的像素电路的一种示例性叠层结构；图7J为图7H所示的像素电路的另一种示例性叠层结构。
如图7H所示，在示例性版图中，图6所示的像素电路20包含第三电容C3。在图7G、图7H、图7I和图7J中，除用于形成第三电容C3的结构之外，其余部分与图7A～图7F相 同，在此不再赘述。图7I和图7J所示的叠层示意图例如以第三晶体管T3为例，也即图中所示的第一有源层701、第一导电层702为分别对应于该晶体管的有源层和栅极。
例如，参考图图7H和图7I所示，与第三晶体管的漏极直接电连接的导体化部分705和第一导电层702构成第三电容C3。为了形成第三电容C3，对于第一导电层702形成第五晶体管T5的栅极的部分进行修改，形成延伸部分7021，该延伸部分7021与第五晶体管T5的栅极一体形成，同时与导体化部分705在垂直于衬底基板的方向上彼此重叠。
又例如，参考图图7H和图7J所示，与第三晶体管的漏极直接电连接的导体化部分705和第一导电层702以及第二导电层703共同构成第三电容C3。为了形成第三电容C3，对于第一导电层702形成第五晶体管T5的栅极的部分进行修改，形成延伸部分7021，该延伸部分7021与第五晶体管T5的栅极一体形成，同时与导体化部分705在垂直于衬底基板的方向上彼此重叠。并且，由于第二导电层703中形成第二电容C2的第一电容电极的部分与导体化部分705通过过孔7051以及第一源漏电极层706中的连接电极而电连接，而上述延伸部分7021还与第二电容C2的第一电容电极在垂直于衬底基板710的方向上彼此重叠。因此，在该示例中，第三电容C3包括彼此并联的两部分，即形成在导体化层705和延伸部分之间的第一部分，以及形成在延伸部分和第二电容C2的第一电极之间的第二部分。
图7K为本公开一实施例提供的图6所示的像素电路的另一种示例性部分版图。图7L为图7K所示的像素电路的一种示例性叠层结构。图7L所示的叠层示意图例如以第三晶体管T3为例，也即图中所示的第一有源层701、第一导电层702为分别对应于该晶体管的有源层和栅极。在图7K和图7L中，除用于形成第三电容C3的结构之外，其余部分与图7A～图7F相同，在此不再赘述。
如图7K和图7L所示，与第三晶体管的漏极直接电连接的导体化部分705和第一导电层702以及第二导电层703构成第三电容C3。第二导电层703的一部分(例如形成第二电容C2的第一电极的部分)与导体化部分705通过过孔7051以及第一源漏电极层706中的连接电极而电连接，该部分作为第三电容C3的第一电容电极；第一导电层中用于形成第五晶体管T5的栅极的部分作为第三电容C3的第二电容电极(在该实施例中没有上述延伸部分7021)。该第三电容C3的第一电容电极和第二电容电极在垂直于衬底基板710的方向上彼此重叠，由此形成第三电容C3。
图7M为本公开一实施例提供的图6所示的像素电路的另一种示例性部分版图。图7N为图7M所示的像素电路的一种示例性叠层结构。图7N所示的叠层示意图例如以第三晶体管T3为例，也即图中所示的第一有源层701、第一导电层702为分别对应于该晶体管的有源层和栅极。在图7M和图7N中，除用于形成第三电容C3的结构之外，其余部分与图7A～图7F相同，在此不再赘述。
对比图7A和图7M，例如可以将第二导电层703沿Y方向加宽得到第二导电层Y方向的伸出部7031。如图7M和图7N所示，第二导电层703中的伸出部7031可以作为第三电容C3的第一电容电极，第一导电层702中用于形成第一发光控制信号线EM的部分7022 作为第三电容C3的第二电容电极。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
本公开至少一个实施例还提供一种阵列基板，包括阵列排布的多个像素单元，每个像素单元包括本公开任一实施例提供的像素电路。
图8为本公开一实施例提供的一种阵列基板的示意框图。如图8所示阵列基板11设置在显示装置1中，并与栅极驱动器12、定时控制器13和数据驱动器14电连接。该阵列基板11包括根据多条扫描线GL和多条数据线DL交叉限定的像素单元P；栅极驱动器12用于驱动多条扫描线GL；数据驱动器14用于驱动多条数据线DL；定时控制器13用于处理从显示装置1外部输入的图像数据RGB、向数据驱动器14提供处理的图像数据RGB以及向栅极驱动器12和数据驱动器14输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器12和数据驱动器14进行控制。
例如，该阵列基板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路10。例如，包括图6所示像素电路20。如图8所示，阵列基板11还包括多条扫描线GL和多条数据线DL。例如，该多条扫描线对应连接到每行像素单元的像素电路10中的数据写入电路200以提供第一扫描信号。
例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图8所示，每个像素单元P连接到五条扫描线GL(分别提供第一扫描信号Gate_N、第一复位控制信号Re_N、第二复位控制信号Re_P、第一发光控制信号EM1以及第二发光控制信号EM2)、一条数据线DL、用于提供第一电源电压VDD的第一电压线、用于提供第二电压VSS的第二电压线以及用于提供第一初始化电压Vinit1的电压线和第二初始电压Vinit2的电压线。需要说明的是，在图10中仅示出了部分的像素单元P、扫描线GL、数据线DL。
例如，该多个像素单元P排列为多行，每一行像素单元P的像素电路的第一初始化电路500连接到同一条扫描线GL，每一行像素单元P的像素电路的第二初始化电路600连接到另一条扫描线GL，每一行像素单元P的像素电路的数据写入电路200连接到另一条扫描线GL以接收第一扫描信号。例如，每一列的数据线DL和本列像素电路10中的数据写入电路200连接以提供数据信号。
例如，多个像素单元排列为多行，第n(n为大于1的整数)行像素单元的像素电路的第一发光控制电路300连接到同一条发光控制线，第n行像素单元的像素电路的第二发光控制电路400连接到另一条发光控制线。
例如，栅极驱动器12根据源自定时控制器13的多个扫描控制信号GCS向多个扫描线GL提供多个选通信号。多个选通信号包括第一扫描信号、第二扫描信号、第一发光控制信 号、第二发光控制信号以及复位信号(即第二扫描信号)。这些信号通过多个扫描线GL提供给每个像素单元P。
例如，数据驱动器14使用参考伽玛电压根据源自定时控制器13的多个数据控制信号DCS将从定时控制器13输入的数字图像数据RGB转换成数据信号。数据驱动器14向多条数据线DL提供转换的数据信号。
例如，定时控制器13对外部输入的图像数据RGB进行处理以匹配阵列基板11的大小和分辨率，然后向数据驱动器14提供处理的图像数据。定时控制器13使用从显示装置外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器13分别向栅极驱动器12和数据驱动器14提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器12和数据驱动器14的控制。
例如，数据驱动电器14可以与多条数据线DL连接，以提供数据信号Vdata；同时还可以与多条第一电压线、多条第二电压线和多条复位电压线连接以分别提供第一电压、第二电压和复位电压。
例如，栅极驱动器12和数据驱动器14可以实现为半导体芯片。该显示装置1还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，本实施例提供的阵列基板11可以应用于电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
关于阵列基板11的技术效果可以参考本公开的实施例中提供的像素电路10的技术效果，这里不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种像素电路，包括：驱动电路、数据写入电路、第一发光控制电路、第二发光控制电路、第一初始化电路、第二初始化电路和储能电路，其中，
    所述驱动电路包括控制端、第一端和第二端，且配置为控制流经所述第一端和所述第二端的用于驱动发光元件发光的驱动电流；
    所述数据写入电路被配置为在第一扫描信号的控制下将数据信号写入所述驱动电路的控制端；
    所述第一发光控制电路被配置为在第一发光控制信号的控制下将第一电源端的第一电源电压施加至所述驱动电路的第一端；
    所述第二发光控制电路被配置为在第二发光控制信号的控制下将来自所述驱动电路的第二端的所述驱动电流施加至所述发光元件；
    所述第一初始化电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至所述驱动电路的控制端；
    所述第二初始化电路被配置为在第二复位控制信号的控制下将第二初始化电压施加至所述驱动电路的第二端；
    所述储能电路被配置为存储写入到所述驱动电路的控制端的所述数据信号，
    其中，所述第一初始化电路包括第一晶体管，所述数据写入电路包括第二晶体管，所述驱动电路包括第三晶体管，
    所述第一晶体管的第一有源层的半导材料的漏电流特性小于所述第三晶体管的第三有源层的半导材料的漏电流特性；所述第二晶体管的第二有源层的半导材料的漏电流特性小于所述第三晶体管的第三有源层的半导材料的漏电流特性。
  2. 根据权利要求1所述的像素电路，其中，所述第一晶体管的第一有源层的半导材料和所述第二晶体管的第二有源层的半导材料相同。
  3. 根据权利要求2所述的像素电路，其中，所述第一晶体管的第一有源层的半导材料为氧化物半导体；
    所述第三晶体管的第三有源层的多晶硅半导材料。
  4. 根据权利要求3所述的像素电路，其中，所述氧化物半导体为氧化铟半导体材料；
    所述多晶硅半导材料为低温多晶硅半导体材料。
  5. 根据权利要求2～4任一项所述的像素电路，其中，所述第一发光控制电路、所述第二发光控制电路，所述第二初始化电路分别包括的晶体管的有源层的半导材料与所述第三晶体管的第三有源层的半导材料相同且同层设置。
  6. 根据权利要求1～5任一项所述的像素电路，其中，所述储能电路包括第一电容和第二电容，
    所述第一电容电连接在所述驱动电路的控制端和所述驱动电路的第一端之间，所述第 二电容电连接在所述驱动电路的第一端与所述第一电源电压端之间，且所述第一电容与所述驱动电路的第一端电连接的电极和所述第二电容与所述驱动电路的第一端电连接的电极电连接。
  7. 根据权利要求1～6任一项所述的像素电路，还包括复位电路，其中，所述复位电路被配置为将所述第一发光控制信号的变化耦合至所述驱动电路的第一端。
  8. 根据权利要求7所述的像素电路，其中，所述复位电路包括第三电容，所述第三电容电连接在所述第一发光控制电路的控制端与所述驱动电路的第一端之间。
  9. 根据权利要求8所述的像素电路，其中，所述第三电容包括彼此相对且位于不同层的第一电容电极和第二电容电极，
    其中，所述第一电容电极与所述第三晶体管的第三有源层一体设置，或者所述第一电容电极经过孔与所述第三晶体管的第三有源层电连接，
    所述第二电容电极与所述第一发光控制电路的控制端一体设置。
  10. 根据权利要求1～9任一项所述的像素电路，其中，所述第一初始化电压和所述第二初始化电压彼此不同。
  11. 根据权利要求1～10所述的像素电路，其中，所述第一发光控制信号和所述第二发光控制信号相同。
  12. 一种阵列基板，包括：阵列排布的多个像素单元，其中，每个所述像素单元包括权利要求1-11任一所述像素电路。
  13. 一种显示装置，包括如权利要求12所述的阵列基板。
  14. 一种驱动根据权利要求1-11任一所述的像素电路的方法，其中，所述方法包括第一操作时段，所述第一操作时段包括复位阶段、采样阶段、写入阶段和发光阶段，其中，
    在所述复位阶段，使得所述第一初始化电路在所述第一复位控制信号的控制下导通，将所述第一初始化电压施加至所述驱动电路的控制端，使得所述第二初始化电路在所述第二复位控制信号的控制下导通，将所述第二初始化电压施加至所述驱动电路的第二端；
    在所述采样阶段，使得所述第一发光控制电路和所述第二发光控制电路截止，且使得所述第一初始化电路在所述第一复位控制信号的控制下保持导通，将所述第一初始化电压施加至所述驱动电路的控制端，使得所述第二初始化电路在所述第二复位控制信号的控制下保持导通，将所述第二初始化电压施加至所述驱动电路的第二端；
    在所述写入阶段，使得所述第一初始化电路、所述第二初始化电路、所述第一发光控制电路和所述第二发光控制电路截止，使得所述数据写入电路在所述第一扫描信号的控制下将接收的所述数据信号写入到所述驱动电路的控制端，通过所述储能电路将所述数据信号存储在所述储能电路之中；
    在所述发光阶段，使得所述第一初始化电路和所述第二初始化电路截止，且使得所述第一发光控制电路在所述第一发光控制信号的控制下导通，将所述第一电源端的第一电源电压施加至所述驱动电路的第一端，使得所述第二发光控制电路在所述第二发光控制信号的 控制下导通，将来自所述驱动电路的第二端的所述驱动电流施加至所述发光元件，以驱动所述发光元件。
  15. 根据权利要求14的所述方法，其中，所述方法还包括第二操作时段，所述第二操作时段在时间上紧接在所述第一操作时段之后，
    所述第一发光控制信号、所述第二发光控制信号以及所述第二复位控制信号具有第一频率，所述第一复位控制信号和所述第一扫描信号具有第二频率，所述第一频率大于所述第二频率，
    与所述第一操作时段相比，在所述第二操作时段中，所述第一发光控制信号、所述第二发光控制信号以及所述第二复位控制信号进入不同的周期，所述第一复位控制信号和所述第一扫描信号仍然在同一周期。
  16. 根据权利要求15的所述方法，其中，所述第一频率大于30Hz，所述第二频率为1Hz～10Hz。
  17. 根据权利要求14～16任一项的所述方法，其中，在所述复位阶段，还使得所述第一发光控制电路在所述第一发光控制信号的控制下导通，将所述第一电源端的第一电源电压施加至所述驱动电路的第一端，还使得所述第二发光控制电路在所述第二发光控制信号的控制下导通，将来自所述第二初始化电路的所述第二初始化电压施加至发光元件。
  18. 根据权利要求17的所述方法，其中，在所述第二初始化电路将所述第二初始化电压施加至发光元件的情况下，使得所述第二初始化电压避免发光元件导通。
PCT/CN2022/104828 2021-07-30 2022-07-11 像素电路及其驱动方法、阵列基板和显示装置 WO2023005648A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/273,695 US12118939B2 (en) 2021-07-30 2022-07-11 Pixel circuit and driving method therefor, array substrate, and display device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CNPCT/CN2021/109890 2021-07-30
PCT/CN2021/109890 WO2023004813A1 (zh) 2021-07-30 2021-07-30 像素电路、驱动方法和显示装置
CN202110898678.6A CN115691421A (zh) 2021-07-30 2021-08-05 像素电路及其驱动方法、阵列基板和显示装置
CN202110898678.6 2021-08-05

Publications (1)

Publication Number Publication Date
WO2023005648A1 true WO2023005648A1 (zh) 2023-02-02

Family

ID=78963010

Family Applications (6)

Application Number Title Priority Date Filing Date
PCT/CN2021/109890 WO2023004813A1 (zh) 2021-07-30 2021-07-30 像素电路、驱动方法和显示装置
PCT/CN2022/104828 WO2023005648A1 (zh) 2021-07-30 2022-07-11 像素电路及其驱动方法、阵列基板和显示装置
PCT/CN2022/105232 WO2023005660A1 (zh) 2021-07-30 2022-07-12 像素驱动电路、像素驱动方法和显示装置
PCT/CN2022/105233 WO2023005661A1 (zh) 2021-07-30 2022-07-12 像素电路、驱动方法和显示装置
PCT/CN2022/106018 WO2023005694A1 (zh) 2021-07-30 2022-07-15 像素电路及其驱动方法、显示面板
PCT/CN2022/106020 WO2023005695A1 (zh) 2021-07-30 2022-07-15 像素电路及其驱动方法、显示面板

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/109890 WO2023004813A1 (zh) 2021-07-30 2021-07-30 像素电路、驱动方法和显示装置

Family Applications After (4)

Application Number Title Priority Date Filing Date
PCT/CN2022/105232 WO2023005660A1 (zh) 2021-07-30 2022-07-12 像素驱动电路、像素驱动方法和显示装置
PCT/CN2022/105233 WO2023005661A1 (zh) 2021-07-30 2022-07-12 像素电路、驱动方法和显示装置
PCT/CN2022/106018 WO2023005694A1 (zh) 2021-07-30 2022-07-15 像素电路及其驱动方法、显示面板
PCT/CN2022/106020 WO2023005695A1 (zh) 2021-07-30 2022-07-15 像素电路及其驱动方法、显示面板

Country Status (3)

Country Link
US (6) US12236866B2 (zh)
CN (6) CN114514573B (zh)
WO (6) WO2023004813A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118737055A (zh) * 2024-09-03 2024-10-01 惠科股份有限公司 像素驱动电路、显示面板及其驱动方法、显示装置

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023004817A1 (zh) 2021-07-30 2023-02-02 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
US12236866B2 (en) * 2021-07-30 2025-02-25 Boe Technology Group Co., Ltd. Pixel circuit, driving method and display device
KR20230099110A (ko) * 2021-12-27 2023-07-04 엘지디스플레이 주식회사 표시 장치
CN114974110B (zh) * 2022-04-26 2024-08-09 Oppo广东移动通信有限公司 像素驱动电路、控制方法、显示屏及显示设备
CN114974130A (zh) * 2022-05-24 2022-08-30 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板及显示装置
WO2023225931A1 (zh) * 2022-05-26 2023-11-30 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN114783379B (zh) * 2022-05-26 2024-02-09 云谷（固安）科技有限公司 像素电路及其驱动方法、显示面板
WO2023245438A1 (zh) * 2022-06-21 2023-12-28 京东方科技集团股份有限公司 显示基板和显示装置
CN115188309B (zh) 2022-06-29 2024-08-27 武汉天马微电子有限公司 显示面板及显示装置
CN115019729B (zh) 2022-08-04 2022-11-25 惠科股份有限公司 像素驱动电路、显示面板及其控制方法
CN115376461A (zh) * 2022-08-29 2022-11-22 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
CN115331634A (zh) * 2022-08-30 2022-11-11 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示基板和显示装置
CN115359759B (zh) * 2022-08-31 2024-07-30 武汉天马微电子有限公司 显示面板及其驱动方法、显示装置
CN115482780A (zh) * 2022-09-28 2022-12-16 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN115527486B (zh) * 2022-10-24 2025-02-11 京东方科技集团股份有限公司 显示基板及显示装置
WO2024152283A1 (zh) * 2023-01-19 2024-07-25 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
WO2024197776A1 (zh) * 2023-03-31 2024-10-03 京东方科技集团股份有限公司 像素电路、驱动方法、显示基板、显示面板和显示装置
CN119181325A (zh) * 2023-06-21 2024-12-24 京东方科技集团股份有限公司 像素电路和显示装置
CN117012145A (zh) * 2023-06-30 2023-11-07 天马新型显示技术研究院(厦门)有限公司 一种像素驱动电路、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105427803A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN107146577A (zh) * 2017-06-26 2017-09-08 武汉天马微电子有限公司 一种像素电路、其驱动方法、显示面板及显示装置
CN108206008A (zh) * 2018-01-11 2018-06-26 京东方科技集团股份有限公司 像素电路、驱动方法、电致发光显示面板及显示装置
CN111199711A (zh) * 2018-11-16 2020-05-26 乐金显示有限公司 数据驱动电路、显示面板和显示装置
CN111445854A (zh) * 2020-05-11 2020-07-24 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
CN111583866A (zh) * 2020-06-30 2020-08-25 上海天马有机发光显示技术有限公司 输出控制单元、输出控制电路、显示面板和显示装置

Family Cites Families (109)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4195337B2 (ja) * 2002-06-11 2008-12-10 三星エスディアイ株式会社 発光表示装置及びその表示パネルと駆動方法
US7173590B2 (en) 2004-06-02 2007-02-06 Sony Corporation Pixel circuit, active matrix apparatus and display apparatus
US20090231308A1 (en) 2005-03-29 2009-09-17 Takaji Numao Display Device and Driving Method Thereof
JP2007011214A (ja) 2005-07-04 2007-01-18 Sony Corp 画素回路および表示装置、並びに画素回路の駆動方法
KR100833753B1 (ko) 2006-12-21 2008-05-30 삼성에스디아이 주식회사 유기 전계 발광 표시 장치 및 그 구동방법
JP5081341B2 (ja) 2008-05-23 2012-11-28 双葉電子工業株式会社 蛍光表示管の駆動回路
KR100926634B1 (ko) 2008-05-26 2009-11-11 삼성모바일디스플레이주식회사 유기 전계발광 표시장치
KR101791664B1 (ko) 2010-10-28 2017-11-21 삼성디스플레이 주식회사 유기전계발광 표시장치
KR20120065137A (ko) 2010-12-10 2012-06-20 삼성모바일디스플레이주식회사 화소, 이를 이용한 표시 장치, 및 그의 구동 방법
KR101870925B1 (ko) 2011-06-30 2018-06-26 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR101848506B1 (ko) * 2011-11-18 2018-04-12 엘지디스플레이 주식회사 유기발광 표시장치
JP6153830B2 (ja) 2013-09-13 2017-06-28 株式会社ジャパンディスプレイ 表示装置及びその駆動方法
CN103594059B (zh) * 2013-11-29 2017-01-11 中国科学院上海高等研究院 有源矩阵有机发光二极管像素驱动电路及其驱动方法
TWI498873B (zh) 2013-12-04 2015-09-01 Au Optronics Corp 有機發光二極體電路及其驅動方法
CN104091560B (zh) 2014-06-23 2016-08-24 上海天马有机发光显示技术有限公司 有机发光二极管像素补偿电路及其显示面板、显示装置
KR102317720B1 (ko) 2015-04-29 2021-10-26 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
US10395589B1 (en) 2015-09-18 2019-08-27 Apple Inc. Hybrid microdriver architectures having relaxed comparator requirements
KR102457757B1 (ko) 2015-10-28 2022-10-24 삼성디스플레이 주식회사 화소 회로 및 이를 포함하는 유기 발광 표시 장치
US10121430B2 (en) 2015-11-16 2018-11-06 Apple Inc. Displays with series-connected switching transistors
CN105427806B (zh) 2016-01-06 2018-10-23 京东方科技集团股份有限公司 像素电路、显示基板及显示装置、驱动显示基板的方法
KR102561294B1 (ko) 2016-07-01 2023-08-01 삼성디스플레이 주식회사 화소 및 스테이지 회로와 이를 가지는 유기전계발광 표시장치
CN205920745U (zh) 2016-08-22 2017-02-01 京东方科技集团股份有限公司 像素电路、显示面板及显示设备
CN106384739B (zh) 2016-08-29 2019-05-07 上海天马微电子有限公司 有机发光显示面板及其驱动方法、有机发光显示装置
KR102547871B1 (ko) 2016-12-01 2023-06-28 삼성디스플레이 주식회사 화소 및 이를 가지는 유기전계발광 표시장치
CN106910468B (zh) 2017-04-28 2019-05-10 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
CN107274830B (zh) * 2017-07-12 2019-07-02 上海天马有机发光显示技术有限公司 一种像素电路、其驱动方法及有机电致发光显示面板
CN107256695B (zh) 2017-07-31 2019-11-19 上海天马有机发光显示技术有限公司 像素电路、其驱动方法、显示面板及显示装置
US10304378B2 (en) 2017-08-17 2019-05-28 Apple Inc. Electronic devices with low refresh rate display pixels
KR102393141B1 (ko) 2017-08-21 2022-05-02 엘지디스플레이 주식회사 게이트 구동회로 및 이를 이용한 표시장치와 그 구동 방법
CN116030764A (zh) 2017-08-25 2023-04-28 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN109509427A (zh) 2017-09-15 2019-03-22 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN109599062A (zh) 2017-09-30 2019-04-09 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN107803636A (zh) 2017-10-13 2018-03-16 沈艳 电能表自动装表机
CN107610651B (zh) 2017-10-31 2019-11-08 武汉天马微电子有限公司 像素电路、像素电路的驱动方法和显示面板
KR102470378B1 (ko) * 2017-11-30 2022-11-23 엘지디스플레이 주식회사 게이트 구동 회로 및 이를 포함하는 발광 표시 장치
CN110021273B (zh) 2018-01-10 2021-12-03 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
JP2019128447A (ja) 2018-01-24 2019-08-01 株式会社ジャパンディスプレイ 表示装置及び表示装置の駆動方法
CN111727470B (zh) 2018-02-20 2022-09-20 索尼半导体解决方案公司 像素电路、显示装置、驱动像素电路的方法以及电子设备
CN110176213B (zh) 2018-06-08 2023-09-26 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN108777130A (zh) * 2018-06-21 2018-11-09 京东方科技集团股份有限公司 像素电路及显示装置
CN109087610A (zh) 2018-08-20 2018-12-25 武汉华星光电半导体显示技术有限公司 Amoled像素驱动电路、驱动方法及显示面板
CN109215582A (zh) 2018-09-28 2019-01-15 昆山国显光电有限公司 显示面板、像素电路的驱动方法及显示装置
KR102693495B1 (ko) 2018-10-08 2024-08-12 삼성디스플레이 주식회사 표시 장치
KR102639185B1 (ko) 2018-11-07 2024-02-23 삼성디스플레이 주식회사 입력 감지 유닛을 포함하는 표시 장치
CN109102778A (zh) 2018-11-15 2018-12-28 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示装置
CN110226195A (zh) 2018-11-22 2019-09-10 京东方科技集团股份有限公司 用于单列中的多行像素的显示驱动电路、显示装置和显示方法
CN109215585A (zh) 2018-11-26 2019-01-15 京东方科技集团股份有限公司 像素电路及其驱动方法和显示装置
CN109285500B (zh) 2018-12-05 2020-11-13 武汉天马微电子有限公司 像素驱动电路和有机发光显示装置
US10916198B2 (en) 2019-01-11 2021-02-09 Apple Inc. Electronic display with hybrid in-pixel and external compensation
KR20200108146A (ko) 2019-03-06 2020-09-17 삼성디스플레이 주식회사 디스플레이 패널 및 이를 포함한 디스플레이 장치
CN109817165B (zh) 2019-03-08 2021-04-20 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法、显示面板和显示装置
CN109830208B (zh) * 2019-03-28 2020-08-25 厦门天马微电子有限公司 像素电路及其驱动方法、显示面板和显示装置
CN110033734B (zh) 2019-04-25 2021-08-10 京东方科技集团股份有限公司 一种显示驱动电路及其驱动方法、显示装置
CN110010057B (zh) 2019-04-25 2021-01-22 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法和显示装置
KR102706311B1 (ko) * 2019-05-08 2024-09-19 삼성디스플레이 주식회사 화소, 화소를 포함하는 표시 장치 및 그의 구동 방법
KR102665185B1 (ko) 2019-06-12 2024-05-16 삼성디스플레이 주식회사 표시 장치
CN110223640A (zh) * 2019-06-26 2019-09-10 昆山国显光电有限公司 一种像素驱动电路及显示装置
KR102764928B1 (ko) 2019-07-26 2025-02-12 삼성디스플레이 주식회사 표시 장치
CN110660360B (zh) 2019-10-12 2021-05-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
TWI714317B (zh) * 2019-10-23 2020-12-21 友達光電股份有限公司 畫素電路與相關的顯示裝置
KR102694077B1 (ko) 2019-10-24 2024-08-12 삼성디스플레이 주식회사 표시 장치
CN110648629B (zh) 2019-10-31 2023-09-22 厦门天马微电子有限公司 显示面板及其制作方法、显示装置
CN112767873B (zh) 2019-11-01 2022-03-22 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示面板、显示装置
CN110767163B (zh) * 2019-11-08 2021-01-26 京东方科技集团股份有限公司 一种像素电路及显示面板
KR102636598B1 (ko) * 2019-12-13 2024-02-13 엘지디스플레이 주식회사 화소 구동 회로를 포함한 전계발광 표시장치
US20210193049A1 (en) 2019-12-23 2021-06-24 Apple Inc. Electronic Display with In-Pixel Compensation and Oxide Drive Transistors
KR102746604B1 (ko) * 2020-01-22 2024-12-24 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
KR102681836B1 (ko) * 2020-03-03 2024-07-04 삼성디스플레이 주식회사 표시장치
KR102734877B1 (ko) 2020-03-10 2024-11-28 삼성디스플레이 주식회사 화소 회로
CN111354314A (zh) 2020-03-16 2020-06-30 昆山国显光电有限公司 像素电路、像素电路的驱动方法和显示面板
CN111354307B (zh) 2020-04-09 2022-02-15 武汉天马微电子有限公司 一种像素驱动电路及驱动方法、有机发光显示面板
KR102662925B1 (ko) * 2020-05-20 2024-05-08 삼성디스플레이 주식회사 화소 회로 및 이를 포함하는 표시 장치
CN111402809B (zh) 2020-05-27 2022-05-17 武汉天马微电子有限公司 一种显示面板和显示装置
KR20210148475A (ko) * 2020-05-28 2021-12-08 삼성디스플레이 주식회사 표시 장치
CN111489700B (zh) 2020-05-29 2022-07-29 武汉天马微电子有限公司 一种显示面板、驱动方法及显示装置
CN111508426B (zh) 2020-05-29 2022-04-15 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN111710300B (zh) * 2020-06-30 2021-11-23 厦门天马微电子有限公司 一种显示面板、驱动方法及显示装置
CN111710299B (zh) 2020-06-30 2022-01-07 厦门天马微电子有限公司 一种显示面板、其驱动方法及显示装置
CN117542318A (zh) 2020-07-15 2024-02-09 武汉华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示装置
CN111798789B (zh) 2020-07-16 2022-09-20 昆山国显光电有限公司 像素电路及其驱动方法、显示面板
CN111754938B (zh) 2020-07-24 2023-11-28 武汉华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示装置
CN111754922B (zh) 2020-07-24 2024-08-13 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板
CN111883055B (zh) 2020-07-30 2021-09-10 维信诺科技股份有限公司 像素电路及其驱动方法
CN112133253A (zh) 2020-09-22 2020-12-25 Oppo广东移动通信有限公司 像素驱动电路及显示设备、驱动方法
CN112053661B (zh) 2020-09-28 2023-04-11 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示面板和显示装置
CN112233616A (zh) 2020-10-12 2021-01-15 Oppo广东移动通信有限公司 像素驱动电路及显示设备、驱动方法
CN117975871A (zh) 2020-10-15 2024-05-03 厦门天马微电子有限公司 显示面板及其驱动方法以及显示装置
CN112331134A (zh) * 2020-10-23 2021-02-05 厦门天马微电子有限公司 显示面板及显示装置
CN112150964B (zh) * 2020-10-23 2024-04-09 厦门天马微电子有限公司 显示面板及其驱动方法以及显示装置
CN112289269A (zh) 2020-10-30 2021-01-29 合肥维信诺科技有限公司 一种像素电路及其控制方法和显示面板
CN112331678A (zh) 2020-11-03 2021-02-05 京东方科技集团股份有限公司 显示基板、其制作方法及显示面板、显示装置
CN112397030A (zh) 2020-11-17 2021-02-23 武汉华星光电半导体显示技术有限公司 像素驱动电路及oled显示面板
CN112397029B (zh) 2020-11-17 2022-04-08 武汉华星光电半导体显示技术有限公司 像素驱动电路及ltpo显示面板
CN112420794B (zh) 2020-11-18 2023-04-14 京东方科技集团股份有限公司 显示基板和显示装置
KR20220072109A (ko) 2020-11-24 2022-06-02 삼성디스플레이 주식회사 표시 장치
CN112435630A (zh) 2020-11-25 2021-03-02 京东方科技集团股份有限公司 一种像素驱动电路、驱动方法及显示面板
CN112382235A (zh) 2020-12-01 2021-02-19 合肥维信诺科技有限公司 一种像素电路及其控制方法、显示面板
CN112397026B (zh) 2020-12-04 2022-06-28 武汉天马微电子有限公司 像素驱动电路、显示面板及其驱动方法
CN112365844A (zh) 2020-12-09 2021-02-12 武汉华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN112397565B (zh) 2020-12-09 2022-08-05 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN112599099B (zh) 2020-12-21 2022-04-26 京东方科技集团股份有限公司 像素驱动电路及其像素驱动方法
KR20220097678A (ko) 2020-12-30 2022-07-08 삼성디스플레이 주식회사 디스플레이 장치
CN112909054A (zh) 2021-01-26 2021-06-04 武汉华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN114974112B (zh) * 2021-03-16 2024-07-02 上海天马微电子有限公司 显示面板及显示装置
CN113140179B (zh) 2021-04-12 2022-08-05 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板
CN112992071A (zh) 2021-04-22 2021-06-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN113192988A (zh) 2021-04-23 2021-07-30 深圳市华星光电半导体显示技术有限公司 一种显示器件
CN117042523A (zh) 2021-05-06 2023-11-10 京东方科技集团股份有限公司 显示面板、显示装置
US12236866B2 (en) 2021-07-30 2025-02-25 Boe Technology Group Co., Ltd. Pixel circuit, driving method and display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105427803A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN107146577A (zh) * 2017-06-26 2017-09-08 武汉天马微电子有限公司 一种像素电路、其驱动方法、显示面板及显示装置
CN108206008A (zh) * 2018-01-11 2018-06-26 京东方科技集团股份有限公司 像素电路、驱动方法、电致发光显示面板及显示装置
CN111199711A (zh) * 2018-11-16 2020-05-26 乐金显示有限公司 数据驱动电路、显示面板和显示装置
CN111445854A (zh) * 2020-05-11 2020-07-24 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
CN111583866A (zh) * 2020-06-30 2020-08-25 上海天马有机发光显示技术有限公司 输出控制单元、输出控制电路、显示面板和显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118737055A (zh) * 2024-09-03 2024-10-01 惠科股份有限公司 像素驱动电路、显示面板及其驱动方法、显示装置
CN118737055B (zh) * 2024-09-03 2025-01-24 惠科股份有限公司 像素驱动电路、显示面板及其驱动方法、显示装置

Also Published As

Publication number Publication date
US20240062721A1 (en) 2024-02-22
WO2023005660A1 (zh) 2023-02-02
WO2023005695A1 (zh) 2023-02-02
US20240169905A1 (en) 2024-05-23
CN114627807A (zh) 2022-06-14
CN113838419A (zh) 2021-12-24
WO2023004813A1 (zh) 2023-02-02
US12230204B2 (en) 2025-02-18
US20240087514A1 (en) 2024-03-14
US20240233637A9 (en) 2024-07-11
CN115691407A (zh) 2023-02-03
CN114514573A (zh) 2022-05-17
CN115691422A (zh) 2023-02-03
US20240212598A1 (en) 2024-06-27
US20240135875A1 (en) 2024-04-25
WO2023005661A1 (zh) 2023-02-02
CN115691421A (zh) 2023-02-03
CN114514573B (zh) 2022-08-09
US12118939B2 (en) 2024-10-15
CN113838419B (zh) 2022-07-15
US12236866B2 (en) 2025-02-25
WO2023005694A1 (zh) 2023-02-02
US20240144870A1 (en) 2024-05-02

Similar Documents

Publication Publication Date Title
WO2023005648A1 (zh) 像素电路及其驱动方法、阵列基板和显示装置
US20240119897A1 (en) Pixel Circuit and Driving Method Therefor and Display Panel
US11881164B2 (en) Pixel circuit and driving method thereof, and display panel
CN110268465B (zh) 像素电路、显示面板及像素电路的驱动方法
WO2021068637A1 (zh) 像素电路及其驱动方法、显示面板
US10978002B2 (en) Pixel circuit and driving method thereof, and display panel
WO2019137105A1 (zh) 像素电路、驱动方法、电致发光显示面板及显示装置
WO2019233120A1 (zh) 像素电路及其驱动方法、显示面板
US11232749B2 (en) Pixel circuit and driving method thereof, array substrate, and display device
CN113950715B (zh) 像素电路及其驱动方法、显示装置
WO2020052287A1 (zh) 像素电路及其驱动方法、显示装置
WO2016011719A1 (zh) 像素驱动电路、驱动方法、阵列基板及显示装置
WO2020253398A1 (zh) 像素电路及其驱动方法、显示面板及显示装置
WO2020192734A1 (zh) 显示驱动电路及其驱动方法、显示面板及显示装置
WO2015188533A1 (zh) 像素驱动电路、驱动方法、阵列基板及显示装置
WO2015188532A1 (zh) 像素驱动电路、驱动方法、阵列基板及显示装置
CN113658554B (zh) 像素驱动电路、像素驱动方法及显示装置
WO2019205671A1 (zh) 像素电路及其驱动方法、显示面板和显示设备
GB2620507A (en) Pixel circuit and driving method therefor and display panel
WO2021035414A1 (zh) 像素电路及驱动方法、显示基板及驱动方法、显示装置
US11527199B2 (en) Pixel circuit including discharge control circuit and storage control circuit and method for driving pixel circuit, display panel and electronic device
WO2024041217A1 (zh) 像素电路及其驱动方法、显示面板、显示装置
WO2023201678A1 (zh) 像素电路及其驱动方法、显示面板、显示装置
CN115116395A (zh) 驱动电路、驱动方法及显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22848253

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18273695

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26/06/2024)

122 Ep: pct application non-entry in european phase

Ref document number: 22848253

Country of ref document: EP

Kind code of ref document: A1