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WO2023005694A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2023005694A1
WO2023005694A1 PCT/CN2022/106018 CN2022106018W WO2023005694A1 WO 2023005694 A1 WO2023005694 A1 WO 2023005694A1 CN 2022106018 W CN2022106018 W CN 2022106018W WO 2023005694 A1 WO2023005694 A1 WO 2023005694A1
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WO
WIPO (PCT)
Prior art keywords
transistor
circuit
control signal
terminal
reset
Prior art date
Application number
PCT/CN2022/106018
Other languages
English (en)
French (fr)
Inventor
刘聪
王本莲
黄耀
黄炜赟
王彬艳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/270,094 priority Critical patent/US20240062721A1/en
Publication of WO2023005694A1 publication Critical patent/WO2023005694A1/zh

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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display panel.
  • Organic light-emitting diode Organic Light-Emitting Diode (Organic Light-Emitting Diode, OLED) display panel has thin, light, wide viewing angle, active light emission, continuously adjustable light color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range , simple production process, high luminous efficiency and flexible display, etc., are more and more widely used in display fields such as mobile phones, tablet computers, and digital cameras.
  • At least some embodiments of the present disclosure provide a pixel circuit, including: a driving circuit, a data writing circuit, a compensation control circuit, an energy storage circuit, a first light emission control circuit, a second light emission control circuit, a first initialization circuit, and a second initialization circuit.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light ;
  • the data writing circuit is configured to write a data signal into the first end of the drive circuit under the control of the first scanning signal;
  • the compensation control circuit is configured to write the data signal to the first end of the driving circuit under the control of the second scanning signal
  • the driving circuit is compensated;
  • the energy storage circuit is configured to store the voltage of the control terminal of the driving circuit;
  • the first light emission control circuit is configured to convert the first A power supply voltage is applied to the first terminal of the driving circuit;
  • the second light emitting control circuit is configured to apply the driving current to the first pole of the light emitting element under the control of a second light emitting control signal;
  • the first initialization circuit is configured to apply a first initialization voltage to the control terminal of the driving circuit under the control of the first reset control signal;
  • the transmission circuit is configured to transmit the
  • the second initialization circuit is configured to apply a second initialization voltage to the first pole of the light emitting element under the control of a second reset control signal; wherein, the second light emission control circuit is further configured to Under the control of the second light-emitting control signal, the second initialization voltage of the first pole of the light-emitting element is transmitted to the second terminal of the driving circuit; or, the first initialization circuit and the transmission
  • the circuits are jointly configured to apply the first initialization voltage to the control terminal of the drive circuit, and the compensation control circuit is further configured to apply all the control terminals of the drive circuit under the control of the second scan signal.
  • the first initialization voltage is transmitted to the second terminal of the driving circuit; or, the first initialization circuit and the transmission circuit are jointly configured to apply the first initialization voltage to the second terminal of the driving circuit
  • the compensation control circuit is further configured to transmit the first initialization voltage at the second terminal of the driving circuit to the control terminal of the driving circuit under the control of the second scan signal.
  • the driving circuit includes a third transistor; the gate of the third transistor serves as the control terminal of the driving circuit, and the first electrode of the third transistor serves as The first terminal of the driving circuit and the second pole of the third transistor serve as the second terminal of the driving circuit.
  • the data writing circuit includes a fourth transistor; the gate of the fourth transistor is connected to the first scanning signal terminal to receive the first scanning signal, so The first pole of the fourth transistor is connected to the data signal terminal to receive the data signal, and the second pole of the fourth transistor is connected to the first terminal of the driving circuit.
  • the compensation control circuit includes a second transistor
  • the energy storage circuit includes a storage capacitor
  • the gate of the second transistor is connected to the second scanning signal terminal to receive
  • the first pole of the second transistor is connected to the second terminal of the driving circuit
  • the second pole of the second transistor is connected to the control terminal of the driving circuit
  • the storage capacitor The first terminal of the storage capacitor is coupled to the control terminal of the driving circuit
  • the second terminal of the storage capacitor is coupled to the first power supply terminal.
  • the second transistor is an N-type oxide thin film transistor
  • the N-type oxide thin film transistor includes a first metal layer, an active layer, and an active layer that are sequentially stacked and insulated from each other.
  • the width of the second metal layer is not greater than the width of the first metal layer;
  • the second metal layer and the second scanning signal terminal connected to serve as the gate of the second transistor, or both the second metal layer and the first metal layer are connected to the second scan signal terminal to serve as the gate of the second transistor;
  • the active layer includes a channel region covered by the first metal layer, and the value range of the width-to-length ratio of the channel region of the N-type oxide thin film transistor is [1/2, 7/8].
  • the first light emission control circuit includes a fifth transistor, and the gate of the fifth transistor is connected to the first light emission control signal terminal to receive the first light emission control signal terminal. signal, the first pole of the fifth transistor is connected to the first power supply terminal to receive the first power supply voltage, and the second pole of the fifth transistor is connected to the first terminal of the driving circuit.
  • the second light emission control circuit includes a sixth transistor, and the gate of the sixth transistor is connected to the second light emission control signal terminal to receive the second light emission control signal terminal. signal, the first pole of the sixth transistor is connected to the second terminal of the driving circuit, and the second pole of the sixth transistor is connected to the first pole of the light emitting element.
  • the second initialization circuit includes a seventh transistor, the gate of the seventh transistor is connected to the second reset control signal terminal to receive the second reset control signal
  • the first electrode of the seventh transistor is connected to the second initialization voltage terminal to receive the second initialization voltage
  • the second electrode of the seventh transistor is connected to the first electrode of the light emitting element.
  • the first initialization circuit includes a first transistor
  • the transfer circuit includes an eighth transistor
  • the gate of the first transistor is connected to the first reset control signal terminal
  • the first pole of the first transistor is connected to the first initialization voltage terminal to receive the first initialization voltage
  • the second pole of the first transistor is connected to the eighth transistor
  • the first pole of the eighth transistor is connected to the transmission control signal terminal to receive the transmission control signal
  • the second pole of the eighth transistor is connected to the control terminal of the driving circuit.
  • both the second transistor and the seventh transistor are N-type oxide thin film transistors
  • the third transistor, the fourth transistor, the fifth The transistor, the sixth transistor, the first transistor, and the eighth transistor are all P-type thin film transistors
  • the value range of the width-to-length ratio of the channel region of the first transistor is [1/3,3 /4]
  • the value range of the width-to-length ratio of the channel region of the eighth transistor is [1/3, 3/4]
  • the second reset control signal and the first light emission control signal are the same control signal
  • the transmission control signal and the second light emission control signal are the same control signal.
  • the second transistor is an N-type oxide thin film transistor
  • the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor , the seventh transistor, the first transistor and the eighth transistor are all P-type thin film transistors
  • the value range of the width-to-length ratio of the channel region of the first transistor is [1/3, 3/ 4]
  • the value range of the width-to-length ratio of the channel region of the eighth transistor is [1/3, 3/4]
  • the second reset control signal and the first reset control signal are the same control signal
  • the transmission control signal is the same control signal as the first light emission control signal or the second light emission control signal.
  • the first initialization circuit includes a first transistor
  • the transfer circuit includes an eighth transistor.
  • the gate of the first transistor is connected to the first reset control signal terminal to receive the first reset control signal
  • the first pole of the first transistor is connected to the second pole of the second transistor
  • the first The second pole of a transistor is connected to the control terminal of the driving circuit
  • the gate of the eighth transistor is connected to the transmission control signal terminal to receive the transmission control signal
  • the first pole of the eighth transistor is connected to the transmission control signal terminal.
  • the first initialization voltage end is connected to receive the first initialization voltage
  • the second pole of the eighth transistor is connected to the first pole of the first transistor
  • the second pole of the second transistor is connected through the first The transistor is connected with the control terminal of the driving circuit.
  • both the second transistor and the seventh transistor are N-type oxide thin film transistors
  • the third transistor, the fourth transistor, the fifth The transistor, the sixth transistor, the first transistor, and the eighth transistor are all P-type thin film transistors
  • the value range of the width-to-length ratio of the channel region of the first transistor is [1/3,3 /4]
  • the value range of the width-to-length ratio of the channel region of the eighth transistor is [1/3, 3/4]
  • the second reset control signal and the first light emission control signal are the same control signal
  • the transmission control signal and the second light emission control signal are the same control signal.
  • the second transistor is an N-type oxide thin film transistor
  • the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor , the seventh transistor, the first transistor and the eighth transistor are all P-type thin film transistors
  • the value range of the width-to-length ratio of the channel region of the first transistor is [1/3, 3/ 4]
  • the value range of the width-to-length ratio of the channel region of the eighth transistor is [1/3, 3/4]
  • the second reset control signal and the first reset control signal are the same control signal
  • the transmission control signal and the second light emission control signal are the same control signal.
  • the first initialization circuit includes a first transistor
  • the transfer circuit includes an eighth transistor
  • the gate of the first transistor is connected to the first reset control signal terminal
  • the first pole of the first transistor is connected to the first initialization voltage terminal to receive the first initialization voltage
  • the second pole of the first transistor is connected to the eighth transistor
  • the first pole of the eighth transistor is connected to the transmission control signal terminal to receive the transmission control signal
  • the second pole of the eighth transistor is connected to the second terminal of the driving circuit.
  • both the second transistor and the seventh transistor are N-type oxide thin film transistors
  • the third transistor, the fourth transistor, the fifth The transistor, the sixth transistor, the first transistor, and the eighth transistor are all P-type thin film transistors
  • the value range of the width-to-length ratio of the channel region of the first transistor is [1/3,3 /4]
  • the value range of the width-to-length ratio of the channel region of the eighth transistor is [1/3, 3/4]
  • the second reset control signal and the second light emission control signal are the same control signal
  • the transmission control signal and the first lighting control signal are the same control signal.
  • the second transistor is an N-type oxide thin film transistor
  • the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor , the seventh transistor, the first transistor and the eighth transistor are all P-type thin film transistors
  • the value range of the width-to-length ratio of the channel region of the first transistor is [1/3, 3/ 4]
  • the value range of the width-to-length ratio of the channel region of the eighth transistor is [1/3, 3/4]
  • the second reset control signal and the first scan signal are the same control signal
  • the transmission control signal and the first lighting control signal are the same control signal.
  • At least some embodiments of the present disclosure further provide a display panel, comprising: a plurality of pixel units arranged in an array; wherein each pixel unit of the plurality of pixel units includes the pixel circuit provided by any embodiment of the present disclosure.
  • At least some embodiments of the present disclosure further provide a driving method corresponding to the pixel circuit provided by any embodiment of the present disclosure, including: a reset phase; wherein, in the reset phase, inputting the second light emission control signal, the The first reset control signal, the second reset control signal and the transmission control signal turn on the second lighting control circuit, the first initialization circuit, the second initialization circuit and the transmission circuit, through the The first initialization circuit and the transmission circuit apply the first initialization voltage to the control terminal of the drive circuit to reset the control terminal of the drive circuit, and the second An initialization voltage is applied to the first pole of the light emitting element to reset the light emitting element, and the second initialization voltage is applied to the driving circuit through the second initialization circuit and the second light emission control circuit
  • the second terminal is used to reset the second terminal of the driving circuit; or, input the second scanning signal, the first reset control signal, the second reset control signal and the transmission control signal to turn on the The compensation control circuit, the first initialization circuit, the second initialization circuit and the transmission circuit, the first initialization voltage
  • the driving method provided by some embodiments of the present disclosure further includes: a data writing and compensation phase, a holding phase, and a light emitting phase; wherein, in the data writing and compensation phase, the first scan signal and the The second scanning signal turns on the data writing circuit, the driving circuit and the compensation control circuit, writes the data signal into the compensation control circuit through the data writing circuit, and writes the data signal into the compensation control circuit through the compensation control circuit.
  • Compensating the driving circuit in the holding phase, inputting the second scanning signal, closing the compensation control circuit, and maintaining the voltage of the control terminal of the driving circuit through the energy storage circuit; in the lighting phase , input the first light emission control signal and the second light emission control signal, turn on the first light emission control circuit, the second light emission control circuit and the driving circuit, and turn all the light emission control circuits through the first light emission control circuit
  • the first power supply voltage is applied to the first terminal of the driving circuit so that the driving circuit generates the driving current according to the voltage of the control terminal of the driving circuit, and the driving current is applied to the
  • the light emitting element causes the light emitting element to emit light.
  • FIG. 1A is a schematic diagram of a 7T1C pixel circuit
  • FIG. 1B is a signal timing diagram of a driving method of the 7T1C pixel circuit shown in FIG. 1A;
  • Fig. 2 is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure
  • Fig. 3 is a schematic block diagram of another pixel circuit provided by at least some embodiments of the present disclosure.
  • Fig. 4 is a schematic block diagram of another pixel circuit provided by at least some embodiments of the present disclosure.
  • FIG. 5 is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 2;
  • FIG. 6 is a schematic circuit structure diagram of another specific implementation example of the pixel circuit shown in FIG. 2;
  • FIG. 7 is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 3;
  • FIG. 8 is a schematic circuit structure diagram of another specific implementation example of the pixel circuit shown in FIG. 3;
  • FIG. 9 is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 4;
  • FIG. 10 is a schematic circuit structure diagram of another specific implementation example of the pixel circuit shown in FIG. 4;
  • FIG. 11A is a schematic diagram of a partial planar structure of an oxide thin film transistor provided by at least some embodiments of the present disclosure.
  • FIG. 11B is a schematic diagram of a partial cross-sectional structure of an oxide thin film transistor provided by at least some embodiments of the present disclosure.
  • 12-15 are signal timing diagrams of various pixel circuit driving methods provided by at least some embodiments of the present disclosure.
  • FIG. 16 is a schematic diagram of the effect of PWM reset on the fourth node in the driving method of the pixel circuit provided by at least some embodiments of the present disclosure.
  • Fig. 17 is a schematic block diagram of a display panel provided by at least some embodiments of the present disclosure.
  • the pixel circuit in the OLED display panel generally adopts a matrix driving method, which is divided into active matrix (Active Matrix, AM) driving and passive matrix (Passive Matrix, PM) driving according to whether switching components are introduced into each pixel unit.
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit (also called "pixel driving circuit") of each pixel. Through the driving control of the thin film transistors and storage capacitors, the current flowing through the OLED is realized. control so that the OLED emits light as desired. Therefore, AMOLED requires a small driving current, low power consumption, and a longer lifespan, which can meet the needs of large-scale display with high resolution and multiple gray scales.
  • AMOLED has obvious advantages in terms of viewing angle, color reproduction, power consumption, and response time, and is suitable for display devices with high information content and high resolution.
  • the basic pixel circuit used in an AMOLED display panel is usually a 2T1C pixel circuit, which uses two TFTs (Thin-film transistor, thin film transistor) and a storage capacitor C to realize the basic function of driving OLED to emit light.
  • the pixel circuits actually used are not limited to the above-mentioned 2T1C pixel circuits, and may also be pixel circuits of other structures, such as 4T1C, 4T2C, 6T1C or 7T1C pixel circuits.
  • FIG. 1A is a schematic diagram of a 7T1C pixel circuit.
  • the 7T1C pixel circuit includes: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a capacitor C.
  • the gate of the driving transistor T3 is connected to the first node N1, the first pole of the driving transistor T3 is connected to the second node N2, the second pole of the driving transistor T3 is connected to the third node N3; the first pole of the fourth transistor T4 is connected to the data signal terminal Da, the second pole of the fourth transistor T4 is connected to the second node N2, the gate of the fourth transistor T4 is connected to the gate drive signal terminal G2; the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, and the fifth transistor T5
  • the second pole of the second transistor T2 is connected to the second node N2, the gate of the fifth transistor T5 is connected to the enable signal terminal EM; the first pole of the second transistor T2 is connected to the first node N1, and the second pole of the second transistor T2 is connected to the third node N3, the gate of the second transistor T2 is connected to the gate drive signal terminal G1; the first pole of the sixth transistor T6 is connected to the third node N3, the second pole of the sixth transistor
  • the pixel circuit may be connected to a light emitting unit OLED for driving the light emitting unit OLED to emit light, and the light emitting unit OLED may be connected between the fourth node N4 and the second power supply terminal VSS.
  • the first transistor T1 and the second transistor T2 can be N-type transistors, for example, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, and the N-type metal oxide transistors have a small leakage current, so that they can To avoid the light-emitting phase, the node N1 leaks electricity through the first transistor T1 and the second transistor T2.
  • the drive transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, for example, the drive transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be P-type low-temperature polysilicon transistors.
  • Low-temperature polysilicon transistors have high carrier mobility, which is conducive to achieving high resolution, high response speed, high pixel density, and high aperture ratio. display panel.
  • the first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 may output the same or different voltage signals according to actual conditions.
  • FIG. 1B is a signal timing diagram of a driving method of the 7T1C pixel circuit shown in FIG. 1A .
  • G1 indicates the timing of the gate driving signal terminal G1
  • G2 indicates the timing of the gate driving signal terminal G2
  • Re1 indicates the timing of the first reset signal terminal Re1
  • Re2 indicates the timing of the second reset signal terminal Re2
  • EM indicates enable The timing of the signal terminal EM.
  • the driving method of the pixel circuit may include three stages: a reset stage t01, a data writing and compensation stage t02, and a light emitting stage t03.
  • the first reset signal terminal Re1 inputs a high-level signal
  • the first transistor T1 is turned on
  • the first initial signal terminal Vinit1 inputs the first initial signal Vinit1 to the first node N1, so as to control the first node N1 (ie drive the gate of the transistor) to reset.
  • the gate drive signal terminal G2 inputs a low-level signal
  • the gate drive signal terminal G1 inputs a high-level signal
  • the fourth transistor T4 and the second transistor T2 are turned on
  • the data signal terminal Da Input the data signal Vdata to charge the first node N1 until the voltage of the first node N1 becomes Vdata+Vth
  • the voltage Vdata+Vth of the first node N1 is stored by the storage capacitor C, wherein Vdata is the voltage of the data signal voltage (that is, the data voltage), and Vth is the threshold voltage of the driving transistor T3.
  • the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 generates a driving current under the action of the voltage Vdata+Vth stored in the capacitor C;
  • the drive current can be derived from the following formula:
  • ⁇ represents the carrier mobility
  • Cox represents the gate capacitance per unit area
  • W represents the width of the drive transistor channel
  • L represents the length of the drive transistor channel
  • Vgs represents the gate-source voltage difference of the drive transistor
  • Vth represents the drive transistor VDD represents the first power supply voltage provided by the first power supply terminal VDD.
  • the driving current I LE flowing through the light-emitting element OLED is no longer related to the threshold voltage Vth of the driving transistor T3, but only related to the data signal Vdata that controls the grayscale of the pixel circuit to emit light, so that it can realize
  • the compensation of the pixel circuit solves the problem of the threshold voltage drift of the driving transistor T3 due to the process and long-term operation, and eliminates its influence on the driving current, thereby improving the display effect.
  • the above driving method only resets the first node N1 in the reset phase, and does not reset the second node N2 Resetting with the third node N3 is not conducive to eliminating the effect of hysteresis and improving the afterimage phenomenon.
  • the pixel circuit includes a driving circuit, a data writing circuit, a compensation control circuit, a first light emission control circuit, a second light emission control circuit, a first initialization circuit, a second initialization circuit and a transmission circuit.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control the driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light;
  • the data writing circuit is configured to Write the data signal into the first terminal of the drive circuit under the control of the drive circuit;
  • the compensation control circuit is configured to compensate the drive circuit under the control of the second scanning signal;
  • the energy storage circuit is configured to store the voltage of the control terminal of the drive circuit;
  • the second A light emission control circuit is configured to apply the first power supply voltage to the first end of the drive circuit under the control of the first light emission control signal;
  • the second light emission control circuit is configured to apply the driving current to the first end of the drive circuit under the control of the second light emission control signal Applied to the first pole of the light-emitting element;
  • the first initialization circuit is configured to apply the first initialization voltage to the control terminal of the drive circuit under the control of the first reset control signal;
  • the transmission circuit is configured to transmit the control signal transmitting
  • the second light emission control circuit is further configured to transmit the second initialization voltage of the first pole of the light emitting element to the second terminal of the drive circuit under the control of the second light emission control signal; or, the first initialization circuit and the transmission circuit are jointly controlled by Configured to apply the first initialization voltage to the control terminal of the driving circuit, the compensation control circuit is further configured to transmit the first initialization voltage of the control terminal of the driving circuit to the second terminal of the driving circuit under the control of the second scanning signal; or , the first initialization circuit and the transmission circuit are jointly configured to apply the first initialization voltage to the second terminal of the drive circuit, and the compensation control circuit is further configured to apply the first initialization voltage to the second terminal of the drive circuit under the control of the second scanning signal.
  • the initialization voltage is transmitted to the control terminal of the driving circuit.
  • Some embodiments of the present disclosure also provide a driving method and a display panel corresponding to the above-mentioned pixel circuit.
  • the pixel circuit, its driving method, and the display panel provided by the embodiments of the present disclosure can respectively reset the control terminal and the second terminal of the driving circuit each time the screen is switched, so that the control terminal and the second terminal of the driving circuit
  • Each display screen is in the same bias state (relative to different screens), which can eliminate hysteresis, improve afterimage phenomenon, reduce the risk of screen flicker (Flicker), and improve screen quality.
  • Fig. 2 is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure.
  • the pixel circuit 10 can be used in a pixel unit of an AMOLED display panel.
  • the pixel circuit 10 includes a drive circuit 100, a data writing circuit 200, a compensation control circuit 300, an energy storage circuit 350, a first light emission control circuit 400, a second light emission control circuit 500, a first initialization circuit 600, The second initialization circuit 700 and the transmission circuit 800 .
  • the driving circuit 100 includes a control terminal 110 , a first terminal 120 and a second terminal 130 , and is configured to control a driving current flowing through the first terminal 120 and the second terminal 130 for driving the light emitting element 900 to emit light.
  • the control terminal 110 of the driving circuit 100 is connected to the first node N1
  • the first terminal 120 of the driving circuit 100 is connected to the second node N2
  • the second terminal 130 of the driving circuit 100 is connected to the third node N3. connect.
  • the driving circuit 100 can provide a driving current to the light-emitting element 900 to drive the light-emitting element 900 to emit light, and can display gray scales according to needs (different gray scales correspond to different data signals) Provide corresponding driving current to emit light.
  • the light-emitting element 900 can use organic light-emitting diodes (OLEDs), mini light-emitting diodes (Mini LEDs), micro-light-emitting diodes (Micro LEDs), quantum dot light-emitting diodes (QLEDs), inorganic light-emitting diodes, and the like.
  • OLEDs organic light-emitting diodes
  • Mini LEDs mini light-emitting diodes
  • Micro LEDs micro-light-emitting diodes
  • QLEDs quantum dot light-emitting diodes
  • Embodiments of the present disclosure include but Not limited to this.
  • the data writing circuit 200 is configured to write the data signal Vdata into the first terminal 120 of the driving circuit 100 under the control of the first scan signal SN1 .
  • the data writing circuit 200 is connected to the first scan signal terminal SN1 (providing the first scan signal), the data signal terminal DATA (providing the data signal Vdata) and the second node N2.
  • the data writing circuit 200 in the data writing and compensation stage, is turned on in response to the first scanning signal SN1, so that the data signal Vdata provided by the data signal terminal DATA can be written into the first scanning signal Vdata of the driving circuit 100. 120 at one end.
  • the compensation control circuit 300 is configured to compensate the driving circuit 100 under the control of the second scan signal SN2.
  • the compensation control circuit 300 is connected to the second scanning signal terminal SN2 (providing the first scanning signal), the control terminal 110 (the first node N1) and the second terminal 130 (the third node N3) of the driving circuit 100. )connect.
  • the compensation control circuit 300 in the phase of data writing and compensation, is turned on in response to the second scanning signal SN2, and electrically connects the control terminal 110 and the second terminal 130 of the driving circuit 100, so that the data signal Information such as Vdata and the threshold voltage Vth of the driving circuit 100 can be written into the control terminal 110 of the driving circuit 100 and stored by the energy storage circuit 350 , thereby realizing threshold voltage compensation for the driving circuit 100 .
  • the energy storage circuit 350 is configured to store the voltage of the control terminal 110 of the driving circuit 100 .
  • the energy storage circuit 350 is connected to the control terminal 110 (the first node N1 ) of the driving circuit 100 and the first power supply terminal VDD.
  • the energy storage circuit 350 includes a storage capacitor; during the data writing and compensation phase, the storage capacitor can store the data signal Vdata and the threshold voltage Vth, etc.
  • the voltage of the information, and then in the light-emitting stage, the stored voltage including the data signal Vdata and the threshold voltage Vth can be used to control the driving circuit 100, so that the driving circuit 100 can generate and drive the light-emitting element 700 according to the data signal Vdata when it is compensated.
  • the first light emission control circuit 400 is configured to apply the first power supply voltage VDD to the first terminal 120 of the driving circuit 100 under the control of the first light emission control signal EM1.
  • the first light emission control circuit 400 communicates with the first light emission control signal terminal EM1 (providing the first light emission control signal), the first power supply terminal VDD (providing the first power supply voltage) and the first light emission control circuit 100.
  • Terminal 120 (second node N2) is connected.
  • the first light-emitting control circuit 400 in the light-emitting phase, is turned on in response to the first light-emitting control signal EM1, so that the first power supply voltage VDD can be applied to the first terminal 120 of the driving circuit 100.
  • the driving circuit 100 can apply the first power supply voltage VDD to the light emitting element 900 to drive the light emitting element to emit light.
  • the first power supply voltage VDD may be a driving voltage, such as a high voltage.
  • the second light emission control circuit 500 is configured to apply a driving current to the first pole of the light emitting element 900 under the control of the second light emission control signal EM2 .
  • the second light emission control circuit 500 is connected to the second light emission control signal terminal EM2 (providing the second light emission control signal), the third node N3 and the fourth node N4, and the first pole of the light emitting element 900 (
  • the anode is connected to the fourth node N4
  • the second pole of the light emitting element for example, the cathode
  • VSS providing the second power supply voltage
  • the second power supply voltage VSS is a low voltage (for example, lower than the first power supply voltage), such as a ground voltage or the like.
  • the second light-emitting control circuit 500 in the light-emitting phase, is turned on in response to the second light-emitting control signal EM2, so that the driving circuit 100 can apply a driving current to the light-emitting element 900 through the second light-emitting control circuit 500 to make it shine.
  • the first initialization circuit 600 is configured to apply the first initialization voltage Vinit1 to the control terminal 110 of the driving circuit 100 under the control of the first reset control signal RS1, and the transmission circuit 800 is configured to be controlled by the transmission control signal TC.
  • the first initialization voltage Vinit1 is transmitted.
  • the first initialization circuit 600 is connected to the first reset control terminal RS1 (provides the first reset control signal), the first initialization voltage terminal Vinit1 (provides the first initialization voltage) and the fifth node N5, and transmits
  • the circuit 800 is connected to the transmission control signal terminal TC (providing the transmission control signal), the fifth node N5 and the control terminal 110 (the first node N1 ) of the driving circuit 100 .
  • the first initialization circuit 600 in the reset phase, is turned on in response to the first reset control signal RS1, and the transmission circuit 800 is turned on in response to the transmission control signal TC, so that the first initialization circuit 600 and the The transmission circuit 800 applies the first initialization voltage Vinit1 to the first node N1 to perform a reset operation on the control terminal 110 of the driving circuit 100 , so as to eliminate the influence of the previous light-emitting phase on the control terminal 110 of the driving circuit 100 .
  • the second initialization circuit 700 is configured to apply the second initialization voltage Vinit2 to the first pole of the light emitting element 900 under the control of the second reset control signal RS2.
  • the second initialization circuit 700 is connected to the second reset control signal terminal RS2 (providing the second reset control signal), the second initialization voltage terminal Vinit2 (providing the second initialization voltage) and the fourth node N4.
  • the second initialization circuit 700 in the reset phase, is turned on in response to the second reset control signal RS2, so that the second initialization voltage Vinit2 can be applied to the fourth node N4, and the first The pole is reset to eliminate the influence of the previous light-emitting phase on the first pole of the light-emitting element 900 .
  • the second initialization voltage Vinit2 at the node N4) is transmitted to the second terminal (third node N3) of the light emitting element 900.
  • the second initialization circuit 700 in the reset phase, is turned on in response to the second reset control signal RS2, so that the second initialization voltage Vinit2 can be applied to the fourth node N4; at the same time, the second light emission control circuit 500 is turned on in response to the second light emission control signal EM2, so that the second initialization voltage Vinit2 at the fourth node N4 can be transmitted to the third node N3, and the second terminal 130 of the driving circuit 100 is reset to eliminate the previous The influence of the light-emitting phase of the light-emitting phase on the second terminal 130 of the driving circuit 100 .
  • the first initialization circuit 600 and the transmission circuit 800 are jointly configured to apply the first initialization voltage Vinit1 to the control terminal 110 of the driving circuit 100 to compensate for
  • the control circuit 300 is also configured to transmit the first initialization voltage Vinit1 of the control terminal 110 (first node N1) of the driving circuit 100 to the second terminal 130 (third node N1) of the driving circuit 100 under the control of the second scan signal SN2 N3).
  • the first initialization circuit 600 in the reset phase, is turned on in response to the first reset control signal RS1, and the transmission circuit 800 is turned on in response to the transmission control signal TC, so that the first initialization circuit 600 and the The transmission circuit 800 applies the first initialization voltage Vinit1 to the first node N1; at the same time, the compensation control circuit 300 is turned on in response to the second scan signal SN2, so that the first initialization voltage Vinit1 at the first node N1 can be transmitted to the first node N1.
  • the third node N3 performs a reset operation on the second terminal 130 of the driving circuit 100 to eliminate the influence of the previous light-emitting phase on the second terminal 130 of the driving circuit 100 .
  • the first initialization circuit 600 in the reset phase, is turned on in response to the first reset control signal RS1, and the transmission circuit 800 is turned on in response to the transmission control signal TC, so that the first initialization circuit 600 and the The transmission circuit 800 applies the first initialization voltage Vinit1 to the first node N1; at the same time, the compensation control circuit 300 is turned on in response to the second scanning signal SN2, and the first light emission control circuit 400 is turned on in response to the first light emission control signal EM1
  • the drive circuit 100 is turned on under the control of the first initialization voltage Vinit1 at the first node N1, so that the connection between the first power supply terminal VDD and the first initialization voltage terminal Vinit1 is via the first light emission control circuit 400, the drive circuit 100,
  • the compensation control circuit 300, the transmission circuit 800 and the first initialization circuit 600 form a path, and while resetting the first node N1, the second node N2 and the third node N3 can also be reset, so as to eliminate hysteresis effects to the
  • the aforementioned control signals may be the same signal, for example, the same signal may be transmitted by the same signal line, or may be transmitted by different signal lines.
  • the layout space of the display panel can be saved, which is beneficial to the development of a high-resolution display panel.
  • the first light emission control signal EM1 used to control the first light emission control circuit 400 in the pixel circuit 10 of the current row of pixel units can also be used to control the first light emission control signal EM1 in the pixel circuit 10 of the previous row of pixel units.
  • the second light emission control circuit 500 that is, the second light emission control signal EM2 in the pixel circuit 10 of the pixel unit in the previous row;
  • the second light emission control signal EM2 can also be used to control the first light emission control circuit 400 in the pixel circuit 10 of the next row of pixel units, that is, the first light emission control signal EM1 in the pixel circuit 10 of the next row of pixel units.
  • the embodiments of the present disclosure include but are not limited thereto.
  • the signal pulse of the first light emission control signal EM1 and the signal pulse of the second light emission control signal EM2 may differ by one or two time units, wherein one time unit is, for example, the scanning time of a row of sub-pixels. That is to say, there is a misalignment between the timings of the first light emission control signal EM1 and the second light emission control signal EM2 .
  • the following embodiments are the same as this and will not be repeated here.
  • the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 do not represent actual existing components, but Is a meeting point representing the connection of related circuits in a circuit diagram.
  • symbols VDD, VSS, Vinit1 and Vinit2 can represent both corresponding voltage terminals and corresponding voltages; symbols SN1, SN2, EM1, EM2, RS1, RS2, TC can represent both the corresponding control signal terminal and the corresponding control signal.
  • symbols SN1, SN2, EM1, EM2, RS1, RS2, TC can represent both the corresponding control signal terminal and the corresponding control signal.
  • Fig. 3 is a schematic block diagram of another pixel circuit provided by at least some embodiments of the present disclosure.
  • the difference between the pixel circuit 10 shown in FIG. 3 and the pixel circuit 10 shown in FIG. 2 mainly lies in: the connection modes of the compensation control circuit 300 , the first initialization circuit 600 and the transmission circuit 800 are different.
  • other circuit structures in the pixel circuit 10 shown in FIG. 3 are basically the same as those of the pixel circuit 10 shown in FIG. 2 , and will not be repeated here.
  • the basic functions of each circuit structure in the pixel circuit 10 shown in FIG. 3 are basically the same as the corresponding circuit structure in the pixel circuit 10 shown in FIG. 2 , and will not be repeated here.
  • the compensation control circuit 300 is connected to the second scanning signal terminal SN2, the second terminal 130 (the third node N3) of the drive circuit 100, the fifth node N5, and the first power supply terminal VDD, and the first initialization
  • the circuit 600 is connected to the first reset control terminal RS1, the control terminal 110 (the first node N1) of the drive circuit 100, and the fifth node N5, and the transmission circuit 800 is connected to the transmission control signal terminal TC (providing transmission control signals), the fifth node N5 And the first initialization voltage terminal Vinit1 is connected.
  • the first initialization circuit 600 in the reset phase, is turned on in response to the first reset control signal RS1, and the transmission circuit 800 is turned on in response to the transmission control signal TC, so that the transmission circuit 800 and the first The initialization circuit 600 applies the first initialization voltage Vinit1 to the first node N1 to perform a reset operation on the control terminal 110 of the driving circuit 100 , so as to eliminate the influence of the previous light-emitting phase on the control terminal 110 of the driving circuit 100 .
  • the first initialization circuit 600 is turned on in response to the first reset control signal RS1
  • the compensation control circuit 300 is turned on in response to the second scan signal SN2, through the first The initialization circuit 600 and the compensation control circuit 300 electrically connect the control terminal 110 of the driving circuit 100 to the second terminal 130, so that the data signal Vdata written by the data writing circuit 500 corresponds to the relevant information of the threshold voltage Vth of the driving circuit 100. stored in the tank circuit 350.
  • the second initialization voltage Vinit2 at the node N4) is transmitted to the second terminal (third node N3) of the driving circuit 900.
  • the second initialization circuit 700 is turned on in response to the second reset control signal RS2, so that the second initialization voltage Vinit2 can be applied to the fourth node N4; meanwhile, the second light emission control circuit 500 is turned on in response to the second light emission control signal EM2, so that the second initialization voltage Vinit2 at the fourth node N4 can be transmitted to the third node N3, and the second terminal 130 of the driving circuit 100 is reset to eliminate the previous The influence of the light-emitting phase of the light-emitting phase on the second terminal 130 of the driving circuit 100 .
  • Fig. 4 is a schematic block diagram of another pixel circuit provided by at least some embodiments of the present disclosure.
  • the difference between the pixel circuit 10 shown in FIG. 4 and the pixel circuit 10 shown in FIG. 2 mainly lies in that the connection modes of the first initialization circuit 600 and the transmission circuit 800 are different.
  • other circuit structures in the pixel circuit 10 shown in FIG. 4 are basically the same as those of the pixel circuit 10 shown in FIG. 2 , and will not be repeated here.
  • the basic functions of each circuit structure in the pixel circuit 10 shown in FIG. 4 are basically the same as the corresponding circuit structure in the pixel circuit 10 shown in FIG. 2 , and will not be repeated here.
  • the first initialization circuit 600 and the transfer circuit 800 are jointly configured to apply the first initialization voltage Vinit1 to the second terminal 130 (third node N3) of the driving circuit 100 to compensate for
  • the control circuit 300 is further configured to transmit the first initialization voltage Vinit1 of the second terminal 130 of the driving circuit 100 to the control terminal 110 of the driving circuit 100 under the control of the second scan signal SN2 .
  • FIG. 1 shows that as shown in FIG. 1
  • the first initialization circuit 600 is connected to the first reset control terminal RS1, the first initialization voltage terminal Vinit1 and the fifth node N5, and the transmission circuit 800 is connected to the transmission control signal terminal TC, the fifth node N5 and the drive
  • the second terminal 130 (third node N3) of the circuit 100 is connected.
  • the first initialization circuit 600 in response to the first reset control signal RS1, and the transmission circuit 800 is turned on in response to the transmission control signal TC, so that the first initialization circuit 600 and the The transmission circuit 800 applies the first initialization voltage Vinit1 to the third node N3, and performs a reset operation on the second terminal 130 of the driving circuit 100, so as to eliminate the influence of the previous light-emitting phase on the third terminal 130 of the driving circuit 100; at the same time, the compensation The control circuit 300 is turned on in response to the second scan signal SN2, so that the first initialization voltage Vinit1 at the third node N3 can be transmitted to the first node N1, and the control terminal 110 of the driving circuit 100 is reset to eliminate the previous The influence of the light-emitting phase of the light-emitting phase on the control terminal 110 of the driving circuit 100 .
  • the first light emission control circuit 400 in addition to the working process of the circuit structure described in the above example, in the reset phase, the first light emission control circuit 400 is turned on in response to the first light emission control signal EM1, and the driving circuit 100 at the first node N1 Conducted under the control of the first initialization voltage Vinit1 at , so that the connection between the first power supply terminal VDD and the first initialization voltage terminal Vinit1 is via the first lighting control circuit 400 , the driving circuit 100 , the compensation control circuit 300 , the transmission circuit 800 and The first initialization circuit 600 forms a path to reset the second node N2 while resetting the first node N1 and the third node N3, so as to eliminate hysteresis effects to the greatest extent.
  • FIG. 5 is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 2 .
  • the pixel circuit 10 includes first to eighth transistors T1 - T8 and a storage capacitor Cst.
  • the light emitting element LE shown in FIG. 5 is the aforementioned light emitting element 900 .
  • the third transistor T3 is used as a driving transistor, and the other transistors are used as switching transistors.
  • the light-emitting element LE can be OLED, and the embodiments of the present disclosure include but are not limited thereto. The following embodiments are all described using OLED as an example, and details are not repeated here.
  • the OLED can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., which are not limited by embodiments of the present disclosure.
  • the driving circuit 100 may be implemented as a third transistor T3.
  • the gate of the third transistor T3 is connected to the first node N1 as the control terminal 110 of the driving circuit 100, the first pole of the third transistor T3 is connected to the second node N2 as the first terminal 120 of the driving circuit 100, and the third transistor T3
  • the second pole of the drive circuit 100 is connected to the third node N3 as the second end 130 of the driving circuit 100 .
  • the third transistor T3 can be a P-type thin film transistor; for example, the P-type thin film transistor can include a low-temperature polysilicon transistor, and the low-temperature polysilicon transistor has a higher carrier mobility, which is conducive to realizing high resolution.
  • the P-type thin film transistor is turned on in response to the low level of its control signal, and the following embodiments are the same, and will not be repeated here.
  • the threshold voltage Vth of the third transistor T3 may be greater than or equal to -5V and less than or equal to -2V; the threshold voltage Vth of the third transistor T3 may be greater than or equal to -4V and less than or equal to -2.5V; for example, the third transistor
  • the threshold voltage Vth of T3 can be -4V, -3.5V, -3V or -2.5V, but not limited thereto.
  • the data writing circuit 200 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first scan signal terminal SN1 to receive the first scan signal
  • the first pole of the fourth transistor T4 is connected to the data signal terminal DATA to receive the data signal Vdata
  • the second pole of the fourth transistor T4 connected to the first end of the drive circuit.
  • the fourth transistor T4 may be a P-type thin film transistor, such as a thin film transistor whose active layer is low temperature doped polysilicon.
  • the compensation control circuit 300 can be implemented as a second transistor T2, and the energy storage circuit 350 can be implemented as a storage capacitor Cst.
  • the gate of the second transistor T2 is connected to the second scanning signal terminal SN2 to receive the second scanning signal, the first pole of the second transistor T2 is connected to the second terminal 130 (third node N3) of the driving circuit 100, and the second transistor T2
  • the second pole of T2 is connected to the control terminal 110 (first node N1) of the drive circuit 100;
  • the first terminal of the storage capacitor Cst is coupled to the control terminal 110 (first node N1) of the drive circuit 100, and the first terminal of the storage capacitor Cst is coupled to the control terminal 110 (first node N1) of the drive circuit 100
  • the two terminals are coupled to the first power supply terminal VDD.
  • the second transistor T2 may be an N-type thin film transistor.
  • the second transistor T2 can be an N-type oxide thin film transistor, which can use Indium Gallium Zinc Oxide (IGZO) as the active layer of the thin film transistor; ) or amorphous silicon (such as hydrogenated amorphous silicon) as the active layer of the thin film transistor can effectively reduce the size of the transistor and reduce the leakage current.
  • IGZO Indium Gallium Zinc Oxide
  • amorphous silicon such as hydrogenated amorphous silicon
  • the N-type thin film transistor is turned on in response to the high level of its control signal, the following embodiments are the same as this, and will not be repeated here.
  • the first light emission control circuit 400 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the first light emission control signal terminal EM1 to receive the first light emission control signal
  • the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD to receive the first power supply voltage
  • the fifth transistor T5 The second pole of the drive circuit 100 is connected to the first terminal 120 (the second node N2).
  • the fifth transistor T5 may be a P-type thin film transistor, such as a thin film transistor whose active layer is low temperature doped polysilicon.
  • the first power supply voltage VDD may be a driving voltage, such as a high voltage.
  • the voltage value of the first power supply voltage VDD may be 4.6V, but not limited thereto.
  • the second light emission control circuit 500 may be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the second light emission control signal terminal EM2 to receive the second light emission control signal
  • the first electrode of the sixth transistor T6 is connected to the second terminal 130 (third node N3) of the driving circuit 100
  • the second The second pole of the six transistor T6 is connected to the fourth node N4.
  • the sixth transistor T6 may be a P-type thin film transistor, such as a thin film transistor whose active layer is low temperature doped polysilicon.
  • the second initialization circuit 700 may be implemented as a seventh transistor T7.
  • the gate of the seventh transistor T7 is connected to the second reset control signal terminal RS2 to receive the second reset control signal
  • the first electrode of the seventh transistor T7 is connected to the second initialization voltage terminal Vinit2 to receive the second initialization voltage
  • the seventh transistor The second pole of T7 is connected to the fourth node N4.
  • the seventh transistor T7 may be a P-type thin film transistor, such as a thin film transistor whose active layer is low temperature doped polysilicon.
  • the second initialization voltage Vinit2 can be a DC voltage, and the voltage value of the second initialization voltage Vinit2 can be greater than or equal to -7V and less than or equal to 0V; for example, the voltage value of the second initialization voltage Vinit2 can be -6V, -5V , -4V, -3V or -2V, but not limited to.
  • the first initialization circuit 600 may be implemented as a first transistor T1.
  • the gate of the first transistor T1 is connected to the first reset control signal terminal RS1 to receive the first reset control signal
  • the first electrode of the first transistor T1 is connected to the first initialization voltage terminal Vinit1 to receive the first initialization voltage
  • the first transistor The second pole of T1 is connected to the fifth node N5.
  • the first transistor T1 may be a P-type thin film transistor, such as a thin film transistor whose active layer is low temperature doped polysilicon.
  • the first initialization voltage Vinit1 can be a DC voltage, and the voltage value of the first initialization voltage Vinit1 can be greater than or equal to -7V and less than or equal to 0V; for example, the voltage value of the first initialization voltage Vinit1 can be -6V, -5V , -4V, -3V or -2V, but not limited to.
  • the transmission circuit 800 may be implemented as an eighth transistor T8.
  • the gate of the eighth transistor T8 is connected to the transmission control signal terminal TC to receive the transmission control signal, the first pole of the eighth transistor T8 is connected to the fifth node N5, the second pole of the eighth transistor T8 is connected to the control terminal of the driving circuit 100 110 (the first node N1) is connected.
  • the eighth transistor T8 may be a P-type thin film transistor, such as a thin film transistor whose active layer is low-temperature doped polysilicon.
  • the first pole (eg, anode) of the light emitting element LE is connected to the fourth node N4, and the second pole (eg, cathode) of the light emitting element LE is connected to the second power supply terminal VSS to receive the second voltage.
  • the second power supply voltage VSS can be a low voltage, for example, the second power supply terminal ELVSS can be grounded, so that the second power supply voltage VSS can be a ground voltage (zero voltage).
  • the second reset control signal RS2 can be the same control signal as the first reset control signal RS1; the transmission control signal TC can be equal to the first light emission control signal EM1 or the second light emission control signal EM2. same control signal. It should be noted that the embodiments of the present disclosure do not limit this.
  • FIG. 6 is a schematic circuit structure diagram of another specific implementation example of the pixel circuit shown in FIG. 2 .
  • the difference between the pixel circuit shown in FIG. 6 and the pixel circuit shown in FIG. 5 is mainly that: in the pixel circuit shown in FIG. 6, the seventh transistor T7 is an N-type thin film transistor, such as an N-type oxide thin film transistor, so that It is beneficial to reduce the size of the transistor and reduce the leakage current of the fourth node N4.
  • the seventh transistor T7 is an N-type thin film transistor, such as an N-type oxide thin film transistor, so that It is beneficial to reduce the size of the transistor and reduce the leakage current of the fourth node N4.
  • other circuit structures in the pixel circuit shown in FIG. 6 are basically the same as those of the pixel circuit shown in FIG. 5 , and will not be repeated here.
  • the second reset control signal RS2 can be the same control signal as the first light emission control signal EM1 ; the transmission control signal TC can be the same control signal as the second light emission control signal EM2 . It should be noted that the embodiments of the present disclosure do not limit this.
  • FIG. 7 is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 3 .
  • the difference between the pixel circuit 10 shown in FIG. 7 and the pixel circuit shown in FIG. 5 mainly lies in: the connection modes of the second transistor T2 , the first transistor T1 and the eighth transistor T8 are different.
  • other circuit structures in the pixel circuit shown in FIG. 7 are basically the same as those of the pixel circuit shown in FIG. 5 , and will not be repeated here.
  • the gate of the first transistor T1 is connected to the first reset control signal terminal RS1 to receive the first reset control signal, the first pole of the first transistor T1 is connected to the fifth node N5, and the first transistor T1
  • the second pole of T1 is connected to the control terminal 110 (first node N1) of the drive circuit 100; the gate of the eighth transistor T8 is connected to the transmission control signal terminal TC to receive the transmission control signal, and the first pole of the eighth transistor T8 is connected to the transmission control signal terminal TC.
  • the first initialization voltage terminal Vinit1 is connected to receive the first initialization voltage
  • the second pole of the eighth transistor is connected to the fifth node N5
  • the gate of the second transistor T2 is connected to the second scanning signal terminal SN2 to receive the second scanning signal
  • the first pole of the second transistor T2 is connected to the second terminal 130 (the third node N3 ) of the driving circuit 100
  • the second pole of the second transistor T2 is connected to the fifth node N5 . That is to say, the second pole of the second transistor T2 is connected to the control terminal 110 of the driving circuit 100 through the first transistor T1.
  • the second reset control signal RS2 can be the same control signal as the first reset control signal RS1 ; the transmission control signal TC can be the same control signal as the second light emission control signal EM2 . It should be noted that the embodiments of the present disclosure do not limit this.
  • FIG. 8 is a schematic circuit structure diagram of another specific implementation example of the pixel circuit shown in FIG. 3 .
  • the difference between the pixel circuit shown in FIG. 8 and the pixel circuit shown in FIG. 7 is that: in the pixel circuit shown in FIG. 8 , the seventh transistor T7 is an N-type thin film transistor, such as an N-type oxide thin film transistor, so that It is beneficial to reduce the size of the transistor and reduce the leakage current of the fourth node N4.
  • the seventh transistor T7 is an N-type thin film transistor, such as an N-type oxide thin film transistor, so that It is beneficial to reduce the size of the transistor and reduce the leakage current of the fourth node N4.
  • other circuit structures in the pixel circuit shown in FIG. 8 are basically the same as those of the pixel circuit shown in FIG. 7 , and will not be repeated here.
  • the second reset control signal RS2 can be the same control signal as the first light emission control signal EM1 ; the transmission control signal TC can be the same control signal as the second light emission control signal EM2 . It should be noted that the embodiments of the present disclosure do not limit this.
  • FIG. 9 is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 4 .
  • the difference between the pixel circuit shown in FIG. 9 and the pixel circuit shown in FIG. 5 mainly lies in: the connection modes of the first transistor T1 and the eighth transistor T8 are different.
  • other circuit structures in the pixel circuit shown in FIG. 9 are basically the same as those of the pixel circuit shown in FIG. 5 , and will not be repeated here.
  • the gate of the first transistor T1 is connected to the first reset control signal terminal RS1 to receive the first reset control signal, and the first pole of the first transistor T1 is connected to the first initialization voltage terminal Vinit1 to receive The first initialization voltage, the second pole of the first transistor T1 is connected to the fifth node N5; the gate of the eighth transistor T8 is connected to the transmission control signal terminal TC to receive the transmission control signal, the first pole of the eighth transistor T8 is connected to the first node N5 The fifth node N5 is connected, and the second pole of the eighth transistor is connected to the second terminal 130 (third node N3 ) of the driving circuit 100 .
  • the first transistor T1 in the reset phase, is turned on in response to the first reset control signal RS1, and the eighth transistor T8 is turned on in response to the transmission control signal TC, so that the first transistor T1 and the second
  • the eight-transistor T8 applies the first initialization voltage Vinit1 to the third node N3, and performs a reset operation on the second terminal 130 of the driving circuit 100 (the second pole of the third transistor T3), so as to eliminate the impact on the driving circuit 100 in the previous light-emitting stage.
  • the control terminal 110 (the gate of the third transistor T3 ) performs a reset operation to eliminate the influence of the previous light-emitting phase on the control terminal 110 of the driving circuit 100 .
  • the second reset control signal RS2 can be the same control signal as the first scan signal SN1 ; the transmission control signal TC can be the same control signal as the first light emission control signal EM1 . It should be noted that the embodiments of the present disclosure do not limit this.
  • FIG. 10 is a schematic circuit structure diagram of another specific implementation example of the pixel circuit shown in FIG. 4 .
  • the difference between the pixel circuit shown in FIG. 10 and the pixel circuit shown in FIG. 9 is that in the pixel circuit shown in FIG. 10, the seventh transistor T7 is an N-type thin film transistor, such as an N-type oxide thin film transistor, so that It is beneficial to reduce the size of the transistor and reduce the leakage current of the fourth node N4.
  • the seventh transistor T7 is an N-type thin film transistor, such as an N-type oxide thin film transistor, so that It is beneficial to reduce the size of the transistor and reduce the leakage current of the fourth node N4.
  • other circuit structures in the pixel circuit shown in FIG. 10 are basically the same as those of the pixel circuit shown in FIG. 9 , and will not be repeated here.
  • the second reset control signal RS2 can be the same control signal as the second light emission control signal EM2 ; the transmission control signal TC can be the same control signal as the first light emission control signal EM1 . It should be noted that the embodiments of the present disclosure do not limit this.
  • FIG. 11A is a schematic diagram of a partial planar structure of an oxide thin film transistor provided by at least some embodiments of the present disclosure
  • FIG. 11B is a schematic diagram of a partial cross-sectional structure of an oxide thin film transistor provided by at least some embodiments of the present disclosure.
  • the oxide thin film transistor includes a first metal layer Metal_1 , an active layer S/D, and a second metal layer Metal_2 sequentially stacked in the Z direction and insulated from each other.
  • the oxide thin film transistor is disposed on a base substrate, wherein both the X direction and the Y direction are parallel to the surface of the base substrate, and the Z direction is perpendicular to the surface of the base substrate.
  • the X direction is perpendicular to the Y direction.
  • an insulating layer (not shown in FIG.
  • the material of the active layer S/D may be Indium Gallium Zinc Oxide (IGZO) or the like.
  • the active layer S/D extends in the Y direction.
  • the width of the second metal layer Metal_2 is not greater than the width of the first metal layer Metal_1 .
  • the second metal layer Metal_2 is connected to the second scan signal terminal SN2 to serve as the gate of an oxide thin film transistor (for example, the second transistor T2 and/or the seventh transistor T7, etc.); the first metal layer A direct current signal can be input into Metal_1, which functions as a shield to shield the influence of the external electric field on the oxide thin film transistor.
  • both the second metal layer Metal_2 and the first metal layer Metal_1 are connected to the second scan signal terminal SN2 to serve as oxide thin film transistors (for example, the second transistor T2 and/or the seventh transistor T7, etc. ) gate.
  • the active layer S/D includes a channel region covered by the first metal layer Metal_1, and a source region S and a drain region D located on both sides of the channel region.
  • the source region S and the drain region D are electrically connected to the first electrode and the second electrode of the oxide thin film transistor, respectively.
  • the value range of the width-to-length ratio W/L of the channel region of the oxide thin film transistor is [1/2, 7/8].
  • the general value of the width-to-length ratio W/L of the channel region of an oxide thin film transistor is 2.5/3.0; for example, the value range of W may be [1.5,2.5], and the value range of L may be [2.0, 8.0].
  • the length of the channel region refers to the dimension of the channel region in the direction of extension of the active layer S/D (i.e. the Y direction), and the length of the channel region refers to the dimension between the channel region and the active layer.
  • the dimension in another plane direction that is, the X direction perpendicular to the extension direction of S/D.
  • the value range of the width-to-length ratio of the channel region of the first transistor T1 may be [1/3, 3/4] and the eighth transistor The value range of the width-to-length ratio of the channel region of T8 may also be [1/3, 3/4].
  • the general value of the width-to-length ratio of the channel region of the first transistor T1 is 2.0/3.0; for example, the wide value range of the channel region of the first transistor T1 can be [1.5, 2.5], and the first transistor T1 The long range of the channel region may be [2.0,5.0].
  • the general value of the width-to-length ratio of the channel region of the eighth transistor T8 is 2.0/3.0; for example, the wide value range of the channel region of the eighth transistor T8 can be [1.5, 2.5], the eighth transistor T8 The long range of the channel region may be [2.0,5.0].
  • at least one of the first transistor T1 and the eighth transistor T8 may have a double-gate structure.
  • the general value of the width-to-length ratio of its channel region is 2.0/ (3.0+3.0).
  • the storage capacitor Cst may be a capacitive device manufactured through a process, for example, by making a special capacitive electrode to realize the capacitive device, and each electrode of the capacitor may be made through a metal layer, a semiconductor layer (such as doped polysilicon), etc., and the capacitance can also be the parasitic capacitance between various devices, which can be realized by the transistor itself and other devices and lines.
  • the connection method of the capacitor is not limited to the method described above, and other applicable connection methods may also be used, as long as the level of the corresponding node can be stored.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the embodiments of the present disclosure in order to distinguish the two poles of the transistor except the gate, it is directly described that one pole is the first pole and the other pole is the second pole.
  • the first pole for a P-type transistor, the first pole may be a source, and the second pole may be a drain; for an N-type transistor, the first pole may be The drain, the second pole can be the source.
  • the present disclosure includes but is not limited to this.
  • the second pole (for example, the cathode) of the light emitting element LE is connected to the second power supply voltage VSS (low voltage) as an example for illustration. Including but not limited to this.
  • the first pole (for example, anode) of the light emitting element LE can also be connected to the first power supply voltage VDD (high voltage), while its cathode is directly or indirectly connected to the pixel circuit.
  • active level refers to the level that can make the operated transistor included in it be turned on
  • inactive level refers to A level that cannot cause an operated transistor included therein to be turned on (that is, the transistor is turned off).
  • the active level can be higher or lower than the inactive level.
  • the active level is a low level
  • the inactive level is a high level
  • the inactive level is a low level .
  • At least some embodiments of the present disclosure also provide a driving method of a pixel circuit.
  • 12-18 are signal timing diagrams of various pixel circuit driving methods provided by at least some embodiments of the present disclosure.
  • the signal timings shown in FIGS. 12-14 can all be used to drive the pixel circuit 10 shown in FIG. 2
  • the signal timings shown in FIGS. 12 and 14 can also be used to drive the pixel circuit 10 shown in FIG. 3 . 13
  • the signal timing shown in FIG. 15 can be used to drive the pixel circuit 10 shown in FIG. 4 .
  • the pixel circuit 10 shown in FIGS. 2-4 in combination with the signal timings shown in FIGS. 2-4 (wherein, the pixel circuit shown in FIG.
  • FIG. 2 is specifically implemented as the circuit structure shown in FIG.
  • the pixel circuit shown in FIG. 7 or FIG. 8 is specifically implemented as the circuit structure shown in FIG. 7 or FIG. 8
  • the pixel circuit shown in FIG. 4 is specifically implemented as the circuit structure shown in FIG. 9 or FIG. 10 ).
  • the potential levels of the signal timings shown in Figures 12-18 are only schematic, and do not represent real potential values or relative proportions, corresponding to the embodiments of the present disclosure, and low-level signals correspond to P-type Transistor turn-on signal or N-type transistor turn-off signal, and the high-level signal corresponds to P-type transistor turn-off signal or N-type transistor turn-on signal.
  • the display process of each frame of image may include five stages, namely reset stage t1, data writing and compensation stage t2, hold stage t3&t4, and light emitting stage t5.
  • the timing waveforms of the individual control signals in each phase are shown in Figures 12-18.
  • the second light emission control signal EM2 In the reset phase t1, the second light emission control signal EM2, the first reset control signal RS1, the second reset control signal RS2 and the transmission control signal TC are input, and the second light emission control circuit 500, the first initialization circuit 600, and the second initialization circuit are turned on.
  • the 700 and the transmission circuit 800 apply the first initialization voltage Vinit1 to the control terminal 110 of the driving circuit 100 through the first initialization circuit 600 and the transmission circuit 800 to reset the control terminal 110 of the driving circuit 100, and through the second initialization circuit 700
  • the second initialization voltage Vinit2 is applied to the first pole of the light emitting element 900 to reset the light emitting element 900
  • the second initialization voltage Vinit2 is applied to the second terminal of the driving circuit 100 through the second initialization circuit 700 and the second light emission control circuit 500 130 to reset the second terminal 130 of the driving circuit 100; or, in the reset phase t1, input the second scanning signal SN2, the first reset control signal RS1, the second reset control signal RS2 and the transmission control signal TC to start the compensation control
  • the circuit 300, the first initialization circuit 600, the second initialization circuit 700 and the transmission circuit 800 apply the first initialization voltage Vinit1 to the control terminal 110 of the driving circuit 100 through the first initialization circuit 600 and the transmission circuit 800 to control the driving circuit 100.
  • the control terminal 110 is reset, and the first initialization voltage Vinit1 is applied to the second terminal 130 of the driving circuit 100 through the first initialization circuit 600, the transmission circuit 800 and the compensation control circuit 300 to reset the second terminal 130 of the driving circuit 100, Apply the second initialization voltage Vinit2 to the first pole of the light-emitting element 900 through the second initialization circuit 700 to reset the light-emitting element 900; or, in the reset phase t1, input the second scan signal SN2, the first reset control signal RS1,
  • the second reset control signal RS2 and the transmission control signal TC turn on the compensation control circuit 300, the first initialization circuit 600, the second initialization circuit 700 and the transmission circuit 800, and the first initialization voltage Vinit1 is transmitted through the first initialization circuit 600 and the transmission circuit 800 Apply to the second terminal 130 of the driving circuit 100 to reset the second terminal 130 of the driving circuit 100, and apply the first initialization voltage Vinit1 to the terminal of the driving circuit 100 through the first initialization circuit 600, the transmission circuit 800 and the compensation control circuit 300
  • the P-type sixth transistor T6 is turned on by the low level of the second light emission control signal EM2, and the P-type first transistor T6
  • the transistor T1 is turned on by the low level of the first reset control signal RS1
  • the P-type seventh transistor T7 is turned on by the low level of the second reset control signal RS2
  • the P-type eighth transistor T8 is turned on by the transmission control signal TC.
  • the N-type second transistor T2 is turned off by the low level of the second scanning signal SN2
  • the P-type fourth transistor T4 is turned off by the high level of the first scanning signal SN1
  • the P-type fourth transistor T4 is turned off by the high level of the first scanning signal SN1.
  • the five transistor T5 is turned off by the high level of the first light emitting control signal EM1.
  • the first reset voltage Vinit1 can be transmitted to the first node N1 through the turned-on first transistor T1 and the eighth transistor T8, so as to reset the first node N1 (the control terminal 110 of the driving circuit 100) to Vinit1;
  • the second reset The voltage Vinit2 can be transmitted to the fourth node N4 through the turned-on seventh transistor T7, and further transmitted to the third node N3 through the turned-on sixth transistor T6, so that the fourth node N4 (the first pole of the light emitting element LE) and the third node N3 (the second terminal 130 of the driving circuit 100 ) are reset to Vinit2. Therefore, the display device adopting the above-mentioned pixel circuit resets the first node N1 , the third node N3 and the fourth node N4 every time the screen is switched, thereby eliminating the effect of hysteresis.
  • the P-type fifth transistor T5 is turned on by the low level of the first light emission control signal EM1, and the P-type first transistor T5
  • the transistor T1 is turned on by the low level of the first reset control signal RS1
  • the P-type seventh transistor T7 is turned on by the low level of the second reset control signal RS2
  • the P-type eighth transistor T8 is turned on by the transmission control signal TC.
  • the N-type second transistor T2 When the low level is turned on, the N-type second transistor T2 is turned on by the high level of the second scanning signal SN2; at the same time, the P-type fourth transistor T4 is turned off by the high level of the first scanning signal SN1, and the P-type fourth transistor T4 is turned on by the high level of the first scanning signal SN1.
  • the sixth transistor T6 is turned off by the high level of the second light emitting control signal EM2.
  • a path can be formed between the first power supply terminal VDD and the first initialization voltage terminal Vinit1 via the turned-on fifth transistor T5, the third transistor T3, the second transistor T2, the eighth transistor T8 and the first transistor T1, so as to simultaneously Reset the first node N1, the second node N2 and the third node N3; the second reset voltage Vinit2 can be transmitted to the fourth node N4 through the turned-on seventh transistor T7, so as to turn the fourth node N4 (the light emitting element LE first pole) reset to Vinit2.
  • the display device adopting the above-mentioned pixel circuit resets the first node N1 , the second node N2 , the third node N3 and the fourth node N4 every time the screen is switched, thereby eliminating the effect of hysteresis.
  • the working principle of the reset phase t1 corresponding to the circuit structure shown in Figure 6 and the signal timing shown in Figure 14 is basically the same as the working principle of the reset phase t1 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 12 They are the same (the difference is only in the type of the seventh transistor T7 and the corresponding active level of the second reset control signal RS2 ), and the repeated parts will not be repeated here.
  • the P-type sixth transistor T6 is turned on by the low level of the second light emission control signal EM2, and the P-type first transistor T6
  • the transistor T1 is turned on by the low level of the first reset control signal RS1
  • the P-type seventh transistor T7 is turned on by the low level of the second reset control signal RS2
  • the P-type eighth transistor T8 is turned on by the transmission control signal TC.
  • the N-type second transistor T2 is turned off by the low level of the second scanning signal SN2
  • the P-type fourth transistor T4 is turned off by the high level of the first scanning signal SN1
  • the P-type fourth transistor T4 is turned off by the high level of the first scanning signal SN1.
  • the five transistor T5 is turned off by the high level of the first light emitting control signal EM1.
  • the first reset voltage Vinit1 can be transmitted to the first node N1 through the turned-on eighth transistor T8 and the first transistor T1, so as to reset the first node N1 (the control terminal 110 of the driving circuit 100) to Vinit1;
  • the second reset The voltage Vinit2 can be transmitted to the fourth node N4 through the turned-on seventh transistor T7, and further transmitted to the third node N3 through the turned-on sixth transistor T6, so that the fourth node N4 (the first pole of the light emitting element LE) and the third node N3 (the second terminal 130 of the driving circuit 100 ) are reset to Vinit2. Therefore, the display device adopting the above-mentioned pixel circuit resets the first node N1 , the third node N3 and the fourth node N4 every time the screen is switched, thereby eliminating the effect of hysteresis.
  • the working principle of the reset phase t1 corresponding to the circuit structure shown in Figure 8 and the signal timing shown in Figure 14 is basically the same as the working principle of the reset phase t1 corresponding to the circuit structure shown in Figure 7 and the signal timing shown in Figure 12 They are the same (the difference is only in the type of the seventh transistor T7 and the corresponding active level of the second reset control signal RS2 ), and the repeated parts will not be repeated here.
  • the P-type fifth transistor T5 is turned on by the low level of the first light emission control signal EM1, and the P-type first transistor T5
  • the transistor T1 is turned on by the low level of the first reset control signal RS1
  • the P-type seventh transistor T7 is turned on by the low level of the second reset control signal RS2
  • the P-type eighth transistor T8 is turned on by the transmission control signal TC.
  • the N-type second transistor T2 When the low level is turned on, the N-type second transistor T2 is turned on by the high level of the second scanning signal SN2; at the same time, the P-type fourth transistor T4 is turned off by the high level of the first scanning signal SN1, and the P-type fourth transistor T4 is turned on by the high level of the first scanning signal SN1.
  • the sixth transistor T6 is turned off by the high level of the second light emitting control signal EM2.
  • the first initialization voltage terminal Vinit can be applied to the third node N3 through the turned-on first transistor T1 and the eighth transistor T8, and then applied to the first node N1 through the turned-on second transistor T2, so that the first node N1 is reset; at the same time, a path can be formed between the first power supply terminal VDD and the first initialization voltage terminal Vinit1 via the turned-on fifth transistor T5, the third transistor T3, the eighth transistor T8 and the first transistor T1, so as to simultaneously The second node N2 and the third node N3 are reset; the second reset voltage Vinit2 can be transmitted to the fourth node N4 through the turned-on seventh transistor T7 to reset the fourth node N4 (the first pole of the light emitting element LE) to Vinit2.
  • the display device adopting the above-mentioned pixel circuit resets the first node N1 , the second node N2 , the third node N3 and the fourth node N4 every time the screen is switched, thereby eliminating the effect of hysteresis.
  • the working principle of the reset phase t1 corresponding to the circuit structure shown in Figure 10 and the signal timing shown in Figure 15 is basically the same as the working principle of the reset phase t1 corresponding to the circuit structure shown in Figure 9 and the signal timing shown in Figure 13 They are the same (the difference is only in the type of the seventh transistor T7 and the corresponding active level of the second reset control signal RS2 ), and the repeated parts will not be repeated here.
  • the first scanning signal SN1 and the second scanning signal SN2 are input, the data writing circuit 200, the driving circuit 100 and the compensation control circuit 300 are turned on, and the data signal Vdata is written into the data through the data writing circuit 200.
  • the compensation control circuit 300 compensates the driving circuit 100 through the compensation control circuit 300 .
  • the P-type first transistor T1 is turned on by the low level of the first reset control signal RS1
  • P The seventh transistor T7 of the N-type is turned on by the low level of the second reset control signal RS2
  • the second transistor T2 of the N-type is turned on by the high level of the second scan signal SN2
  • the fourth transistor T4 of the P-type is turned on by the first The low level of the scan signal SN1 is turned on.
  • the third transistor T3 is in a diode connection mode (the gate of the third transistor T3 is connected to the second pole); at the same time, the P-type The sixth transistor T6 is turned off by the high level of the second light emission control signal EM2, the P-type eighth transistor T8 is turned off by the high level of the transmission control signal TC, and the P-type fifth transistor T5 is turned off by the high level of the first light emission control signal EM1. High cut-off.
  • the second reset voltage Vinit2 can still be transmitted to the fourth node N4 through the turned-on seventh transistor T7, so as to continuously reset the fourth node N4 (the first pole of the light-emitting element LE); the data signal Vdata passes through the turned-on seventh transistor T7
  • the fourth transistor T4, the third transistor T3 and the second transistor T2 charge the first node N1 (that is, charge the first terminal of the capacitor Cst).
  • the potential of the second node N2 remains at Vdata, and at the same time, according to the characteristics of the third transistor T3, when the potential of the first node N1 (that is, the potential of the first end of the storage capacitor Cst) reaches Vdata+Vth, the second The three transistors T3 are turned off, and the charging process ends.
  • Vdata represents the voltage value of the data signal
  • Vth represents the threshold voltage of the third transistor T3.
  • the third transistor T3 is a P-type transistor, so the threshold voltage Vth here can be a negative value.
  • the first reset control signal RS1 and the second reset control signal RS2 can also be adjusted so that the first transistor T1 and the seventh transistor T7 are turned off without causing any damage to the pixel circuit in the subsequent light-emitting stage. impact, which is not limited by the embodiments of the present disclosure.
  • circuit structure shown in Figure 5 and the signal timing shown in Figure 13 correspond to the data writing and compensation stage t2
  • circuit structure shown in Figure 5 and the signal timing shown in Figure 12 correspond to the data writing
  • the working principle is basically the same as that of the compensation stage t2, and the repetitive parts will not be repeated here.
  • circuit structure shown in Figure 6 and the signal timing shown in Figure 14 correspond to the data writing and compensation stage t2
  • circuit structure shown in Figure 5 and the signal timing shown in Figure 12 correspond to the data writing
  • the working principle is basically the same as that of the compensation stage t2 (the difference is only in the type of the seventh transistor T7 and the corresponding active level of the second reset control signal RS2 ), and the repetition is omitted here.
  • the P-type first transistor T1 is turned on by the low level of the first reset control signal RS1
  • P The seventh transistor T7 of the N-type is turned on by the low level of the second reset control signal RS2
  • the second transistor T2 of the N-type is turned on by the high level of the second scan signal SN2
  • the fourth transistor T4 of the P-type is turned on by the first The low level of the scan signal SN1 is turned on.
  • the third transistor T3 is in a diode connection mode (the gate of the third transistor T3 is connected to the second pole); at the same time, the P-type The sixth transistor T6 is turned off by the high level of the second light emission control signal EM2, the P-type eighth transistor T8 is turned off by the high level of the transmission control signal TC, and the P-type fifth transistor T5 is turned off by the high level of the first light emission control signal EM1. High cut-off.
  • the second reset voltage Vinit2 can still be transmitted to the fourth node N4 through the turned-on seventh transistor T7, so as to continuously reset the fourth node N4 (the first pole of the light-emitting element LE); the data signal Vdata passes through the turned-on seventh transistor T7
  • the fourth transistor T4, the third transistor T3, the second transistor T2 and the first transistor T1 charge the first node N1 (that is, charge the first terminal of the capacitor Cst).
  • the potential of the second node N2 remains at Vdata, and at the same time, according to the characteristics of the third transistor T3, when the potential of the first node N1 (that is, the potential of the first end of the storage capacitor Cst) reaches Vdata+Vth, the second The three transistors T3 are turned off, and the charging process ends.
  • Vdata represents the voltage value of the data signal
  • Vth represents the threshold voltage of the third transistor T3.
  • the third transistor T3 is a P-type transistor, so the threshold voltage Vth here can be a negative value.
  • the second reset control signal RS2 can also be adjusted so that the seventh transistor T7 is turned off without affecting the subsequent light-emitting stage of the pixel circuit, which is not limited by the embodiments of the present disclosure.
  • circuit structure shown in Figure 8 and the signal timing shown in Figure 14 correspond to the data writing and compensation stage t2
  • circuit structure shown in Figure 7 and the signal timing shown in Figure 12 correspond to the data writing
  • the working principle is basically the same as that of the compensation stage t2 (the difference is only in the type of the seventh transistor T7 and the corresponding active level of the second reset control signal RS2 ), and the repetition is omitted here.
  • circuit structure shown in Figure 9 and the signal timing shown in Figure 13 correspond to the data writing and compensation phase t2
  • circuit structure shown in Figure 5 and the signal timing shown in Figure 13 correspond to the data writing
  • the working principle is basically the same as that of the compensation stage t2, and the repetitive parts will not be repeated here.
  • the circuit structure shown in Figure 10 and the signal timing shown in Figure 15 correspond to the data writing and compensation phase t2
  • the circuit structure shown in Figure 9 and the signal timing shown in Figure 13 correspond to the data writing
  • the working principle is basically the same as that of the compensation stage t2 (the difference is only in the type of the seventh transistor T7 and the corresponding active level of the second reset control signal RS2 ), and the repetition is omitted here.
  • the time interval may be greater than a predetermined time interval to pass the third
  • the gate potential of the transistor T3 is reset in advance to improve the hysteresis phenomenon of the third transistor and reduce high and low frequency flicker (Flicker) of the pixel circuit.
  • the second scanning signal SN2 is input, the compensation control circuit 300 is turned off, and the voltage of the control terminal 110 of the driving circuit 100 is maintained through the energy storage circuit 350 .
  • the holding period t3&t4 includes a first holding period t3 and a second holding period t4.
  • the P-type fourth transistor T4 is turned on by the low level of the first scan signal SN1;
  • the first transistor T1 is turned off by the high level of the first reset control signal RS1
  • the P-type seventh transistor T7 is turned off by the high level of the second reset control signal RS2
  • the N-type second transistor T2 is turned off by the second scan signal
  • the low level of SN2 is cut off
  • the P-type sixth transistor T6 is cut off by the high level of the second light emission control signal EM2
  • the P-type eighth transistor T8 is cut off by the high level of the transmission control signal TC
  • the P-type fifth transistor T6 is cut off by the high level of the transmission control signal TC.
  • the transistor T5 is turned off by the high level of the first light emitting control signal EM1. Therefore, in the first holding period t3, the fourth transistor T4 is turned on, and the data signal Vdata is continuously written into the second node N2, and the potential of the second node N2 is kept at Vdata; the third transistor T3 is turned off, and due to the storage capacitor Cst In nature, the potential of the first node N1 is maintained at Vdata+Vth, which is used for providing grayscale display data and compensating the threshold voltage of the third transistor T3 itself during the subsequent light-emitting phase.
  • the P-type fifth transistor T5 is turned on by the low level of the first light emission control signal EM1; at the same time, the P-type fourth transistor T4 is turned off by the high level of the first scan signal SN1, P The first transistor T1 of type N is turned off by the high level of the first reset control signal RS1, the seventh transistor T7 of P type is turned off by the high level of the second reset control signal RS2, and the second transistor T2 of N type is turned off by the second scan The low level of the signal SN2 is turned off, the P-type sixth transistor T6 is turned off by the high level of the second light emission control signal EM2 , and the P-type eighth transistor T8 is turned off by the high level of the transmission control signal TC.
  • the potential of the first node N1 is still kept at Vdata+Vth; the first power supply terminal VDD charges the second node N2 through the turned-on fifth transistor T5, The potential of the second node N2 changes from Vdata to the first power supply voltage VDD. Since the sixth transistor T6 is turned off at this stage, it is ready for the light emitting element LE to emit light in the next stage.
  • the P-type fourth transistor T4 is turned on by the low level of the first scan signal SN1;
  • the first transistor T1 is turned off by the high level of the first reset control signal RS1
  • the P-type seventh transistor T7 is turned off by the high level of the second reset control signal RS2
  • the N-type second transistor T2 is turned off by the second scan signal
  • the low level of SN2 is cut off
  • the P-type sixth transistor T6 is cut off by the high level of the second light emission control signal EM2
  • the P-type eighth transistor T8 is cut off by the high level of the transmission control signal TC
  • the P-type fifth transistor T6 is cut off by the high level of the transmission control signal TC.
  • the transistor T5 is turned off by the high level of the first light emitting control signal EM1. Therefore, in the first holding period t3, the fourth transistor T4 is turned on, and the data signal Vdata is continuously written into the second node N2, and the potential of the second node N2 is kept at Vdata; the third transistor T3 is turned off, and due to the storage capacitor Cst In nature, the potential of the first node N1 is maintained at Vdata+Vth, which is used for providing grayscale display data and compensating the threshold voltage of the third transistor T3 itself during the subsequent light-emitting phase.
  • the P-type sixth transistor T6 is turned on by the low level of the second light emission control signal EM2; at the same time, the P-type fourth transistor T4 is turned off by the high level of the first scanning signal SN1, P The first transistor T1 of type N is turned off by the high level of the first reset control signal RS1, the seventh transistor T7 of P type is turned off by the high level of the second reset control signal RS2, and the second transistor T2 of N type is turned off by the second scan The low level of the signal SN2 is turned off, the P-type fifth transistor T5 is turned off by the high level of the first light emission control signal EM1 , and the P-type eighth transistor T8 is turned off by the high level of the transmission control signal TC.
  • the potential of the first node N1 is still kept at Vdata+Vth; the third node N3 is connected to the fourth node N4 through the turned-on sixth transistor T6.
  • the fifth transistor T5 is turned off, so it is ready for the light emitting element LE in the next stage.
  • the P-type fourth transistor T4 is turned on by the low level of the first scanning signal SN1, and the N-type fourth transistor T4
  • the seven transistor T7 is turned on by the high level of the second reset control signal RS2; at the same time, the P-type first transistor T1 is turned off by the high level of the first reset control signal RS1, and the N-type second transistor T2 is turned on by the second scan
  • the low level of the signal SN2 is turned off
  • the P-type sixth transistor T6 is turned off by the high level of the second light emission control signal EM2
  • the P-type eighth transistor T8 is turned off by the high level of the transmission control signal TC
  • the P-type sixth transistor T6 is turned off by the high level of the transmission control signal TC.
  • the five transistor T5 is turned off by the high level of the first light emitting control signal EM1. Therefore, in the first holding period t3, the fourth transistor T4 is turned on, and the data signal Vdata is continuously written into the second node N2, and the potential of the second node N2 is kept at Vdata; the third transistor T3 is turned off, and due to the storage capacitor Cst nature, the potential of the first node N1 is kept at Vdata+Vth, which is used to provide grayscale display data and compensate the threshold voltage of the third transistor T3 itself during the subsequent light-emitting phase; in addition, the second reset voltage Vinit2 can still be It is transmitted to the fourth node N4 through the turned-on seventh transistor T7 to continuously reset the fourth node N4 (the first pole of the light emitting element LE).
  • the second reset control signal RS2 can also be adjusted to turn off the seventh transistor T7 without affecting the subsequent light-emitting stage of the pixel circuit, which is not limited by the embodiments of the present disclosure.
  • the P-type fifth transistor T5 is turned on by the low level of the first light emission control signal EM1; at the same time, the P-type fourth transistor T4 is turned off by the high level of the first scan signal SN1, P
  • the first N-type transistor T1 is turned off by the high level of the first reset control signal RS1
  • the N-type seventh transistor T7 is turned off by the low level of the second reset control signal RS2
  • the N-type second transistor T2 is turned off by the second scan
  • the low level of the signal SN2 is turned off
  • the P-type sixth transistor T6 is turned off by the high level of the second light emission control signal EM2
  • the P-type eighth transistor T8 is turned off by the high level of the transmission control signal TC.
  • the potential of the first node N1 is still kept at Vdata+Vth; the first power supply terminal VDD charges the second node N2 through the turned-on fifth transistor T5, The potential of the second node N2 changes from Vdata to the first power supply voltage VDD. Since the sixth transistor T6 is turned off at this stage, it is ready for the light emitting element LE to emit light in the next stage.
  • the working principle of the holding phase t3&t4 corresponding to the circuit structure shown in Figure 7 and the signal timing shown in Figure 12 is basically the same as the working principle of the holding phase t3&t4 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 12 The same, the repetition will not be repeated here.
  • the working principle of the holding phase t3&t4 corresponding to the circuit structure shown in Figure 8 and the signal timing shown in Figure 14 is basically the same as that of the holding phase t3&t4 corresponding to the circuit structure shown in Figure 6 and the signal timing shown in Figure 14 The same, the repetition will not be repeated here.
  • the working principle of the holding phase t3&t4 corresponding to the circuit structure shown in Figure 9 and the signal timing shown in Figure 13 is basically the same as the working principle of the holding phase t3&t4 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 13 The same, the repetition will not be repeated here.
  • the P-type fourth transistor T4 is turned on by the low level of the first scan signal SN1, and the N-type fourth transistor T4
  • the seven transistor T7 is turned on by the high level of the second reset control signal RS2; at the same time, the P-type first transistor T1 is turned off by the high level of the first reset control signal RS1, and the N-type second transistor T2 is turned on by the second scan
  • the low level of the signal SN2 is turned off
  • the P-type sixth transistor T6 is turned off by the high level of the second light emission control signal EM2
  • the P-type eighth transistor T8 is turned off by the high level of the transmission control signal TC
  • the P-type sixth transistor T6 is turned off by the high level of the transmission control signal TC.
  • the five transistor T5 is turned off by the high level of the first light emitting control signal EM1. Therefore, in the first holding period t3, the fourth transistor T4 is turned on, and the data signal Vdata is continuously written into the second node N2, and the potential of the second node N2 is kept at Vdata; the third transistor T3 is turned off, and due to the storage capacitor Cst nature, the potential of the first node N1 is kept at Vdata+Vth, which is used to provide grayscale display data and compensate the threshold voltage of the third transistor T3 itself during the subsequent light-emitting phase; in addition, the second reset voltage Vinit2 can still be It is transmitted to the fourth node N4 through the turned-on seventh transistor T7 to continuously reset the fourth node N4 (the first pole of the light emitting element LE).
  • the second reset control signal RS2 can also be adjusted to turn off the seventh transistor T7 without affecting the subsequent light-emitting stage of the pixel circuit, which is not limited by the embodiments of the present disclosure.
  • the P-type sixth transistor T6 is turned on by the low level of the second light emission control signal EM2; at the same time, the P-type fourth transistor T4 is turned off by the high level of the first scanning signal SN1, P
  • the first N-type transistor T1 is turned off by the high level of the first reset control signal RS1
  • the N-type seventh transistor T7 is turned off by the low level of the second reset control signal RS2
  • the N-type second transistor T2 is turned off by the second scan
  • the low level of the signal SN2 is turned off
  • the P-type fifth transistor T5 is turned off by the high level of the first light emission control signal EM1
  • the P-type eighth transistor T8 is turned off by the high level of the transmission control signal TC.
  • the potential of the first node N1 is still kept at Vdata+Vth; the third node N3 is connected to the fourth node N4 through the turned-on sixth transistor T6.
  • the fifth transistor T5 is turned off, so it is ready for the light emitting element LE in the next stage.
  • the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are input, the first light-emitting control circuit 400, the second light-emitting control circuit 500 and the driving circuit 100 are turned on, and the first power supply is turned on by the first light-emitting control circuit 400
  • the voltage VDD is applied to the first terminal 120 of the driving circuit 100 so that the driving circuit 100 generates a driving current according to the voltage of the control terminal 110 of the driving circuit 100, and the driving current is applied to the light emitting element 900 through the second light emission control circuit 500 so that the light emitting element 900 glow.
  • the P-type fifth transistor T5 is turned on by the low level of the first light-emitting control signal EM1, and the P-type sixth transistor T5
  • the transistor T6 is turned on by the low level of the second light emission control signal EM2; at the same time, the P-type first transistor T1 is turned off by the high level of the first reset control signal RS1, and the P-type seventh transistor T7 is controlled by the second reset
  • the high level of the signal RS2 is turned off, the N-type second transistor T2 is turned off by the low level of the second scanning signal SN2, the P-type eighth transistor T8 is turned off by the high level of the transmission control signal TC, and the P-type fourth transistor T8 is turned off by the high level of the transmission control signal TC.
  • the transistor T4 is turned on by the low level of the first scan signal SN1.
  • the potential of the first node N1 is Vdata+Vth
  • the potential of the second node N2 is VDD, so at this stage, the third transistor T3 is also kept turned on.
  • the driving current generated by the third transistor T3 can be obtained according to the following formula:
  • ⁇ represents the carrier mobility
  • Cox represents the gate capacitance per unit area
  • W represents the width of the third transistor channel
  • L represents the length of the third transistor channel
  • Vgs represents the gate-source voltage difference of the third transistor
  • Vth represents the threshold voltage of the third transistor
  • VDD represents the first power supply voltage provided by the first power supply terminal VDD.
  • the driving current I LE flowing through the light-emitting element OLED is no longer related to the threshold voltage Vth of the third transistor T3, but only related to the data signal Vdata that controls the gray scale of light emitted by the pixel circuit, so that Realizing the compensation of the pixel circuit solves the problem of the threshold voltage drift of the third transistor T3 due to the process and long-term operation, and eliminates its influence on the driving current, so that the display effect can be improved.
  • the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 13 is basically the same as the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 12 The same, the repetition will not be repeated here.
  • the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 6 and the signal timing shown in Figure 14 is basically the same as the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 12 The same, the repetition will not be repeated here.
  • the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 7 and the signal timing shown in Figure 12 is basically the same as the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 12 The same, the repetition will not be repeated here.
  • the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 8 and the signal timing shown in Figure 14 is basically the same as the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 12 The same, the repetition will not be repeated here.
  • the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 9 and the signal timing shown in Figure 13 is basically the same as the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 12 The same, the repetition will not be repeated here.
  • the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 10 and the signal timing shown in Figure 15 is basically the same as the working principle of the light-emitting stage t5 corresponding to the circuit structure shown in Figure 5 and the signal timing shown in Figure 12 The same, the repetition will not be repeated here.
  • FIGS. 12-15 are schematic.
  • the signal timing during operation can be determined according to actual needs, and this disclosure does not limit it. .
  • pulse width modulation (PWM) reset may also be performed on the fourth node N4 (the first pole of the light emitting element, such as the anode).
  • PWM pulse width modulation
  • the low gray scale can be greatly improved by increasing the frequency of Anode (anode) refresh. , Low-frequency flicker, so that the human eye can better watch the effect.
  • the technical effect of the driving method of the pixel circuit provided by the embodiments of the present disclosure can refer to the corresponding description about the pixel circuit 10 in the above embodiments, and details are not repeated here.
  • At least some embodiments of the present disclosure further provide a display panel, which includes a plurality of pixel units arranged in an array, and each pixel unit includes the pixel circuit provided by any embodiment of the present disclosure.
  • Fig. 17 is a schematic block diagram of a display panel provided by at least some embodiments of the present disclosure. As shown in FIG. 17 , the display panel 11 is disposed in the display device 1 and is electrically connected to the gate driver 12 , the timing controller 13 and the data driver 14 .
  • the display panel 11 includes a pixel unit P defined by intersections of a plurality of gate lines GL and a plurality of data lines DL; a gate driver 12 is used to drive a plurality of gate lines GL; a data driver 14 is used to drive a plurality of data lines DL;
  • the controller 13 is used for processing the image data RGB input from the outside of the display device 1, providing the processed image data RGB to the data driver 14, and outputting the scan control signal GCS and the data control signal DCS to the gate driver 12 and the data driver 14, so as to control
  • the gate driver 12 and the data driver 14 perform control.
  • the display panel 11 includes a plurality of pixel units P arranged in an array, and the pixel units P include the pixel circuit 10 and the light emitting element 900 provided in any one of the above-mentioned embodiments.
  • the display panel 11 further includes a plurality of gate lines GL and a plurality of data lines DL.
  • the plurality of gate lines are correspondingly connected to the pixel circuits 10 of each row of pixel units to provide various control signals, such as the first scanning signal SN1, the second scanning signal SN2, the first light emission control signal EM1, the second light emission control signal EM2, The first reset control signal RS1, the second reset control signal RS2 and the transfer control signal TC.
  • the same gate line can be used to connect to the corresponding control signal terminal in each row of pixel units 10 to provide the same signal, thereby reducing the number of gate lines and saving the layout of the display panel space, which is conducive to the development of high-resolution display panels.
  • each pixel unit P can be connected to five gate lines GL (refer to the signal timing shown in Figures 12-15, the first scan signal SN1, the second scan signal SN2, the first light emission control signal Among the second light emission control signal EM2, the first reset control signal RS1, the second reset control signal RS2 and the transmission control signal TC, there are two pairs of control signals that can respectively share the same gate line), one data line DL, for providing the first A first power supply voltage line for the power supply voltage VDD, a second power supply voltage line for supplying the second power supply voltage VSS, a first initialization voltage line for supplying the first initialization voltage Vinit1, and a first initialization voltage line for supplying the second initialization voltage Vinit2. Two initialization voltage lines.
  • the first power supply voltage line or the second voltage line can be replaced by a corresponding plate-shaped or mesh-shaped common electrode (such as a common anode or a common cathode).
  • a corresponding plate-shaped or mesh-shaped common electrode such as a common anode or a common cathode.
  • the data line DL corresponding to each column of pixel units is connected to the data writing circuit 200 in the pixel circuit 10 of the column of pixel units P to provide data signals.
  • part of the control signals can be multiplexed to pixel units in different rows, thereby simplifying the layout space around the display panel and facilitating the development of high-resolution display panels.
  • the first light emission control signal EM1 used to control the first light emission control circuit 400 in the pixel circuit 10 of the current row of pixel units can also be used to control the first light emission control signal EM1 in the pixel circuit 10 of the previous row of pixel units.
  • the second light emission control circuit 500 that is, the second light emission control signal EM2 in the pixel circuit 10 of the pixel unit in the previous row;
  • the second light emission control signal EM2 can also be used to control the first light emission control circuit 400 in the pixel circuit 10 of the next row of pixel units, that is, the first light emission control signal EM1 in the pixel circuit 10 of the next row of pixel units.
  • the embodiments of the present disclosure include but are not limited thereto.
  • the gate driver 12 supplies a plurality of control signals to a plurality of gate lines GL according to a plurality of scanning control signals GCS from the timing controller 13 .
  • the multiple control signals include, for example, a first scan signal SN1, a second scan signal SN2, a first light emission control signal EM1, a second light emission control signal EM2, a first reset control signal RS1, a second reset control signal RS2, and a transmission control signal.
  • TC transmission control signal
  • the data driver 14 converts digital image data RGB input from the timing controller 13 into data signals according to a plurality of data control signals DCS from the timing controller 13 using a reference gamma voltage.
  • the data driver 14 supplies converted data signals to a plurality of data lines DL.
  • the timing controller 13 processes externally input image data RGB to match the size and resolution of the display panel 11 , and then supplies the processed image data to the data driver 14 .
  • the timing controller 13 generates a plurality of scanning control signals GCS and a plurality of data control signals DCS using synchronous signals (such as dot clock DCLK, data enable signal DE, horizontal synchronous signal Hsync, and vertical synchronous signal Vsync) input from the display device.
  • the timing controller 13 provides the generated scan control signal GCS and data control signal DCS to the gate driver 12 and the data driver 14 respectively for controlling the gate driver 12 and the data driver 14 .
  • the data driver 14 can be connected with a plurality of data lines DL to provide a data signal Vdata; meanwhile, it can also be connected with a plurality of first power supply voltage lines, a plurality of second power supply voltage lines, a plurality of first initialization voltage lines and a plurality of first initialization voltage lines.
  • the two second initialization voltage lines are connected to provide the first power voltage VDD, the second power voltage VSS, the first initialization voltage Vinit1 and the second initialization voltage Vinit2 respectively.
  • the gate driver 12 and the data driver 14 may be implemented as semiconductor chips.
  • the gate driver 12 can also be implemented as a gate driver circuit and directly integrated on the display panel to form a GOA (Gate driver On Array).
  • the display device 1 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may be existing conventional components, and will not be described in detail here.
  • the display panel 11 provided in this embodiment can implement progressive scanning. It should be noted that, during the progressive scanning process, each control signal (first scanning signal SN1, second scanning signal SN2, first light emission control signal EM1, second light emission control signal EM2, first reset control signal RS1, second light emission control signal Both the reset control signal RS2 and the transmission control signal TC) are applied row by row according to the timing signal; the driving process of each row of pixel units can refer to the relevant description of the aforementioned pixel circuit driving method, and will not be repeated here.
  • the display panel 11 provided in this embodiment can be applied to any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.
  • a display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.

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Abstract

一种像素电路及其驱动方法、显示面板。该像素电路包括驱动电路、数据写入电路、补偿控制电路、储能电路、第一发光控制电路、第二发光控制电路、第一初始化电路、第二初始化电路和传输电路。驱动电路包括控制端、第一端和第二端，且被配置为控制流经第一端和第二端的用于驱动发光元件发光的驱动电流；通过第一初始化电路、传输电路、第二初始化电路与第二发光控制电路或补偿控制电路配合，可以同时对驱动电路的控制端、驱动电路的第二端以及发光元件的第一极进行复位。

Description

像素电路及其驱动方法、显示面板
本申请要求于2021年7月30日递交的PCT专利申请PCT/CN2021/109890及2021年8月5日递交的中国专利申请第202110898683.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示面板。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板具有薄、轻、宽视角、主动发光、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高及可柔性显示等优点，在手机、平板电脑、数码相机等显示领域的应用越来越广泛。
发明内容
本公开至少一些实施例提供一种像素电路，包括：驱动电路、数据写入电路、补偿控制电路、储能电路、第一发光控制电路、第二发光控制电路、第一初始化电路、第二初始化电路和传输电路；其中，所述驱动电路包括控制端、第一端和第二端，且被配置为控制流经所述第一端和所述第二端的用于驱动发光元件发光的驱动电流；所述数据写入电路被配置为在第一扫描信号的控制下将数据信号写入所述驱动电路的第一端；所述补偿控制电路被配置为在第二扫描信号的控制下对所述驱动电路进行补偿；所述储能电路被配置为存储所述驱动电路的控制端的电压；所述第一发光控制电路被配置为在第一发光控制信号的控制下将第一电源端的第一电源电压施加至所述驱动电路的第一端；所述第二发光控制电路被配置为在第二发光控制信号的控制下将所述驱动电流施加至所述发光元件的第一极；所述第一初始化电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至所述驱动电路的控制端；所述传输电路被配置为在传输控制信号的控制下传输所述第一初始化电压；所述第二初始化电路被配置为在第二复位控制信号的控制下将第二初始化电压施加至所述发光元件的第一极；其中，所述第二发光控制电路还被配置为在所述第二发光控制信号的控制下将所述发光元件的第一极的所述第二初始化电压传输至所述驱动电路的第二端；或者，所述第一初始化电路和所述传输电路共同被配置为将所述第一初始化电压施加至所述驱动电路的控制端，所述补偿控制电路还被配置为在所述第二扫描信号的控制下将所述驱动电路的控制端的所述第一初始化电压传输至所述驱动电路的第二端；或者，所述第一初始化电路和所述传输电路共同被配置为将所述第一初始化电压施加至所述驱动电路的第二端，所述补偿控制电路还被配置为在所述第二扫描信号的控制下将所述驱动电路的 第二端的所述第一初始化电压传输至所述驱动电路的控制端。
例如，在本公开一些实施例提供的像素电路中，所述驱动电路包括第三晶体管；所述第三晶体管的栅极作为所述驱动电路的控制端，所述第三晶体管的第一极作为所述驱动电路的第一端，所述第三晶体管的第二极作为所述驱动电路的第二端。
例如，在本公开一些实施例提供的像素电路中，所述数据写入电路包括第四晶体管；所述第四晶体管的栅极和第一扫描信号端连接以接收所述第一扫描信号，所述第四晶体管的第一极和数据信号端连接以接收所述数据信号，所述第四晶体管的第二极和所述驱动电路的第一端连接。
例如，在本公开一些实施例提供的像素电路中，所述补偿控制电路包括第二晶体管，所述储能电路包括存储电容，所述第二晶体管的栅极和第二扫描信号端连接以接收所述第二扫描信号，所述第二晶体管的第一极与所述驱动电路的第二端连接，所述第二晶体管的第二极与所述驱动电路的控制端连接，所述存储电容的第一端与所述驱动电路的控制端耦接，所述存储电容的第二端与所述第一电源端耦接。
例如，在本公开一些实施例提供的像素电路中，所述第二晶体管为N型氧化物薄膜晶体管，所述N型氧化物薄膜晶体管包括依次层叠且相互绝缘的第一金属层、有源层和第二金属层，在所述有源层的延伸方向上，所述第二金属层的宽度不大于所述第一金属层的宽度；所述第二金属层和所述第二扫描信号端连接以作为所述第二晶体管的栅极，或者，所述第二金属层和所述第一金属层均与所述第二扫描信号端连接以同时作为所述第二晶体管的栅极；所述有源层包括被所述第一金属层覆盖的沟道区，所述N型氧化物薄膜晶体管的沟道区的宽长比的取值范围为[1/2,7/8]。
例如，在本公开一些实施例提供的像素电路中，所述第一发光控制电路包括第五晶体管，所述第五晶体管的栅极和第一发光控制信号端连接以接收所述第一发光控制信号，所述第五晶体管的第一极和所述第一电源端连接以接收所述第一电源电压，所述第五晶体管的第二极和所述驱动电路的第一端连接。
例如，在本公开一些实施例提供的像素电路中，所述第二发光控制电路包括第六晶体管，所述第六晶体管的栅极和第二发光控制信号端连接以接收所述第二发光控制信号，所述第六晶体管的第一极和所述驱动电路的第二端连接，所述第六晶体管的第二极和所述发光元件的第一极连接。
例如，在本公开一些实施例提供的像素电路中，所述第二初始化电路包括第七晶体管，所述第七晶体管的栅极和第二复位控制信号端连接以接收所述第二复位控制信号，所述第七晶体管的第一极和第二初始化电压端连接以接收所述第二初始化电压，所述第七晶体管的第二极和所述发光元件的第一极连接。
例如，在本公开一些实施例提供的像素电路中，所述第一初始化电路包括第一晶体管，所述传输电路包括第八晶体管，所述第一晶体管的栅极和第一复位控制信号端连接以接收所述第一复位控制信号，所述第一晶体管的第一极和第一初始化电压端连接以接收所述第 一初始化电压，所述第一晶体管的第二极和所述第八晶体管的第一极连接，所述第八晶体管的栅极和所述传输控制信号端连接以接收所述传输控制信号，所述第八晶体管的第二极和所述驱动电路的控制端连接。
例如，在本公开一些实施例提供的像素电路中，所述第二晶体管和所述第七晶体管均为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；所述第二复位控制信号与所述第一发光控制信号为同一控制信号，所述传输控制信号与所述第二发光控制信号为同一控制信号。
例如，在本公开一些实施例提供的像素电路中，所述第二晶体管为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；所述第二复位控制信号与所述第一复位控制信号为同一控制信号，所述传输控制信号与所述第一发光控制信号或者所述第二发光控制信号为同一控制信号。
例如，在本公开一些实施例提供的像素电路中，所述第一初始化电路包括第一晶体管，所述传输电路包括第八晶体管。
所述第一晶体管的栅极和第一复位控制信号端连接以接收所述第一复位控制信号，所述第一晶体管的第一极和所述第二晶体管的第二极连接，所述第一晶体管的第二极和所述驱动电路的控制端连接，所述第八晶体管的栅极和所述传输控制信号端连接以接收所述传输控制信号，所述第八晶体管的第一极和第一初始化电压端连接以接收所述第一初始化电压，所述第八晶体管的第二极和所述第一晶体管的第一极连接，所述第二晶体管的第二极通过所述第一晶体管与所述驱动电路的控制端连接。
例如，在本公开一些实施例提供的像素电路中，所述第二晶体管和所述第七晶体管均为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；所述第二复位控制信号与所述第一发光控制信号为同一控制信号，所述传输控制信号与所述第二发光控制信号为同一控制信号。
例如，在本公开一些实施例提供的像素电路中，所述第二晶体管为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；所述第二复位控制信号与所述第一复位控制信号为同一控制信号，所述传输控制信号与所述第二发光控制信号为同一控制信号。
例如，在本公开一些实施例提供的像素电路中，所述第一初始化电路包括第一晶体管，所述传输电路包括第八晶体管，所述第一晶体管的栅极和第一复位控制信号端连接以接收所述第一复位控制信号，所述第一晶体管的第一极和第一初始化电压端连接以接收所述第一初始化电压，所述第一晶体管的第二极和所述第八晶体管的第一极连接，所述第八晶体管的栅极和所述传输控制信号端连接以接收所述传输控制信号，所述第八晶体管的第二极和所述驱动电路的第二端连接。
例如，在本公开一些实施例提供的像素电路中，所述第二晶体管和所述第七晶体管均为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；所述第二复位控制信号与所述第二发光控制信号为同一控制信号，所述传输控制信号与所述第一发光控制信号为同一控制信号。
例如，在本公开一些实施例提供的像素电路中，所述第二晶体管为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；所述第二复位控制信号与所述第一扫描信号为同一控制信号，所述传输控制信号与所述第一发光控制信号为同一控制信号。
本公开至少一些实施例还提供一种显示面板，包括：阵列排布的多个像素单元；其中，所述多个像素单元中的每个像素单元包括本公开任一实施例提供的像素电路。
本公开至少一些实施例还提供一种对应于本公开任一实施例提供的像素电路的驱动方法，包括：复位阶段；其中，在所述复位阶段，输入所述第二发光控制信号、所述第一复位控制信号、所述第二复位控制信号和所述传输控制信号，开启所述第二发光控制电路、所述第一初始化电路、所述第二初始化电路和所述传输电路，通过所述第一初始化电路和所述传输电路将所述第一初始化电压施加至所述驱动电路的控制端以对所述驱动电路的控制端进行复位，通过所述第二初始化电路将所述第二初始化电压施加至所述发光元件的第一极以对所述发光元件进行复位，通过所述第二初始化电路和所述第二发光控制电路将所述第二初始化电压施加至所述驱动电路的第二端以对所述驱动电路的第二端进行复位；或者，输入所述第二扫描信号、所述第一复位控制信号、所述第二复位控制信号和所述传输控制信号，开启所述补偿控制电路、所述第一初始化电路、所述第二初始化电路和所述传输电路，通过所述第一初始化电路和所述传输电路将所述第一初始化电压施加至所述驱动电路的第二端以对所述驱动电路的第二端进行复位，通过所述第一初始化电路、所述传输电路和所述补偿控制电路将所述第一初始化电压施加至所述驱动电路的控制端以对所述驱动电路的控制端进行复位，通过所述第二初始化电路将所述第二初始化电压施加至所述发光元件的第一极以对所述发光元件进行复位；或者，输入所述第二扫描信号、所述第一复 位控制信号、所述第二复位控制信号和所述传输控制信号，开启所述补偿控制电路、所述第一初始化电路、所述第二初始化电路和所述传输电路，通过所述第一初始化电路和所述传输电路将所述第一初始化电压施加至所述驱动电路的控制端以对所述驱动电路的控制端进行复位，通过所述第一初始化电路、所述传输电路和所述补偿控制电路将所述第一初始化电压施加至所述驱动电路的第二端以对所述驱动电路的第二端进行复位，通过所述第二初始化电路将所述第二初始化电压施加至所述发光元件的第一极以对所述发光元件进行复位。
例如，本公开一些实施例提供的驱动方法，还包括：数据写入和补偿阶段、保持阶段和发光阶段；其中，在所述数据写入和补偿阶段，输入所述第一扫描信号和所述第二扫描信号，开启所述数据写入电路、所述驱动电路和所述补偿控制电路，通过所述数据写入电路将所述数据信号写入所述补偿控制电路，通过所述补偿控制电路对所述驱动电路进行补偿；在所述保持阶段，输入所述第二扫描信号，关闭所述补偿控制电路，通过所述储能电路保持所述驱动电路的控制端的电压；在所述发光阶段，输入所述第一发光控制信号和所述第二发光控制信号，开启所述第一发光控制电路、所述第二发光控制电路和所述驱动电路，通过所述第一发光控制电路将所述第一电源电压施加所述驱动电路的第一端以使所述驱动电路根据所述驱动电路的控制端的电压产生所述驱动电流，通过所述第二发光控制电路将所述驱动电流施加至所述发光元件以使所述发光元件发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种7T1C像素电路的示意图；
图1B为图1A所示的7T1C像素电路的一种驱动方法的信号时序图；
图2为本公开至少一些实施例提供的一种像素电路的示意框图；
图3为本公开至少一些实施例提供的另一种像素电路的示意框图；
图4为本公开至少一些实施例提供的又一种像素电路的示意框图；
图5为图2所示的像素电路的一种具体实现示例的电路结构示意图；
图6为图2所示的像素电路的另一种具体实现示例的电路结构示意图；
图7为图3所示的像素电路的一种具体实现示例的电路结构示意图；
图8为图3所示的像素电路的另一种具体实现示例的电路结构示意图；
图9为图4所示的像素电路的一种具体实现示例的电路结构示意图；
图10为图4所示的像素电路的另一种具体实现示例的电路结构示意图；
图11A为本公开至少一些实施例提供的一种氧化物薄膜晶体管的局部平面结构示意图；
图11B为本公开至少一些实施例提供的一种氧化物薄膜晶体管的局部截面结构示意图；
图12-15为本公开至少一些实施例提供的各种像素电路的驱动方法的信号时序图；
图16为本公开至少一些实施例提供的像素电路的驱动方法中对第四节点进行PWM复位的效果示意图；以及
图17为本公开至少一些实施例提供的一种显示面板的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部(元)件的详细说明。当本公开实施例的任一部(元)件在一个以上的附图中出现时，该部(元)件在每个附图中由相同或类似的参考标号表示。
OLED显示面板中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。其中，AMOLED在每一个像素的像素电路(也称为“像素驱动电路”)中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。因此，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
AMOLED显示面板中使用的基础像素电路通常为2T1C像素电路，即利用两个TFT(Thin-film transistor，薄膜晶体管)和一个存储电容C来实现驱动OLED发光的基本功能。需要注意的是，实际使用的像素电路不限于上述2T1C像素电路，还可以是其他结构的像素电路，例如4T1C、4T2C、6T1C或7T1C的像素电路等。
图1A为一种7T1C像素电路的示意图。如图1A所示，该7T1C像素电路包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管 T6、第七晶体管T7和电容C。驱动晶体管T3的栅极连接第一节点N1，驱动晶体管T3的第一极连接第二节点N2，驱动晶体管T3的第二极连接第三节点N3；第四晶体管T4的第一极连接数据信号端Da，第四晶体管T4的第二极连接第二节点N2，第四晶体管T4的栅极连接栅极驱动信号端G2；第五晶体管T5的第一极连接第一电源端VDD，第五晶体管T5的第二极连接第二节点N2，第五晶体管T5的栅极连接使能信号端EM；第二晶体管T2的第一极连接第一节点N1，第二晶体管T2的第二极连接第三节点N3，第二晶体管T2的栅极连接栅极驱动信号端G1；第六晶体管T6的第一极连接第三节点N3，第六晶体管T6的第二极连接第四节点N4，第六晶体管T6的栅极连接使能信号端EM；第七晶体管T7的第一极连接第四节点N4，第七晶体管T7的第二极连接第二初始信号端Vinit2，第七晶体管T7的栅极连接第二复位信号端Re2；第一晶体管T1的第一极连接第一节点N1，第一晶体管T1的第二极连接第一初始信号端Vinit1，第一晶体管T1的栅极连接第一复位信号端Re1，电容C连接于第一电源端VDD和第一节点N1之间。该像素电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第四节点N4和第二电源端VSS之间。第一晶体管T1和第二晶体管T2可以为N型晶体管，例如，第一晶体管T1和第二晶体管T2可以为N型金属氧化物晶体管，N型金属氧化物晶体管具有较小的漏电流，从而可以避免发光阶段，节点N1通过第一晶体管T1和第二晶体管T2漏电。同时，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型晶体管，例如，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，低温多晶体硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。第一初始信号端Vinit1和第二初始信号端Vinit2可以根据实际情况输出相同或不同电压信号。
图1B为图1A所示的7T1C像素电路的一种驱动方法的信号时序图。其中，G1表示栅极驱动信号端G1的时序，G2表示栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序。该像素电路的驱动方法可以包括三个阶段：复位阶段t01、数据写入和补偿阶段t02、发光阶段t03。在复位阶段t01，第一复位信号端Re1输入高电平信号，第一晶体管T1导通，第一初始信号端Vinit1向第一节点N1输入第一初始信号Vinit1，以对第一节点N1(即驱动晶体管的栅极)进行复位。在数据写入和补偿阶段t2，栅极驱动信号端G2输入低电平信号，栅极驱动信号端G1输入高电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输入数据信号Vdata，以对第一节点N1进行充电，直到第一节点N1的电压变为Vdata+Vth为止，第一节点N1的电压Vdata+Vth通过存储电容C进行存储，其中Vdata为数据信号的电压(即数据电压)，Vth为驱动晶体管T3的阈值电压。在发光阶段t03，使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下产生驱动电流；驱动晶体管产生的驱动电流可以根据以下公式得出：
I＝0.5μCox*(W/L)*(Vgs-Vth) 2
＝0.5μCox*(W/L)*((Vdata+Vth-VDD)-Vth) 2
＝0.5μCox*(W/L)*(Vdata-VDD) 2
其中，μ表示载流子迁移率，Cox表示单位面积栅极电容量，W表示驱动晶体管沟道的宽度，L表示驱动晶体管沟道的长度，Vgs表示驱动晶体管栅源电压差，Vth表示驱动晶体管的阈值电压，VDD表示第一电源端VDD提供的第一电源电压。从上述公式可以看出，流经发光元件OLED的驱动电流I LE不再与驱动晶体管T3的阈值电压Vth有关，而只与控制该像素电路发光的灰度的数据信号Vdata有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管T3由于工艺制程及长时间的操作使用造成的阈值电压漂移的问题，消除其对驱动电流的影响，从而可以改善显示效果。
在上述像素电路中，在第一节点N1、第二节点N2和第三节点N3处均存在寄生电容；然而，上述驱动方法在复位阶段仅对第一节点N1进行复位，而不对第二节点N2和第三节点N3进行复位，不利于消除迟滞影响及改善残像现象。
本公开至少一些实施例提供一种像素电路。该像素电路包括驱动电路、数据写入电路、补偿控制电路、第一发光控制电路、第二发光控制电路、第一初始化电路、第二初始化电路和传输电路。驱动电路包括控制端、第一端和第二端，且被配置为控制流经第一端和第二端的用于驱动发光元件发光的驱动电流；数据写入电路被配置为在第一扫描信号的控制下将数据信号写入驱动电路的第一端；补偿控制电路被配置为在第二扫描信号的控制下对驱动电路进行补偿；储能电路被配置为存储驱动电路的控制端的电压；第一发光控制电路被配置为在第一发光控制信号的控制下将第一电源电压施加至驱动电路的第一端；第二发光控制电路被配置为在第二发光控制信号的控制下将驱动电流施加至所述发光元件的第一极；第一初始化电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至驱动电路的控制端；传输电路被配置为在传输控制信号的控制下传输第一初始化电压；第二初始化电路被配置为在第二复位控制信号的控制下将第二初始化电压施加至发光元件的第一极。第二发光控制电路还被配置为在第二发光控制信号的控制下将发光元件的第一极的第二初始化电压传输至驱动电路的第二端；或者，第一初始化电路和传输电路共同被配置为将第一初始化电压施加至驱动电路的控制端，补偿控制电路还被配置为在第二扫描信号的控制下将驱动电路的控制端的第一初始化电压传输至驱动电路的第二端；或者，第一初始化电路和传输电路共同被配置为将第一初始化电压施加至驱动电路的第二端，补偿控制电路还被配置为在第二扫描信号的控制下将驱动电路的第二端的第一初始化电压传输至驱动电路的控制端。
本公开的一些实施例还提供对应于上述像素电路的驱动方法、显示面板。
本公开的实施例提供的像素电路及其驱动方法、显示面板，在每次切换画面时，可以分别对驱动电路的控制端和第二端进行复位操作，使驱动电路的控制端和第二端每次显示画面时分别处于同样的偏压状态(相对于不同的画面)下，从而可以消除迟滞影响，改善残像现象，降低屏幕闪烁(Flicker)风险，提高屏幕质量。
下面结合附图对本公开的一些实施例及其示例进行详细说明。
图2为本公开至少一些实施例提供的一种像素电路的示意框图。例如，像素电路10可以用于AMOLED显示面板的像素单元中。如图2所示，像素电路10包括驱动电路100、数据写入电路200、补偿控制电路300、储能电路350、第一发光控制电路400、第二发光控制电路500、第一初始化电路600、第二初始化电路700和传输电路800。
例如，驱动电路100包括控制端110、第一端120和第二端130，且被配置为控制流经第一端120和第二端130的用于驱动发光元件900发光的驱动电流。例如，如图2所示，驱动电路100的控制端110和第一节点N1连接，驱动电路100的第一端120和第二节点N2连接，驱动电路100的第二端130和第三节点N3连接。例如，在一些示例中，在发光阶段，驱动电路100可以向发光元件900提供驱动电流以驱动发光元件900进行发光，且可以根据需要显示的灰阶(不同的灰阶对应于不同的数据信号)提供相应的驱动电流发光。例如，发光元件900可以采用有机发光二极管(OLED)、迷你发光二极管(Mini LED)、微发光二极管(Micro LED)、量子点发光二极管(QLED)、无机发光二极管等，本公开的实施例包括但不限于此。
例如，数据写入电路200被配置为在第一扫描信号SN1的控制下将数据信号Vdata写入驱动电路100的第一端120。例如，如图2所示，数据写入电路200与第一扫描信号端SN1(提供第一扫描信号)、数据信号端DATA(提供数据信号Vdata)以及第二节点N2连接。例如，在一些示例中，在数据写入和补偿阶段，数据写入电路200响应于第一扫描信号SN1而导通，从而可以将数据信号端DATA提供的数据信号Vdata写入驱动电路100的第一端120。
例如，补偿控制电路300被配置为在第二扫描信号SN2的控制下对驱动电路100进行补偿。例如，如图2所示，补偿控制电路300与第二扫描信号端SN2(提供第一扫描信号)、驱动电路100的控制端110(第一节点N1)和第二端130(第三节点N3)连接。例如，在一些示例中，在数据写入和补偿阶段，补偿控制电路300响应于第二扫描信号SN2而导通，将驱动电路100的控制端110和第二端130电连接，从而使数据信号Vdata以及驱动电路100的阈值电压Vth的等信息可以写入驱动电路100的控制端110，并由储能电路350存储，由此实现对驱动电路100的阈值电压补偿。
例如，储能电路350被配置为存储所述驱动电路100的控制端110的电压。例如，如图2所示，储能电路350与驱动电路100的控制端110(第一节点N1)和第一电源端VDD连接。例如，在一些示例中，储能电路350包括存储电容；在数据写入和补偿阶段，该存储电容可以存储补偿电路300写入驱动电路100的控制端110的包括数据信号Vdata以及阈值电压Vth等信息的电压，进而在发光阶段可以利用存储的包括数据信号Vdata以及阈值电压Vth等信息的电压对驱动电路100进行控制，使得驱动电路100在得到补偿的情况下根据数据信号Vdata产生驱动发光元件700发光的驱动电流。例如，第一发光控制电路400被配置为在第一发光控制信号EM1的控制下将第一电源电压VDD施加至驱动电路100的 第一端120。例如，如图2所示，第一发光控制电路400与第一发光控制信号端EM1(提供第一发光控制信号)、第一电源端VDD(提供第一电源电压)以及驱动电路100的第一端120(第二节点N2)连接。例如，在一些示例中，在发光阶段，第一发光控制电路400响应于第一发光控制信号EM1而导通，从而可以将第一电源电压VDD施加至驱动电路100的第一端120，在驱动电路100导通时，驱动电路100可以将该第一电源电压VDD施加至发光元件900以驱动发光元件发光。例如，第一电源电压VDD可以是驱动电压，例如高电压。
例如，第二发光控制电路500被配置为在第二发光控制信号EM2的控制下将驱动电流施加至发光元件900的第一极。例如，如图2所示，第二发光控制电路500与第二发光控制信号端EM2(提供第二发光控制信号)、第三节点N3以及第四节点N4连接，发光元件900的第一极(例如，阳极)与第四节点N4连接，发光元件的第二极(例如，阴极)与第二电源电压端VSS(提供第二电源电压)连接。例如，第二电源电压VSS为低电压(例如，低于第一电源电压)，例如接地电压等。例如，在一些示例中，在发光阶段，第二发光控制电路500响应于第二发光控制信号EM2而导通，从而驱动电路100可以通过第二发光控制电路500将驱动电流施加至发光元件900以使其发光。
例如，第一初始化电路600被配置为在第一复位控制信号RS1的控制下将第一初始化电压Vinit1施加至驱动电路100的控制端110，传输电路800被配置为在传输控制信号TC的控制下传输第一初始化电压Vinit1。例如，如图2所示，第一初始化电路600与第一复位控制端RS1(提供第一复位控制信号)、第一初始化电压端Vinit1(提供第一初始化电压)以及第五节点N5连接，传输电路800与传输控制信号端TC(提供传输控制信号)、第五节点N5以及驱动电路100的控制端110(第一节点N1)连接。例如，在一些示例中，在复位阶段，第一初始化电路600响应于第一复位控制信号RS1而导通，传输电路800响应于传输控制信号TC而导通，从而可以通过第一初始化电路600和传输电路800将第一初始化电压Vinit1施加至第一节点N1，对驱动电路100的控制端110进行复位操作，以消除之前的发光阶段对驱动电路100的控制端110的影响。
例如，第二初始化电路700被配置为在第二复位控制信号RS2的控制下将第二初始化电压Vinit2施加至发光元件900的第一极。例如，如图2所示，第二初始化电路700与第二复位控制信号端RS2(提供第二复位控制信号)、第二初始化电压端Vinit2(提供第二初始化电压)以及第四节点N4连接。例如，在一些示例中，在复位阶段，第二初始化电路700响应于第二复位控制信号RS2而导通，从而可以将第二初始化电压Vinit2施加至第四节点N4，对发光元件900的第一极进行复位操作，以消除之前的发光阶段对发光元件900的第一极的影响。
例如，在一些实施例中，在图2所示的像素电路10中，第二发光控制电路500还被配置为在第二发光控制信号EM2的控制下将发光元件900的第一极(第四节点N4)的第二初始化电压Vinit2传输至发光元件900的第二端(第三节点N3)。例如，在一些示例中， 在复位阶段，第二初始化电路700响应于第二复位控制信号RS2而导通，从而可以将第二初始化电压Vinit2施加至第四节点N4；同时，第二发光控制电路500响应于第二发光控制信号EM2而导通，从而可以将第四节点N4处的第二初始化电压Vinit2传输至第三节点N3，对驱动电路100的第二端130进行复位操作，以消除之前的发光阶段对驱动电路100的第二端130的影响。
例如，在另一些实施例中，在图2所示的像素电路10中，第一初始化电路600和传输电路800共同被配置为将第一初始化电压Vinit1施加至驱动电路100的控制端110，补偿控制电路300还被配置为在第二扫描信号SN2的控制下将驱动电路100的控制端110(第一节点N1)的第一初始化电压Vinit1传输至驱动电路100的第二端130(第三节点N3)。例如，在一些示例中，在复位阶段，第一初始化电路600响应于第一复位控制信号RS1而导通，传输电路800响应于传输控制信号TC而导通，从而可以通过第一初始化电路600和传输电路800将第一初始化电压Vinit1施加至第一节点N1；同时，补偿控制电路300响应于第二扫描信号SN2而导通，从而可以将第一节点N1处的第一初始化电压Vinit1传输至第三节点N3，对驱动电路100的第二端130进行复位操作，以消除之前的发光阶段对驱动电路100的第二端130的影响。例如，在一些示例中，在复位阶段，第一初始化电路600响应于第一复位控制信号RS1而导通，传输电路800响应于传输控制信号TC而导通，从而可以通过第一初始化电路600和传输电路800将第一初始化电压Vinit1施加至第一节点N1；同时，补偿控制电路300响应于第二扫描信号SN2而导通，第一发光控制电路400响应于第一发光控制信号EM1而导通，驱动电路100在第一节点N1处的第一初始化电压Vinit1的控制下导通，从而，第一电源端VDD与第一初始化电压端Vinit1之间经由第一发光控制电路400、驱动电路100、补偿控制电路300、传输电路800和第一初始化电路600形成通路，在对第一节点N1进行复位的同时，还可以对第二节点N2和第三节点N3进行复位，以最大程度消除迟滞影响。
需要说明的是，在本公开的实施例中，在可行的前提下，前述控制信号(包括第一扫描信号SN1、第二扫描信号SN2、第一发光控制信号EM1、第二发光控制信号EM2、第一复位控制信号RS1、第二复位控制信号RS2和传输控制信号TC)中的部分信号可以为同一信号，例如，该同一信号可以由同一信号线传输，也可以由不同的信号线传输。例如，在部分控制信号由同一信号线传输的情况下，可以节省显示面板的布局空间，有利于实现高分辨率显示面板的开发。
另外，在本公开的实施例中，当显示面板中的多个像素单元的像素电路10呈阵列排布时，部分控制信号可以复用于例如不同行的像素单元，从而简化显示面板周围的布局空间，有利于实现高分辨率显示面板的开发。例如，对于一行像素单元而言，用于控制本行像素单元的像素电路10中的第一发光控制电路400的第一发光控制信号EM1还可以用于控制上一行像素单元的像素电路10中的第二发光控制电路500，即作为上一行像素单元的像素电路10中的第二发光控制信号EM2；同样地，用于控制本行像素单元的像素电路10中的 第二发光控制电路500的第二发光控制信号EM2还可以用于控制下一行像素单元的像素电路10中的第一发光控制电路400，即作为下一行像素单元的像素电路10中的第一发光控制信号EM1。需要说明的是，本公开的实施例包括但不限于此。
应当理解的是，第一发光控制信号EM1的信号脉冲与第二发光控制信号EM2的信号脉冲可以相差一个或两个时间单元，其中，一个所述时间单元例如为一行子像素扫描的时间。也就是说，第一发光控制信号EM1与第二发光控制信号EM2的时序之间存在错位。以下各实施例与此相同，不再赘述。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3、第四节点N4以及第五节点N5(后续介绍)并非表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号VDD、VSS、Vinit1和Vinit2既可以表示相应的电压端又可以表示相应的电压；符号SN1、SN2、EM1、EM2、RS1、RS2、TC既可以表示相应的控制信号端又可以表示相应的控制信号。以下各实施例与此相同，不再赘述。
图3为本公开至少一些实施例提供的另一种像素电路的示意框图。图3所示的像素电路10与图2所示的像素电路10的区别主要在于：补偿控制电路300、第一初始化电路600以及传输电路800的连接方式不同。需要说明的是，图3所示的像素电路10中的其他电路结构与图2所示的像素电路10基本相同，在此重复之处不再赘述。应当理解的是，图3所示的像素电路10中的各电路结构的基本功能与图2所示的像素电路10中对应的电路结构基本相同，在此重复之处不再赘述。
例如，如图3所示，补偿控制电路300与第二扫描信号端SN2、驱动电路100的第二端130(第三节点N3)、第五节点N5以及第一电源端VDD连接，第一初始化电路600与第一复位控制端RS1、驱动电路100的控制端110(第一节点N1)以及第五节点N5连接，传输电路800与传输控制信号端TC(提供传输控制信号)、第五节点N5以及第一初始化电压端Vinit1连接。例如，在一些示例中，在复位阶段，第一初始化电路600响应于第一复位控制信号RS1而导通，传输电路800响应于传输控制信号TC而导通，从而可以通过传输电路800和第一初始化电路600将第一初始化电压Vinit1施加至第一节点N1，对驱动电路100的控制端110进行复位操作，以消除之前的发光阶段对驱动电路100的控制端110的影响。例如，在一些示例中，在数据写入和补偿阶段，第一初始化电路600响应于第一复位控制信号RS1而导通，补偿控制电路300响应于第二扫描信号SN2而导通，通过第一初始化电路600和补偿控制电路300将驱动电路100的控制端110和第二端130电连接，从而使，数据写入电路500写入的数据信号Vdata和驱动电路100的阈值电压Vth的相关信息相应地存储在储能电路350中。
例如，在一些实施例中，在图3所示的像素电路10中，第二发光控制电路500还被配置为在第二发光控制信号EM2的控制下将发光元件900的第一极(第四节点N4)的第二 初始化电压Vinit2传输至驱动电路900的第二端(第三节点N3)。例如，在一些示例中，在复位阶段，第二初始化电路700响应于第二复位控制信号RS2而导通，从而可以将第二初始化电压Vinit2施加至第四节点N4；同时，第二发光控制电路500响应于第二发光控制信号EM2而导通，从而可以将第四节点N4处的第二初始化电压Vinit2传输至第三节点N3，对驱动电路100的第二端130进行复位操作，以消除之前的发光阶段对驱动电路100的第二端130的影响。
图4为本公开至少一些实施例提供的又一种像素电路的示意框图。图4所示的像素电路10与图2所示的像素电路10的区别主要在于：第一初始化电路600以及传输电路800的连接方式不同。需要说明的是，图4所示的像素电路10中的其他电路结构与图2所示的像素电路10基本相同，在此重复之处不再赘述。应当理解的是，图4所示的像素电路10中的各电路结构的基本功能与图2所示的像素电路10中对应的电路结构基本相同，在此重复之处不再赘述。
例如，在图4所示的像素电路10中，第一初始化电路600和传输电路800共同被配置为将第一初始化电压Vinit1施加至驱动电路100的第二端130(第三节点N3)，补偿控制电路300还被配置为在第二扫描信号SN2的控制下将驱动电路100的第二端130的第一初始化电压Vinit1传输至驱动电路100的控制端110。例如，如图4所示，第一初始化电路600与第一复位控制端RS1、第一初始化电压端Vinit1以及第五节点N5连接，传输电路800与传输控制信号端TC、第五节点N5以及驱动电路100的第二端130(第三节点N3)连接。例如，在一些示例中，在复位阶段，第一初始化电路600响应于第一复位控制信号RS1而导通，传输电路800响应于传输控制信号TC而导通，从而可以通过第一初始化电路600和传输电路800将第一初始化电压Vinit1施加至第三节点N3，对驱动电路100的第二端130进行复位操作，以消除之前的发光阶段对驱动电路100的第三端130的影响；同时，补偿控制电路300响应于第二扫描信号SN2而导通，从而可以将第三节点N3处的第一初始化电压Vinit1传输至第一节点N1，对驱动电路100的控制端110进行复位操作，以消除之前的发光阶段对驱动电路100的控制端110的影响。例如，在另一些示例中，除了上述示例所描述的电路结构的工作过程，在复位阶段，第一发光控制电路400响应于第一发光控制信号EM1而导通，驱动电路100在第一节点N1处的第一初始化电压Vinit1的控制下导通，从而，第一电源端VDD与第一初始化电压端Vinit1之间经由第一发光控制电路400、驱动电路100、补偿控制电路300、传输电路800和第一初始化电路600形成通路，在对第一节点N1和第三节点N3进行复位的同时，还可以对第二节点N2进行复位，以最大程度消除迟滞影响。
图5为图2所示的像素电路的一种具体实现示例的电路结构示意图。如图5所示，该像素电路10包括第一至第八晶体管T1-T8以及存储电容Cst，图5中所示的发光元件LE即为前述发光元件900。例如，第三晶体管T3被用作驱动晶体管，其他晶体管被用作开关晶体管。例如，发光元件LE可以采用OLED，本公开的实施例包括但不限于此，以下实施例 均以OLED为例进行说明，不再赘述。该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图5所示，驱动电路100可以实现为第三晶体管T3。第三晶体管T3的栅极作为驱动电路100的控制端110和第一节点N1连接，第三晶体管T3的第一极作为驱动电路100的第一端120和第二节点N2连接，第三晶体管T3的第二极作为驱动电路100的第二端130和第三节点N3连接。例如，如图5所示，第三晶体管T3可以为P型薄膜晶体管；例如，P型薄膜晶体管可以包括低温多晶硅晶体管，低温多晶硅晶体管具有较高的载流子迁移率，有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。例如，P型薄膜晶体管响应于其控制信号的低电平而导通，以下实施例与此相同，不再重复赘述。例如，第三晶体管T3的阈值电压Vth可以大于或等于-5V而小于或等于-2V；第三晶体管T3的阈值电压Vth可以大于或等于-4V而小于或等于-2.5V；例如，第三晶体管T3的阈值电压Vth可以为-4V、-3.5V、-3V或-2.5V，但不以此为限。
例如，如图5所示，数据写入电路200可以实现为第四晶体管T4。第四晶体管T4的栅极和第一扫描信号端SN1连接以接收第一扫描信号，第四晶体管T4的第一极和数据信号端DATA连接以接收数据信号Vdata，第四晶体管T4的第二极和驱动电路的第一端连接。例如，如图5所示，第四晶体管T4可以为P型薄膜晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。
例如，如图5所示，补偿控制电路300可以实现为第二晶体管T2，储能电路350可以实现为存储电容Cst。第二晶体管T2的栅极和第二扫描信号端SN2连接以接收第二扫描信号，第二晶体管T2的第一极与驱动电路100的第二端130(第三节点N3)连接，第二晶体管T2的第二极与驱动电路100的控制端110(第一节点N1)连接；存储电容Cst的第一端与驱动电路100的控制端110(第一节点N1)耦接，存储电容Cst的第二端与第一电源端VDD耦接。例如，如图5所示，第二晶体管T2可以为N型薄膜晶体管。例如，第二晶体管T2可以为N型氧化物薄膜晶体管，其可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层；相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及减小漏电流。例如，N型薄膜晶体管响应于其控制信号的高电平而导通，以下实施例与此相同，不再重复赘述。
例如，如图5所示，第一发光控制电路400可以实现为第五晶体管T5。第五晶体管T5的栅极和第一发光控制信号端EM1连接以接收第一发光控制信号，第五晶体管T5的第一极和第一电源端VDD连接以接收第一电源电压，第五晶体管T5的第二极和驱动电路100的第一端120(第二节点N2)连接。例如，如图5所示，第五晶体管T5可以为P型薄膜晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。例如，第一电源电压VDD可以为驱动电压，例如高电压。例如，第一电源电压VDD的电压值可以为4.6V，但不限于此。
例如，如图5所示，第二发光控制电路500可以实现为第六晶体管T6。第六晶体管T6 的栅极和第二发光控制信号端EM2连接以接收第二发光控制信号，第六晶体管T6的第一极和驱动电路100的第二端130(第三节点N3)连接，第六晶体管T6的第二极和第四节点N4连接。例如，如图5所示，第六晶体管T6可以为P型薄膜晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。
例如，如图5所示，第二初始化电路700可以实现为第七晶体管T7。第七晶体管T7的栅极和第二复位控制信号端RS2连接以接收第二复位控制信号，第七晶体管T7的第一极和第二初始化电压端Vinit2连接以接收第二初始化电压，第七晶体管T7的第二极和第四节点N4连接。例如，如图5所示，第七晶体管T7可以为P型薄膜晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。例如，第二初始化电压Vinit2可以为直流电压，第二初始化电压Vinit2的电压值可以在大于或等于-7V而小于或等于0V；例如，第二初始化电压Vinit2的电压值可以为-6V、-5V、-4V、-3V或-2V，但不限于此。
例如，如图5所示，第一初始化电路600可以实现为第一晶体管T1。第一晶体管T1的栅极和第一复位控制信号端RS1连接以接收第一复位控制信号，第一晶体管T1的第一极和第一初始化电压端Vinit1连接以接收第一初始化电压，第一晶体管T1的第二极和第五节点N5连接。例如，如图5所示，第一晶体管T1可以为P型薄膜晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。例如，第一初始化电压Vinit1可以为直流电压，第一初始化电压Vinit1的电压值可以在大于或等于-7V而小于或等于0V；例如，第一初始化电压Vinit1的电压值可以为-6V、-5V、-4V、-3V或-2V，但不限于此。
例如，如图5所示，传输电路800可以实现为第八晶体管T8。第八晶体管T8的栅极和传输控制信号端TC连接以接收传输控制信号，第八晶体管T8的第一极和第五节点N5连接，第八晶体管T8的第二极和驱动电路100的控制端110(第一节点N1)连接。例如，如图5所示，第八晶体管T8可以为P型薄膜晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。
例如，如图5所示，发光元件LE的第一极(例如，阳极)和第四节点N4连接，发光元件LE的第二极(例如，阴极)与第二电源端VSS连接以接收第二电源电压。例如，第二电源电压VSS可以为低电压，例如，第二电源端ELVSS可以接地，从而第二电源电压VSS可以为接地电压(零电压)。
例如，对于图5所示的像素电路，第二复位控制信号RS2可以与第一复位控制信号RS1为同一控制信号；传输控制信号TC可以与第一发光控制信号EM1或者第二发光控制信号EM2为同一控制信号。需要说明的是，本公开的实施例对此不作限制。
图6为图2所示的像素电路的另一种具体实现示例的电路结构示意图。图6所示的像素电路与图5所示的像素电路的区别主要在于：在图6所示的像素电路中，第七晶体管T7为N型薄膜晶体管，例如N型氧化物薄膜晶体管，从而有利于减小晶体管的尺寸以及减小第四节点N4的漏电流。需要说明的是，图6所示的像素电路中的其他电路结构与图5所示的像素电路基本相同，在此重复之处不再赘述。
例如，对于图6所示的像素电路，第二复位控制信号RS2可以与第一发光控制信号EM1为同一控制信号；传输控制信号TC可以与第二发光控制信号EM2为同一控制信号。需要说明的是，本公开的实施例对此不作限制。
图7为图3所示的像素电路的一种具体实现示例的电路结构示意图。图7所示的像素电路10与图5所示的像素电路的区别主要在于：第二晶体管T2、第一晶体管T1以及第八晶体管T8的连接方式不同。需要说明的是，图7所示的像素电路中的其他电路结构与图5所示的像素电路基本相同，在此重复之处不再赘述。
例如，如图7所示，第一晶体管T1的栅极和第一复位控制信号端RS1连接以接收第一复位控制信号，第一晶体管T1的第一极和第五节点N5连接，第一晶体管T1的第二极和驱动电路100的控制端110(第一节点N1)连接；第八晶体管T8的栅极和传输控制信号端TC连接以接收传输控制信号，第八晶体管T8的第一极和第一初始化电压端Vinit1连接以接收第一初始化电压，第八晶体管的第二极和第五节点N5连接；第二晶体管T2的栅极和第二扫描信号端SN2连接以接收第二扫描信号，第二晶体管T2的第一极与驱动电路100的第二端130(第三节点N3)连接，第二晶体管T2的第二极与第五节点N5连接。也就是说，第二晶体管T2的第二极通过第一晶体管T1与驱动电路100的控制端110连接。
例如，对于图7所示的像素电路，第二复位控制信号RS2可以与第一复位控制信号RS1为同一控制信号；传输控制信号TC可以与第二发光控制信号EM2为同一控制信号。需要说明的是，本公开的实施例对此不作限制。
图8为图3所示的像素电路的另一种具体实现示例的电路结构示意图。图8所示的像素电路与图7所示的像素电路的区别主要在于：在图8所示的像素电路中，第七晶体管T7为N型薄膜晶体管，例如N型氧化物薄膜晶体管，从而有利于减小晶体管的尺寸以及减小第四节点N4的漏电流。需要说明的是，图8所示的像素电路中的其他电路结构与图7所示的像素电路基本相同，在此重复之处不再赘述。
例如，对于图8所示的像素电路，第二复位控制信号RS2可以与第一发光控制信号EM1为同一控制信号；传输控制信号TC可以与第二发光控制信号EM2为同一控制信号。需要说明的是，本公开的实施例对此不作限制。
图9为图4所示的像素电路的一种具体实现示例的电路结构示意图。图9所示的像素电路与图5所示的像素电路的区别主要在于：第一晶体管T1和第八晶体管T8的连接方式不同。需要说明的是，图9所示的像素电路中的其他电路结构与图5所示的像素电路基本相同，在此重复之处不再赘述。
例如，如图9所示，第一晶体管T1的栅极和第一复位控制信号端RS1连接以接收第一复位控制信号，第一晶体管T1的第一极和第一初始化电压端Vinit1连接以接收第一初始化电压，第一晶体管T1的第二极和第五节点N5连接；第八晶体管T8的栅极和传输控制信号端TC连接以接收传输控制信号，第八晶体管T8的第一极和第五节点N5连接，第八晶体管的第二极和驱动电路100的第二端130(第三节点N3)连接。例如，在一些示例中，在 复位阶段，第一晶体管T1响应于第一复位控制信号RS1而导通，第八晶体管T8响应于传输控制信号TC而导通，从而可以通过第一晶体管T1和第八晶体管T8将第一初始化电压Vinit1施加至第三节点N3，对驱动电路100的第二端130(第三晶体管T3的第二极)进行复位操作，以消除之前的发光阶段对驱动电路100的第三端130的影响；同时，第二晶体管T2响应于第二扫描信号SN2而导通，从而可以将第三节点N3处的第一初始化电压Vinit1传输至第一节点N1，对驱动电路100的控制端110(第三晶体管T3的栅极)进行复位操作，以消除之前的发光阶段对驱动电路100的控制端110的影响。
例如，对于图9所示的像素电路，第二复位控制信号RS2可以与第一扫描信号SN1为同一控制信号；传输控制信号TC可以与第一发光控制信号EM1为同一控制信号。需要说明的是，本公开的实施例对此不作限制。
图10为图4所示的像素电路的另一种具体实现示例的电路结构示意图。图10所示的像素电路与图9所示的像素电路的区别主要在于：在图10所示的像素电路中，第七晶体管T7为N型薄膜晶体管，例如N型氧化物薄膜晶体管，从而有利于减小晶体管的尺寸以及减小第四节点N4的漏电流。需要说明的是，图10所示的像素电路中的其他电路结构与图9所示的像素电路基本相同，在此重复之处不再赘述。
例如，对于图10所示的像素电路，第二复位控制信号RS2可以与第二发光控制信号EM2为同一控制信号；传输控制信号TC可以与第一发光控制信号EM1为同一控制信号。需要说明的是，本公开的实施例对此不作限制。
图11A为本公开至少一些实施例提供的一种氧化物薄膜晶体管的局部平面结构示意图，图11B为本公开至少一些实施例提供的一种氧化物薄膜晶体管的局部截面结构示意图。
例如，如图11A和图11B所示，氧化物薄膜晶体管包括在Z方向上依次层叠且相互绝缘的第一金属层Metal_1、有源层S/D和第二金属层Metal_2。例如，氧化物薄膜晶体管设置在一衬底基板上，其中，X方向和Y方向均平行于该衬底基板的表面，Z方向垂直于该衬底基板的表面。例如，X方向垂直于Y方向。例如，第一金属层Metal_1和有源层S/D之间设置有绝缘层(图11B中未示出)，有源层S/D和第二金属层Metal_2之间也设置有绝缘层(图11B中未示出)。例如，有源层S/D的材料可以采用氧化铟镓锌(IGZO)等。
例如，如图11A所示，有源层S/D沿Y方向延伸。在有源层S/D的延伸方向(即Y方向)上，第二金属层Metal_2的宽度不大于第一金属层Metal_1的宽度。例如，在一些示例中，第二金属层Metal_2和第二扫描信号端SN2连接以作为氧化物薄膜晶体管(例如，第二晶体管T2和/或第七晶体管T7等)的栅极；第一金属层Metal_1中可以输入直流信号，起屏蔽作用，屏蔽外界电场对氧化物薄膜晶体管的影响。例如，在另一些示例中，第二金属层Metal_2和第一金属层Metal_1均与第二扫描信号端SN2连接以同时作为氧化物薄膜晶体管(例如，第二晶体管T2和/或第七晶体管T7等)的栅极。
例如，有源层S/D包括被第一金属层Metal_1覆盖的沟道区、以及位于沟道区两侧的源极区S和漏极区D。例如，源极区S和漏极区D分别与氧化物薄膜晶体管的第一极和第二 极电连接。
例如，氧化物薄膜晶体管的沟道区的宽长比W/L的取值范围为[1/2,7/8]。例如，氧化物薄膜晶体管的沟道区的宽长比W/L的一般值为2.5/3.0；例如，W的取值范围可以为[1.5,2.5]，L的取值范围可以为[2.0,8.0]。应当理解的是，沟道区的长度是指沟道区在有源层S/D的延伸方向(即Y方向)上的尺寸，而沟道区的长度是指沟道区在与有源层S/D的延伸方向垂直的另一平面方向(即X方向)上的尺寸。
例如，在一些实施例中，为了减小第一节点N1的漏电流，第一晶体管T1的沟道区的宽长比的取值范围可以为[1/3,3/4]，第八晶体管T8的沟道区的宽长比的取值范围也可以为[1/3,3/4]。例如，第一晶体管T1的沟道区的宽长比的一般值为2.0/3.0；例如，第一晶体管T1的沟道区的宽的取值范围可以为[1.5,2.5]，第一晶体管T1的沟道区的长的取值范围可以为[2.0,5.0]。例如，第八晶体管T8的沟道区的宽长比的一般值为2.0/3.0；例如，第八晶体管T8的沟道区的宽的取值范围可以为[1.5,2.5]，第八晶体管T8的沟道区的长的取值范围可以为[2.0,5.0]。例如，在一些示例中，第一晶体管T1和第八晶体管T8至少之一可以具有双栅结构，例如，对于双栅结构的晶体管而言，其沟道区的宽长比的一般值为2.0/(3.0+3.0)。
需要说明的是，在本公开的实施例中，存储电容Cst可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，电容也可以是各个器件之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。电容的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储相应节点的电平即可。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，需要说明的是，在本公开的实施例中，对于P型晶体管而言，第一极可以是源极，第二极可以是漏极；对于N型晶体管而言，第一极可以是漏极，第二极可以是源极。需要说明的是，本公开包括但不限于此。需要说明的是，在本公开的实施例中，均是以发光元件LE的第二极(例如，阴极)接入第二电源电压VSS(低电压)为例进行说明的，本公开的实施例包括但不限于此。例如，还可以使发光元件LE的第一极(例如，阳极)接入第一电源电压VDD(高电压)，而其阴极则直接或间接地连接到像素电路。
需要说明的是，在本公开的实施例提供的像素电路中，“有效电平”指的是能够使得其包括的被操作晶体管被导通的电平，相应地“无效电平”指的是不能使得其包括的被操作晶体管被导通(即，该晶体管被截止)的电平。根据移位寄存器单元的电路结构中的晶体管的类型(N型或P型)等因素，有效电平可以比无效电平高或者低。例如，在本公开实施例中，对于P型晶体管，有效电平为低电平，无效电平为高电平；对于N型晶体管， 有效电平为高电平，无效电平为低电平。
本公开至少一些实施例还提供一种像素电路的驱动方法。图12-18为本公开至少一些实施例提供的各种像素电路的驱动方法的信号时序图。例如，图12-14所示的信号时序均可以用于驱动图2所示的像素电路10，图12和图14所示的信号时序还可以用于驱动图3所示的像素电路10，图13和图15所示的信号时序均可以用于驱动图4所示的像素电路10。下面结合图12-18所示的信号时序，对图2-4所示的像素电路10(其中，图2所示的像素电路具体实现为图5或图6所示的电路结构，图3所示的像素电路具体实现为图7或图8所示的电路结构，图4所示的像素电路具体实现为图9或图10所示的电路结构)的驱动方法进行说明。需要说明的是，图12-18中所示的信号时序的电位的高低仅是示意性的，不代表真实电位值或相对比例，对应于本公开的实施例，低电平信号对应于P型晶体管的导通信号或N型晶体管的截止信号，而高电平信号对应于P型晶体管的截止信号或N型晶体管的导通信号。
例如，如图12-18所示，每一帧图像的显示过程可以包括五个阶段，分别为复位阶段t1、数据写入和补偿阶段t2、保持阶段t3&t4以及发光阶段t5。图12-18中示出了每个阶段中各个控制信号的时序波形。
在复位阶段t1，输入第二发光控制信号EM2、第一复位控制信号RS1、第二复位控制信号RS2和传输控制信号TC，开启第二发光控制电路500、第一初始化电路600、第二初始化电路700和传输电路800，通过第一初始化电路600和传输电路800将第一初始化电压Vinit1施加至驱动电路100的控制端110以对驱动电路100的控制端110进行复位，通过第二初始化电路700将第二初始化电压Vinit2施加至发光元件900的第一极以对发光元件900进行复位，通过第二初始化电路700和第二发光控制电路500将第二初始化电压Vinit2施加至驱动电路100的第二端130以对驱动电路100的第二端130进行复位；或者，在复位阶段t1，输入第二扫描信号SN2、第一复位控制信号RS1、第二复位控制信号RS2和传输控制信号TC，开启补偿控制电路300、第一初始化电路600、第二初始化电路700和传输电路800，通过第一初始化电路600和传输电路800将第一初始化电压Vinit1施加至驱动电路100的控制端110以对驱动电路100的控制端110进行复位，通过第一初始化电路600、传输电路800和补偿控制电路300将第一初始化电压Vinit1施加至驱动电路100的第二端130以对驱动电路100的第二端130进行复位，通过第二初始化电路700将第二初始化电压Vinit2施加至发光元件900的第一极以对发光元件900进行复位；或者，在复位阶段t1，输入第二扫描信号SN2、第一复位控制信号RS1、第二复位控制信号RS2和传输控制信号TC，开启补偿控制电路300、第一初始化电路600、第二初始化电路700和传输电路800，通过第一初始化电路600和传输电路800将第一初始化电压Vinit1施加至驱动电路100的第二端130以对驱动电路100的第二端130进行复位，通过第一初始化电路600、传输电路800和补偿控制电路300将第一初始化电压Vinit1施加至驱动电路100的控制端110以对驱动电路100的控制端110进行复位，通过第二初始化电路700将第二初始化电压Vinit2施加 至发光元件900的第一极以对发光元件900进行复位。
例如，参考图5所示的电路结构和图12所示的信号时序，在复位阶段t1，P型的第六晶体管T6被第二发光控制信号EM2的低电平导通，P型的第一晶体管T1被第一复位控制信号RS1的低电平导通，P型的第七晶体管T7被第二复位控制信号RS2的低电平导通，P型的第八晶体管T8被传输控制信号TC的低电平导通；同时，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第四晶体管T4被第一扫描信号SN1的高电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止。从而，第一复位电压Vinit1可以通过导通的第一晶体管T1和第八晶体管T8传输至第一节点N1，以将第一节点N1(驱动电路100的控制端110)复位至Vinit1；第二复位电压Vinit2可以通过导通的第七晶体管T7传输至第四节点N4，并进一步通过导通的第六晶体管T6传输至第三节点N3，以将第四节点N4(发光元件LE的第一极)和第三节点N3(驱动电路100的第二端130)复位至Vinit2。因此，采用上述像素电路的显示装置在每次切换画面时均会对第一节点N1、第三节点N3以及第四节点N4进行复位，进而可以消除迟滞影响。
例如，参考图5所示的电路结构和图13所示的信号时序，在复位阶段t1，P型的第五晶体管T5被第一发光控制信号EM1的低电平导通，P型的第一晶体管T1被第一复位控制信号RS1的低电平导通，P型的第七晶体管T7被第二复位控制信号RS2的低电平导通，P型的第八晶体管T8被传输控制信号TC的低电平导通，N型的第二晶体管T2被第二扫描信号SN2的高电平导通；同时，P型的第四晶体管T4被第一扫描信号SN1的高电平截止，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止。从而，第一电源端VDD与第一初始化电压端Vinit1之间可以经由导通的第五晶体管T5、第三晶体管T3、第二晶体管T2、第八晶体管T8和第一晶体管T1形成通路，以同时对第一节点N1、第二节点N2和第三节点N3进行复位；第二复位电压Vinit2可以通过导通的第七晶体管T7传输至第四节点N4，以将第四节点N4(发光元件LE的第一极)复位至Vinit2。因此，采用上述像素电路的显示装置在每次切换画面时均会对第一节点N1、第二节点N2、第三节点N3以及第四节点N4进行复位，进而可以消除迟滞影响。
例如，图6所示的电路结构和图14所示的信号时序对应的复位阶段t1的工作原理与图5所示的电路结构和图12所示的信号时序对应的复位阶段t1的工作原理基本相同(区别仅在于第七晶体管T7的类型及对应的第二复位控制信号RS2的有效电平不同)，重复之处在此不再赘述。
例如，参考图7所示的电路结构和图12所示的信号时序，在复位阶段t1，P型的第六晶体管T6被第二发光控制信号EM2的低电平导通，P型的第一晶体管T1被第一复位控制信号RS1的低电平导通，P型的第七晶体管T7被第二复位控制信号RS2的低电平导通，P型的第八晶体管T8被传输控制信号TC的低电平导通；同时，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第四晶体管T4被第一扫描信号SN1的高电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止。从而，第一复位电压Vinit1 可以通过导通的第八晶体管T8和第一晶体管T1传输至第一节点N1，以将第一节点N1(驱动电路100的控制端110)复位至Vinit1；第二复位电压Vinit2可以通过导通的第七晶体管T7传输至第四节点N4，并进一步通过导通的第六晶体管T6传输至第三节点N3，以将第四节点N4(发光元件LE的第一极)和第三节点N3(驱动电路100的第二端130)复位至Vinit2。因此，采用上述像素电路的显示装置在每次切换画面时均会对第一节点N1、第三节点N3以及第四节点N4进行复位，进而可以消除迟滞影响。
例如，图8所示的电路结构和图14所示的信号时序对应的复位阶段t1的工作原理与图7所示的电路结构和图12所示的信号时序对应的复位阶段t1的工作原理基本相同(区别仅在于第七晶体管T7的类型及对应的第二复位控制信号RS2的有效电平不同)，重复之处在此不再赘述。
例如，参考图9所示的电路结构和图13所示的信号时序，在复位阶段t1，P型的第五晶体管T5被第一发光控制信号EM1的低电平导通，P型的第一晶体管T1被第一复位控制信号RS1的低电平导通，P型的第七晶体管T7被第二复位控制信号RS2的低电平导通，P型的第八晶体管T8被传输控制信号TC的低电平导通，N型的第二晶体管T2被第二扫描信号SN2的高电平导通；同时，P型的第四晶体管T4被第一扫描信号SN1的高电平截止，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止。从而，第一初始化电压端Vinit可以通过导通的第一晶体管T1和第八晶体管T8施加至第三节点N3，进而通过导通的第二晶体管T2施加至第一节点N1，以对第一节点N1进行复位；同时，第一电源端VDD与第一初始化电压端Vinit1之间可以经由导通的第五晶体管T5、第三晶体管T3、第八晶体管T8和第一晶体管T1形成通路，以同时对第二节点N2和第三节点N3进行复位；第二复位电压Vinit2可以通过导通的第七晶体管T7传输至第四节点N4，以将第四节点N4(发光元件LE的第一极)复位至Vinit2。因此，采用上述像素电路的显示装置在每次切换画面时均会对第一节点N1、第二节点N2、第三节点N3以及第四节点N4进行复位，进而可以消除迟滞影响。
例如，图10所示的电路结构和图15所示的信号时序对应的复位阶段t1的工作原理与图9所示的电路结构和图13所示的信号时序对应的复位阶段t1的工作原理基本相同(区别仅在于第七晶体管T7的类型及对应的第二复位控制信号RS2的有效电平不同)，重复之处在此不再赘述。
在数据写入和补偿阶段t2，输入第一扫描信号SN1和第二扫描信号SN2，开启数据写入电路200、驱动电路100和补偿控制电路300，通过数据写入电路200将数据信号Vdata写入补偿控制电路300，通过补偿控制电路300对驱动电路100进行补偿。
例如，参考图5所示的电路结构和图12所示的信号时序，在数据写入和补偿阶段t2，P型的第一晶体管T1被第一复位控制信号RS1的低电平导通，P型的第七晶体管T7被第二复位控制信号RS2的低电平导通，N型的第二晶体管T2被第二扫描信号SN2的高电平导通，P型的第四晶体管T4被第一扫描信号SN1的低电平导通，此时，由于第二晶体管 T2的导通，第三晶体管T3呈二极管连接方式(第三晶体管T3的栅极和第二极连接)；同时，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止。从而，第二复位电压Vinit2仍然可以通过导通的第七晶体管T7传输至第四节点N4，以持续对第四节点N4(发光元件LE的第一极)进行复位；数据信号Vdata经过导通的第四晶体管T4、第三晶体管T3和第二晶体管T2对第一节点N1进行充电(即对电容Cst的第一端)进行充电。容易理解，第二节点N2的电位保持为Vdata，同时，根据第三晶体管T3的自身特性，当第一节点N1的电位(即存储电容Cst的第一端的电位)达到Vdata+Vth时，第三晶体管T3截止，充电过程结束。需要说明的是，Vdata表示数据信号的电压值，Vth表示第三晶体管T3的阈值电压，由于在本实施例中，第三晶体管T3为P型晶体管，所以此处阈值电压Vth可以是个负值。需要注意的是，在此阶段，也可以调整第一复位控制信号RS1和第二复位控制信号RS2，使得第一晶体管T1和第七晶体管T7截止，而不会对该像素电路的后续发光阶段造成影响，本公开的实施例对此不作限制。
例如，图5所示的电路结构和图13所示的信号时序对应的数据写入和补偿阶段t2的工作原理与图5所示的电路结构和图12所示的信号时序对应的数据写入和补偿阶段t2的工作原理基本相同，重复之处在此不再赘述。
例如，图6所示的电路结构和图14所示的信号时序对应的数据写入和补偿阶段t2的工作原理与图5所示的电路结构和图12所示的信号时序对应的数据写入和补偿阶段t2的工作原理基本相同(区别仅在于第七晶体管T7的类型及对应的第二复位控制信号RS2的有效电平不同)，重复之处在此不再赘述。
例如，参考图7所示的电路结构和图12所示的信号时序，在数据写入和补偿阶段t2，P型的第一晶体管T1被第一复位控制信号RS1的低电平导通，P型的第七晶体管T7被第二复位控制信号RS2的低电平导通，N型的第二晶体管T2被第二扫描信号SN2的高电平导通，P型的第四晶体管T4被第一扫描信号SN1的低电平导通，此时，由于第二晶体管T2的导通，第三晶体管T3呈二极管连接方式(第三晶体管T3的栅极和第二极连接)；同时，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止。从而，第二复位电压Vinit2仍然可以通过导通的第七晶体管T7传输至第四节点N4，以持续对第四节点N4(发光元件LE的第一极)进行复位；数据信号Vdata经过导通的第四晶体管T4、第三晶体管T3、第二晶体管T2和第一晶体管T1对第一节点N1进行充电(即对电容Cst的第一端)进行充电。容易理解，第二节点N2的电位保持为Vdata，同时，根据第三晶体管T3的自身特性，当第一节点N1的电位(即存储电容Cst的第一端的电位)达到Vdata+Vth时，第三晶体管T3截止，充电过程结束。需要说明的是，Vdata表示数据信号的电压值，Vth表示第三晶体管T3的阈值电压，由于在本实施例中，第三晶体管T3为P型晶体管，所以此处阈值电压Vth可以是个负值。需要注意的是，在此阶段，也 可以调整第二复位控制信号RS2，使得第七晶体管T7截止，而不会对该像素电路的后续发光阶段造成影响，本公开的实施例对此不作限制。
例如，图8所示的电路结构和图14所示的信号时序对应的数据写入和补偿阶段t2的工作原理与图7所示的电路结构和图12所示的信号时序对应的数据写入和补偿阶段t2的工作原理基本相同(区别仅在于第七晶体管T7的类型及对应的第二复位控制信号RS2的有效电平不同)，重复之处在此不再赘述。
例如，图9所示的电路结构和图13所示的信号时序对应的数据写入和补偿阶段t2的工作原理与图5所示的电路结构和图13所示的信号时序对应的数据写入和补偿阶段t2的工作原理基本相同，重复之处在此不再赘述。
例如，图10所示的电路结构和图15所示的信号时序对应的数据写入和补偿阶段t2的工作原理与图9所示的电路结构和图13所示的信号时序对应的数据写入和补偿阶段t2的工作原理基本相同(区别仅在于第七晶体管T7的类型及对应的第二复位控制信号RS2的有效电平不同)，重复之处在此不再赘述。
需要说明的是，在本公开的一些实施例中，复位阶段t1与数据写入和补偿阶段t2之间可以存在一定的时间间隔，例如，该时间间隔可以大于预定时间间隔，以通过对第三晶体管T3的栅极电位提前进行复位，改善第三晶体管的磁滞现象，降低像素电路的高低频闪烁(Flicker)。
在保持阶段t3&t4，输入第二扫描信号SN2，关闭补偿控制电路300，通过储能电路350保持驱动电路100的控制端110的电压。
例如，保持阶段t3&t4包括第一保持阶段t3和第二保持阶段t4。
例如，参考图5所示的电路结构和图12所示的信号时序，在第一保持阶段t3，P型的第四晶体管T4被第一扫描信号SN1的低电平导通；同时，P型的第一晶体管T1被第一复位控制信号RS1的高电平截止，P型的第七晶体管T7被第二复位控制信号RS2的高电平截止，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止。从而，在第一保持阶段t3，第四晶体管T4导通，持续将数据信号Vdata写入第二节点N2，第二节点N2的电位保持为Vdata；第三晶体管T3截止，且由于存储电容Cst的性质，第一节点N1的电位保持在Vdata+Vth，以用于后续在发光阶段时，提供灰度显示数据和对第三晶体管T3自身的阈值电压进行补偿。在第二保持阶段t4，P型的第五晶体管T5被第一发光控制信号EM1的低电平导通；同时，P型的第四晶体管T4被第一扫描信号SN1的高电平截止，P型的第一晶体管T1被第一复位控制信号RS1的高电平截止，P型的第七晶体管T7被第二复位控制信号RS2的高电平截止，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止。从而，在第二保持阶段t4，由于存储电容Cst的性质，第一节点N1的 电位仍保持在Vdata+Vth；第一电源端VDD通过导通的第五晶体管T5对第二节点N2进行充电，第二节点N2的电位由Vdata变为第一电源电压VDD，由于在此阶段，第六晶体管T6截止，所以为下一阶段的发光元件LE的发光作准备。
例如，参考图5所示的电路结构和图13所示的信号时序，在第一保持阶段t3，P型的第四晶体管T4被第一扫描信号SN1的低电平导通；同时，P型的第一晶体管T1被第一复位控制信号RS1的高电平截止，P型的第七晶体管T7被第二复位控制信号RS2的高电平截止，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止。从而，在第一保持阶段t3，第四晶体管T4导通，持续将数据信号Vdata写入第二节点N2，第二节点N2的电位保持为Vdata；第三晶体管T3截止，且由于存储电容Cst的性质，第一节点N1的电位保持在Vdata+Vth，以用于后续在发光阶段时，提供灰度显示数据和对第三晶体管T3自身的阈值电压进行补偿。在第二保持阶段t4，P型的第六晶体管T6被第二发光控制信号EM2的低电平导通；同时，P型的第四晶体管T4被第一扫描信号SN1的高电平截止，P型的第一晶体管T1被第一复位控制信号RS1的高电平截止，P型的第七晶体管T7被第二复位控制信号RS2的高电平截止，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止。从而，在第二保持阶段t4，由于存储电容Cst的性质，第一节点N1的电位仍保持在Vdata+Vth；第三节点N3通过导通的第六晶体管T6与第四节点N4连接，由于在此阶段，第五晶体管T5截止，所以为下一阶段的发光元件LE的发光作准备。
例如，参考图6所示的电路结构和图14所示的信号时序，在第一保持阶段t3，P型的第四晶体管T4被第一扫描信号SN1的低电平导通，N型的第七晶体管T7被第二复位控制信号RS2的高电平导通；同时，P型的第一晶体管T1被第一复位控制信号RS1的高电平截止，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止。从而，在第一保持阶段t3，第四晶体管T4导通，持续将数据信号Vdata写入第二节点N2，第二节点N2的电位保持为Vdata；第三晶体管T3截止，且由于存储电容Cst的性质，第一节点N1的电位保持在Vdata+Vth，以用于后续在发光阶段时，提供灰度显示数据和对第三晶体管T3自身的阈值电压进行补偿；另外，第二复位电压Vinit2仍然可以通过导通的第七晶体管T7传输至第四节点N4，以持续对第四节点N4(发光元件LE的第一极)进行复位。需要注意的是，在此阶段，也可以调整第二复位控制信号RS2，使得第七晶体管T7截止，而不会对该像素电路的后续发光阶段造成影响，本公开的实施例对此不作限制。在第二保持阶段t4，P型的第五晶体管T5被第一发光控制信号EM1的低电平导通；同时，P型的第四晶体管T4被第一扫描信号SN1的高电平截止，P型的第一晶体管T1被第一复位控制信号RS1的高电平截止， N型的第七晶体管T7被第二复位控制信号RS2的低电平截止，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止。从而，在第二保持阶段t4，由于存储电容Cst的性质，第一节点N1的电位仍保持在Vdata+Vth；第一电源端VDD通过导通的第五晶体管T5对第二节点N2进行充电，第二节点N2的电位由Vdata变为第一电源电压VDD，由于在此阶段，第六晶体管T6截止，所以为下一阶段的发光元件LE的发光作准备。
例如，图7所示的电路结构和图12所示的信号时序对应的保持阶段t3&t4的工作原理与图5所示的电路结构和图12所示的信号时序对应的保持阶段t3&t4的工作原理基本相同，重复之处在此不再赘述。
例如，图8所示的电路结构和图14所示的信号时序对应的保持阶段t3&t4的工作原理与图6所示的电路结构和图14所示的信号时序对应的保持阶段t3&t4的工作原理基本相同，重复之处在此不再赘述。
例如，图9所示的电路结构和图13所示的信号时序对应的保持阶段t3&t4的工作原理与图5所示的电路结构和图13所示的信号时序对应的保持阶段t3&t4的工作原理基本相同，重复之处在此不再赘述。
例如，参考图10所示的电路结构和图15所示的信号时序，在第一保持阶段t3，P型的第四晶体管T4被第一扫描信号SN1的低电平导通，N型的第七晶体管T7被第二复位控制信号RS2的高电平导通；同时，P型的第一晶体管T1被第一复位控制信号RS1的高电平截止，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第六晶体管T6被第二发光控制信号EM2的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止。从而，在第一保持阶段t3，第四晶体管T4导通，持续将数据信号Vdata写入第二节点N2，第二节点N2的电位保持为Vdata；第三晶体管T3截止，且由于存储电容Cst的性质，第一节点N1的电位保持在Vdata+Vth，以用于后续在发光阶段时，提供灰度显示数据和对第三晶体管T3自身的阈值电压进行补偿；另外，第二复位电压Vinit2仍然可以通过导通的第七晶体管T7传输至第四节点N4，以持续对第四节点N4(发光元件LE的第一极)进行复位。需要注意的是，在此阶段，也可以调整第二复位控制信号RS2，使得第七晶体管T7截止，而不会对该像素电路的后续发光阶段造成影响，本公开的实施例对此不作限制。在第二保持阶段t4，P型的第六晶体管T6被第二发光控制信号EM2的低电平导通；同时，P型的第四晶体管T4被第一扫描信号SN1的高电平截止，P型的第一晶体管T1被第一复位控制信号RS1的高电平截止，N型的第七晶体管T7被第二复位控制信号RS2的低电平截止，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第五晶体管T5被第一发光控制信号EM1的高电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止。从而，在第二保持阶段t4，由于存储电容Cst的性质，第一节点N1的电位仍保持在Vdata+Vth；第三节点N3通过导 通的第六晶体管T6与第四节点N4连接，由于在此阶段，第五晶体管T5截止，所以为下一阶段的发光元件LE的发光作准备。
在发光阶段t5，输入第一发光控制信号EM1和第二发光控制信号EM2，开启第一发光控制电路400、第二发光控制电路500和驱动电路100，通过第一发光控制电路400将第一电源电压VDD施加驱动电路100的第一端120以使驱动电路100根据驱动电路100的控制端110的电压产生驱动电流，通过第二发光控制电路500将驱动电流施加至发光元件900以使发光元件900发光。
例如，参考图5所示的电路结构和图12所示的信号时序，在发光阶段t5，P型的第五晶体管T5被第一发光控制信号EM1的低电平导通，P型的第六晶体管T6被第二发光控制信号EM2的低电平导通；同时，P型的第一晶体管T1被第一复位控制信号RS1的高电平截止，P型的第七晶体管T7被第二复位控制信号RS2的高电平截止，N型的第二晶体管T2被第二扫描信号SN2的低电平截止，P型的第八晶体管T8被传输控制信号TC的高电平截止，P型的第四晶体管T4被第一扫描信号SN1的低电平导通。另外，第一节点N1的电位为Vdata+Vth，第二节点N2的电位为VDD，所以在此阶段，第三晶体管T3也保持导通。第三晶体管T3产生的驱动电流可以根据以下公式得出：
I＝0.5μCox*(W/L)*(Vgs-Vth) 2
＝0.5μCox*(W/L)*((Vdata+Vth-VDD)-Vth) 2
＝0.5μCox*(W/L)*(Vdata-VDD) 2
其中，μ表示载流子迁移率，Cox表示单位面积栅极电容量，W表示第三晶体管沟道的宽度，L表示第三晶体管沟道的长度，Vgs表示第三晶体管栅源电压差，Vth表示第三晶体管的阈值电压，VDD表示第一电源端VDD提供的第一电源电压。从上述公式可以看出，流经发光元件OLED的驱动电流I LE不再与第三晶体管T3的阈值电压Vth有关，而只与控制该像素电路发光的灰度的数据信号Vdata有关，由此可以实现对该像素电路的补偿，解决了第三晶体管T3由于工艺制程及长时间的操作使用造成的阈值电压漂移的问题，消除其对驱动电流的影响，从而可以改善显示效果。
例如，图5所示的电路结构和图13所示的信号时序对应的发光阶段t5的工作原理与图5所示的电路结构和图12所示的信号时序对应的发光阶段t5的工作原理基本相同，重复之处在此不再赘述。
例如，图6所示的电路结构和图14所示的信号时序对应的发光阶段t5的工作原理与图5所示的电路结构和图12所示的信号时序对应的发光阶段t5的工作原理基本相同，重复之处在此不再赘述。
例如，图7所示的电路结构和图12所示的信号时序对应的发光阶段t5的工作原理与图5所示的电路结构和图12所示的信号时序对应的发光阶段t5的工作原理基本相同，重复之处在此不再赘述。
例如，图8所示的电路结构和图14所示的信号时序对应的发光阶段t5的工作原理与图 5所示的电路结构和图12所示的信号时序对应的发光阶段t5的工作原理基本相同，重复之处在此不再赘述。
例如，图9所示的电路结构和图13所示的信号时序对应的发光阶段t5的工作原理与图5所示的电路结构和图12所示的信号时序对应的发光阶段t5的工作原理基本相同，重复之处在此不再赘述。
例如，图10所示的电路结构和图15所示的信号时序对应的发光阶段t5的工作原理与图5所示的电路结构和图12所示的信号时序对应的发光阶段t5的工作原理基本相同，重复之处在此不再赘述。
需要说明的是，图12-15所示的信号时序图是示意性的，对于本公开的实施例提供的像素电路，其工作时的信号时序可以根据实际需要而定，本公开对此不作限制。
例如，在上述像素电路的驱动方法中，在发光阶段t5，还可以对第四节点N4(发光元件的第一极，例如阳极)进行脉冲宽度调制(PWM)复位。例如，在像素单元显示低灰阶时，往往会借助高频PWM进行亮度的降低；然而，在本公开的实施例中，可以在低频时增加PWM Anode刷新功能，从而可以对低频闪烁(Flicker)有极大的改善。例如，如图16所示(No Anode Reset对应于不进行阳极PWM复位的情形，Anode Reset对应于进行阳极PWM复位的情形)，通过增加Anode(阳极)刷新的频率可以极大的提高低灰阶、低频的闪烁，使得人眼能够更佳的观看效果。
本公开的实施例提供的像素电路的驱动方法的技术效果可以参考上述实施例中关于像素电路10的相应描述，在此不再赘述。
本公开至少一些实施例还提供一种显示面板，该显示面板包括阵列排布的多个像素单元，每个像素单元包括本公开任一实施例提供的像素电路。
图17为本公开至少一些实施例提供的一种显示面板的示意框图。如图17所示，显示面板11设置在显示装置1中，并与栅极驱动器12、定时控制器13和数据驱动器14电连接。该显示面板11包括根据多条栅线GL和多条数据线DL交叉限定的像素单元P；栅极驱动器12用于驱动多条栅线GL；数据驱动器14用于驱动多条数据线DL；定时控制器13用于处理从显示装置1外部输入的图像数据RGB、向数据驱动器14提供处理的图像数据RGB以及向栅极驱动器12和数据驱动器14输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器12和数据驱动器14进行控制。
例如，该显示面板11包括阵列排布的多个像素单元P，该像素单元P包括上述任一实施例提供的像素电路10以及发光元件900。如图17所示，显示面板11还包括多条栅线GL和多条数据线DL。例如，该多条栅线对应连接每行像素单元的像素电路10以提供各个控制信号，如第一扫描信号SN1、第二扫描信号SN2、第一发光控制信号EM1、第二发光控制信号EM2、第一复位控制信号RS1、第二复位控制信号RS2和传输控制信号TC。例如，在部分控制信号为同一信号的情况下，可以使用同一栅线与每行像素单元10中的相应控制信号端连接以提供该同一信号，从而可以减少栅线的数量，节省显示面板的布局空间，有 利于实现高分辨率显示面板的开发。
例如，如图10所示，每个像素单元P可以连接五条栅线GL(参考图12-15所示的信号时序，第一扫描信号SN1、第二扫描信号SN2、第一发光控制信号EM1、第二发光控制信号EM2、第一复位控制信号RS1、第二复位控制信号RS2和传输控制信号TC中有两对控制信号可以分别共用同一条栅线)、一条数据线DL、用于提供第一电源电压VDD的第一电源电压线、用于提供第二电源电压VSS的第二电源电压线、用于提供第一初始化电压Vinit1的第一初始化电压线和用于提供第二初始化电压Vinit2的第二初始化电压线。例如，第一电源电压线或第二电压线可以用相应的板状或网状公共电极(例如公共阳极或公共阴极)替代。需要说明的是，在图17中仅示出了部分的像素单元P、栅线GL、数据线DL。
例如，每一列像素单元对应的数据线DL和本列像素单元P的像素电路10中的数据写入电路200连接以提供数据信号。
例如，部分控制信号可以复用于例如不同行的像素单元，从而简化显示面板周围的布局空间，有利于实现高分辨率显示面板的开发。例如，对于一行像素单元而言，用于控制本行像素单元的像素电路10中的第一发光控制电路400的第一发光控制信号EM1还可以用于控制上一行像素单元的像素电路10中的第二发光控制电路500，即作为上一行像素单元的像素电路10中的第二发光控制信号EM2；同样地，用于控制本行像素单元的像素电路10中的第二发光控制电路500的第二发光控制信号EM2还可以用于控制下一行像素单元的像素电路10中的第一发光控制电路400，即作为下一行像素单元的像素电路10中的第一发光控制信号EM1。需要说明的是，本公开的实施例包括但不限于此。
例如，栅极驱动器12根据源自定时控制器13的多个扫描控制信号GCS向多个栅线GL提供多个控制信号。该多个控制信号例如包括第一扫描信号SN1、第二扫描信号SN2、第一发光控制信号EM1、第二发光控制信号EM2、第一复位控制信号RS1、第二复位控制信号RS2和传输控制信号TC。这些控制信号通过多条栅线GL提供给每个像素单元P。
例如，数据驱动器14使用参考伽玛电压根据源自定时控制器13的多个数据控制信号DCS将从定时控制器13输入的数字图像数据RGB转换成数据信号。数据驱动器14向多条数据线DL提供转换的数据信号。
例如，定时控制器13对外部输入的图像数据RGB进行处理以匹配显示面板11的大小和分辨率，然后向数据驱动器14提供处理的图像数据。定时控制器13使用从显示装置外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器13分别向栅极驱动器12和数据驱动器14提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器12和数据驱动器14的控制。
例如，数据驱动电器14可以与多条数据线DL连接，以提供数据信号Vdata；同时还可以与多条第一电源电压线、多条第二电源电压线、多条第一初始化电压线和多条第二初始化电压线连接以分别提供第一电源电压VDD、第二电源电压VSS、第一初始化电压Vinit1 和第二初始化电压Vinit2。
例如，栅极驱动器12和数据驱动器14可以实现为半导体芯片。例如，栅极驱动器12还可以实现为栅极驱动电路并直接集成在显示面板上构成GOA(Gate driver On Array)。例如，该显示装置1还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，本实施例提供的显示面板11可以实现逐行扫描。需要说明的是，在逐行扫描过程中，各个控制信号(第一扫描信号SN1、第二扫描信号SN2、第一发光控制信号EM1、第二发光控制信号EM2、第一复位控制信号RS1、第二复位控制信号RS2和传输控制信号TC)都是根据时序信号逐行施加的；每行像素单元的驱动过程可以参考前述像素电路的驱动方法的相关描述，在此不再重复赘述。
例如，本实施例提供的显示面板11可以应用于电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
本公开的实施例提供的显示面板的技术效果可以参考上述实施例中关于像素电路10的相应描述，在此不再赘述。
对于本公开，有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种像素电路，包括：驱动电路、数据写入电路、补偿控制电路、储能电路、第一发光控制电路、第二发光控制电路、第一初始化电路、第二初始化电路和传输电路；其中，
    所述驱动电路包括控制端、第一端和第二端，且被配置为控制流经所述第一端和所述第二端的用于驱动发光元件发光的驱动电流；
    所述数据写入电路被配置为在第一扫描信号的控制下将数据信号写入所述驱动电路的第一端；
    所述补偿控制电路被配置为在第二扫描信号的控制下对所述驱动电路进行补偿；
    所述储能电路被配置为存储所述驱动电路的控制端的电压；
    所述第一发光控制电路被配置为在第一发光控制信号的控制下将第一电源端的第一电源电压施加至所述驱动电路的第一端；
    所述第二发光控制电路被配置为在第二发光控制信号的控制下将所述驱动电流施加至所述发光元件的第一极；
    所述第一初始化电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至所述驱动电路的控制端；
    所述传输电路被配置为在传输控制信号的控制下传输所述第一初始化电压；
    所述第二初始化电路被配置为在第二复位控制信号的控制下将第二初始化电压施加至所述发光元件的第一极；
    其中，所述第二发光控制电路还被配置为在所述第二发光控制信号的控制下将所述发光元件的第一极的所述第二初始化电压传输至所述驱动电路的第二端，或者，
    所述第一初始化电路和所述传输电路共同被配置为将所述第一初始化电压施加至所述驱动电路的控制端，所述补偿控制电路还被配置为在所述第二扫描信号的控制下将所述驱动电路的控制端的所述第一初始化电压传输至所述驱动电路的第二端，或者，
    所述第一初始化电路和所述传输电路共同被配置为将所述第一初始化电压施加至所述驱动电路的第二端，所述补偿控制电路还被配置为在所述第二扫描信号的控制下将所述驱动电路的第二端的所述第一初始化电压传输至所述驱动电路的控制端。
  2. 根据权利要求1所述的像素电路，其中，所述驱动电路包括第三晶体管；
    所述第三晶体管的栅极作为所述驱动电路的控制端，所述第三晶体管的第一极作为所述驱动电路的第一端，所述第三晶体管的第二极作为所述驱动电路的第二端。
  3. 根据权利要求2所述的像素电路，其中，所述数据写入电路包括第四晶体管；
    所述第四晶体管的栅极和第一扫描信号端连接以接收所述第一扫描信号，所述第四晶体管的第一极和数据信号端连接以接收所述数据信号，所述第四晶体管的第二极和所述驱动电路的第一端连接。
  4. 根据权利要求3所述的像素电路，其中，所述补偿控制电路包括第二晶体管，所述 储能电路包括存储电容，
    所述第二晶体管的栅极和第二扫描信号端连接以接收所述第二扫描信号，所述第二晶体管的第一极与所述驱动电路的第二端连接，所述第二晶体管的第二极与所述驱动电路的控制端连接，
    所述存储电容的第一端与所述驱动电路的控制端耦接，所述存储电容的第二端与所述第一电源端耦接。
  5. 根据权利要求4所述的像素电路，其中，所述第二晶体管为N型氧化物薄膜晶体管，所述N型氧化物薄膜晶体管包括依次层叠且相互绝缘的第一金属层、有源层和第二金属层，
    在所述有源层的延伸方向上，所述第二金属层的宽度不大于所述第一金属层的宽度；
    所述第二金属层和所述第二扫描信号端连接以作为所述第二晶体管的栅极，或者，所述第二金属层和所述第一金属层均与所述第二扫描信号端连接以同时作为所述第二晶体管的栅极；
    所述有源层包括被所述第一金属层覆盖的沟道区，所述N型氧化物薄膜晶体管的沟道区的宽长比的取值范围为[1/2,7/8]。
  6. 根据权利要求4或5所述的像素电路，其中，所述第一发光控制电路包括第五晶体管，
    所述第五晶体管的栅极和第一发光控制信号端连接以接收所述第一发光控制信号，所述第五晶体管的第一极和所述第一电源端连接以接收所述第一电源电压，所述第五晶体管的第二极和所述驱动电路的第一端连接。
  7. 根据权利要求6所述的像素电路，其中，所述第二发光控制电路包括第六晶体管，
    所述第六晶体管的栅极和第二发光控制信号端连接以接收所述第二发光控制信号，所述第六晶体管的第一极和所述驱动电路的第二端连接，所述第六晶体管的第二极和所述发光元件的第一极连接。
  8. 根据权利要求7所述的像素电路，其中，所述第二初始化电路包括第七晶体管，
    所述第七晶体管的栅极和第二复位控制信号端连接以接收所述第二复位控制信号，所述第七晶体管的第一极和第二初始化电压端连接以接收所述第二初始化电压，所述第七晶体管的第二极和所述发光元件的第一极连接。
  9. 根据权利要求8所述的像素电路，其中，所述第一初始化电路包括第一晶体管，所述传输电路包括第八晶体管，
    所述第一晶体管的栅极和第一复位控制信号端连接以接收所述第一复位控制信号，所述第一晶体管的第一极和第一初始化电压端连接以接收所述第一初始化电压，所述第一晶体管的第二极和所述第八晶体管的第一极连接，
    所述第八晶体管的栅极和所述传输控制信号端连接以接收所述传输控制信号，所述第八晶体管的第二极和所述驱动电路的控制端连接。
  10. 根据权利要求9所述的像素电路，其中，所述第二晶体管和所述第七晶体管均为N 型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；
    所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；
    所述第二复位控制信号与所述第一发光控制信号为同一控制信号，所述传输控制信号与所述第二发光控制信号为同一控制信号。
  11. 根据权利要求9所述的像素电路，其中，所述第二晶体管为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；
    所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；
    所述第二复位控制信号与所述第一复位控制信号为同一控制信号，所述传输控制信号与所述第一发光控制信号或者所述第二发光控制信号为同一控制信号。
  12. 根据权利要求8所述的像素电路，其中，所述第一初始化电路包括第一晶体管，所述传输电路包括第八晶体管，
    所述第一晶体管的栅极和第一复位控制信号端连接以接收所述第一复位控制信号，所述第一晶体管的第一极和所述第二晶体管的第二极连接，所述第一晶体管的第二极和所述驱动电路的控制端连接，
    所述第八晶体管的栅极和所述传输控制信号端连接以接收所述传输控制信号，所述第八晶体管的第一极和第一初始化电压端连接以接收所述第一初始化电压，所述第八晶体管的第二极和所述第一晶体管的第一极连接，
    所述第二晶体管的第二极通过所述第一晶体管与所述驱动电路的控制端连接。
  13. 根据权利要求12所述的像素电路，其中，所述第二晶体管和所述第七晶体管均为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；
    所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；
    所述第二复位控制信号与所述第一发光控制信号为同一控制信号，所述传输控制信号与所述第二发光控制信号为同一控制信号。
  14. 根据权利要求12所述的像素电路，其中，所述第二晶体管为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；
    所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；
    所述第二复位控制信号与所述第一复位控制信号为同一控制信号，所述传输控制信号 与所述第二发光控制信号为同一控制信号。
  15. 根据权利要求8所述的像素电路，其中，所述第一初始化电路包括第一晶体管，所述传输电路包括第八晶体管，
    所述第一晶体管的栅极和第一复位控制信号端连接以接收所述第一复位控制信号，所述第一晶体管的第一极和第一初始化电压端连接以接收所述第一初始化电压，所述第一晶体管的第二极和所述第八晶体管的第一极连接，
    所述第八晶体管的栅极和所述传输控制信号端连接以接收所述传输控制信号，所述第八晶体管的第二极和所述驱动电路的第二端连接。
  16. 根据权利要求15所述的像素电路，其中，所述第二晶体管和所述第七晶体管均为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；
    所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；
    所述第二复位控制信号与所述第二发光控制信号为同一控制信号，所述传输控制信号与所述第一发光控制信号为同一控制信号。
  17. 根据权利要求15所述的像素电路，其中，所述第二晶体管为N型氧化物薄膜晶体管，所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第一晶体管和所述第八晶体管均为P型薄膜晶体管；
    所述第一晶体管的沟道区的宽长比的取值范围为[1/3,3/4]，所述第八晶体管的沟道区的宽长比的取值范围为[1/3,3/4]；
    所述第二复位控制信号与所述第一扫描信号为同一控制信号，所述传输控制信号与所述第一发光控制信号为同一控制信号。
  18. 一种显示面板，包括：阵列排布的多个像素单元；其中，
    所述多个像素单元中的每个像素单元包括根据权利要求1-17任一项所述的像素电路。
  19. 一种根据权利要求1所述的像素电路的驱动方法，包括：复位阶段；其中，在所述复位阶段，
    输入所述第二发光控制信号、所述第一复位控制信号、所述第二复位控制信号和所述传输控制信号，开启所述第二发光控制电路、所述第一初始化电路、所述第二初始化电路和所述传输电路，通过所述第一初始化电路和所述传输电路将所述第一初始化电压施加至所述驱动电路的控制端以对所述驱动电路的控制端进行复位，通过所述第二初始化电路将所述第二初始化电压施加至所述发光元件的第一极以对所述发光元件进行复位，通过所述第二初始化电路和所述第二发光控制电路将所述第二初始化电压施加至所述驱动电路的第二端以对所述驱动电路的第二端进行复位；或者
    输入所述第二扫描信号、所述第一复位控制信号、所述第二复位控制信号和所述传输控制信号，开启所述补偿控制电路、所述第一初始化电路、所述第二初始化电路和所述传 输电路，通过所述第一初始化电路和所述传输电路将所述第一初始化电压施加至所述驱动电路的第二端以对所述驱动电路的第二端进行复位，通过所述第一初始化电路、所述传输电路和所述补偿控制电路将所述第一初始化电压施加至所述驱动电路的控制端以对所述驱动电路的控制端进行复位，通过所述第二初始化电路将所述第二初始化电压施加至所述发光元件的第一极以对所述发光元件进行复位；或者
    输入所述第二扫描信号、所述第一复位控制信号、所述第二复位控制信号和所述传输控制信号，开启所述补偿控制电路、所述第一初始化电路、所述第二初始化电路和所述传输电路，通过所述第一初始化电路和所述传输电路将所述第一初始化电压施加至所述驱动电路的控制端以对所述驱动电路的控制端进行复位，通过所述第一初始化电路、所述传输电路和所述补偿控制电路将所述第一初始化电压施加至所述驱动电路的第二端以对所述驱动电路的第二端进行复位，通过所述第二初始化电路将所述第二初始化电压施加至所述发光元件的第一极以对所述发光元件进行复位。
  20. 根据权利要求19所述的驱动方法，还包括：数据写入和补偿阶段、保持阶段和发光阶段；其中，
    在所述数据写入和补偿阶段，输入所述第一扫描信号和所述第二扫描信号，开启所述数据写入电路、所述驱动电路和所述补偿控制电路，通过所述数据写入电路将所述数据信号写入所述补偿控制电路，通过所述补偿控制电路对所述驱动电路进行补偿；
    在所述保持阶段，输入所述第二扫描信号，关闭所述补偿控制电路，通过所述储能电路保持所述驱动电路的控制端的电压；
    在所述发光阶段，输入所述第一发光控制信号和所述第二发光控制信号，开启所述第一发光控制电路、所述第二发光控制电路和所述驱动电路，通过所述第一发光控制电路将所述第一电源电压施加所述驱动电路的第一端以使所述驱动电路根据所述驱动电路的控制端的电压产生所述驱动电流，通过所述第二发光控制电路将所述驱动电流施加至所述发光元件以使所述发光元件发光。
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