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WO2024197776A1 - 像素电路、驱动方法、显示基板、显示面板和显示装置 - Google Patents

像素电路、驱动方法、显示基板、显示面板和显示装置 Download PDF

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Publication number
WO2024197776A1
WO2024197776A1 PCT/CN2023/085358 CN2023085358W WO2024197776A1 WO 2024197776 A1 WO2024197776 A1 WO 2024197776A1 CN 2023085358 W CN2023085358 W CN 2023085358W WO 2024197776 A1 WO2024197776 A1 WO 2024197776A1
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WO
WIPO (PCT)
Prior art keywords
control
circuit
line
electrically connected
transistor
Prior art date
Application number
PCT/CN2023/085358
Other languages
English (en)
French (fr)
Inventor
肖丽
郑皓亮
玄明花
赵蛟
郭玉珍
张晨阳
崔晓荣
高立鹏
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202380008525.7A priority Critical patent/CN119096290A/zh
Priority to PCT/CN2023/085358 priority patent/WO2024197776A1/zh
Priority to CN202480000630.0A priority patent/CN119096286B/zh
Priority to PCT/CN2024/084436 priority patent/WO2024199361A1/zh
Publication of WO2024197776A1 publication Critical patent/WO2024197776A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, a display substrate, a display panel and a display device.
  • the related pixel circuit including a micro light-emitting diode or a mini light-emitting diode adopts a first data line and a second data line, wherein the first data line is used to provide a light-emitting time data voltage, and the second data line is used to provide a display data voltage, and the first data line and the second data line are arranged between two columns of pixel circuits, so that the number of side signals is large, and due to the coupling influence of the signal on the first data line and the signal on the second data line in the charging compensation stage, the voltage jump caused by the display data voltage in the charging compensation stage will cause column-wise defects in the related pixel circuit.
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, a first light-emitting control circuit, a first control circuit, and a second control circuit;
  • the driving circuit is used to generate a driving current for driving the light-emitting element
  • the first light emitting control circuit is electrically connected to the first control node, the first end of the driving circuit and the light emitting element respectively, and is used to control the connection between the first end of the driving circuit and the light emitting element under the control of the potential of the first control node;
  • the first control circuit is electrically connected to the data line, the first reset control line, the first light-emitting control line, the first control node and the second control node respectively, and is used to provide the first control voltage provided by the data line to the second control node under the control of the first reset control signal provided by the first reset control line, and to control the first light-emitting control line to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node;
  • the second control circuit is electrically connected to the data line, the second reset control line, the second light-emitting control line, the first control node and the third control node respectively, and is used to write the second control voltage provided by the data line into the control node under the control of the second reset control signal provided by the second reset control line.
  • the third control node under the control of the potential of the third control node, controls the second light emitting control line to provide a second light emitting control signal to the first control node.
  • the first control circuit includes a first write control circuit, a first energy storage circuit and a second write control circuit;
  • the first write control circuit is electrically connected to the first reset control line, the data line and the second control node respectively, and is used to provide the first control voltage provided by the data line to the second control node under the control of the first reset control signal;
  • the first energy storage circuit is electrically connected to the second control node and is used for energy storage circuit
  • the second write control circuit is electrically connected to the second control node, the first light-emitting control line and the first control node respectively, and is used to control the first light-emitting control line to provide a first light-emitting control signal to the first control node under the control of the potential of the second control node.
  • the second control circuit includes a third write control circuit, a second energy storage circuit and a fourth write control circuit;
  • the third write control circuit is electrically connected to the second reset control line, the data line and the third control node respectively, and writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal;
  • the second energy storage circuit is electrically connected to the third control node and is used to store electrical energy
  • the fourth write control circuit is electrically connected to the third control node, the second light-emitting control line and the first control node respectively, and is used to control the second light-emitting control line to provide a second light-emitting control signal to the first control node under the control of the potential of the third control node.
  • the first write control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second write control circuit includes a second transistor;
  • the gate of the first transistor is electrically connected to the first reset control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second control node;
  • the first plate of the first capacitor is electrically connected to the second control node, and the second plate of the first capacitor is electrically connected to the first initial voltage line;
  • the gate of the second transistor is electrically connected to the second control node, the first electrode of the second transistor is electrically connected to the first light emitting control line, and the second electrode of the second transistor is electrically connected to the first The control nodes are electrically connected.
  • the third write control circuit includes a third transistor
  • the second energy storage circuit includes a second capacitor
  • the fourth write control circuit includes a fourth transistor
  • the gate of the third transistor is electrically connected to the second reset control line, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the third control node;
  • the first plate of the second capacitor is electrically connected to the third control node, and the second plate of the second capacitor is electrically connected to the second initial voltage line;
  • a gate of the fourth transistor is electrically connected to the third control node, a first electrode of the fourth transistor is electrically connected to the second light emitting control line, and a second electrode of the fourth transistor is electrically connected to the first control node.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second light emitting control circuit
  • the second light-emitting control circuit is electrically connected to the first light-emitting control line, the power supply voltage line and the second end of the driving circuit respectively, and is used to control the connection between the power supply voltage line and the second end of the driving circuit under the control of the first light-emitting control signal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit, a compensation control circuit and a third energy storage circuit;
  • the data writing circuit is electrically connected to the scan line, the data line and the second end of the driving circuit respectively, and is used to write the display data voltage provided by the data line into the second end of the driving circuit under the control of the scan signal provided by the scan line;
  • the compensation control circuit is electrically connected to the scan line, the control end of the drive circuit and the first end of the drive circuit respectively, and is used to control the control end of the drive circuit to be connected to the first end of the drive circuit under the control of the scan signal;
  • the third energy storage circuit is electrically connected to the control end of the driving circuit and is used for storing electric energy.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first reset circuit
  • the first reset circuit is electrically connected to the third reset control line, the third initial voltage line and the control end of the drive circuit respectively, and is used to write the third initial voltage provided by the third initial voltage line into the control end of the drive circuit under the control of the third reset control signal provided by the third reset control line.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit
  • the second reset circuit is electrically connected to the fourth reset control line, the fourth initial voltage line and the first electrode of the light-emitting element respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage line into the first electrode of the light-emitting element under the control of the fourth reset control signal provided by the fourth reset control line;
  • the second electrode of the light emitting element is electrically connected to the first voltage line.
  • the third reset control line is the first reset control line or the second reset control line
  • the fourth reset control line is the first reset control line or the second reset control line.
  • the second light emitting control circuit includes a fifth transistor
  • a gate of the fifth transistor is electrically connected to the first light emitting control line, a first electrode of the fifth transistor is electrically connected to the power supply voltage line, and a second electrode of the fifth transistor is electrically connected to the second end of the driving circuit.
  • the data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor; and the driving circuit includes a driving transistor;
  • the gate of the sixth transistor is electrically connected to the scan line, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor;
  • the gate of the seventh transistor is electrically connected to the scan line, the first electrode of the seventh transistor is electrically connected to the gate of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the driving transistor;
  • the first plate of the third capacitor is electrically connected to the gate of the driving transistor, and the second plate of the third capacitor is electrically connected to the power supply voltage line.
  • the first reset circuit includes an eighth transistor
  • the gate of the eighth transistor is electrically connected to the third reset control line, the first electrode of the eighth transistor is electrically connected to the third initial voltage line, and the second electrode of the eighth transistor is electrically connected to the control terminal of the driving circuit.
  • the second reset circuit includes a ninth transistor
  • the gate of the ninth transistor is electrically connected to the fourth reset control line, and the ninth transistor
  • the first electrode of the transistor is electrically connected to the fourth initial voltage line
  • the second electrode of the ninth transistor is electrically connected to the first electrode of the light emitting element.
  • the pixel circuit described in the embodiment of the present disclosure includes a multiplexing control circuit
  • the multiplexing control circuit is electrically connected to the multiplexing control terminal, the voltage output terminal of the source driver and the data line respectively, and is used to control the connection between the voltage output terminal and the data line under the control of the multiplexing control signal provided by the multiplexing control terminal.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit, wherein the display phase includes a first writing phase and a second writing phase; the driving method includes:
  • the first control circuit provides the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether to provide the first light emitting control signal to the first control node under the control of the potential of the second control node;
  • the second control circuit writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal, and the second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.
  • the driving method described in at least one embodiment of the present disclosure includes:
  • the first control circuit controls the first light-emitting control signal to be provided to the first control node under the control of the potential of the second control node
  • the second control circuit controls the second light-emitting control signal to be stopped from being provided to the first control node under the control of the potential of the third control node
  • the first control circuit stops controlling the provision of the first light-emitting control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls the provision of the second light-emitting control signal to the first control node under the control of the potential of the third control node.
  • an embodiment of the present disclosure provides a display substrate, including a base substrate and a plurality of rows and columns of the above-mentioned pixel circuits arranged on the base substrate.
  • the pixel circuits in the same column are arranged between two columns of data lines; the data lines extend along the first direction;
  • the pixel circuit in the ath row is arranged between the scan line in the ath row and the first voltage line in the ath row, where a is a positive integer. number;
  • the a-th row of scan lines and the a-th row of first voltage lines extend along a second direction;
  • the first direction and the second direction intersect.
  • an embodiment of the present disclosure provides a display panel, comprising the above-mentioned display substrate.
  • the display panel described in at least one embodiment of the present disclosure further includes a source driver, a plurality of columns of data lines and a multiplexing circuit;
  • a plurality of pixel circuits located in the same column are electrically connected to the data line in the same column;
  • the multiplexing circuit is electrically connected to multiple voltage output terminals, multiple multiplexing control terminals and the multiple columns of data lines of the source driver respectively, and is used to write the voltage signal provided by the source driver through its voltage output terminal into the data line under the control of the multiplexing control signal provided by the multiplexing control terminal.
  • the multiplexing circuit is electrically connected to N multiplexing control terminals respectively, and the multiplexing circuit includes M multiplexing sub-circuits, where N and M are integers greater than 1;
  • Each of the multiplexing sub-circuits is electrically connected to the voltage output terminal of the source driver, the N multiplexing control terminals and the N columns of data lines, and is used to control the voltage signal provided by the voltage output terminal to be transmitted to the nth data line in the N columns of data lines under the control of the nth multiplexing control signal provided by the nth multiplexing control terminal;
  • n is a positive integer less than or equal to N.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned display panel, wherein a display period includes a first writing time period and a second writing time period; the first writing time period includes a first data writing time period and a second data writing time period, and the second writing time period includes a third data writing time period and a fourth data writing time period; the driving method includes:
  • the multiplexing circuit writes the first control voltage provided by the source driver through its voltage output terminal into the data line under the control of the reset control signal;
  • the first control circuit provides the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether to provide the first light emitting control signal to the first control node under the control of the potential of the second control node;
  • the multiplexing circuit writes the second control voltage provided by the source driver through its voltage output terminal into the data line under the control of the reset control signal;
  • the second control circuit writes the second control voltage provided by the data line to the third control node under the control of the second reset control signal, and the second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.
  • the first data writing time period and the second data writing time period are set successively, and the third data writing time period and the fourth data writing time period are set successively; or,
  • the first data writing time period is included in the second data writing time period, and the third data writing time period is included in the fourth data writing time period.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned display panel.
  • FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG4 of the present disclosure.
  • FIG6 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG4 of the present disclosure.
  • FIG. 7 is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure.
  • FIG8A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG8B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 9 is a layout diagram of at least one embodiment of the pixel circuit shown in FIG. 4 ;
  • FIG10 is a layout diagram of the first gate metal layer in FIG9 ;
  • FIG11 is a layout diagram of the semiconductor layer in FIG9;
  • FIG12 is a layout diagram of the second gate metal layer in FIG9;
  • FIG13 is a layout diagram of the source/drain metal layer in FIG9 ;
  • FIG14 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG15 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG16 is a circuit diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG17 is a timing diagram of operation of at least one embodiment of the display panel shown in FIG16 of the present disclosure.
  • FIG18 is a timing diagram of operation of at least one embodiment of the display panel shown in FIG16 of the present disclosure.
  • FIG19 is a timing diagram of operation of at least one embodiment of the display panel shown in FIG16 of the present disclosure.
  • FIG20 is a timing diagram of operation of at least one embodiment of the display panel shown in FIG16 of the present disclosure.
  • FIG. 21 is an operation timing diagram of a display panel according to at least one embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the pixel circuit includes a light emitting element E0, a driving circuit 10, a first light emitting control circuit 11, a first control circuit 12, and a second control circuit 13;
  • the driving circuit 10 is used to generate a driving current for driving the light emitting element E0;
  • the first light emitting control circuit 11 is electrically connected to the first control node N1, the first end of the driving circuit 10 and the light emitting element E0 respectively, and is used to control the connection between the first end of the driving circuit 10 and the light emitting element E0 under the control of the potential of the first control node N1;
  • the first control circuit 12 is electrically connected to the data line DT, the first reset control line RA, the first light emitting control line E1, the first control node N1 and the second control node N2, respectively, and is used to provide the first control voltage provided by the data line DT to the second control node N2 under the control of the first reset control signal provided by the first reset control line RA. Under the control of the potential of , controlling the first light emitting control line E1 to provide a first light emitting control signal to the first control node N1;
  • the second control circuit 13 is electrically connected to the data line DT, the second reset control line RB, the second light-emitting control line Hf, the first control node N1 and the third control node N3, respectively, and is used to write the second control voltage provided by the data line DT into the third control node N3 under the control of the second reset control signal provided by the second reset control line RB, and to control the second light-emitting control line Hf to provide a second light-emitting control signal to the first control node N1 under the control of the potential of the third control node N3.
  • only one data line is used to provide the display data voltage Data_I and the light-emitting time control data voltage Data_T in a time-sharing manner, which can reduce the number of side signals and solve the problem of grayscale signal loss when adding multiplexing transistors.
  • the integration of the display data voltage Data_I and the light-emitting time control data voltage Data_T also avoids the coupling effect of the two signals in the charging compensation stage, reduces the voltage jump caused by the display data voltage Data_I in the charging compensation stage, and thus solves the column-wise defect of the original pixel circuit.
  • the first control voltage and the second control voltage may be light emitting time control data voltages.
  • the light emitting element may be a Mini LED (mini light emitting diode) or a Micro LED (micro light emitting diode), but is not limited thereto.
  • the light emitting element may also be an organic light emitting diode.
  • At least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure is in operation.
  • the first light emitting control line E1 is controlled to provide a first light emitting control signal to the first control node N1, and different light emitting currents are generated by inputting different display data voltage values;
  • a light-emitting current + light-emitting time control method is adopted to provide the second light-emitting control signal on the second light-emitting control line Hf to the first control node N1.
  • the second light-emitting control signal is a high-frequency signal to reduce the flicker problem under low grayscale.
  • the display phase when in operation, may include a first writing phase and a second writing phase; the driving method includes:
  • the first control circuit 12 under the control of the first reset control signal, writes the data
  • the first control voltage provided by the data line DT is provided to the second control node N2, and the first control circuit 12 controls whether to provide the first light emitting control signal to the first control node N1 under the control of the potential of the second control node N2;
  • the second control circuit 13 writes the second control voltage provided by the data line DT into the third control node N3 under the control of the second reset control signal, and the second control circuit 13 controls whether to provide the second light-emitting control signal to the first control node N1 under the control of the potential of the third control node N3.
  • At least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure is in operation.
  • the first control circuit 12 controls the first light-emitting control signal to be provided to the first control node N1 under the control of the potential of the second control node N2
  • the second control circuit 13 controls the second light-emitting control signal to be stopped from being provided to the first control node N1 under the control of the potential of the third control node N3;
  • the first control circuit 12 stops controlling the provision of the first light-emitting control signal to the first control node N1 under the control of the potential of the second control node N2, and in the second writing stage, the second control circuit 13 controls the provision of the second light-emitting control signal to the first control node N1 under the control of the potential of the third control node N3.
  • the first control circuit includes a first write control circuit, a first energy storage circuit, and a second write control circuit;
  • the first write control circuit is electrically connected to the first reset control line, the data line and the second control node respectively, and is used to provide the first control voltage provided by the data line to the second control node under the control of the first reset control signal;
  • the first energy storage circuit is electrically connected to the second control node and is used for energy storage circuit
  • the second write control circuit is electrically connected to the second control node, the first light-emitting control line and the first control node respectively, and is used to control the first light-emitting control line to provide a first light-emitting control signal to the first control node under the control of the potential of the second control node.
  • the first control circuit may include a first write control circuit, a first energy storage circuit, and a second write control circuit.
  • the first write control circuit controls the first control voltage to be written into the first The second control node
  • the second write control circuit controls the first light emitting control signal to be written into the first control node.
  • the second control circuit includes a third write control circuit, a second energy storage circuit, and a fourth write control circuit;
  • the third write control circuit is electrically connected to the second reset control line, the data line and the third control node respectively, and writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal;
  • the second energy storage circuit is electrically connected to the third control node and is used to store electrical energy
  • the fourth write control circuit is electrically connected to the third control node, the second light-emitting control line and the first control node respectively, and is used to control the second light-emitting control line to provide a second light-emitting control signal to the first control node under the control of the potential of the third control node.
  • the second control circuit may include a third write control circuit, a second energy storage circuit and a fourth write control circuit, the third write control circuit controls writing the second control voltage into the third control node, and the fourth write control circuit controls providing the second light-emitting control signal to the first control node.
  • FIG. 2 based on at least one embodiment of the pixel circuit shown in FIG. 1 ,
  • the first control circuit includes a first write control circuit 21, a first energy storage circuit 22 and a second write control circuit 23;
  • the first write control circuit 21 is electrically connected to the first reset control line RA, the data line DT and the second control node N2 respectively, and is used to provide the first control voltage provided by the data line DT to the second control node N2 under the control of the first reset control signal;
  • the first energy storage circuit 22 is electrically connected to the second control node N2 and is used for storing electrical energy
  • the second write control circuit 23 is electrically connected to the second control node N2, the first light emitting control line E1 and the first control node N1 respectively, and is used to control the first light emitting control line E1 to provide a first light emitting control signal to the first control node N1 under the control of the potential of the second control node N2;
  • the second control circuit includes a third write control circuit 24, a second energy storage circuit 25 and a fourth write control circuit 26;
  • the third write control circuit 24 is electrically connected to the second reset control line RB, the data line DT and the third control node N3 respectively.
  • the second control voltage provided by the data line DT is written into the third control node N3;
  • the second energy storage circuit 25 is electrically connected to the third control node N3 and is used to store electrical energy
  • the fourth write control circuit 26 is electrically connected to the third control node N3, the second light-emitting control line Hf and the first control node N1 respectively, and is used to control the second light-emitting control line Hf to provide a second light-emitting control signal to the first control node N1 under the control of the potential of the third control node N3.
  • the first write control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second write control circuit includes a second transistor;
  • the gate of the first transistor is electrically connected to the first reset control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second control node;
  • the first plate of the first capacitor is electrically connected to the second control node, and the second plate of the first capacitor is electrically connected to the first initial voltage line;
  • a gate of the second transistor is electrically connected to the second control node, a first electrode of the second transistor is electrically connected to the first light emitting control line, and a second electrode of the second transistor is electrically connected to the first control node.
  • the third write control circuit includes a third transistor
  • the second energy storage circuit includes a second capacitor
  • the fourth write control circuit includes a fourth transistor
  • the gate of the third transistor is electrically connected to the second reset control line, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the third control node;
  • the first plate of the second capacitor is electrically connected to the third control node, and the second plate of the second capacitor is electrically connected to the second initial voltage line;
  • a gate of the fourth transistor is electrically connected to the third control node, a first electrode of the fourth transistor is electrically connected to the second light emitting control line, and a second electrode of the fourth transistor is electrically connected to the first control node.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second light emitting control circuit
  • the second light-emitting control circuit is electrically connected to the first light-emitting control line, the power supply voltage line and the second end of the driving circuit respectively, and is used to control the first light-emitting control signal to control the first light-emitting control line.
  • the source voltage line is connected to the second end of the driving circuit.
  • the pixel circuit may further include a second light emitting control circuit, which controls the connection between the power supply voltage line and the second end of the driving circuit under the control of the first light emitting control signal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit, a compensation control circuit and a third energy storage circuit;
  • the data writing circuit is electrically connected to the scan line, the data line and the second end of the driving circuit respectively, and is used to write the display data voltage provided by the data line into the second end of the driving circuit under the control of the scan signal provided by the scan line;
  • the compensation control circuit is electrically connected to the scan line, the control end of the drive circuit and the first end of the drive circuit respectively, and is used to control the control end of the drive circuit to be connected to the first end of the drive circuit under the control of the scan signal;
  • the third energy storage circuit is electrically connected to the control end of the driving circuit and is used for storing electric energy.
  • the pixel circuit may further include a data writing circuit, a compensation control circuit and a third energy storage circuit.
  • the data writing circuit under the control of a scanning signal, writes the display data voltage into the second end of the driving circuit.
  • the compensation control circuit under the control of a scanning signal, controls the control end of the driving circuit to be connected to the first end of the driving circuit to perform threshold voltage compensation control.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first reset circuit
  • the first reset circuit is electrically connected to the third reset control line, the third initial voltage line and the control end of the drive circuit respectively, and is used to write the third initial voltage provided by the third initial voltage line into the control end of the drive circuit under the control of the third reset control signal provided by the third reset control line.
  • the pixel circuit may further include a first reset circuit
  • the first reset circuit Under the control of the third reset control signal, the first reset circuit writes the third initial voltage into the control terminal of the drive circuit, so that the drive transistor included in the drive circuit can be turned on when the charging compensation phase begins.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit
  • the second reset circuit is electrically connected to the fourth reset control line, the fourth initial voltage line and the first electrode of the light emitting element respectively, and is used to provide a fourth reset control signal on the fourth reset control line Under the control of , writing the fourth initial voltage provided by the fourth initial voltage line into the first electrode of the light emitting element;
  • the second electrode of the light emitting element is electrically connected to the first voltage line.
  • the first voltage line may be a low voltage line, but is not limited thereto.
  • the pixel circuit may further include a second reset circuit; under the control of a fourth reset control signal, the second reset circuit writes a fourth initial voltage into the first electrode of the light-emitting element to control the light-emitting element not to emit light and clear the residual charge in the first electrode of the light-emitting element.
  • the third reset control line is the first reset control line or the second reset control line
  • the fourth reset control line is the first reset control line or the second reset control line.
  • the third reset control line may be the first reset control line or the second reset control line
  • the fourth reset control line may be the first reset control line or the second reset control line, so as to reduce the number of control lines used.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second light emitting control circuit 31, a data writing circuit 32, a compensation control circuit 33, a third energy storage circuit 34, a first reset circuit 35 and a second reset circuit 36;
  • the second light emitting control circuit 31 is electrically connected to the first light emitting control line E1, the power supply voltage line VDD and the second end of the driving circuit 10 respectively, and is used to control the connection between the power supply voltage line VDD and the second end of the driving circuit 10 under the control of the first light emitting control signal provided by the first light emitting control line E1;
  • the data writing circuit 32 is electrically connected to the scan line G1, the data line DT and the second end of the driving circuit 10 respectively, and is used to write the display data voltage provided by the data line DT into the second end of the driving circuit 10 under the control of the scan signal provided by the scan line G1;
  • the compensation control circuit 33 is electrically connected to the scan line G1, the control end of the drive circuit 10 and the first end of the drive circuit 10 respectively, and is used to control the control end of the drive circuit 10 to be connected to the first end of the drive circuit 10 under the control of the scan signal;
  • the third energy storage circuit 34 is electrically connected to the control end of the driving circuit 10 and is used for storing electric energy.
  • the first reset circuit 35 is connected to the first reset control line RA, the third initial voltage line I3 and The control end of the driving circuit 10 is electrically connected to write the third initial voltage provided by the third initial voltage line I3 into the control end of the driving circuit 10 under the control of the first reset control signal provided by the first reset control line RA;
  • the second reset circuit 36 is electrically connected to the first reset control line RA, the fourth initial voltage line I4 and the first electrode of the light emitting element E0 respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage line I4 into the first electrode of the light emitting element E0 under the control of the first reset control signal provided by the first reset control line RA;
  • the second electrode of the light emitting element E0 is electrically connected to the first voltage line.
  • the third reset control line is the first reset control line
  • the fourth reset control line is the first reset control line
  • the third reset control line and the fourth reset control line may both be second reset control lines, or the third reset control line is the first reset control line and the fourth reset control line is the second reset control line; or the third reset control line is the second reset control line and the fourth reset control line is the first reset control line.
  • the first initial voltage line, the second initial voltage line, the third initial voltage line and the fourth initial voltage line may be the same initial voltage line to reduce the number of initial voltage lines used.
  • the second light emitting control circuit includes a fifth transistor
  • a gate of the fifth transistor is electrically connected to the first light emitting control line, a first electrode of the fifth transistor is electrically connected to the power supply voltage line, and a second electrode of the fifth transistor is electrically connected to the second end of the driving circuit.
  • the data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor; and the driving circuit includes a driving transistor;
  • the gate of the sixth transistor is electrically connected to the scan line, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor;
  • the gate of the seventh transistor is electrically connected to the scan line, the first electrode of the seventh transistor is electrically connected to the gate of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the driving transistor;
  • the first plate of the third capacitor is electrically connected to the gate of the driving transistor, and the second plate of the third capacitor is electrically connected to the power supply voltage line.
  • the first reset circuit includes an eighth transistor
  • the gate of the eighth transistor is electrically connected to the third reset control line, the first electrode of the eighth transistor is electrically connected to the third initial voltage line, and the second electrode of the eighth transistor is electrically connected to the control terminal of the driving circuit.
  • the second reset circuit includes a ninth transistor
  • a gate of the ninth transistor is electrically connected to the fourth reset control line, a first electrode of the ninth transistor is electrically connected to the fourth initial voltage line, and a second electrode of the ninth transistor is electrically connected to a first electrode of the light emitting element.
  • the first write control circuit includes a first transistor M1
  • the first energy storage circuit includes a first capacitor C1
  • the second write control circuit includes a second transistor M2 ;
  • the gate of the first transistor M1 is electrically connected to the first reset control line RA, the source of the first transistor M1 is electrically connected to the data line DT, and the drain of the first transistor M1 is electrically connected to the second control node N2;
  • the first plate of the first capacitor C1 is electrically connected to the second control node N2, and the second plate of the first capacitor C1 is electrically connected to the initial voltage line I0; the initial voltage line I0 is used to provide an initial voltage Vinit;
  • the gate of the second transistor M2 is electrically connected to the second control node N2, the source of the second transistor M2 is electrically connected to the first light emitting control line E1, and the drain of the second transistor M2 is electrically connected to the first control node N1;
  • the third write control circuit includes a third transistor M3, the second energy storage circuit includes a second capacitor C2, and the fourth write control circuit includes a fourth transistor M4;
  • the gate of the third transistor M3 is electrically connected to the second reset control line RB, the source of the third transistor M3 is electrically connected to the data line DT, and the drain of the third transistor M3 is electrically connected to the third control node N3;
  • the first plate of the second capacitor C2 is electrically connected to the third control node N3, and the second plate of the second capacitor C2 is electrically connected to the initial voltage line I0;
  • a gate of the fourth transistor M4 is electrically connected to the third control node N3, a source of the fourth transistor M4 is electrically connected to the second light emitting control line Hf, and a drain of the fourth transistor M4 is electrically connected to the first control node N1;
  • the second light emitting control circuit includes a fifth transistor M5;
  • the gate of the fifth transistor M5 is electrically connected to the first light emitting control line E1, the source of the fifth transistor M5 is electrically connected to the power supply voltage line VDD, and the drain of the fifth transistor M5 is electrically connected to the source of the driving transistor M0;
  • the data writing circuit includes a sixth transistor M6, the compensation control circuit includes a seventh transistor M7, the third energy storage circuit includes a third capacitor C3; the driving circuit includes a driving transistor M0;
  • the gate of the sixth transistor M6 is electrically connected to the scan line G1, the source of the sixth transistor M6 is electrically connected to the data line DT, and the drain of the sixth transistor M6 is electrically connected to the drain of the driving transistor M0;
  • the gate of the seventh transistor M7 is electrically connected to the scan line G1, the source of the seventh transistor M7 is electrically connected to the gate of the driving transistor M0, and the drain of the seventh transistor M7 is electrically connected to the drain of the driving transistor M0;
  • the first plate of the third capacitor C3 is electrically connected to the gate of the driving transistor M0, and the second plate of the third capacitor C3 is electrically connected to the power supply voltage line VDD;
  • the first reset circuit includes an eighth transistor M8;
  • the gate of the eighth transistor M8 is electrically connected to the first reset control line RA, the source of the eighth transistor M8 is electrically connected to the initial voltage line I0, and the drain of the eighth transistor M8 is electrically connected to the gate of the driving transistor M0;
  • the second reset circuit includes a ninth transistor M9;
  • the gate of the ninth transistor M9 is electrically connected to the first reset control line RA, the source of the ninth transistor M9 is electrically connected to the initial voltage line I0, and the drain of the ninth transistor M9 is electrically connected to the anode of the micro light emitting diode ML;
  • the cathode of the micro light emitting diode ML is electrically connected to the low voltage line VSS;
  • the first light emitting control circuit includes a tenth transistor M10;
  • the gate of M10 is electrically connected to the first control node N1, and the source of M10 is electrically connected to the drain of M0.
  • the drain of M10 is electrically connected to the anode of ML.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the light emitting element is a micro light emitting diode ML, but the present invention is not limited thereto.
  • the gate of M8 may also be electrically connected to the second reset control line RB. In this case, in the second writing phase S2 , M8 is turned on to initialize the potential of the gate of M0 .
  • the gate signal of M6, the gate signal of M1, and the gate signal of M3 are separated to realize time-sharing writing of the display data voltage, the first control voltage, and the second control voltage.
  • the first control voltage and the second control voltage can be the luminous time control data voltage.
  • the display cycle includes a first writing stage S1 , a second writing stage S2 , a charging compensation stage S3 and a light emitting stage S4 which are successively arranged;
  • RA provides a low voltage signal
  • RB provides a high voltage signal
  • G1 provides a high voltage signal
  • EM and Hf provide high voltage signals
  • DT provides a first control voltage
  • M1 is turned on to write the first control voltage Data_T1 into the second control node N2.
  • the first control voltage is a low voltage signal
  • M2 is turned on to control the connection between E1 and the first control node N1;
  • the first control voltage is a high voltage signal, M2 is turned off, and C1 maintains the potential of the second control node N2;
  • RA In the first writing stage S1, RA provides a low voltage signal, M8 and M9 are turned on, and I0 provides an initial voltage Vinit to the gate of M0 and the anode of ML, so that at the beginning of the charge compensation stage, M0 can be turned on and control ML not to emit light, and clear the residual charge on the anode of ML;
  • RA provides a high voltage signal
  • RB provides a low voltage signal
  • G1 provides a high voltage signal
  • EM and Hf provide high voltage signals
  • DT provides a second control voltage
  • M3 is turned on to write the second control voltage Data_T2 into the third control node N3; when performing medium and high grayscale display, the second control voltage is a high voltage signal, and M4 is turned off; when performing low grayscale display, the second control voltage is a low voltage signal, M4 is turned on to control the connection between Hf and N1, and C2 maintains the third control node The potential of N3;
  • RA provides a high voltage signal
  • RB provides a high voltage signal
  • G1 provides a low voltage signal
  • EM and Hf provide a high voltage signal
  • DT provides a display data voltage Data_I
  • M6 and M7 are turned on, and the display data voltage Data_I is written into the source of M0, and the gate of M3 is connected to the drain of M3;
  • EM provides a low voltage signal
  • Hf provides a low voltage signal
  • N1 is connected to EM, and in the light-emitting stage S4, M3 drives ML to emit light;
  • N1 is connected to Hf, and when Hf outputs a low voltage signal, M3 drives ML to emit light.
  • the low-level pulse width of the first reset control signal provided by RA, the low-level pulse width of the second reset control signal provided by RB, and the low-level pulse width of the scan signal provided by G1 are equal. Therefore, the first reset control signal, the second reset control signal and the scan signal can be provided through a GOA (Gate On Array, array substrate row drive) circuit to reduce the number of GOA circuits used, which is conducive to achieving a narrow frame.
  • GOA Gate On Array, array substrate row drive
  • the low level pulse width of the first reset control signal provided by RA, the low level pulse width of the second reset control signal provided by RB, and the low level pulse width of the scan signal provided by G1 are adjustable, and the low level pulse widths may be inconsistent.
  • the low-level pulse width of the scan signal provided by G1 may be greater than or equal to 2 ⁇ s, so as to fully perform charging and threshold voltage compensation.
  • Figure 6 is a working timing diagram of at least one embodiment of the pixel circuit shown in Figure 4.
  • the difference between Figure 6 and Figure 5 is that the low-level pulse width of the scanning signal provided by G1 is longer, the low-level pulse width of the scanning signal provided by G1 is greater than the low-level pulse width of the first reset control signal provided by RSTA, and the low-level pulse width of the scanning signal provided by G1 is greater than the low-level pulse width of the second reset control signal provided by RSTB, so as to increase the charging compensation time and fully perform threshold voltage compensation.
  • the display cycle when at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure is in operation, the display cycle includes a first writing stage S1 , a second writing stage S2 , a charging compensation stage S3 , and a light emitting stage S4 which are successively arranged;
  • RA provides a high voltage signal
  • RB provides a low voltage signal
  • G1 provides a high voltage signal
  • EM and Hf provide high voltage signals
  • DT provides a first control voltage Data_T1
  • M1 is turned off
  • M3 is turned on
  • DT provides the first control voltage Data_T1 to the third control node N3
  • C2 maintains the potential of the third control node N3, when performing a medium-high grayscale display, the first control voltage Data_T1 is a high voltage signal, when performing a low grayscale display, the first control voltage Data_T1 is a low voltage signal, M4 is turned on, and the first control node N1 is connected to Hf;
  • RA provides a low voltage signal
  • RB provides a high voltage signal
  • G1 provides a high voltage signal
  • EM and Hf provide high voltage signals
  • DT provides a second control voltage Data_T2
  • M1 is turned on
  • M3 is turned off
  • DT provides the second control voltage Data_T2 to the second control node N2
  • C1 maintains the potential of the second control node N2
  • the second control voltage Data_T2 is a low voltage signal
  • M2 is turned on
  • the first control node N1 is connected to E1
  • the second control voltage Data_T2 is a high voltage signal
  • RA provides a high voltage signal
  • RB provides a high voltage signal
  • G1 provides a low voltage signal
  • EM and Hf provide a high voltage signal
  • DT provides a display data voltage Data_I
  • M6 and M7 are turned on, and the display data voltage Data_I is written into the source of M0, and the gate of M3 is connected to the drain of M3;
  • EM provides a low voltage signal
  • Hf provides a low voltage signal
  • N1 is connected to EM, and in the light-emitting stage S4, M3 drives ML to emit light;
  • N1 is connected to Hf, and when Hf outputs a low voltage signal, M3 drives ML to emit light.
  • the low level pulse width of the scanning signal provided by G1 is greater than the low level pulse width of the first reset control signal.
  • the low level pulse width of the scanning signal provided by G1 is greater than the low level pulse width of the second reset control signal, so that the charging compensation phase lasts for a long time and can fully compensate for the threshold voltage of the driving transistor.
  • the low level pulse width of the scanning signal provided by G1, the low level pulse width of the first reset control signal, and the low level pulse width of the second reset control signal can also be equal.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 8A of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure is that the gate of M8 and the gate of M9 are both electrically connected to the second reset control line RB.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a multiplexing control circuit
  • the multiplexing control circuit is electrically connected to the multiplexing control terminal, the voltage output terminal of the source driver and the data line respectively, and is used to control the connection between the voltage output terminal and the data line under the control of the multiplexing control signal provided by the multiplexing control terminal.
  • the pixel circuit may further include a multiplexing control circuit, which controls the voltage output terminal of the source driver to be electrically connected to the data line under the control of a multiplexing control signal, thereby reducing the number of voltage output terminals of the source driver.
  • a multiplexing control circuit which controls the voltage output terminal of the source driver to be electrically connected to the data line under the control of a multiplexing control signal, thereby reducing the number of voltage output terminals of the source driver.
  • the pixel circuit according to at least one embodiment of the present disclosure may further include a multiplexing control circuit 80 ;
  • the multiplexing control circuit 80 is electrically connected to the multiplexing control terminal MX, the voltage output terminal CH of the source driver SD, and the data line DT respectively, and is used to control the connection between the voltage output terminal CH and the data line DT under the control of the multiplexing control signal provided by the multiplexing control terminal MX.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display stage includes a first writing stage and a second writing stage; the driving method includes:
  • the first control circuit provides the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether to provide the first light emitting control signal to the first control node under the control of the potential of the second control node;
  • the second control circuit writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal, and the second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.
  • the first control circuit controls the first light-emitting control signal to be provided to the first control node under the control of the potential of the second control node
  • the second control circuit controls the second light-emitting control signal to be stopped from being provided to the first control node under the control of the potential of the third control node
  • the first control circuit stops controlling the provision of the first light-emitting control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls the provision of the second light-emitting control signal to the first control node under the control of the potential of the third control node.
  • the display substrate described in the embodiment of the present disclosure includes a base substrate and a plurality of rows and columns of the above-mentioned pixel circuits arranged on the base substrate.
  • pixel circuits located in the same column are arranged between two columns of data lines; the data lines extend along a first direction;
  • the pixel circuit of the ath row is arranged between the scan line of the ath row and the first voltage line of the ath row, where a is a positive integer;
  • the a-th row of scan lines and the a-th row of first voltage lines extend along a second direction;
  • the first direction and the second direction intersect.
  • the first direction may be a vertical direction
  • the second direction may be a horizontal direction, but is not limited thereto.
  • two columns of data lines are arranged between two adjacent columns of pixel circuits, one column of data lines is used to provide a light-emitting time data voltage, and the other column of data lines is used to provide a display data voltage.
  • only one column of data lines is arranged between two adjacent columns of pixel circuits.
  • Fig. 9 is a layout diagram of at least one embodiment of the pixel circuit shown in Fig. 4.
  • Fig. 10 is a layout diagram of the first gate metal layer in Fig. 9,
  • Fig. 11 is a layout diagram of the semiconductor layer in Fig. 9,
  • Fig. 12 is a layout diagram of the second gate metal layer in Fig. 9, and
  • Fig. 13 is a layout diagram of the source-drain metal layer in Fig. 9.
  • the first gate metal layer, the semiconductor layer, the second gate metal layer and the source-drain metal layer may be arranged in sequence along a direction away from the substrate.
  • the line labeled VSS is a low voltage line
  • the line labeled DT is a data line
  • the line labeled I0 is an initial voltage line
  • the line labeled RA is a first reset control line
  • the line labeled RB is a first reset control line.
  • Two reset control lines the one labeled E1 is the first light emitting control line
  • the one labeled G1 is the scanning line.
  • the second light emitting control line Hf may include a first light emitting control line portion Hf1 extending in a vertical direction and a second light emitting control line portion Hf2 extending in a horizontal direction which are electrically connected to each other.
  • VSS, I0, RB, RA, E1, VDD, and G1 all extend in the horizontal direction;
  • the first capacitor C1 and the second capacitor C2 are arranged between VSS and I0;
  • M3 is set between RB and I0;
  • M1, M8, M9, M4 and M2 are all set between RA and VDD;
  • C2b1 is the first plate portion of the second capacitor
  • C1b1 is the first plate portion of the first capacitor
  • C3b1 is the first plate portion of the third capacitor
  • G0a is the bottom gate of M0.
  • the active graphic labeled A0 is M0
  • the active graphic labeled A1 is M1
  • the active graphic labeled A2 is M2
  • the active graphic labeled A3 is M3
  • the active graphic labeled A4 is M4
  • the active graphic labeled A5 is M5
  • the active graphic labeled A6 is M6
  • the active graphic labeled A7 is M7
  • the active graphic labeled A8 is M8
  • the active graphic labeled A9 is M9
  • the active graphic labeled A10 is M10.
  • G0b is the top gate of G0
  • C1a is the first plate of the first capacitor
  • C2a is the first plate of the second capacitor
  • C3a is the first plate of the third capacitor.
  • C2b2 is the second plate portion of the second capacitor
  • C1b2 is the second plate portion of the first capacitor
  • C3b2 is the second plate portion of the third capacitor.
  • C1b1 is electrically connected to C1b2, C1b1 and C1b2 constitute the second electrode plate of C1, C2b1 is electrically connected to C2b2, C2b1 and C2b2 constitute the second electrode plate of C2, and C3b1 is electrically connected to C3b2, C3b1 and C3b2 constitute the second electrode plate of C3.
  • the display panel described in the embodiment of the present disclosure includes the above-mentioned display substrate.
  • the display panel described in at least one embodiment of the present disclosure further includes a source driver, a plurality of columns of data lines and Multiplexing circuits;
  • a plurality of pixel circuits located in the same column are electrically connected to the data line in the same column;
  • the multiplexing circuit is electrically connected to multiple voltage output terminals, multiple multiplexing control terminals and the multiple columns of data lines of the source driver respectively, and is used to write the voltage signal provided by the source driver through its voltage output terminal into the data line under the control of the multiplexing control signal provided by the multiplexing control terminal.
  • the display panel may further include a source driver, a plurality of columns of data lines and a multiplexing circuit. Under the control of a multiplexing control signal, the multiplexing circuit writes a voltage signal provided by the source driver through its voltage output terminal into the data line.
  • the display panel described in at least one embodiment of the present disclosure further includes a source driver SD, a multiplexing circuit 90, a first column data line DL1, a second column data line DL2, a third column data line DL3, a fourth column data line DL4, a fifth column data line DL5, a sixth column data line DL6, a seventh column data line DL7, an eighth column data line DL8, a ninth column data line DL9, a tenth column data line DL10, an eleventh column data line DL11, a twelfth column data line DL12, a thirteenth column data line DL13, a fourteenth column data line DL14, a fifteenth column data line DL15, a sixteenth column data line DL16, a seventeenth column data line DL17, and an eighteenth column data line DL18;
  • the source driver SD includes a first voltage output terminal CH1, a second voltage output terminal CH2 and a third voltage output terminal CH3;
  • the first voltage output terminal CH1, the second voltage output terminal CH2 and the third voltage output terminal CH3 are electrically connected to the input terminal of the multiplexing circuit 90 respectively;
  • the output end of the multiplexing circuit 90 is electrically connected to DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, DL12, DL13, DL14, DL15, DL16, DL17 and DL18 respectively;
  • the multiplexing circuit 90 is electrically connected to the first multiplexing control terminal MX1, the second multiplexing control terminal MX2, the third multiplexing control terminal MX3, the fourth multiplexing control terminal MX4, the fifth multiplexing control terminal MX5 and the sixth multiplexing control terminal MX6, respectively, and is used to control the connection or disconnection between each voltage output terminal and each data line under the control of the multiplexing control signal provided by each multiplexing control terminal.
  • the multiplexing circuit is electrically connected to N multiplexing control terminals respectively, and the multiplexing circuit includes M multiplexing sub-circuits, where N and M are integers greater than 1;
  • Each of the multiplexing sub-circuits is electrically connected to the voltage output terminal of the source driver, the N multiplexing control terminals and the N columns of data lines, and is used to control the voltage signal provided by the voltage output terminal to be transmitted to the nth data line in the N columns of data lines under the control of the nth multiplexing control signal provided by the nth multiplexing control terminal;
  • n is a positive integer less than or equal to N.
  • the multiplexing circuit when the multiplexing circuit is electrically connected to N multiplexing control terminals respectively, the multiplexing circuit may include M multiplexing sub-circuits; under the control of the nth multiplexing control signal, the multiplexing sub-circuit provides the voltage signal provided by the voltage output terminal of the source driver to the data line.
  • the multiplexing circuit includes a first multiplexing sub-circuit 101 , a second multiplexing sub-circuit 102 and a third multiplexing sub-circuit 103 ;
  • the first multiplexing sub-circuit 101 is electrically connected to the first multiplexing control terminal MX1, the second multiplexing control terminal MX2, the third multiplexing control terminal MX3, the fourth multiplexing control terminal MX4, the fifth multiplexing control terminal MX5 and the sixth multiplexing control terminal MX6, the first voltage output terminal CH1, the first column data line DL1, the fourth column data line DL4, the seventh column data line DL7, the tenth column data line DL10, the thirteenth column data line DL13 and the sixteenth column data line DL16, respectively, and is used to control the connection between CH1 and DL1 under the control of the first multiplexing control signal provided by MX1.
  • the connection between CH1 and DL4 is controlled; under the control of the third multiplexing control signal provided by MX3, the connection between CH1 and DL7 is controlled; under the control of the fourth multiplexing control signal provided by MX4, the connection between CH1 and DL10 is controlled; under the control of the fifth multiplexing control signal provided by MX5, the connection between CH1 and DL13 is controlled; under the control of the sixth multiplexing control signal provided by MX6, the connection between CH1 and DL16 is controlled;
  • the second multiplexing sub-circuit 102 is electrically connected to the first multiplexing control terminal MX1, the second multiplexing control terminal MX2, the third multiplexing control terminal MX3, the fourth multiplexing control terminal MX4, the fifth multiplexing control terminal MX5 and the sixth multiplexing control terminal MX6, the first voltage output terminal CH1, the second column data line DL2, the fifth column data line DL5, the eighth column data line DL8, the eleventh column data line DL11, the fourteenth column data line DL14 and the seventeenth column data line DL17, respectively, and is used to control the connection or disconnection between CH1 and DL2 under the control of the first multiplexing control signal provided by MX1, and control the connection or disconnection between CH1 and DL2 under the control of the second multiplexing control signal provided by MX2.
  • the connection between CH1 and DL8 is controlled to be connected or disconnected.
  • the connection between CH1 and DL11 is controlled to be connected or disconnected.
  • the connection between CH1 and DL14 is controlled to be connected or disconnected.
  • the connection between CH1 and DL17 is controlled to be connected or disconnected.
  • the third multiplexing sub-circuit 103 is electrically connected to the first multiplexing control terminal MX1, the second multiplexing control terminal MX2, the third multiplexing control terminal MX3, the fourth multiplexing control terminal MX4, the fifth multiplexing control terminal MX5 and the sixth multiplexing control terminal MX6, the first voltage output terminal CH1, the third column data line DL3, the sixth column data line DL6, the ninth column data line DL9, the twelfth column data line DL12, the fifteenth column data line DL15 and the eighteenth column data line DL18, respectively, and is used to control CH1 and DL3 under the control of the first multiplexing control signal provided by MX1.
  • CH1 and DL6 are controlled to be connected or disconnected.
  • CH1 and DL9 are controlled to be connected or disconnected.
  • CH1 and DL12 are controlled to be connected or disconnected.
  • CH1 and DL15 are controlled to be connected or disconnected.
  • CH1 and DL18 are controlled to be connected or disconnected.
  • the first multiplexing sub-circuit may include a first multiplexing transistor T1, a second multiplexing transistor T2, a third multiplexing transistor T3, a fourth multiplexing transistor T4, a fifth multiplexing transistor T5, and a sixth multiplexing transistor T6;
  • the gate of T1 is electrically connected to MX1, the source of T1 is electrically connected to CH1, and the drain of T1 is electrically connected to DL1;
  • the gate of T2 is electrically connected to MX2, the source of T2 is electrically connected to CH1, and the drain of T2 is electrically connected to DL4;
  • the gate of T3 is electrically connected to MX3, the source of T3 is electrically connected to CH1, and the drain of T3 is electrically connected to DL7;
  • the gate of T4 is electrically connected to MX4, the source of T4 is electrically connected to CH1, and the drain of T4 is electrically connected to DL10;
  • the gate of T5 is electrically connected to MX5, the source of T5 is electrically connected to CH1, and the drain of T5 is electrically connected to DL13;
  • the gate of T6 is electrically connected to MX6, the source of T6 is electrically connected to CH1, and the drain of T6 is electrically connected to DL16;
  • the second multiplexing sub-circuit may include a seventh multiplexing transistor T7, an eighth multiplexing transistor T8, a ninth multiplexing transistor T9, a tenth multiplexing transistor T10, an eleventh multiplexing transistor T11 and a twelfth multiplexing transistor T12;
  • the gate of T7 is electrically connected to MX1, the source of T7 is electrically connected to CH2, and the drain of T7 is electrically connected to DL2;
  • the gate of T8 is electrically connected to MX2, the source of T8 is electrically connected to CH2, and the drain of T8 is electrically connected to DL5;
  • the gate of T9 is electrically connected to MX3, the source of T9 is electrically connected to CH2, and the drain of T9 is electrically connected to DL8;
  • the gate of T10 is electrically connected to MX4, the source of T10 is electrically connected to CH2, and the drain of T10 is electrically connected to DL11;
  • the gate of T11 is electrically connected to MX5, the source of T11 is electrically connected to CH2, and the drain of T11 is electrically connected to DL14;
  • the gate of T12 is electrically connected to MX6, the source of T12 is electrically connected to CH2, and the drain of T12 is electrically connected to DL17;
  • the third multiplexing sub-circuit may include a thirteenth multiplexing transistor T13, a fourteenth multiplexing transistor T14, a fifteenth multiplexing transistor T15, a sixteenth multiplexing transistor T16, a seventeenth multiplexing transistor T17 and an eighteenth multiplexing transistor T18;
  • the gate of T13 is electrically connected to MX1, the source of T13 is electrically connected to CH3, and the drain of T13 is electrically connected to DL3;
  • the gate of T14 is electrically connected to MX2, the source of T14 is electrically connected to CH3, and the drain of T14 is electrically connected to DL6;
  • the gate of T15 is electrically connected to MX3, the source of T15 is electrically connected to CH3, and the drain of T15 is electrically connected to DL9;
  • the gate of T16 is electrically connected to MX4, the source of T16 is electrically connected to CH3, and the drain of T16 is electrically connected to DL12;
  • the gate of T17 is electrically connected to MX5, the source of T17 is electrically connected to CH3, and the drain of T17 is electrically connected to DL15 electrical connection;
  • the gate of T18 is electrically connected to MX6, the source of T18 is electrically connected to CH3, and the drain of T18 is electrically connected to DL18.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • DL1, DL4, DL7, DL10, DL13 and DL16 may be red data lines
  • DL2, DL5, DL8, DL11, DL14 and DL17 may be green data lines
  • DL3, DL6, DL9, DL12, DL15 and DL18 may be blue data lines, but the present invention is not limited thereto;
  • the red data line may be a data line that provides a data voltage for a red pixel circuit
  • the green data line may be a data line that provides a data voltage for a green pixel circuit
  • the blue data line may be a data line that provides a data voltage for a blue pixel circuit.
  • At least one embodiment of the display panel shown in FIG. 16 of the present disclosure is in operation.
  • MX1 provides a low voltage signal
  • MX2, MX3, MX4, MX5 and MX6 all output high voltage signals
  • T1, T7 and T13 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL1, CH2 is connected to DL2, and CH3 is connected to DL3;
  • MX2 When MX2 provides a low voltage signal, MX1, MX3, MX4, MX5 and MX6 all output high voltage signals, T2, T8 and T14 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL4, CH2 is connected to DL5, and CH3 is connected to DL6;
  • MX3 When MX3 provides a low voltage signal, MX1, MX2, MX4, MX5 and MX6 all output high voltage signals, T3, T9 and T15 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL7, CH2 is connected to DL8, and CH3 is connected to DL9;
  • MX4 When MX4 provides a low voltage signal, MX1, MX2, MX3, MX5 and MX6 all output high voltage signals, T4, T10 and T16 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL10, CH2 is connected to DL11, and CH3 is connected to DL12;
  • MX5 provides a low voltage signal
  • MX1, MX2, MX3, MX4 and MX6 all output high voltage signals
  • T5 T11 and T17 are turned on
  • other multiplexed transistors are turned off
  • CH1 is connected to DL13
  • CH2 is connected to DL14
  • CH3 is connected to DL15;
  • MX6 When MX6 provides a low voltage signal, MX1, MX2, MX3, MX4 and MX5 all output High voltage signal, T6, T12 and T18 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL16, CH2 is connected to DL17, and CH3 is connected to DL18.
  • the display cycle includes a first writing time period XT1 , a second writing time period XT2 , a third writing time period XT3 and a light emitting stage FT which are successively set;
  • the first writing time period XT1 includes a first data writing time period t11 and a second data writing time period t12 which are arranged successively;
  • the second writing time period XT2 includes a third data writing time period t21 and a fourth data writing time period t22 which are arranged successively;
  • the third writing time period XT3 includes a fifth data writing time period t31 and a sixth data writing time period t32 which are arranged successively;
  • MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals
  • T1, T7 and T13 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL1, CH2 is connected to DL2, CH3 is connected to DL3, CH1 provides a first light-emitting time control data voltage to DL1, CH2 provides a second light-emitting time control data voltage to DL2, and CH3 provides a third light-emitting time control data voltage to DL3;
  • T2, T8 and T14 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL4, CH2 is connected to DL5, CH3 is connected to DL6, CH1 provides the fourth light-emitting time control data voltage to DL4, CH2 provides the fifth light-emitting time control data voltage to DL5, and CH3 provides the ninth light-emitting time control data voltage to DL6;
  • T3, T9 and T15 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL7, CH2 is connected to DL8, CH3 is connected to DL9, CH1 provides the fourth light-emitting time control data voltage to DL7, CH2 provides the fifth light-emitting time control data voltage to DL8, and CH3 provides the ninth light-emitting time control data voltage to DL9;
  • T4 When MX4 provides a low voltage signal, T4, T10 and T16 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL10, CH2 is connected to DL11, CH3 is connected to DL12, CH1 provides the tenth light-emitting time control data voltage to DL10, CH2 provides the eleventh light-emitting time control data voltage to DL11, and CH3 provides the twelfth light-emitting time control data voltage to DL12;
  • T5 When MX5 provides a low voltage signal, T5, T11 and T17 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL13, CH2 is connected to DL14, CH3 is connected to DL15, CH1 provides the thirteenth light-emitting time control data voltage to DL13, CH2 provides the fourteenth light-emitting time control data voltage to DL14, and CH3 provides the fifteenth light-emitting time control data voltage to DL15;
  • T6, T12 and T18 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL16, CH2 is connected to DL17, CH3 is connected to DL18, CH1 provides the sixteenth light-emitting time control data voltage to DL16, CH2 provides the seventeenth light-emitting time control data voltage to DL17, and CH3 provides the eighteenth light-emitting time control data voltage to DL18;
  • each light-emitting time controls the data voltage to be charged to the parasitic capacitor of each data line;
  • RA provides a low voltage signal
  • RB provides a high voltage signal
  • the first transistor M1 in the pixel circuit is turned on to write the light emitting time control data voltage on each data line into the second control node N2;
  • MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals
  • T1, T7 and T13 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL1, CH2 is connected to DL2, CH3 is connected to DL3, CH1 provides the nineteenth light-emitting time control data voltage to DL1, CH2 provides the twentieth light-emitting time control data voltage to DL2, and CH3 provides the twenty-first light-emitting time control data voltage to DL3;
  • T2, T8 and T14 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL4, CH2 is connected to DL5, CH3 is connected to DL6, CH1 provides the twenty-second light-emitting time control data voltage to DL4, CH2 provides the twenty-third light-emitting time control data voltage to DL5, and CH3 provides the twenty-fourth light-emitting time control data voltage to DL6;
  • T3, T9 and T15 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL7, CH2 is connected to DL8, CH3 is connected to DL9, CH1 provides the twenty-fifth light-emitting time control data voltage to DL7, CH2 provides the twenty-sixth light-emitting time control data voltage to DL8, and CH3 provides the twenty-seventh light-emitting time control data voltage to DL9;
  • T4 When MX4 provides a low voltage signal, T4, T10 and T16 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL10, CH2 is connected to DL11, and CH3 is connected to DL12. Pass, CH1 provides the twenty-eighth light-emitting time control data voltage to DL10, CH2 provides the twenty-ninth light-emitting time control data voltage to DL11, and CH3 provides the thirtieth light-emitting time control data voltage to DL12;
  • T5 When MX5 provides a low voltage signal, T5, T11 and T17 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL13, CH2 is connected to DL14, CH3 is connected to DL15, CH1 provides a thirty-first light-emitting time control data voltage to DL13, CH2 provides a thirty-second light-emitting time control data voltage to DL14, and CH3 provides a thirty-third light-emitting time control data voltage to DL15;
  • T6, T12 and T18 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL16, CH2 is connected to DL17, CH3 is connected to DL18, CH1 provides a thirty-fourth light-emitting time control data voltage to DL16, CH2 provides a thirty-fifth light-emitting time control data voltage to DL17, and CH3 provides a thirty-sixth light-emitting time control data voltage to DL18;
  • each light-emitting time controls the data voltage to be charged to the parasitic capacitor of each data line;
  • RB provides a low voltage signal
  • RA provides a high voltage signal
  • M3 in the pixel circuit is turned on to write the light emitting time control data voltage on each data line into the third control node N3;
  • MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals
  • T1, T7 and T13 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL1, CH2 is connected to DL2, CH3 is connected to DL3, CH1 provides a first display data voltage to DL1, CH2 provides a second display data voltage to DL2, and CH3 provides a third display data voltage to DL3;
  • T2, T8 and T14 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL4, CH2 is connected to DL5, CH3 is connected to DL6, CH1 provides the fourth display data voltage to DL4, CH2 provides the fifth display data voltage to DL5, and CH3 provides the sixth display data voltage to DL6;
  • T3, T9 and T15 are turned on, and other multiplexed transistors are turned off.
  • CH1 is connected to DL7
  • CH2 is connected to DL8, and CH3 is connected to DL9.
  • CH1 provides the seventh display data voltage to DL7
  • CH2 provides the eighth display data voltage to DL8, and CH3 provides the ninth display data voltage to DL9;
  • T4 When MX4 provides a low voltage signal, T4, T10 and T16 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL10, CH2 is connected to DL11, CH3 is connected to DL12, CH1 provides the tenth display data voltage to DL10, CH2 provides the eleventh display data voltage to DL11, and CH3 provides the twelfth display data voltage to DL12;
  • T5 When MX5 provides a low voltage signal, T5, T11 and T17 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL13, CH2 is connected to DL14, CH3 is connected to DL15, CH1 provides the thirteenth display data voltage to DL13, CH2 provides the fourteenth display data voltage to DL14, and CH3 provides the fifteenth display data voltage to DL15;
  • T6, T12 and T18 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL16, CH2 is connected to DL17, CH3 is connected to DL18, CH1 provides the sixteenth display data voltage to DL16, CH2 provides the seventeenth display data voltage to DL17, and CH3 provides the eighteenth display data voltage to DL18;
  • each light-emitting time controls the data voltage to be charged to the parasitic capacitor of each data line;
  • G1 provides a low voltage signal, and M6 and M7 in the pixel circuit are turned on to perform charging and threshold voltage compensation, thereby realizing display data voltage writing;
  • E1 provides a low voltage signal
  • M5 is turned on to control the connection between the power supply voltage line VDD and the source of the driving transistor M0;
  • M2 in the pixel circuit is turned on to control the connection between the first light emitting control line E1 and the first control node N1;
  • M4 in the pixel circuit is turned on to control the second light emitting control line Hf to be connected to the first control node N1.
  • the display panel described in at least one embodiment of the present disclosure can also control RA to provide a high voltage signal and RB to provide a low voltage signal in the second data writing time period, and control RA to provide a low voltage signal and RB to provide a high voltage signal in the fourth data writing time period.
  • the opening time of each multiplexing control terminal can be reduced, and the operation can be completed quickly.
  • the light emission time on the paired data lines controls the storage of the data voltage to increase the on-time of RA, the on-time of RB and the on-time of G1 to provide more sufficient time for data voltage writing, charging and threshold voltage compensation inside the pixel circuit.
  • GOA Gate On Array, array substrate row drive
  • all low-level stages of the second light-emitting control line Hf are in the light-emitting stage, so as to avoid the potential of the second light-emitting control signal being pulled down by high frequency to cause coupling influence on the writing of display data voltage and generate disturbance on the gate voltage of the driving transistor, thereby reducing one transistor for preventing Hf coupling influence compared with the related pixel circuit.
  • the data lines may be coupled to each other and change the voltage.
  • the data voltage Vdata connected to DL1 may be 18V;
  • the data voltage Vdata connected to DL1 may be 0V;
  • the data voltage Vdata connected to DL1 may be 13V;
  • the 18V voltage signal and the 0V voltage signal are signals that control the access of the first light-emitting control line and the second light-emitting control line, respectively, and have little effect on the grayscale display.
  • the voltage on DL1 will jump with the voltage on DL4, which will affect the data voltage writing and cause the write voltage to be a higher potential, thereby causing the pixels electrically connected to DL1 to display darker than expected.
  • the data voltage Vdata connected to DL1 may be 0V;
  • the data voltage Vdata connected to DL1 may be 18V;
  • the data voltage Vdata connected to DL1 may be 13V;
  • the display cycle includes a first writing time period, a second writing time period, a third writing time period and a light emitting stage FT which are successively set;
  • the second writing time period includes a third data writing time period t21 and a fourth data writing time period t22; the third data writing time period t21 is included in the fourth data writing time period t22;
  • the third writing time period includes a fifth data writing time period t31 and a sixth data writing time period t32 which are set successively;
  • MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals, and the transistors controlled by MX1, MX2, MX3, MX4, MX5 and MX6 are sequentially turned on to write the corresponding light emitting time control data voltage;
  • RA provides a low voltage signal
  • RB and G1 provide a high voltage signal
  • the first transistor M1 in the pixel circuit is turned on to write the light emission time control data voltage on each data line into the second control node N2;
  • RB provides a low voltage signal
  • RA and G1 provide a high voltage signal
  • M3 in the pixel circuit is turned on to write the light emitting time control data voltage on each data line into the third control node N3;
  • MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals, and the transistors controlled by MX1, MX2, MX3, MX4, MX5 and MX6 are sequentially turned on to write the corresponding display data voltage;
  • G1 provides a low voltage signal
  • RA and RB provide a high voltage signal
  • M6 and M7 in the pixel circuit are turned on to perform charging and threshold voltage compensation to achieve display data voltage writing;
  • EM outputs a low voltage signal
  • Hf outputs a low voltage signal
  • the driving transistor M0 in the pixel circuit drives the micro light-emitting diode ML to emit light;
  • the driving transistor M0 in the pixel circuit drives the micro light emitting diode ML to emit light.
  • the light emitting control line labeled E1_N is the next row adjacent to E1.
  • current + time control is usually used to emit light for a short time at a fixed current to achieve low grayscale display.
  • the LED light emitting diode
  • the LED enters a black state, and the human eye can clearly feel the flicker, causing discomfort to the viewer.
  • at least one embodiment of the present disclosure provides a pixel circuit that controls the light emission time at high frequency, disperses the short light emission time into a frame time, and reduces flicker.
  • the light control signal provided by E1 since the light control signal provided by E1 continues to be a low voltage signal for a relatively long time, the light control signal provided by Hf is a high-frequency pulse signal during the entire time that E1 continues to be a low voltage signal.
  • FIG. 21 is an operation timing diagram of a display panel according to at least one embodiment of the present disclosure.
  • the first starting voltage is labeled ESTV
  • the first clock signal is labeled ECK
  • the second clock signal is labeled ECB
  • the second starting voltage is labeled GSTV
  • the third clock signal is labeled GCK
  • the fourth clock signal is labeled GCB
  • the second light-emitting control line is labeled Hf
  • the first multiplexing control terminal is labeled MX1
  • the second multiplexing control terminal is labeled MX2
  • the third multiplexing control terminal is labeled MX3
  • the fourth multiplexing control terminal is labeled MX4
  • the fifth multiplexing control terminal is labeled MX5
  • the sixth multiplexing control terminal is labeled MX6, and the data voltage is labeled Vdata.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned display panel, wherein the display period includes a first writing time period and a second writing time period; the first writing time period includes a first data writing time period and a second data writing time period, and the second writing time period includes a third data writing time period. segment and a fourth data writing time period; the driving method comprises:
  • the multiplexing circuit writes the first control voltage provided by the source driver through its voltage output terminal into the data line under the control of the reset control signal;
  • the first control circuit provides the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether to provide the first light emitting control signal to the first control node under the control of the potential of the second control node;
  • the multiplexing circuit writes the second control voltage provided by the source driver through its voltage output terminal into the data line under the control of the reset control signal;
  • the second control circuit writes the second control voltage provided by the data line to the third control node under the control of the second reset control signal, and the second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.
  • the first data writing time period and the second data writing time period are set successively, and the third data writing time period and the fourth data writing time period are set successively; or,
  • the first data writing time period is included in the second data writing time period, and the third data writing time period is included in the fourth data writing time period.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

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Abstract

一种像素电路、驱动方法、显示基板、显示面板和显示装置。像素电路包括发光元件（E0）、驱动电路（10）、第一发光控制电路（11）、第一控制电路（12）和第二控制电路（13）；第一控制电路（12）在第一复位控制信号的控制下，将第一控制电压提供至第二控制节点（N2），在第二控制节点（N2）的电位的控制下，控制第一发光控制线（E1）提供第一发光控制信号至第一控制节点（N1）；第二控制电路（13）在第二复位控制信号的控制下，将第二控制电压写入第三控制节点（N3），在第三控制节点（N3）的电位的控制下，控制第二发光控制线（Hf）提供第二发光控制信号至第一控制节点（N1）。解决了像素电路的列向不良，减少了侧边信号数量。

Description

像素电路、驱动方法、显示基板、显示面板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法、显示基板、显示面板和显示装置。
背景技术
相关的包括微型发光二极管或迷你发光二极管的像素电路采用第一数据线和第二数据线，其中，第一数据线用于提供发光时间数据电压，第二数据线用于提供显示数据电压，并第一数据线和第二数据线设置于两列像素电路之间，使得侧边信号数量多，并由于第一数据线上的信号和第二数据线上的信号在充电补偿阶段的耦合影响，在充电补偿阶段显示数据电压带来的电压跳变，会导致相关的像素电路的列向不良。
发明内容
在一个方面中，本公开实施例提供一种像素电路，包括发光元件、驱动电路、第一发光控制电路、第一控制电路和第二控制电路；
所述驱动电路用于产生驱动发光元件的驱动电流；
所述第一发光控制电路分别与第一控制节点、所述驱动电路的第一端和发光元件电连接，用于在所述第一控制节点的电位的控制下，控制所述驱动电路的第一端与所述发光元件之间连通；
所述第一控制电路分别与数据线、第一复位控制线、第一发光控制线、所述第一控制节点和第二控制节点电连接，用于在所述第一复位控制线提供的第一复位控制信号的控制下，将所述数据线提供的第一控制电压提供至所述第二控制节点，在所述第二控制节点的电位的控制下，控制所述第一发光控制线提供第一发光控制信号至所述第一控制节点；
所述第二控制电路分别与所述数据线、第二复位控制线、第二发光控制线、所述第一控制节点和第三控制节点电连接，用于在所述第二复位控制线提供的第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入 所述第三控制节点，在所述第三控制节点的电位的控制下，控制所述第二发光控制线提供第二发光控制信号至所述第一控制节点。
可选的，所述第一控制电路包括第一写入控制电路、第一储能电路和第二写入控制电路；
所述第一写入控制电路分别与第一复位控制线、所述数据线和第二控制节点电连接，用于在所述第一复位控制信号的控制下，将所述数据线提供的第一控制电压提供至所述第二控制节点；
所述第一储能电路与所述第二控制节点电连接，用于储能电路；
所述第二写入控制电路分别与所述第二控制节点、所述第一发光控制线和所述第一控制节点电连接，用于在所述第二控制节点的电位的控制下，控制所述第一发光控制线提供第一发光控制信号至所述第一控制节点。
可选的，所述第二控制电路包括第三写入控制电路、第二储能电路和第四写入控制电路；
所述第三写入控制电路分别与所述第二复位控制线、所述数据线和所述第三控制节点电连接，在所述第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入所述第三控制节点；
所述第二储能电路与所述第三控制节点电连接，用于储存电能；
所述第四写入控制电路分别与所述第三控制节点、所述第二发光控制线和所述第一控制节点电连接，用于在所述第三控制节点的电位的控制下，控制所述第二发光控制线提供第二发光控制信号至所述第一控制节点。
可选的，所述第一写入控制电路包括第一晶体管，所述第一储能电路包括第一电容，第二写入控制电路包括第二晶体管；
所述第一晶体管的栅极与所述第一复位控制线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述第二控制节点电连接；
所述第一电容的第一极板与所述第二控制节点电连接，所述第一电容的第二极板与第一初始电压线电连接；
所述第二晶体管的栅极与所述第二控制节点电连接，所述第二晶体管的第一极与所述第一发光控制线电连接，所述第二晶体管的第二极与所述第一 控制节点电连接。
可选的，第三写入控制电路包括第三晶体管，所述第二储能电路包括第二电容，所述第四写入控制电路包括第四晶体管；
所述第三晶体管的栅极与所述第二复位控制线电连接，所述第三晶体管的的第一极与所述数据线电连接，所述第三晶体管的第二极与所述第三控制节点电连接；
所述第二电容的第一极板与所述第三控制节点电连接，所述第二电容的第二极板与第二初始电压线电连接；
所述第四晶体管的栅极与所述第三控制节点电连接，所述第四晶体管的第一极与所述第二发光控制线电连接，所述第四晶体管的第二极与所述第一控制节点电连接。
可选的，本公开至少一实施例所述的像素电路还包括第二发光控制电路；
所述第二发光控制电路分别与第一发光控制线、电源电压线和所述驱动电路的第二端电连接，用于在所述第一发光控制信号的控制下，控制所述电源电压线与所述驱动电路的第二端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路、补偿控制电路和第三储能电路；
所述数据写入电路分别与扫描线、所述数据线和所述驱动电路的第二端电连接，用于在所述扫描线提供的扫描信号的控制下，将所述数据线提供的显示数据电压写入所述驱动电路的第二端；
所述补偿控制电路分别与所述扫描线、所述驱动电路的控制端和所述驱动电路的第一端电连接，用于在所述扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
所述第三储能电路与所述驱动电路的控制端电连接，用于储存电能。
可选的，本公开至少一实施例所述的像素电路还包括第一复位电路；
所述第一复位电路分别与第三复位控制线、第三初始电压线和所述驱动电路的控制端电连接，用于在所述第三复位控制线提供的第三复位控制信号的控制下，将所述第三初始电压线提供的第三初始电压写入所述驱动电路的控制端。
可选的，本公开至少一实施例所述的像素电路还包括第二复位电路；
所述第二复位电路分别与第四复位控制线、第四初始电压线和所述发光元件的第一极电连接，用于在所述第四复位控制线提供的第四复位控制信号的控制下，将所述第四初始电压线提供的第四初始电压写入所述发光元件的第一极；
所述发光元件的第二极与第一电压线电连接。
可选的，所述第三复位控制线为所述第一复位控制线或所述第二复位控制线；
所述第四复位控制线为所述第一复位控制线或所述第二复位控制线。
可选的，所述第二发光控制电路包括第五晶体管；
所述第五晶体管的栅极与所述第一发光控制线电连接，所述第五晶体管的第一极与所述电源电压线电连接，所述第五晶体管的第二极与所述驱动电路的第二端电连接。
可选的，所述数据写入电路包括第六晶体管，所述补偿控制电路包括第七晶体管，所述第三储能电路包括第三电容；所述驱动电路包括驱动晶体管；
所述第六晶体管的栅极与所述扫描线电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述驱动晶体管的第二极电连接；
所述第七晶体管的栅极与所述扫描线电连接，所述第七晶体管的第一极与所述驱动晶体管的栅极电连接，所述第七晶体管的第二极与所述驱动晶体管的第一极电连接；
所述第三电容的第一极板与所述驱动晶体管的栅极电连接，所述第三电容的第二极板与电源电压线电连接。
可选的，所述第一复位电路包括第八晶体管；
所述第八晶体管的栅极与所述第三复位控制线电连接，所述第八晶体管的第一极与第三初始电压线电连接，所述第八晶体管的第二极与所述驱动电路的控制端电连接。
可选的，所述第二复位电路包括第九晶体管；
所述第九晶体管的栅极与所述第四复位控制线电连接，所述第九晶体管 的第一极与所述第四初始电压线电连接，所述第九晶体管的第二极与所述发光元件的第一极电连接。
可选的，本公开实施例所述的像素电路包括复用控制电路；
所述复用控制电路分别与复用控制端、源极驱动器的电压输出端和所述数据线电连接，用于在所述复用控制端提供的复用控制信号的控制下，控制所述电压输出端与所述数据线之间连通。
在第二个方面中，本公开实施例提供一种驱动方法，应用于上述的像素电路，显示阶段包括第一写入阶段和第二写入阶段；所述驱动方法包括：
在第一写入阶段，第一控制电路在第一复位控制信号的控制下，将数据线提供的第一控制电压提供至第二控制节点，第一控制电路在所述第二控制节点的电位的控制下，控制是否将第一发光控制信号提供至第一控制节点；
在第二写入阶段，第二控制电路在第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入第三控制节点，第二控制电路在所述第三控制节点的电位的控制下，控制是否将第二发光控制信号提供至所述第一控制节点。
可选的，本公开至少一实施例所述的驱动方法包括：
在进行中高灰阶显示时，在所述第一写入阶段，第一控制电路在所述第二控制节点的电位的控制下，控制将第一发光控制信号提供至第一控制节点，在所述第二写入阶段，所述第二控制电路在所述第三控制节点的电位的控制下，控制停止将第二发光控制信号提供至至所述第一控制节点；
在进行低灰阶显示时，在所述第一写入阶段，第一控制电路在所述第二控制节点的电位的控制下，停止控制将第一发光控制信号提供至第一控制节点，在所述第二写入阶段，所述第二控制电路在所述第三控制节点的电位的控制下，控制将第二发光控制信号提供至所述第一控制节点。
在第三个方面中，本公开实施例提供一种显示基板，包括衬底基板和设置于所述衬底基板上的多行多列上述的像素电路。
可选的，位于同一列的像素电路设置于两列数据线之间；所述数据线沿第一方向延伸；
第a行像素电路设置于第a行扫描线和第a行第一电压线之间，a为正整 数；
所述第a行扫描线和所述第a行第一电压线沿第二方向延伸；
所述第一方向和所述第二方向相交。
在第四个方面中，本公开实施例提供一种显示面板，包括上述的显示基板。
可选的，本公开至少一实施例所述的显示面板还包括源极驱动器、多列数据线和多路复用电路；
位于同一列的多个像素电路都与同一列数据线电连接；
所述多路复用电路分别与所述源极驱动器的多个电压输出端、多个复用控制端和所述多列数据线电连接，用于在所述复用控制端提供的复用控制信号的控制下，将所述源极驱动器通过其电压输出端提供的电压信号写入所述数据线。
可选的，所述多路复用电路分别与N个复用控制端电连接，所述多路复用电路包括M个复用子电路，N和M为大于1的整数；
每一所述复用子电路都与所述源极驱动器的电压输出端、所述N个复用控制端和N列所述数据线电连接，用于在第n个复用控制端提供的第n复用控制信号的控制下，控制将该电压输出端提供的电压信号至所述N列数据线中的第n数据线；
n为小于等于N的正整数。
在第五个方面中，本公开实施例提供一种驱动方法，应用于上述的显示面板，显示周期包括第一写入时间段和第二写入时间段；所述第一写入时间段包括第一数据写入时间段和第二数据写入时间段，所述第二写入时间段包括第三数据写入时间段和第四数据写入时间段；所述驱动方法包括：
在第一数据写入时间段，多路复用电路在复位控制信号的控制下，将源极驱动器通过其电压输出端提供的第一控制电压写入数据线；
在第二数据写入时间段，第一控制电路在第一复位控制信号的控制下，将数据线提供的第一控制电压提供至第二控制节点，第一控制电路在所述第二控制节点的电位的控制下，控制是否将第一发光控制信号提供至第一控制节点；
在第三数据写入时间段，多路复用电路在复位控制信号的控制下，将源极驱动器通过其电压输出端提供的第二控制电压写入数据线；
在第四数据写入时间段，第二控制电路在第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入第三控制节点，第二控制电路在所述第三控制节点的电位的控制下，控制是否将第二发光控制信号提供至所述第一控制节点。
可选的，所述第一数据写入时间段和第二数据写入时间段先后设置，所述第三数据写入时间段和第四数据写入时间段先后设置；或者，
所述第一数据写入时间段包含于所述第二数据写入时间段，所述第三数据写入时间段包含于所述第四数据写入时间段。
在第六个方面中，本公开实施例提供一种显示装置，包括上述的显示面板。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的电路图；
图5是本公开图4所示的像素电路的至少一实施例的工作时序图；
图6是本公开图4所示的像素电路的至少一实施例的工作时序图；
图7是本公开图4所示的像素电路的至少一实施例的工作时序图；
图8A是本公开至少一实施例所述的像素电路的电路图；
图8B是本公开至少一实施例所述的像素电路的结构图；
图9是图4所示的像素电路的至少一实施例的布局图；
图10是图9中的第一栅金属层的布局图；
图11是图9中的半导体层的布局图；
图12是图9中的第二栅金属层的布局图；
图13是图9中的源漏金属层的布局图；
图14是本公开至少一实施例所述的显示面板的结构图；
图15是本公开至少一实施例所述的显示面板的结构图；
图16是本公开至少一实施例所述的显示面板的电路图；
图17是本公开图16所示的显示面板的至少一实施例的工作时序图；
图18是本公开图16所示的显示面板的至少一实施例的工作时序图；
图19是本公开图16所示的显示面板的至少一实施例的工作时序图；
图20是本公开图16所示的显示面板的至少一实施例的工作时序图；
图21是本公开至少一实施例所述的显示面板的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开至少一实施例所述的像素电路包括发光元件E0、驱动电路10、第一发光控制电路11、第一控制电路12和第二控制电路13；
所述驱动电路10用于产生驱动发光元件E0的驱动电流；
所述第一发光控制电路11分别与第一控制节点N1、所述驱动电路10的第一端和发光元件E0电连接，用于在所述第一控制节点N1的电位的控制下，控制所述驱动电路10的第一端与所述发光元件E0之间连通；
所述第一控制电路12分别与数据线DT、第一复位控制线RA、第一发光控制线E1、所述第一控制节点N1和第二控制节点N2电连接，用于在所述第一复位控制线RA提供的第一复位控制信号的控制下，将所述数据线DT提供的第一控制电压提供至所述第二控制节点N2，在所述第二控制节点N2 的电位的控制下，控制所述第一发光控制线E1提供第一发光控制信号至所述第一控制节点N1；
所述第二控制电路13分别与所述数据线DT、第二复位控制线RB、第二发光控制线Hf、所述第一控制节点N1和第三控制节点N3电连接，用于在所述第二复位控制线RB提供的第二复位控制信号的控制下，将所述数据线DT提供的第二控制电压写入所述第三控制节点N3，在所述第三控制节点N3的电位的控制下，控制所述第二发光控制线Hf提供第二发光控制信号至所述第一控制节点N1。
在本公开图1所示的像素电路的至少一实施例中，仅采用一条数据线以分时提供显示数据电压Data_I和发光时间控制数据电压Data_T，可以减少侧边信号数量，同时可以解决增加多路复用晶体管时灰阶信号丢失的情况，并且，显示数据电压Data_I与发光时间控制数据电压Data_T的整合也避免了两个信号在充电补偿阶段的耦合影响，减少在充电补偿阶段显示数据电压Data_I带来的电压跳变，从而解决原像素电路的列向不良。
在本公开至少一实施例中，所述第一控制电压和所述第二控制电压可以为发光时间控制数据电压。
可选的，所述发光元件可以为Mini LED(迷你发光二极管)或Micro LED(微型发光二极管)，但不以此为限。在具体实施时，所述发光元件也可以为有机发光二极管。
本公开图1所示的像素电路的至少一实施例在工作时，
在进行中高灰阶显示时，控制将所述第一发光控制线E1提供第一发光控制信号至所述第一控制节点N1，通过给入的不同的显示数据电压的电压值，以产生不同发光电流；
在进行低灰阶显示时，采用发光电流+发光时间的控制方式，将所述第二发光控制线Hf上的第二发光控制信号提供至所述第一控制节点N1，所述第二发光控制信号为高频信号，减少低灰阶下闪烁问题。
本公开图1所示的像素电路的至少一实施例在工作时，显示阶段可以包括第一写入阶段和第二写入阶段；所述驱动方法包括：
在第一写入阶段，第一控制电路12在第一复位控制信号的控制下，将数 据线DT提供的第一控制电压提供至第二控制节点N2，第一控制电路12在所述第二控制节点N2的电位的控制下，控制是否将第一发光控制信号提供至第一控制节点N1；
在第二写入阶段，第二控制电路13在第二复位控制信号的控制下，将所述数据线DT提供的第二控制电压写入第三控制节点N3，第二控制电路13在所述第三控制节点N3的电位的控制下，控制是否将第二发光控制信号提供至所述第一控制节点N1。
本公开图1所示的像素电路的至少一实施例在工作时，
在进行中高灰阶显示时，在所述第一写入阶段，第一控制电路12在所述第二控制节点N2的电位的控制下，控制将第一发光控制信号提供至第一控制节点N1，在所述第二写入阶段，所述第二控制电路13在所述第三控制节点N3的电位的控制下，控制停止将第二发光控制信号提供至至所述第一控制节点N1；
在进行低灰阶显示时，在所述第一写入阶段，第一控制电路12在所述第二控制节点N2的电位的控制下，停止控制将第一发光控制信号提供至第一控制节点N1，在所述第二写入阶段，所述第二控制电路13在所述第三控制节点N3的电位的控制下，控制将第二发光控制信号提供至所述第一控制节点N1。
在本公开至少一实施例中，所述第一控制电路包括第一写入控制电路、第一储能电路和第二写入控制电路；
所述第一写入控制电路分别与第一复位控制线、所述数据线和第二控制节点电连接，用于在所述第一复位控制信号的控制下，将所述数据线提供的第一控制电压提供至所述第二控制节点；
所述第一储能电路与所述第二控制节点电连接，用于储能电路；
所述第二写入控制电路分别与所述第二控制节点、所述第一发光控制线和所述第一控制节点电连接，用于在所述第二控制节点的电位的控制下，控制所述第一发光控制线提供第一发光控制信号至所述第一控制节点。
在具体实施时，所述第一控制电路可以包括第一写入控制电路、第一储能电路和第二写入控制电路，第一写入控制电路控制将第一控制电压写入第 二控制节点，第二写入控制电路控制将第一发光控制信号写入第一控制节点。
在本公开至少一实施例中，所述第二控制电路包括第三写入控制电路、第二储能电路和第四写入控制电路；
所述第三写入控制电路分别与所述第二复位控制线、所述数据线和所述第三控制节点电连接，在所述第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入所述第三控制节点；
所述第二储能电路与所述第三控制节点电连接，用于储存电能；
所述第四写入控制电路分别与所述第三控制节点、所述第二发光控制线和所述第一控制节点电连接，用于在所述第三控制节点的电位的控制下，控制所述第二发光控制线提供第二发光控制信号至所述第一控制节点。
在具体实施时，所述第二控制电路可以包括第三写入控制电路、第二储能电路和第四写入控制电路，第三写入控制电路控制将第二控制电压写入第三控制节点，第四写入控制电路控制将第二发光控制信号提供至第一控制节点。
如图2所示，在图1所示的像素电路的至少一实施例的基础上，
所述第一控制电路包括第一写入控制电路21、第一储能电路22和第二写入控制电路23；
所述第一写入控制电路21分别与第一复位控制线RA、所述数据线DT和第二控制节点N2电连接，用于在所述第一复位控制信号的控制下，将所述数据线DT提供的第一控制电压提供至所述第二控制节点N2；
所述第一储能电路22与所述第二控制节点N2电连接，用于储能电能；
所述第二写入控制电路23分别与所述第二控制节点N2、所述第一发光控制线E1和所述第一控制节点N1电连接，用于在所述第二控制节点N2的电位的控制下，控制所述第一发光控制线E1提供第一发光控制信号至所述第一控制节点N1；
所述第二控制电路包括第三写入控制电路24、第二储能电路25和第四写入控制电路26；
所述第三写入控制电路24分别与所述第二复位控制线RB、所述数据线DT和所述第三控制节点N3电连接，在所述第二复位控制信号的控制下，将 所述数据线DT提供的第二控制电压写入所述第三控制节点N3；
所述第二储能电路25与所述第三控制节点N3电连接，用于储存电能；
所述第四写入控制电路26分别与所述第三控制节点N3、所述第二发光控制线Hf和所述第一控制节点N1电连接，用于在所述第三控制节点N3的电位的控制下，控制所述第二发光控制线Hf提供第二发光控制信号至所述第一控制节点N1。
可选的，所述第一写入控制电路包括第一晶体管，所述第一储能电路包括第一电容，第二写入控制电路包括第二晶体管；
所述第一晶体管的栅极与所述第一复位控制线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述第二控制节点电连接；
所述第一电容的第一极板与所述第二控制节点电连接，所述第一电容的第二极板与第一初始电压线电连接；
所述第二晶体管的栅极与所述第二控制节点电连接，所述第二晶体管的第一极与所述第一发光控制线电连接，所述第二晶体管的第二极与所述第一控制节点电连接。
可选的，第三写入控制电路包括第三晶体管，所述第二储能电路包括第二电容，所述第四写入控制电路包括第四晶体管；
所述第三晶体管的栅极与所述第二复位控制线电连接，所述第三晶体管的的第一极与所述数据线电连接，所述第三晶体管的第二极与所述第三控制节点电连接；
所述第二电容的第一极板与所述第三控制节点电连接，所述第二电容的第二极板与第二初始电压线电连接；
所述第四晶体管的栅极与所述第三控制节点电连接，所述第四晶体管的第一极与所述第二发光控制线电连接，所述第四晶体管的第二极与所述第一控制节点电连接。
本公开至少一实施例所述的像素电路还包括第二发光控制电路；
所述第二发光控制电路分别与第一发光控制线、电源电压线和所述驱动电路的第二端电连接，用于在所述第一发光控制信号的控制下，控制所述电 源电压线与所述驱动电路的第二端之间连通。
在具体实施时，所述像素电路还可以包括第二发光控制电路，第二发光控制电路在第一发光控制信号的控制下，控制电源电压线与驱动电路的第二端之间连通。
本公开至少一实施例所述的像素电路还包括数据写入电路、补偿控制电路和第三储能电路；
所述数据写入电路分别与扫描线、所述数据线和所述驱动电路的第二端电连接，用于在所述扫描线提供的扫描信号的控制下，将所述数据线提供的显示数据电压写入所述驱动电路的第二端；
所述补偿控制电路分别与所述扫描线、所述驱动电路的控制端和所述驱动电路的第一端电连接，用于在所述扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
所述第三储能电路与所述驱动电路的控制端电连接，用于储存电能。
在具体实施时，所述像素电路还可以包括数据写入电路、补偿控制电路和第三储能电路，数据写入电路在扫描信号的控制下，将显示数据电压写入驱动电路的第二端，补偿控制电路在扫描信号的控制下，控制驱动电路的控制端与驱动电路的第一端之间连通，以进行阈值电压补偿控制。
本公开至少一实施例所述的像素电路还包括第一复位电路；
所述第一复位电路分别与第三复位控制线、第三初始电压线和所述驱动电路的控制端电连接，用于在所述第三复位控制线提供的第三复位控制信号的控制下，将所述第三初始电压线提供的第三初始电压写入所述驱动电路的控制端。
在具体实施时，所述像素电路还可以包括第一复位电路；
第一复位电路在第三复位控制信号的控制下，将第三初始电压写入所述驱动电路的控制端，以使得在充电补偿阶段开始时，驱动电路包括的驱动晶体管能够打开。
本公开至少一实施例所述的像素电路还包括第二复位电路；
所述第二复位电路分别与第四复位控制线、第四初始电压线和所述发光元件的第一极电连接，用于在所述第四复位控制线提供的第四复位控制信号 的控制下，将所述第四初始电压线提供的第四初始电压写入所述发光元件的第一极；
所述发光元件的第二极与第一电压线电连接。
可选的，所述第一电压线可以为低电压线，但不以此为限。
在具体实施时，所述像素电路还可以包括第二复位电路；所述第二复位电路在第四复位控制信号的控制下，将第四初始电压写入发光元件的第一极，以控制发光元件不发光，并清除发光元件的第一极残留的电荷。
可选的，所述第三复位控制线为所述第一复位控制线或所述第二复位控制线；
所述第四复位控制线为所述第一复位控制线或所述第二复位控制线。
在本公开至少一实施例中，第三复位控制线可以为第一复位控制线或第二复位控制线，第四复位控制线可以为第一复位控制线或第二复位控制线，以减少采用的控制线的数目。
如图3所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二发光控制电路31、数据写入电路32、补偿控制电路33、第三储能电路34、第一复位电路35和第二复位电路36；
所述第二发光控制电路31分别与第一发光控制线E1、电源电压线VDD和所述驱动电路10的第二端电连接，用于在所述第一发光控制线E1提供的第一发光控制信号的控制下，控制所述电源电压线VDD与所述驱动电路10的第二端之间连通；
所述数据写入电路32分别与扫描线G1、所述数据线DT和所述驱动电路10的第二端电连接，用于在所述扫描线G1提供的扫描信号的控制下，将所述数据线DT提供的显示数据电压写入所述驱动电路10的第二端；
所述补偿控制电路33分别与所述扫描线G1、所述驱动电路10的控制端和所述驱动电路10的第一端电连接，用于在所述扫描信号的控制下，控制所述驱动电路10的控制端与所述驱动电路10的第一端之间连通；
所述第三储能电路34与所述驱动电路10的控制端电连接，用于储存电能。
所述第一复位电路35分别与第一复位控制线RA、第三初始电压线I3和 所述驱动电路10的控制端电连接，用于在所述第一复位控制线RA提供的第一复位控制信号的控制下，将所述第三初始电压线I3提供的第三初始电压写入所述驱动电路10的控制端；
所述第二复位电路36分别与第一复位控制线RA、第四初始电压线I4和所述发光元件E0的第一极电连接，用于在所述第一复位控制线RA提供的第一复位控制信号的控制下，将所述第四初始电压线I4提供的第四初始电压写入所述发光元件E0的第一极；
所述发光元件E0的第二极与第一电压线电连接。
在图3所示的至少一实施例中，第三复位控制线为第一复位控制线，第四复位控制线为第一复位控制线。
在具体实施时，所述第三复位控制线和所述第四复位控制线还可以都为第二复位控制线，或者，所述第三复位控制线为第一复位控制线，所述第四复位控制线为第二复位控制线；或者，所述第三复位控制线为第二复位控制线，所述第四复位控制线为第一复位控制线。
本公开至少一实施例中，第一初始电压线、第二初始电压线、第三初始电压线和第四初始电压线可以为同一初始电压线，以减少采用的初始电压线的个数。
可选的，所述第二发光控制电路包括第五晶体管；
所述第五晶体管的栅极与所述第一发光控制线电连接，所述第五晶体管的第一极与所述电源电压线电连接，所述第五晶体管的第二极与所述驱动电路的第二端电连接。
可选的，所述数据写入电路包括第六晶体管，所述补偿控制电路包括第七晶体管，所述第三储能电路包括第三电容；所述驱动电路包括驱动晶体管；
所述第六晶体管的栅极与所述扫描线电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述驱动晶体管的第二极电连接；
所述第七晶体管的栅极与所述扫描线电连接，所述第七晶体管的第一极与所述驱动晶体管的栅极电连接，所述第七晶体管的第二极与所述驱动晶体管的第一极电连接；
所述第三电容的第一极板与所述驱动晶体管的栅极电连接，所述第三电容的第二极板与电源电压线电连接。
可选的，所述第一复位电路包括第八晶体管；
所述第八晶体管的栅极与所述第三复位控制线电连接，所述第八晶体管的第一极与第三初始电压线电连接，所述第八晶体管的第二极与所述驱动电路的控制端电连接。
可选的，所述第二复位电路包括第九晶体管；
所述第九晶体管的栅极与所述第四复位控制线电连接，所述第九晶体管的第一极与所述第四初始电压线电连接，所述第九晶体管的第二极与所述发光元件的第一极电连接。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，所述第一写入控制电路包括第一晶体管M1，所述第一储能电路包括第一电容C1，第二写入控制电路包括第二晶体管M2；
所述第一晶体管M1的栅极与所述第一复位控制线RA电连接，所述第一晶体管M1的源极与所述数据线DT电连接，所述第一晶体管M1的漏极与所述第二控制节点N2电连接；
所述第一电容C1的第一极板与所述第二控制节点N2电连接，所述第一电容C1的第二极板与初始电压线I0电连接；所述初始电压线I0用于提供初始电压Vinit；
所述第二晶体管M2的栅极与所述第二控制节点N2电连接，所述第二晶体管M2的源极与所述第一发光控制线E1电连接，所述第二晶体管M2的漏极与所述第一控制节点N1电连接；
第三写入控制电路包括第三晶体管M3，所述第二储能电路包括第二电容C2，所述第四写入控制电路包括第四晶体管M4；
所述第三晶体管M3的栅极与所述第二复位控制线RB电连接，所述第三晶体管M3的源极与所述数据线DT电连接，所述第三晶体管M3的漏极与所述第三控制节点N3电连接；
所述第二电容C2的第一极板与所述第三控制节点N3电连接，所述第二电容C2的第二极板与所述初始电压线I0电连接；
所述第四晶体管M4的栅极与所述第三控制节点N3电连接，所述第四晶体管M4的源极与所述第二发光控制线Hf电连接，所述第四晶体管M4的漏极与所述第一控制节点N1电连接；
所述第二发光控制电路包括第五晶体管M5；
所述第五晶体管M5的栅极与所述第一发光控制线E1电连接，所述第五晶体管M5的源极与所述电源电压线VDD电连接，所述第五晶体管M5的漏极与所述驱动晶体管M0的源极电连接；
所述数据写入电路包括第六晶体管M6，所述补偿控制电路包括第七晶体管M7，所述第三储能电路包括第三电容C3；所述驱动电路包括驱动晶体管M0；
所述第六晶体管M6的栅极与所述扫描线G1电连接，所述第六晶体管M6的源极与所述数据线DT电连接，所述第六晶体管M6的漏极与所述驱动晶体管M0的漏极电连接；
所述第七晶体管M7的栅极与所述扫描线G1电连接，所述第七晶体管M7的源极与所述驱动晶体管M0的栅极电连接，所述第七晶体管M7的漏极与所述驱动晶体管M0的漏极电连接；
所述第三电容C3的第一极板与所述驱动晶体管M0的栅极电连接，所述第三电容C3的第二极板与电源电压线VDD电连接；
所述第一复位电路包括第八晶体管M8；
所述第八晶体管M8的栅极与所述第一复位控制线RA电连接，所述第八晶体管M8的源极与所述初始电压线I0电连接，所述第八晶体管M8的漏极与所述驱动晶体管M0的栅极电连接；
所述第二复位电路包括第九晶体管M9；
所述第九晶体管M9的栅极与所述第一复位控制线RA电连接，所述第九晶体管M9的源极与所述初始电压线I0电连接，所述第九晶体管M9的漏极与微型发光二极管ML的阳极电连接；
所述微型发光二极管ML的阴极与低电压线VSS电连接；
所述第一发光控制电路包括第十晶体管M10；
M10的栅极与第一控制节点N1电连接，M10的源极与M0的漏极电连 接，M10的漏极与ML的阳极电连接。
在图4所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图4所示的像素电路的至少一实施例中，所述发光元件为微型发光二极管ML，但不以此为限。
在图4所示的像素电路的至少一实施例中，M8的栅极也可以与第二复位控制线RB电连接，此时，在第二写入阶段S2，M8打开，以对M0的栅极的电位进行初始化。
在图4所示的像素电路的至少一实施例中，将M6的栅极信号、M1的栅极信号和M3的栅极信号分开，以实现显示数据电压、第一控制电压、第二控制电压的分时写入，所述第一控制电压和所述第二控制电压可以为发光时间控制数据电压。
如图5所示，本公开图4所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的第一写入阶段S1、第二写入阶段S2、充电补偿阶段S3和发光阶段S4；
在第一写入阶段S1，RA提供低电压信号，RB提供高电压信号，G1提供高电压信号，EM和Hf提供高电压信号，DT提供第一控制电压，M1打开，以将第一控制电压Data_T1写入第二控制节点N2，在进行中高灰阶显示时，第一控制电压为低电压信号，M2打开，以控制E1与第一控制节点N1之间连通；在进行低灰阶显示时，第一控制电压为高电压信号，M2关断，C1维持第二控制节点N2的电位；
在第一写入阶段S1，RA提供低电压信号，M8和M9打开，I0提供初始电压Vinit至M0的栅极和ML的阳极，以使得在充电补偿阶段开始时，M0能够导通，并控制ML不发光，并清除ML的阳极残留的电荷；
在第二写入阶段S2，RA提供高电压信号，RB提供低电压信号，G1提供高电压信号，EM和Hf提供高电压信号，DT提供第二控制电压，M3打开，以将第二控制电压Data_T2写入第三控制节点N3；在进行中高灰阶显示时，第二控制电压为高电压信号，M4关断；在进行低灰阶显示时，第二控制电压为低电压信号，M4打开，以控制Hf与N1之间连通，C2维持第三控制节点 N3的电位；
在充电补偿阶段S3，RA提供高电压信号，RB提供高电压信号，G1提供低电压信号，EM和Hf提供高电压信号，DT提供显示数据电压Data_I，M6和M7打开，将显示数据电压Data_I写入M0的源极，M3的栅极与M3的漏极之间连通；
在充电补偿阶段S3开始时，M0导通，显示数据电压Data_I通过导通的M0和M7为C3充电，直至M0关断，此时M0的栅极的电位为Data_I+Vth，Vth为M0的阈值电压；
在发光阶段S4，EM提供低电压信号，在发光阶段S4包括的部分时间段，Hf提供低电压信号；
当进行中高灰阶显示时，N1与EM之间连通，在发光阶段S4，M3驱动ML发光；
当进行低灰阶显示时，N1与Hf之间连通，当Hf输出低电压信号时，M3驱动ML发光。
如图5所示，RA提供的第一复位控制信号的低电平脉宽、RB提供的第二复位控制信号的低电平脉宽，以及，G1提供的扫描信号的低电平脉宽相等，因此能够通过一个GOA(Gate On Array，阵列基板行驱动)电路提供第一复位控制信号、第二复位控制信号和扫描信号，以减少采用的GOA电路的数目，利于实现窄边框。
在本公开至少一实施例中，RA提供的第一复位控制信号的低电平脉宽、RB提供的第二复位控制信号的低电平脉宽，以及，G1提供的扫描信号的低电平脉宽可调整，且低电平脉宽可以不一致。
在本公开至少一实施例中，G1提供的扫描信号的低电平脉宽可以大于等于2μs，以能够充分进行充电及阈值电压补偿。
图6是图4所示的像素电路的至少一实施例的工作时序图，图6与图5的区别在于：G1提供的扫描信号的低电平脉宽较长，G1提供的扫描信号的低电平脉宽大于RSTA提供的第一复位控制信号的低电平脉宽，G1提供的扫描信号的低电平脉宽大于RSTB提供的第二复位控制信号的低电平脉宽，以提升充电补偿的时间，能够充分进行阈值电压补偿。
如图7所示，本公开图4所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的第一写入阶段S1、第二写入阶段S2、充电补偿阶段S3和发光阶段S4；
在第一写入阶段S1，RA提供高电压信号，RB提供低电压信号，G1提供高电压信号，EM和Hf提供高电压信号，DT提供第一控制电压Data_T1，M1关断，M3打开，DT提供第一控制电压Data_T1至第三控制节点N3，C2维持第三控制节点N3的电位，在进行中高灰阶显示时，第一控制电压Data_T1为高电压信号，在进行低灰阶显示时，第一控制电压Data_T1为低电压信号，M4导通，第一控制节点N1与Hf之间连通；
在第二写入阶段S2，RA提供低电压信号，RB提供高电压信号，G1提供高电压信号，EM和Hf提供高电压信号，DT提供第二控制电压Data_T2，M1打开，M3关断，DT提供第二控制电压Data_T2至第二控制节点N2，C1维持第二控制节点N2的电位；在进行中高灰阶显示时，第二控制电压Data_T2为低电压信号，M2导通，第一控制节点N1与E1之间连通；在进行低灰阶显示时，第二控制电压Data_T2为高电压信号；
在充电补偿阶段S3，RA提供高电压信号，RB提供高电压信号，G1提供低电压信号，EM和Hf提供高电压信号，DT提供显示数据电压Data_I，M6和M7打开，将显示数据电压Data_I写入M0的源极，M3的栅极与M3的漏极之间连通；
在充电补偿阶段S3开始时，M0导通，显示数据电压Data_I通过导通的M0和M7为C3充电，直至M0关断，此时M0的栅极的电位为Data_I+Vth，Vth为M0的阈值电压；
在发光阶段S4，EM提供低电压信号，在发光阶段S4包括的部分时间段，Hf提供低电压信号；
当进行中高灰阶显示时，N1与EM之间连通，在发光阶段S4，M3驱动ML发光；
当进行低灰阶显示时，N1与Hf之间连通，当Hf输出低电压信号时，M3驱动ML发光。
在图7中，G1提供的扫描信号的低电平脉宽大于第一复位控制信号的低 电平脉宽，G1提供的扫描信号的低电平脉宽大于第二复位控制信号的低电平脉宽，以使得充电补偿阶段持续的时间长，能够充分对驱动晶体管的阈值电压进行补偿。在实际操作时，G1提供的扫描信号的低电平脉宽、第一复位控制信号的低电平脉宽和第二复位控制信号的低电平脉宽也可以相等。
本公开图8A所示的像素电路的至少一实施例与本公开图4所示的像素电路的至少一实施例的区别在于：M8的栅极和M9的栅极都与第二复位控制线RB电连接。
本公开至少一实施例所述的像素电路还包括复用控制电路；
所述复用控制电路分别与复用控制端、源极驱动器的电压输出端和所述数据线电连接，用于在所述复用控制端提供的复用控制信号的控制下，控制所述电压输出端与所述数据线之间连通。
在具体实施时，所述像素电路还可以包括复用控制电路，其在复用控制信号的控制下，控制所述源极驱动器的电压输出端与所述数据线电连接，这样可以减少所述源极驱动器的电压输出端的个数。
如图8B所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括复用控制电路80；
所述复用控制电路80分别与复用控制端MX、源极驱动器SD的电压输出端CH，以及，所述数据线DT电连接，用于在所述复用控制端MX提供的复用控制信号的控制下，控制所述电压输出端CH与所述数据线DT之间连通。
本公开实施例所述的驱动方法，应用于上述的像素电路，显示阶段包括第一写入阶段和第二写入阶段；所述驱动方法包括：
在第一写入阶段，第一控制电路在第一复位控制信号的控制下，将数据线提供的第一控制电压提供至第二控制节点，第一控制电路在所述第二控制节点的电位的控制下，控制是否将第一发光控制信号提供至第一控制节点；
在第二写入阶段，第二控制电路在第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入第三控制节点，第二控制电路在所述第三控制节点的电位的控制下，控制是否将第二发光控制信号提供至所述第一控制节点。
本公开至少一实施例所述的驱动方法包括：
在进行中高灰阶显示时，在所述第一写入阶段，第一控制电路在所述第二控制节点的电位的控制下，控制将第一发光控制信号提供至第一控制节点，在所述第二写入阶段，所述第二控制电路在所述第三控制节点的电位的控制下，控制停止将第二发光控制信号提供至至所述第一控制节点；
在进行低灰阶显示时，在所述第一写入阶段，第一控制电路在所述第二控制节点的电位的控制下，停止控制将第一发光控制信号提供至第一控制节点，在所述第二写入阶段，所述第二控制电路在所述第三控制节点的电位的控制下，控制将第二发光控制信号提供至所述第一控制节点。
本公开实施例所述的显示基板包括衬底基板和设置于所述衬底基板上的多行多列上述的像素电路。
在本公开至少一实施例中，位于同一列的像素电路设置于两列数据线之间；所述数据线沿第一方向延伸；
第a行像素电路设置于第a行扫描线和第a行第一电压线之间，a为正整数；
所述第a行扫描线和所述第a行第一电压线沿第二方向延伸；
所述第一方向和所述第二方向相交。
可选的，所述第一方向可以为竖直方向，所述第二方向可以为水平方向，但不以此为限。
在相关技术中，在相邻两列像素电路间设置有两列数据线，其中一列数据线用于提供发光时间数据电压，另一列数据线用于提供显示数据电压。而在本公开至少一实施例中，在相邻两列像素电路之间仅设置有一列数据线。
图9是图4所示的像素电路的至少一实施例的布局图。图10是图9中的第一栅金属层的布局图，图11是图9中的半导体层的布局图，图12是图9中的第二栅金属层的布局图，图13是图9中的源漏金属层的布局图。
在本公开至少一实施例中，第一栅金属层、半导体层、第二栅金属层和源漏金属层可以沿着远离衬底基板的方向依次排列。
如图9所示，标号为VSS的为低电压线，标号为DT的为数据线，标号为I0的为初始电压线，标号为RA的为第一复位控制线，标号为RB的为第 二复位控制线，标号为E1的为第一发光控制线，标号为G1的为扫描线。
在图9所示的至少一实施例中，第二发光控制线Hf可以包括相互电连接的沿竖直方向延伸的第一发光控制线部Hf1和沿水平方向延伸的第二发光控制线部Hf2。
如图9所示，VSS、I0、RB、RA、E1、VDD和G1都沿水平方向延伸；
DT沿竖直方向延伸；
第一电容C1和第二电容C2设置于VSS与I0之间；
M3设置于RB与I0之间；
M1、M8、M9、M4和M2都设置于RA与VDD之间；
C3、M5、M10、M6、M0和M7都设置于E1与G1之间。
在图10中，标号为C2b1的为第二电容的第一极板部，标号为C1b1的为第一电容的第一极板部，标号为C3b1的为第三电容的第一极板部，标号为G0a的为M0的底栅。
在图11中，标号为A0的为M0的有源图形，标号为A1的为M1的有源图形，标号为A2的为M2的有源图形，标号为A3的为M3的有源图形，标号为A4的为M4的有源图形，标号为A5的为M5的有源图形，标号为A6的为M6的有源图形，标号为A7的为M7的有源图形，标号为A8的为M8的有源图形，标号为A9的为M9的有源图形，标号为A10的为M10的有源图形。
在图12中，标号为G0b的为G0的顶栅，标号为C1a的为第一电容的第一极板，标号为C2a的为第二电容的第一极板，标号为C3a的为第三电容的第一极板。
在图13中，标号为C2b2的为第二电容的第二极板部，标号为C1b2的为第一电容的第二极板部，标号为C3b2的为第三电容的第二极板部。
在图9-图13的至少一实施例中，C1b1与C1b2电连接，C1b1与C1b2组成C1的第二极板，C2b1与C2b2电连接，C2b1与C2b2组成C2的第二极板，C3b1与C3b2电连接，C3b1与C3b2组成C3的第二极板。
本公开实施例所述的显示面板包括上述的显示基板。
本公开至少一实施例所述的显示面板还包括源极驱动器、多列数据线和 多路复用电路；
位于同一列的多个像素电路都与同一列数据线电连接；
所述多路复用电路分别与所述源极驱动器的多个电压输出端、多个复用控制端和所述多列数据线电连接，用于在所述复用控制端提供的复用控制信号的控制下，将所述源极驱动器通过其电压输出端提供的电压信号写入所述数据线。
在具体实施时，所述显示面板还可以包括源极驱动器、多列数据线和多路复用电路，多路复用电路在复用控制信号的控制下，将源极驱动器通过其电压输出端提供的电压信号写入数据线。
如图14所示，本公开至少一实施例所述的显示面板还包括源极驱动器SD、多路复用电路90、第一列数据线DL1、第二列数据线DL2、第三列数据线DL3、第四列数据线DL4、第五列数据线DL5、第六列数据线DL6、第七列数据线DL7、第八列数据线DL8、第九列数据线DL9、第十列数据线DL10、第十一列数据线DL11、第十二列数据线DL12、第十三列数据线DL13、第十四列数据线DL14、第十五列数据线DL15、第十六列数据线DL16、第十七列数据线DL17和第十八列数据线DL18；
所述源极驱动器SD包括第一电压输出端CH1、第二电压输出端CH2和第三电压输出端CH3；
所述第一电压输出端CH1、所述第二电压输出端CH2和所述第三电压输出端CH3分别与所述多路复用电路90的输入端电连接；
所述多路复用电路90的输出端分别与DL1、DL2、DL3、DL4、DL5、DL6、DL7、DL8、DL9、DL10、DL11、DL12、DL13、DL14、DL15、DL16、DL17和DL18电连接；
所述多路复用电路90分别与第一复用控制端MX1、第二复用控制端MX2、第三复用控制端MX3、第四复用控制端MX4、第五复用控制端MX5和第六复用控制端MX6电连接，用于在各复用控制端提供的复用控制信号的控制下，控制各电压输出端与各数据线之间连通或断开。
在本公开至少一实施例中，所述多路复用电路分别与N个复用控制端电连接，所述多路复用电路包括M个复用子电路，N和M为大于1的整数；
每一所述复用子电路都与所述源极驱动器的电压输出端、所述N个复用控制端和N列所述数据线电连接，用于在第n个复用控制端提供的第n复用控制信号的控制下，控制将该电压输出端提供的电压信号至所述N列数据线中的第n数据线；
n为小于等于N的正整数。
在具体实施时，当所述多路复用电路分别与N个复用控制端电连接时，所述多路复用电路可以包括M个复用子电路；所述复用子电路在第n复用控制信号的控制下，将所述源极驱动器的电压输出端提供的电压信号提供至数据线。
如图15所示，在图14所示的显示面板的至少一实施例的基础上，所述多路复用电路包括第一复用子电路101、第二复用子电路102和第三复用子电路103；
所述第一复用子电路101分别与第一复用控制端MX1、第二复用控制端MX2、第三复用控制端MX3、第四复用控制端MX4、第五复用控制端MX5和第六复用控制端MX6、第一电压输出端CH1、第一列数据线DL1、第四列数据线DL4、第七列数据线DL7、第十列数据线DL10、第十三列数据线DL13和第十六列数据线DL16电连接，用于在MX1提供的第一复用控制信号的控制下，控制CH1与DL1之间连通或断开，在MX2提供的第二复用控制信号的控制下，控制CH1与DL4之间连通，在MX3提供的第三复用控制信号的控制下，控制CH1与DL7之间连通或断开，在MX4提供的第四复用控制信号的控制下，控制CH1与DL10之间连通或断开，在MX5提供的第五复用控制信号的控制下，控制CH1与DL13之间连通或断开，在MX6提供的第六复用控制信号的控制下，控制CH1与DL16之间连通或断开；
所述第二复用子电路102分别与第一复用控制端MX1、第二复用控制端MX2、第三复用控制端MX3、第四复用控制端MX4、第五复用控制端MX5和第六复用控制端MX6、第一电压输出端CH1、第二列数据线DL2、第五列数据线DL5、第八列数据线DL8、第十一列数据线DL11、第十四列数据线DL14和第十七列数据线DL17电连接，用于在MX1提供的第一复用控制信号的控制下，控制CH1与DL2之间连通或断开，在MX2提供的第二复用控 制信号的控制下，控制CH1与DL5之间连通，在MX3提供的第三复用控制信号的控制下，控制CH1与DL8之间连通或断开，在MX4提供的第四复用控制信号的控制下，控制CH1与DL11之间连通或断开，在MX5提供的第五复用控制信号的控制下，控制CH1与DL14之间连通或断开，在MX6提供的第六复用控制信号的控制下，控制CH1与DL17之间连通或断开；
所述第三复用子电路103分别与第一复用控制端MX1、第二复用控制端MX2、第三复用控制端MX3、第四复用控制端MX4、第五复用控制端MX5和第六复用控制端MX6、第一电压输出端CH1、第三列数据线DL3、第六列数据线DL6、第九列数据线DL9、第十二列数据线DL12、第十五列数据线DL15和第十八列数据线DL18电连接，用于在MX1提供的第一复用控制信号的控制下，控制CH1与DL3之间连通或断开，在MX2提供的第二复用控制信号的控制下，控制CH1与DL6之间连通，在MX3提供的第三复用控制信号的控制下，控制CH1与DL9之间连通或断开，在MX4提供的第四复用控制信号的控制下，控制CH1与DL12之间连通或断开，在MX5提供的第五复用控制信号的控制下，控制CH1与DL15之间连通或断开，在MX6提供的第六复用控制信号的控制下，控制CH1与DL18之间连通或断开。
如图16所示，在图15所示的显示面板的至少一实施例的基础上，所述第一复用子电路可以包括第一复用晶体管T1、第二复用晶体管T2、第三复用晶体管T3、第四复用晶体管T4、第五复用晶体管T5和第六复用晶体管T6；
T1的栅极与MX1电连接，T1的源极与CH1电连接，T1的漏极与DL1电连接；
T2的栅极与MX2电连接，T2的源极与CH1电连接，T2的漏极与DL4电连接；
T3的栅极与MX3电连接，T3的源极与CH1电连接，T3的漏极与DL7电连接；
T4的栅极与MX4电连接，T4的源极与CH1电连接，T4的漏极与DL10电连接；
T5的栅极与MX5电连接，T5的源极与CH1电连接，T5的漏极与DL13电连接；
T6的栅极与MX6电连接，T6的源极与CH1电连接，T6的漏极与DL16电连接；
所述第二复用子电路可以包括第七复用晶体管T7、第八复用晶体管T8、第九复用晶体管T9、第十复用晶体管T10、第十一复用晶体管T11和第十二复用晶体管T12；
T7的栅极与MX1电连接，T7的源极与CH2电连接，T7的漏极与DL2电连接；
T8的栅极与MX2电连接，T8的源极与CH2电连接，T8的漏极与DL5电连接；
T9的栅极与MX3电连接，T9的源极与CH2电连接，T9的漏极与DL8电连接；
T10的栅极与MX4电连接，T10的源极与CH2电连接，T10的漏极与DL11电连接；
T11的栅极与MX5电连接，T11的源极与CH2电连接，T11的漏极与DL14电连接；
T12的栅极与MX6电连接，T12的源极与CH2电连接，T12的漏极与DL17电连接；
所述第三复用子电路可以包括第十三复用晶体管T13、第十四复用晶体管T14、第十五复用晶体管T15、第十六复用晶体管T16、第十七复用晶体管T17和第十八复用晶体管T18；
T13的栅极与MX1电连接，T13的源极与CH3电连接，T13的漏极与DL3电连接；
T14的栅极与MX2电连接，T14的源极与CH3电连接，T14的漏极与DL6电连接；
T15的栅极与MX3电连接，T15的源极与CH3电连接，T15的漏极与DL9电连接；
T16的栅极与MX4电连接，T16的源极与CH3电连接，T16的漏极与DL12电连接；
T17的栅极与MX5电连接，T17的源极与CH3电连接，T17的漏极与 DL15电连接；
T18的栅极与MX6电连接，T18的源极与CH3电连接，T18的漏极与DL18电连接。
在图16所示的显示面板的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图16所示的显示面板的至少一实施例中，DL1、DL4、DL7、DL10、DL13和DL16可以为红色数据线，DL2、DL5、DL8、DL11、DL14和DL17可以为绿色数据线，DL3、DL6、DL9、DL12、DL15和DL18可以为蓝色数据线，但不以此为限；
其中，所述红色数据线可以是为红色像素电路提供数据电压的数据线，所述绿色数据线可以是为绿色像素电路提供数据电压的数据线，所述蓝色数据线可以是为蓝色像素电路提供数据电压的数据线。
本公开图16所示的显示面板的至少一实施例在工作时，
当MX1提供低电压信号时，MX2、MX3、MX4、MX5和MX6都输出高高电压信号，T1、T7和T13打开，其他复用晶体管关断，CH1与DL1之间连通，CH2与DL2之间连通，CH3与DL3之间连通；
当MX2提供低电压信号时，MX1、MX3、MX4、MX5和MX6都输出高高电压信号，T2、T8和T14打开，其他复用晶体管关断，CH1与DL4之间连通，CH2与DL5之间连通，CH3与DL6之间连通；
当MX3提供低电压信号时，MX1、MX2、MX4、MX5和MX6都输出高高电压信号，T3、T9和T15打开，其他复用晶体管关断，CH1与DL7之间连通，CH2与DL8之间连通，CH3与DL9之间连通；
当MX4提供低电压信号时，MX1、MX2、MX3、MX5和MX6都输出高高电压信号，T4、T10和T16打开，其他复用晶体管关断，CH1与DL10之间连通，CH2与DL11之间连通，CH3与DL12之间连通；
当MX5提供低电压信号时，MX1、MX2、MX3、MX4和MX6都输出高高电压信号，T5、T11和T17打开，其他复用晶体管关断，CH1与DL13之间连通，CH2与DL14之间连通，CH3与DL15之间连通；
当MX6提供低电压信号时，MX1、MX2、MX3、MX4和MX5都输出 高高电压信号，T6、T12和T18打开，其他复用晶体管关断，CH1与DL16之间连通，CH2与DL17之间连通，CH3与DL18之间连通。
如图17所示，本公开图16所示的显示面板的至少一实施例在工作时，显示周期包括先后设置的第一写入时间段XT1、第二写入时间段XT2、第三写入时间段XT3和发光阶段FT；
所述第一写入时间段XT1包括先后设置的第一数据写入时间段t11和第二数据写入时间段t12；
所述第二写入时间段XT2包括先后设置的第三数据写入时间段t21和第四数据写入时间段t22；
所述第三写入时间段XT3包括先后设置的第五数据写入时间段t31和第六数据写入时间段t32；
在第一数据写入时间段t11，MX1、MX2、MX3、MX4、MX5和MX6依次输出低电压信号；
当MX1输出低电压信号时，T1、T7和T13打开，其他复用晶体管关断，CH1与DL1之间连通，CH2与DL2之间连通，CH3与DL3之间连通，CH1提供第一发光时间控制数据电压至DL1，CH2提供第二发光时间控制数据电压至DL2，CH3提供第三发光时间控制数据电压至DL3；
当MX2输出低电压信号时，T2、T8和T14打开，其他复用晶体管关断，CH1与DL4之间连通，CH2与DL5之间连通，CH3与DL6之间连通，CH1提供第四发光时间控制数据电压至DL4，CH2提供第五发光时间控制数据电压至DL5，CH3提供第九发光时间控制数据电压至DL6；
当MX3输出低电压信号时，T3、T9和T15打开，其他复用晶体管关断，CH1与DL7之间连通，CH2与DL8之间连通，CH3与DL9之间连通，CH1提供第四发光时间控制数据电压至DL7，CH2提供第五发光时间控制数据电压至DL8，CH3提供第九发光时间控制数据电压至DL9；
当MX4提供低电压信号时，T4、T10和T16打开，其他复用晶体管关断，CH1与DL10之间连通，CH2与DL11之间连通，CH3与DL12之间连通，CH1提供第十发光时间控制数据电压至DL10，CH2提供第十一发光时间控制数据电压至DL11，CH3提供第十二发光时间控制数据电压至DL12；
当MX5提供低电压信号时，T5、T11和T17打开，其他复用晶体管关断，CH1与DL13之间连通，CH2与DL14之间连通，CH3与DL15之间连通，CH1提供第十三发光时间控制数据电压至DL13，CH2提供第十四发光时间控制数据电压至DL14，CH3提供第十五发光时间控制数据电压至DL15；
当MX6提供低电压信号时，T6、T12和T18打开，其他复用晶体管关断，CH1与DL16之间连通，CH2与DL17之间连通，CH3与DL18之间连通，CH1提供第十六发光时间控制数据电压至DL16，CH2提供第十七发光时间控制数据电压至DL17，CH3提供第十八发光时间控制数据电压至DL18；
由于各数据线上具有寄生电容，因此各发光时间控制数据电压充电至各数据线的寄生电容；
在第二数据写入时间段t12，RA提供低电压信号，RB提供高电压信号，像素电路中的第一晶体管M1导通，以将各数据线上的发光时间控制数据电压写入第二控制节点N2；
在第三数据写入时间段t21，MX1、MX2、MX3、MX4、MX5和MX6依次输出低电压信号；
当MX1输出低电压信号时，T1、T7和T13打开，其他复用晶体管关断，CH1与DL1之间连通，CH2与DL2之间连通，CH3与DL3之间连通，CH1提供第十九发光时间控制数据电压至DL1，CH2提供第二十发光时间控制数据电压至DL2，CH3提供第二十一发光时间控制数据电压至DL3；
当MX2输出低电压信号时，T2、T8和T14打开，其他复用晶体管关断，CH1与DL4之间连通，CH2与DL5之间连通，CH3与DL6之间连通，CH1提供第二十二发光时间控制数据电压至DL4，CH2提供第二十三发光时间控制数据电压至DL5，CH3提供第二十四发光时间控制数据电压至DL6；
当MX3输出低电压信号时，T3、T9和T15打开，其他复用晶体管关断，CH1与DL7之间连通，CH2与DL8之间连通，CH3与DL9之间连通，CH1提供第二十五发光时间控制数据电压至DL7，CH2提供第二十六发光时间控制数据电压至DL8，CH3提供第二十七发光时间控制数据电压至DL9；
当MX4提供低电压信号时，T4、T10和T16打开，其他复用晶体管关断，CH1与DL10之间连通，CH2与DL11之间连通，CH3与DL12之间连 通，CH1提供第二十八发光时间控制数据电压至DL10，CH2提供第二十九发光时间控制数据电压至DL11，CH3提供第三十发光时间控制数据电压至DL12；
当MX5提供低电压信号时，T5、T11和T17打开，其他复用晶体管关断，CH1与DL13之间连通，CH2与DL14之间连通，CH3与DL15之间连通，CH1提供第三十一发光时间控制数据电压至DL13，CH2提供第三十二发光时间控制数据电压至DL14，CH3提供第三十三发光时间控制数据电压至DL15；
当MX6提供低电压信号时，T6、T12和T18打开，其他复用晶体管关断，CH1与DL16之间连通，CH2与DL17之间连通，CH3与DL18之间连通，CH1提供第三十四发光时间控制数据电压至DL16，CH2提供第三十五发光时间控制数据电压至DL17，CH3提供第三十六发光时间控制数据电压至DL18；
由于各数据线上具有寄生电容，因此各发光时间控制数据电压充电至各数据线的寄生电容；
在第四数据写入时间段t22，RB提供低电压信号，RA提供高电压信号，像素电路中的M3导通，以将各数据线上的发光时间控制数据电压写入第三控制节点N3；
在第五数据写入时间段t31，MX1、MX2、MX3、MX4、MX5和MX6依次输出低电压信号；
当MX1输出低电压信号时，T1、T7和T13打开，其他复用晶体管关断，CH1与DL1之间连通，CH2与DL2之间连通，CH3与DL3之间连通，CH1提供第一显示数据电压至DL1，CH2提供第二显示数据电压至DL2，CH3提供第三显示数据电压至DL3；
当MX2输出低电压信号时，T2、T8和T14打开，其他复用晶体管关断，CH1与DL4之间连通，CH2与DL5之间连通，CH3与DL6之间连通，CH1提供第四显示数据电压至DL4，CH2提供第五显示数据电压至DL5，CH3提供第六显示数据电压至DL6；
当MX3输出低电压信号时，T3、T9和T15打开，其他复用晶体管关断， CH1与DL7之间连通，CH2与DL8之间连通，CH3与DL9之间连通，CH1提供第七显示数据电压至DL7，CH2提供第八显示数据电压至DL8，CH3提供第九显示数据电压至DL9；
当MX4提供低电压信号时，T4、T10和T16打开，其他复用晶体管关断，CH1与DL10之间连通，CH2与DL11之间连通，CH3与DL12之间连通，CH1提供第十显示数据电压至DL10，CH2提供第十一显示数据电压至DL11，CH3提供第十二显示数据电压至DL12；
当MX5提供低电压信号时，T5、T11和T17打开，其他复用晶体管关断，CH1与DL13之间连通，CH2与DL14之间连通，CH3与DL15之间连通，CH1提供第十三显示数据电压至DL13，CH2提供第十四显示数据电压至DL14，CH3提供第十五显示数据电压至DL15；
当MX6提供低电压信号时，T6、T12和T18打开，其他复用晶体管关断，CH1与DL16之间连通，CH2与DL17之间连通，CH3与DL18之间连通，CH1提供第十六显示数据电压至DL16，CH2提供第十七显示数据电压至DL17，CH3提供第十八显示数据电压至DL18；
由于各数据线上具有寄生电容，因此各发光时间控制数据电压充电至各数据线的寄生电容；
在第六数据写入时间段t32，G1提供低电压信号，像素电路中的M6和M7打开，以进行充电和阈值电压补偿，实现显示数据电压写入；
在发光阶段FT，E1提供低电压信号，M5打开，以控制电源电压线VDD与驱动晶体管M0的源极之间连通；
在进行中高灰阶显示时，像素电路中的M2打开，以控制第一发光控制线E1与第一控制节点N1之间连通；
在进行低灰阶显示时，像素电路中的M4打开，以控制第二发光控制线Hf与第一控制节点N1之间连通。
本公开至少一实施例所述的显示面板在工作时，也可以在第二数据写入时间段，控制RA提供高电压信号，控制RB提供低电压信号，在第四数据写入时间段，控制RA提供低电压信号，控制RB提供高电压信号。
在本公开至少一实施例中，各复用控制端的开启时间可以减少，快速完 成对数据线上的发光时间控制数据电压的存入，以提升RA的开启时间、RB的开启时间和G1的开启时间，以为像素电路内部的数据电压写入，充电和阈值电压补偿提供更充分的时间。
在本公开至少一实施例中，通过GOA(Gate On Array，阵列基板行驱动)时序控制，使得第二发光控制线Hf的所有低电平阶段处于发光阶段，避免第二发光控制信号的电位被高频拉低对显示数据电压写入造成耦合影响，对驱动晶体管的栅极电压产生扰动，从而较相关的像素电路减少了一个防止Hf耦合影响的晶体管。
在具体实施时，由于数据线上寄生电容的存在，各数据线之间会互相耦合影响而改变电压。
如图18所示，在进行中高灰阶显示时，如果在第二数据写入时间段，RB提供低电压信号，RA提供高电压信号，在第四数据写入阶段，RA提供低电压信号，RB提供高电压信号；
在第一数据写入时间段t11，DL1接入的数据电压Vdata可以为18V；
在第三数据写入时间段t21，DL1接入的数据电压Vdata可以为0V；
在第五数据写入时间段t31，DL1接入的数据电压Vdata可以为13V；
当MX1打开时，DL1写入数据电压，DL1在MX1关闭后保持上一时刻电位，如图18中的DL1的理想电压VDL10，18V电压信号和0V电压信号是分别控制第一发光控制线接入和第二发光控制线接入的信号，对灰阶显示影响较小，而0V至13V跳变时，为G1的开启时刻，DL1上的电压会随DL4上的电压跳变，会影响数据电压写入，造成写入电压为较高电位，从而造成与DL1电连接的像素显示比预期暗。
在图18中，VDL40为DL4上的理想电压，VDL1为DL1上的实际电压。
如图19所示，在进行中高灰阶显示时，如果在第二数据写入时间段t12，RA提供低电压信号，RB提供高电压信号，在第四数据写入时间段t22，RB提供低电压信号，RA提供高电压信号；
在第一数据写入时间段t11，DL1接入的数据电压Vdata可以为0V；
在第三数据写入时间段t21，DL1接入的数据电压Vdata可以为18V；
在第五数据写入时间段t31，DL1接入的数据电压Vdata可以为13V；
通过如上设置，在G1的开启时刻，DL1上的数据电压由18V跳变为13V，降低了数据电压的跳变幅度，改善像素显示存在差异的问题。
如图20所示，本公开图16所示的显示面板的至少一实施例在工作时，显示周期包括先后设置的第一写入时间段、第二写入时间段、第三写入时间段和发光阶段FT；
所述第一写入时间段包括第一数据写入时间段t11和第二数据写入时间段t12；第一数据写入时间段包含于第二数据写入时间段t12；
所述第二写入时间段包括第三数据写入时间段t21和第四数据写入时间段t22；第三数据写入时间段t21包含于第四数据写入时间段t22；
第三写入时间段包括先后设置的第五数据写入时间段t31和第六数据写入时间段t32；
在第一数据写入时间段t11，MX1、MX2、MX3、MX4、MX5和MX6依次输出低电压信号，MX1控制的晶体管、MX2控制的晶体管、MX3控制的晶体管、MX4控制的晶体管、MX5控制的晶体管和MX6控制的晶体管依次打开，以写入相应的发光时间控制数据电压；
在第二数据写入时间段t12，RA提供低电压信号，RB和G1提供高电压信号，像素电路中的第一晶体管M1导通，以将各数据线上的发光时间控制数据电压写入第二控制节点N2；
在第三数据写入时间段t21，MX1、MX2、MX3、MX4、MX5和MX6依次输出低电压信号，MX1控制的晶体管、MX2控制的晶体管、MX3控制的晶体管、MX4控制的晶体管、MX5控制的晶体管和MX6控制的晶体管依次打开，以写入相应的发光时间控制数据电压；
在第四数据写入时间段t22，RB提供低电压信号，RA和G1提供高电压信号，像素电路中的M3导通，以将各数据线上的发光时间控制数据电压写入第三控制节点N3；
在第五数据写入时间段t31，MX1、MX2、MX3、MX4、MX5和MX6依次输出低电压信号，MX1控制的晶体管、MX2控制的晶体管、MX3控制的晶体管、MX4控制的晶体管、MX5控制的晶体管和MX6控制的晶体管依次打开，以写入相应的显示数据电压；
在第六数据写入时间段t32，G1提供低电压信号，RA和RB提供高电压信号，像素电路中的M6和M7打开，以进行充电和阈值电压补偿，实现显示数据电压写入；
在发光阶段FT，EM输出低电压信号；
在发光阶段FT包括的部分时间段，Hf输出低电压信号；
当进行中高灰阶显示时，在所述发光阶段FT，像素电路中的驱动晶体管M0驱动微型发光二极管ML发光；
在进行低灰阶显示时，在所述发光阶段FT，当Hf提供低电压信号时，像素电路中的驱动晶体管M0驱动微型发光二极管ML发光。
在图20中，标号为E1_N的为与E1相邻的下一行发光控制线。
在相关技术中，通常采用的电流+时间控制，在固定电流下较短时间发光，实现低灰阶显示。但是，在一帧显示时间内较短时间发光后，LED(发光二极管)进入黑态，人眼会明显感受到闪烁，从而引起观看者的不适。基于此，本公开至少一实施例提供一种像素电路，通过高频控制发光时长，将短发光时长分散到一帧时间内，减少闪烁。
在本公开至少一实施例中，由于E1提供的发光控制信号持续为低电压信号的时间比较长，因此在E1的整个持续为低电压信号的时间内，Hf提供的发光控制信号为高频脉冲信号。
图21是本公开至少一实施例所述的显示面板的工作时序图。
在图21中，标号为ESTV的为第一起始电压，标号为ECK的为第一时钟信号，标号为ECB的为第二时钟信号，标号为GSTV的为第二起始电压，标号为GCK的为第三时钟信号，标号为GCB的为第四时钟信号，标号为Hf的为第二发光控制线，标号为MX1的为第一复用控制端，标号为MX2的为第二复用控制端，标号为MX3的为第三复用控制端，标号为MX4的为第四复用控制端，标号为MX5的为第五复用控制端，标号为MX6的为第六复用控制端，标号为Vdata的为数据电压。
本公开实施例所述的驱动方法，应用于上述的显示面板，显示周期包括第一写入时间段和第二写入时间段；所述第一写入时间段包括第一数据写入时间段和第二数据写入时间段，所述第二写入时间段包括第三数据写入时间 段和第四数据写入时间段；所述驱动方法包括：
在第一数据写入时间段，多路复用电路在复位控制信号的控制下，将源极驱动器通过其电压输出端提供的第一控制电压写入数据线；
在第二数据写入时间段，第一控制电路在第一复位控制信号的控制下，将数据线提供的第一控制电压提供至第二控制节点，第一控制电路在所述第二控制节点的电位的控制下，控制是否将第一发光控制信号提供至第一控制节点；
在第三数据写入时间段，多路复用电路在复位控制信号的控制下，将源极驱动器通过其电压输出端提供的第二控制电压写入数据线；
在第四数据写入时间段，第二控制电路在第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入第三控制节点，第二控制电路在所述第三控制节点的电位的控制下，控制是否将第二发光控制信号提供至所述第一控制节点。
在本公开至少一实施例中，所述第一数据写入时间段和第二数据写入时间段先后设置，所述第三数据写入时间段和第四数据写入时间段先后设置；或者，
所述第一数据写入时间段包含于所述第二数据写入时间段，所述第三数据写入时间段包含于所述第四数据写入时间段。
本公开实施例所述的显示装置包括上述的显示面板。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (25)

  1. 一种像素电路，包括发光元件、驱动电路、第一发光控制电路、第一控制电路和第二控制电路；
    所述驱动电路用于产生驱动发光元件的驱动电流；
    所述第一发光控制电路分别与第一控制节点、所述驱动电路的第一端和发光元件电连接，用于在所述第一控制节点的电位的控制下，控制所述驱动电路的第一端与所述发光元件之间连通；
    所述第一控制电路分别与数据线、第一复位控制线、第一发光控制线、所述第一控制节点和第二控制节点电连接，用于在所述第一复位控制线提供的第一复位控制信号的控制下，将所述数据线提供的第一控制电压提供至所述第二控制节点，在所述第二控制节点的电位的控制下，控制所述第一发光控制线提供第一发光控制信号至所述第一控制节点；
    所述第二控制电路分别与所述数据线、第二复位控制线、第二发光控制线、所述第一控制节点和第三控制节点电连接，用于在所述第二复位控制线提供的第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入所述第三控制节点，在所述第三控制节点的电位的控制下，控制所述第二发光控制线提供第二发光控制信号至所述第一控制节点。
  2. 如权利要求1所述的像素电路，其中，所述第一控制电路包括第一写入控制电路、第一储能电路和第二写入控制电路；
    所述第一写入控制电路分别与第一复位控制线、所述数据线和第二控制节点电连接，用于在所述第一复位控制信号的控制下，将所述数据线提供的第一控制电压提供至所述第二控制节点；
    所述第一储能电路与所述第二控制节点电连接，用于储能电路；
    所述第二写入控制电路分别与所述第二控制节点、所述第一发光控制线和所述第一控制节点电连接，用于在所述第二控制节点的电位的控制下，控制所述第一发光控制线提供第一发光控制信号至所述第一控制节点。
  3. 如权利要求1所述的像素电路，其中，所述第二控制电路包括第三写入控制电路、第二储能电路和第四写入控制电路；
    所述第三写入控制电路分别与所述第二复位控制线、所述数据线和所述第三控制节点电连接，在所述第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入所述第三控制节点；
    所述第二储能电路与所述第三控制节点电连接，用于储存电能；
    所述第四写入控制电路分别与所述第三控制节点、所述第二发光控制线和所述第一控制节点电连接，用于在所述第三控制节点的电位的控制下，控制所述第二发光控制线提供第二发光控制信号至所述第一控制节点。
  4. 如权利要求2所述的像素电路，其中，所述第一写入控制电路包括第一晶体管，所述第一储能电路包括第一电容，第二写入控制电路包括第二晶体管；
    所述第一晶体管的栅极与所述第一复位控制线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述第二控制节点电连接；
    所述第一电容的第一极板与所述第二控制节点电连接，所述第一电容的第二极板与第一初始电压线电连接；
    所述第二晶体管的栅极与所述第二控制节点电连接，所述第二晶体管的第一极与所述第一发光控制线电连接，所述第二晶体管的第二极与所述第一控制节点电连接。
  5. 如权利要求3所述的像素电路，其中，第三写入控制电路包括第三晶体管，所述第二储能电路包括第二电容，所述第四写入控制电路包括第四晶体管；
    所述第三晶体管的栅极与所述第二复位控制线电连接，所述第三晶体管的的第一极与所述数据线电连接，所述第三晶体管的第二极与所述第三控制节点电连接；
    所述第二电容的第一极板与所述第三控制节点电连接，所述第二电容的第二极板与第二初始电压线电连接；
    所述第四晶体管的栅极与所述第三控制节点电连接，所述第四晶体管的第一极与所述第二发光控制线电连接，所述第四晶体管的第二极与所述第一控制节点电连接。
  6. 如权利要求1所述的像素电路，其中，还包括第二发光控制电路；
    所述第二发光控制电路分别与第一发光控制线、电源电压线和所述驱动电路的第二端电连接，用于在所述第一发光控制信号的控制下，控制所述电源电压线与所述驱动电路的第二端之间连通。
  7. 如权利要求1所述的像素电路，其中，还包括数据写入电路、补偿控制电路和第三储能电路；
    所述数据写入电路分别与扫描线、所述数据线和所述驱动电路的第二端电连接，用于在所述扫描线提供的扫描信号的控制下，将所述数据线提供的显示数据电压写入所述驱动电路的第二端；
    所述补偿控制电路分别与所述扫描线、所述驱动电路的控制端和所述驱动电路的第一端电连接，用于在所述扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
    所述第三储能电路与所述驱动电路的控制端电连接，用于储存电能。
  8. 如权利要求1所述的像素电路，其中，还包括第一复位电路；
    所述第一复位电路分别与第三复位控制线、第三初始电压线和所述驱动电路的控制端电连接，用于在所述第三复位控制线提供的第三复位控制信号的控制下，将所述第三初始电压线提供的第三初始电压写入所述驱动电路的控制端。
  9. 如权利要求8所述的像素电路，其中，还包括第二复位电路；
    所述第二复位电路分别与第四复位控制线、第四初始电压线和所述发光元件的第一极电连接，用于在所述第四复位控制线提供的第四复位控制信号的控制下，将所述第四初始电压线提供的第四初始电压写入所述发光元件的第一极；
    所述发光元件的第二极与第一电压线电连接。
  10. 如权利要求9所述的像素电路，其中，所述第三复位控制线为所述第一复位控制线或所述第二复位控制线；
    所述第四复位控制线为所述第一复位控制线或所述第二复位控制线。
  11. 如权利要求6所述的像素电路，其中，所述第二发光控制电路包括第五晶体管；
    所述第五晶体管的栅极与所述第一发光控制线电连接，所述第五晶体管的第一极与所述电源电压线电连接，所述第五晶体管的第二极与所述驱动电路的第二端电连接。
  12. 如权利要求7所述的像素电路，其中，所述数据写入电路包括第六晶体管，所述补偿控制电路包括第七晶体管，所述第三储能电路包括第三电容；所述驱动电路包括驱动晶体管；
    所述第六晶体管的栅极与所述扫描线电连接，所述第六晶体管的第一极与所述数据线电连接，所述第六晶体管的第二极与所述驱动晶体管的第二极电连接；
    所述第七晶体管的栅极与所述扫描线电连接，所述第七晶体管的第一极与所述驱动晶体管的栅极电连接，所述第七晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述第三电容的第一极板与所述驱动晶体管的栅极电连接，所述第三电容的第二极板与电源电压线电连接。
  13. 如权利要求8所述的像素电路，其中，所述第一复位电路包括第八晶体管；
    所述第八晶体管的栅极与所述第三复位控制线电连接，所述第八晶体管的第一极与第三初始电压线电连接，所述第八晶体管的第二极与所述驱动电路的控制端电连接。
  14. 如权利要求9所述的像素电路，其中，所述第二复位电路包括第九晶体管；
    所述第九晶体管的栅极与所述第四复位控制线电连接，所述第九晶体管的第一极与所述第四初始电压线电连接，所述第九晶体管的第二极与所述发光元件的第一极电连接。
  15. 如权利要求1至14中任一权利要求所述的像素电路，其中，包括复用控制电路；
    所述复用控制电路分别与复用控制端、源极驱动器的电压输出端和所述数据线电连接，用于在所述复用控制端提供的复用控制信号的控制下，控制所述电压输出端与所述数据线之间连通。
  16. 一种驱动方法，应用于如权利要求1至15中任一权利要求所述的像素电路，显示阶段包括第一写入阶段和第二写入阶段；所述驱动方法包括：
    在第一写入阶段，第一控制电路在第一复位控制信号的控制下，将数据线提供的第一控制电压提供至第二控制节点，第一控制电路在所述第二控制节点的电位的控制下，控制是否将第一发光控制信号提供至第一控制节点；
    在第二写入阶段，第二控制电路在第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入第三控制节点，第二控制电路在所述第三控制节点的电位的控制下，控制是否将第二发光控制信号提供至所述第一控制节点。
  17. 如权利要求16所述的驱动方法，其中，包括：
    在进行中高灰阶显示时，在所述第一写入阶段，第一控制电路在所述第二控制节点的电位的控制下，控制将第一发光控制信号提供至第一控制节点，在所述第二写入阶段，所述第二控制电路在所述第三控制节点的电位的控制下，控制停止将第二发光控制信号提供至至所述第一控制节点；
    在进行低灰阶显示时，在所述第一写入阶段，第一控制电路在所述第二控制节点的电位的控制下，停止控制将第一发光控制信号提供至第一控制节点，在所述第二写入阶段，所述第二控制电路在所述第三控制节点的电位的控制下，控制将第二发光控制信号提供至所述第一控制节点。
  18. 一种显示基板，包括衬底基板和设置于所述衬底基板上的多行多列如权利要求1至15中任一权利要求所述的像素电路。
  19. 如权利要求18所述的显示基板，其中，位于同一列的像素电路设置于两列数据线之间；所述数据线沿第一方向延伸；
    第a行像素电路设置于第a行扫描线和第a行第一电压线之间，a为正整数；
    所述第a行扫描线和所述第a行第一电压线沿第二方向延伸；
    所述第一方向和所述第二方向相交。
  20. 一种显示面板，包括如权利要求18或19所述的显示基板。
  21. 如权利要求20所述的显示面板，其中，还包括源极驱动器、多列数据线和多路复用电路；
    位于同一列的多个像素电路都与同一列数据线电连接；
    所述多路复用电路分别与所述源极驱动器的多个电压输出端、多个复用控制端和所述多列数据线电连接，用于在所述复用控制端提供的复用控制信号的控制下，将所述源极驱动器通过其电压输出端提供的电压信号写入所述数据线。
  22. 如权利要求21所述的显示面板，其中，所述多路复用电路分别与N个复用控制端电连接，所述多路复用电路包括M个复用子电路，N和M为大于1的整数；
    每一所述复用子电路都与所述源极驱动器的电压输出端、所述N个复用控制端和N列所述数据线电连接，用于在第n个复用控制端提供的第n复用控制信号的控制下，控制将该电压输出端提供的电压信号至所述N列数据线中的第n数据线；
    n为小于等于N的正整数。
  23. 一种驱动方法，应用于如权利要求21或22所述的显示面板，显示周期包括第一写入时间段和第二写入时间段；所述第一写入时间段包括第一数据写入时间段和第二数据写入时间段，所述第二写入时间段包括第三数据写入时间段和第四数据写入时间段；所述驱动方法包括：
    在第一数据写入时间段，多路复用电路在复位控制信号的控制下，将源极驱动器通过其电压输出端提供的第一控制电压写入数据线；
    在第二数据写入时间段，第一控制电路在第一复位控制信号的控制下，将数据线提供的第一控制电压提供至第二控制节点，第一控制电路在所述第二控制节点的电位的控制下，控制是否将第一发光控制信号提供至第一控制节点；
    在第三数据写入时间段，多路复用电路在复位控制信号的控制下，将源极驱动器通过其电压输出端提供的第二控制电压写入数据线；
    在第四数据写入时间段，第二控制电路在第二复位控制信号的控制下，将所述数据线提供的第二控制电压写入第三控制节点，第二控制电路在所述第三控制节点的电位的控制下，控制是否将第二发光控制信号提供至所述第一控制节点。
  24. 如权利要求23所述的驱动方法，其中，所述第一数据写入时间段和第二数据写入时间段先后设置，所述第三数据写入时间段和第四数据写入时间段先后设置；或者，
    所述第一数据写入时间段包含于所述第二数据写入时间段，所述第三数据写入时间段包含于所述第四数据写入时间段。
  25. 一种显示装置，包括如权利要求20至22中任一权利要求所述的显示面板。
PCT/CN2023/085358 2023-03-31 2023-03-31 像素电路、驱动方法、显示基板、显示面板和显示装置 WO2024197776A1 (zh)

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