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WO2023005661A1 - 像素电路、驱动方法和显示装置 - Google Patents

像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2023005661A1
WO2023005661A1 PCT/CN2022/105233 CN2022105233W WO2023005661A1 WO 2023005661 A1 WO2023005661 A1 WO 2023005661A1 CN 2022105233 W CN2022105233 W CN 2022105233W WO 2023005661 A1 WO2023005661 A1 WO 2023005661A1
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WO
WIPO (PCT)
Prior art keywords
circuit
control
electrically connected
transistor
line
Prior art date
Application number
PCT/CN2022/105233
Other languages
English (en)
French (fr)
Inventor
王丽
刘利宾
Original Assignee
京东方科技集团股份有限公司
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Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/279,621 priority Critical patent/US12230204B2/en
Publication of WO2023005661A1 publication Critical patent/WO2023005661A1/zh

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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device.
  • the magnetic hysteresis of the driving transistor in the driving circuit included in the pixel circuit will cause the characteristic response of the driving transistor to be sluggish, thereby affecting the display.
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, a control circuit, a first initialization circuit, a first light-emitting control circuit, and a second light-emitting control circuit, wherein,
  • the control circuit is electrically connected to the first scanning line, the control terminal and the connection node of the driving circuit, and is used to control the control of the driving circuit under the control of the first scanning signal provided by the first scanning line. terminal is electrically connected to the connection node;
  • the first initialization circuit is electrically connected to the reset control line, the connection node, and the first initial voltage line, and is used to control the reset control signal provided by the reset control line to control the reset control signal provided by the first initial voltage line. writing the first initial voltage into the connection node;
  • the first light emission control circuit is electrically connected to the first light emission control line, the first voltage terminal and the first end of the drive circuit respectively, and is used for controlling the first light emission control signal provided on the first light emission control line Next, controlling the connection between the first voltage terminal and the first terminal of the driving circuit;
  • the second light emission control circuit is electrically connected to the second light emission control line, the second terminal of the driving circuit and the first pole of the light emitting element respectively, and is used for the second light emission control signal provided on the second light emission control line Under the control of , controlling the communication between the second end of the driving circuit and the first pole of the light emitting element;
  • the driving circuit is used to control the communication between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of the potential of the control terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a reset circuit
  • the reset circuit is electrically connected to the reset control line and the first end of the driving circuit, and is used to initialize the potential of the first end of the driving circuit under the control of the reset control signal; or,
  • the reset circuit is respectively electrically connected to the reset control line and the second terminal of the driving circuit, and is used for initializing the potential of the second terminal of the driving circuit under the control of the reset control signal.
  • the reset circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the reset control line, the first electrode of the first transistor is electrically connected to the reset voltage line, and the second electrode of the first transistor is electrically connected to the first terminal or the second terminal of the drive circuit; the reset voltage line is used to provide a reset voltage.
  • the reset circuit includes a first transistor
  • control pole of the first transistor and the first pole of the first transistor are electrically connected to the reset control line, and the second pole of the first transistor is connected to the first terminal of the driving circuit or the first terminal of the driving circuit The second terminal is electrically connected.
  • the first light emission control circuit includes a second transistor, and the second light emission control circuit includes a third transistor;
  • the control electrode of the second transistor is electrically connected to the first light-emitting control line, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the the first end of the driving circuit is electrically connected;
  • the control pole of the third transistor is electrically connected to the second light emission control line
  • the first pole of the third transistor is electrically connected to the second terminal of the driving circuit
  • the second pole of the third transistor is electrically connected to the second terminal of the driving circuit.
  • the first poles of the light emitting elements are electrically connected.
  • the first light emission control line and the second light emission control line are different light emission control lines; or,
  • the first light emission control line and the second light emission control line are the same light emission control line.
  • control circuit includes a fourth transistor
  • the control pole of the fourth transistor is electrically connected to the first scanning line, the first pole of the fourth transistor is electrically connected to the control terminal of the driving circuit, and the second pole of the fourth transistor is electrically connected to the connecting the nodes electrically;
  • the fourth transistor is an oxide thin film transistor.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second initialization circuit
  • the second initialization circuit is electrically connected to the initial control line, the second initial voltage line and the first pole of the light-emitting element respectively, and is used to control the initial control signal provided by the initial control line to convert the initial voltage line provided by the second initial voltage line to The second initial voltage is written into the first pole of the light emitting element.
  • the second initialization circuit includes a fifth transistor
  • the control pole of the fifth transistor is electrically connected to the initial control line, the first pole of the fifth transistor is electrically connected to the second initial voltage line, and the second pole of the fifth transistor is electrically connected to the light emitting the first pole of the element is electrically connected;
  • the fifth transistor is an oxide thin film transistor; the initial control line is the first light emission control line or the second light emission control line.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a compensation control circuit, a data writing circuit, and an energy storage circuit;
  • the compensation control circuit is respectively electrically connected to the second scanning line, the connection node and the second end of the driving circuit, and is used to control the second scanning signal provided by the second scanning line. communication between the connection node and the second end of the driving circuit;
  • the data writing circuit is electrically connected to the second scan line, the data line and the first end of the drive circuit, and is used to write the data voltage on the data line into the second scan line under the control of the second scan signal. the first end of the drive circuit;
  • the energy storage circuit is electrically connected to the control terminal of the drive circuit for storing electric energy.
  • the first initialization circuit includes a sixth transistor
  • the compensation control circuit includes a seventh transistor
  • the data writing circuit includes an eighth transistor
  • the driving circuit includes a driving transistor
  • the energy storage circuit includes storage capacitor
  • the control electrode of the sixth transistor is electrically connected to the reset control line, the first electrode of the sixth transistor is electrically connected to the first initial voltage line, and the second electrode of the sixth transistor is electrically connected to the connection node. connect;
  • the control electrode of the seventh transistor is electrically connected to the second scanning line, the first electrode of the seventh transistor is electrically connected to the connection node, and the second electrode of the seventh transistor is electrically connected to the driving transistor.
  • the second pole is electrically connected;
  • the control electrode of the eighth transistor is electrically connected to the second scanning line, the first electrode of the eighth transistor is electrically connected to the data line, and the second electrode of the eighth transistor is electrically connected to the driving transistor.
  • the first pole is electrically connected;
  • the first end of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second end of the storage capacitor is electrically connected to the first voltage end.
  • the embodiment of the present disclosure also provides a driving method, which is applied to the above-mentioned pixel circuit, and the display cycle includes an initialization phase; the driving method includes:
  • the first initialization circuit writes the first initial voltage into the connection node under the control of the reset control signal, and the control circuit controls the control terminal of the driving circuit to connect to the connection node under the control of the first scanning signal.
  • the connection node is electrically connected to write a first initial voltage into the control terminal of the driving circuit and make the driving transistor in the driving circuit be in a predetermined bias state at the end of the initialization phase.
  • the predetermined bias state is an off-state bias state
  • the driving method further includes:
  • the second light emission control circuit controls the communication between the second terminal of the driving circuit and the first pole of the light emitting element under the control of the second light emission control signal;
  • the driving circuit controls the communication between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of the potential of its control terminal, so as to change the first terminal of the driving circuit.
  • the potential of the terminal until the drive transistor included in the drive circuit is turned off, and the drive transistor is in an off-state bias state.
  • the predetermined bias state is that the driving method further includes:
  • the first light emission control circuit controls the connection between the first terminal of the drive circuit and the first voltage terminal, so that the drive transistor in the drive circuit is in the open bias state.
  • the pixel circuit also includes a data writing circuit
  • the display cycle also includes a data writing phase set after the initialization phase
  • the driving method further includes:
  • the data writing circuit writes the data voltage on the data line into the first end of the driving circuit under the control of the second scanning line.
  • the pixel circuit further includes a second initialization circuit; the driving method further includes:
  • the second initialization circuit Under the control of the initial control signal, the second initialization circuit writes a second initial voltage into the first pole of the light emitting element, so as to control the light emitting element not to emit light.
  • the embodiment of the present disclosure also provides a driving method, which is applied to the above-mentioned pixel circuit, and the pixel circuit further includes a reset circuit; the first light emission control line and the second light emission control line are the same light emission Control line; display cycle including initialization phase;
  • the driving method includes:
  • the first initialization circuit writes the first initial voltage into the connection node under the control of the reset control signal
  • the control circuit controls the control terminal of the driving circuit to connect to the connection node under the control of the first scanning signal.
  • the connection node is electrically connected to write the first initial voltage into the control terminal of the drive circuit; the reset circuit controls the potential of the first terminal of the drive circuit or the potential of the drive circuit under the control of the reset control signal
  • the potential of the second terminal is initialized.
  • the pixel circuit further includes a data writing circuit
  • the display cycle also includes a data writing phase set after the initialization phase
  • the driving method further includes:
  • the data writing circuit writes the data voltage on the data line into the first end of the driving circuit under the control of the second scanning line.
  • the pixel circuit further includes a second initialization circuit; the driving method further includes:
  • the second initialization circuit Under the control of the initial control signal, the second initialization circuit writes a second initial voltage into the first pole of the light emitting element, so as to control the light emitting element not to emit light.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned pixel circuit.
  • FIG. 1 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure
  • Fig. 2 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure
  • Fig. 3 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure.
  • Fig. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 8 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7;
  • FIG. 9 is another working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7;
  • Fig. 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 13 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 12;
  • Fig. 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 15 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 14;
  • Fig. 16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 18 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 17;
  • Fig. 19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 20 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 19;
  • Fig. 21 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 22 is a distribution diagram of pixel circuits in a display device according to at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the first pole when the transistor is a thin film transistor or a field effect transistor, the first pole may be a drain, and the second pole may be a source; or, the first pole may be a source, The second pole may be a drain.
  • the pixel circuit described in the embodiment of the present disclosure includes a light-emitting element 10, a driving circuit 11, a control circuit 12, a first initialization circuit 13, a first light-emitting control circuit 14, and a second light-emitting control circuit 15, wherein,
  • the control circuit 12 is electrically connected to the first scanning line S1, the control terminal of the driving circuit 11, and the connection node N0, and is used to control the first scanning signal provided by the first scanning line S1.
  • the control end of the drive circuit 11 is electrically connected to the connection node N0;
  • the first initialization circuit 13 is electrically connected to the reset control line R1, the connection node N0 and the first initial voltage line respectively, and is used to reset the first initial voltage under the control of the reset control signal provided by the reset control line R1 Writing the first initial voltage Vi1 provided by the voltage line into the connection node N0;
  • the first light emission control circuit 14 is electrically connected to the first light emission control line E1, the first voltage terminal V1 and the first end of the driving circuit 11 respectively, and is used for the first light emission provided by the first light emission control line E1. Under the control of the light emission control signal, control the connection between the first voltage terminal V1 and the first terminal of the driving circuit 11;
  • the second light emission control circuit 15 is electrically connected to the second light emission control line E2, the second end of the driving circuit 11 and the first pole of the light emitting element 10 respectively, for the Under the control of the second light-emitting control signal, control the communication between the second end of the driving circuit 11 and the first pole of the light-emitting element 10;
  • the driving circuit 11 is used to control the communication between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the potential of the control terminal.
  • the control circuit 12 and the first initialization circuit 13 cooperate to write the first initial voltage Vi1 into the driving circuit 11, the first light emission control circuit 14 or the second light emission control circuit 15 works to initialize the potential of the source of the drive transistor included in the drive circuit 11, so as to improve the hysteresis of the drive transistor Phenomenon.
  • the display cycle includes an initialization phase
  • the first initialization circuit writes the first initial voltage into the connection node under the control of the reset control signal, and the control circuit controls the control terminal of the driving circuit to connect to the connection node under the control of the first scanning signal.
  • the connection node is electrically connected to write the first initial voltage into the control terminal of the driving circuit;
  • the second lighting control circuit controls the second terminal of the driving circuit and the first lighting element of the light emitting element under the control of the second lighting control signal. connection between poles;
  • the driving circuit controls the communication between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of the potential of its control terminal, so as to change the first terminal of the driving circuit.
  • the display cycle includes an initialization phase
  • the first initialization circuit writes the first initial voltage into the connection node under the control of the reset control signal, and the control circuit controls the control terminal of the driving circuit to connect to the connection node under the control of the first scanning signal.
  • the connection node is electrically connected to write the first initial voltage into the control terminal of the drive circuit; the first light emission control circuit controls the first terminal of the drive circuit and the first voltage terminal under the control of the first light emission control signal are connected to initialize the potential of the first end of the drive circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a reset circuit
  • the reset circuit is electrically connected to the reset control line and the first end of the driving circuit, and is used to initialize the potential of the first end of the driving circuit under the control of the reset control signal; or,
  • the reset circuit is respectively electrically connected to the reset control line and the second terminal of the driving circuit, and is used for initializing the potential of the second terminal of the driving circuit under the control of the reset control signal.
  • the potential of the first terminal of the driving circuit or the potential of the second terminal of the driving circuit may also be initialized through the reset circuit under the control of a reset control signal, In order to improve the hysteresis phenomenon of the driving transistor in the driving circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a reset circuit 20;
  • the reset circuit 20 is electrically connected to the reset control line R1 and the first end of the driving circuit 11 respectively, and is used to initialize the potential of the first end of the driving circuit 11 under the control of the reset control signal .
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a reset circuit 20 ;
  • the reset circuit 20 is electrically connected to the reset control line R1 and the second end of the driving circuit 11 , and is used to initialize the potential of the second end of the driving circuit 11 under the control of the reset control signal.
  • the reset circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the reset control line, the first electrode of the first transistor is electrically connected to the reset voltage line, and the second electrode of the first transistor is electrically connected to the first terminal or the second terminal of the drive circuit; the reset voltage line is used to provide a reset voltage.
  • the reset circuit includes a first transistor
  • control pole of the first transistor and the first pole of the first transistor are electrically connected to the reset control line, and the second pole of the first transistor is connected to the first terminal of the driving circuit or the first terminal of the driving circuit The second terminal is electrically connected.
  • the first light emission control circuit includes a second transistor, and the second light emission control circuit includes a third transistor;
  • the control electrode of the second transistor is electrically connected to the first light-emitting control line, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the the first end of the driving circuit is electrically connected;
  • the control pole of the third transistor is electrically connected to the second light emission control line
  • the first pole of the third transistor is electrically connected to the second terminal of the driving circuit
  • the second pole of the third transistor is electrically connected to the second terminal of the driving circuit.
  • the first poles of the light emitting elements are electrically connected.
  • first light emission control line and the second light emission control line may be different light emission control lines; or,
  • the first light emission control line and the second light emission control line may be the same light emission control line.
  • control circuit includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the first scanning line, the first electrode of the fourth transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the fourth transistor is electrically connected to the connecting the nodes electrically;
  • the fourth transistor is an oxide thin film transistor to reduce the leakage of the control terminal of the driving circuit, and can ensure the stability of the voltage of the first node when operating at a low frequency, which is conducive to improving display quality, improving display uniformity, and reducing Flicker (flicker) .
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a third initialization circuit
  • the third initialization circuit is electrically connected to the initial control line, the second initial voltage line and the first pole of the light-emitting element respectively, and is used to control the initial control signal provided by the initial control line to convert the initial voltage line provided by the second initial voltage line to The second initial voltage is written into the first pole of the light-emitting element, so that the light-emitting element does not emit light, and the residual charge of the first pole of the light-emitting element is cleared.
  • the second initialization circuit includes a fifth transistor
  • the control pole of the fifth transistor is electrically connected to the initial control line, the first pole of the fifth transistor is electrically connected to the second initial voltage line, and the second pole of the fifth transistor is electrically connected to the light emitting the first pole of the element is electrically connected;
  • the fifth transistor is an oxide thin film transistor; the initial control line is the first light emission control line or the second light emission control line.
  • the fifth transistor may be a p-type transistor, and the control electrode of the fifth transistor may be the first light emission control line or the second light emission control line. Since the first light emission control signal and the second light emission control signal The control line itself is a high-frequency signal, which can easily reset the first pole of the light-emitting element at high frequency to solve the problem of flickering.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a compensation control circuit, a data writing circuit, and an energy storage circuit;
  • the compensation control circuit is respectively electrically connected to the second scanning line, the connection node and the second end of the driving circuit, and is used to control the second scanning signal provided by the second scanning line. communication between the connection node and the second end of the driving circuit;
  • the data writing circuit is electrically connected to the second scan line, the data line and the first end of the drive circuit, and is used to write the data voltage on the data line into the second scan line under the control of the second scan signal. the first end of the drive circuit;
  • the energy storage circuit is electrically connected to the control terminal of the drive circuit for storing electric energy.
  • the data writing circuit in the data writing phase set after the initialization phase, writes the data voltage into the first part of the driving circuit under the control of the second scanning signal.
  • the compensation control circuit controls the communication between the connection node and the second end of the drive circuit;
  • the control circuit controls the control of the drive circuit The terminal is electrically connected to the connection node, so as to write the data voltage into the control terminal of the driving circuit;
  • the drive transistor in the drive circuit is turned on to change the potential of the control terminal of the drive circuit until the drive transistor is turned off. At this time, the potential of the control terminal of the drive circuit is the same as that of the drive transistor. Threshold voltage dependent.
  • the first initialization circuit includes a sixth transistor
  • the compensation control circuit includes a seventh transistor
  • the data writing circuit includes an eighth transistor
  • the driving circuit includes a driving transistor
  • the energy storage circuit includes storage capacitor
  • the control electrode of the sixth transistor is electrically connected to the reset control line, the first electrode of the sixth transistor is electrically connected to the first initial voltage line, and the second electrode of the sixth transistor is electrically connected to the connection node. connect;
  • the control electrode of the seventh transistor is electrically connected to the second scanning line, the first electrode of the seventh transistor is electrically connected to the connection node, and the second electrode of the seventh transistor is electrically connected to the driving transistor.
  • the second pole is electrically connected;
  • the control electrode of the eighth transistor is electrically connected to the second scanning line, the first electrode of the eighth transistor is electrically connected to the data line, and the second electrode of the eighth transistor is electrically connected to the driving transistor.
  • the first pole is electrically connected;
  • the first end of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second end of the storage capacitor is electrically connected to the first voltage end.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second initialization circuit 41, a compensation control circuit 42, a Input circuit 43 and energy storage circuit 44;
  • the second initialization circuit 41 is electrically connected to the initial control line S0, the second initial voltage line and the first pole of the light-emitting element 10 respectively, and is used to set the second initial voltage line under the control of the initial control signal provided by the initial control line S0 Writing the second initial voltage Vi2 provided by the voltage line into the first pole of the light emitting element 10;
  • the compensation control circuit 42 is electrically connected to the second scanning line S2, the connection node N0 and the second end of the driving circuit 11, and is used for controlling the second scanning signal provided on the second scanning line S2. Next, controlling the connection between the connection node N0 and the second end of the driving circuit 11;
  • the data writing circuit 43 is electrically connected to the second scanning line S2, the data line D1 and the first end of the driving circuit 11, and is used to write the data on the data line D1 under the control of the second scanning signal. writing the data voltage into the first end of the driving circuit 11;
  • the energy storage circuit 44 is electrically connected to the control terminal of the driving circuit 11 for storing electric energy.
  • the first light emission control line E1 and the second light emission control line E2 are different light emission control lines.
  • the initial control line S0 may be a second scan line, or the initial control line S0 may be a first light emission control line or a second light emission control line.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second initialization circuit 41, a compensation control circuit 42, a Input circuit 43 and energy storage circuit 44;
  • the second initialization circuit 41 is electrically connected to the initial control line S0, the second initial voltage line and the first pole of the light-emitting element 10 respectively, and is used to set the second initial voltage line under the control of the initial control signal provided by the initial control line S0 Writing the second initial voltage Vi2 provided by the voltage line into the first pole of the light emitting element 10;
  • the compensation control circuit 42 is electrically connected to the second scanning line S2, the connection node N0 and the second end of the driving circuit 11, and is used for controlling the second scanning signal provided on the second scanning line S2. Next, controlling the connection between the connection node N0 and the second end of the driving circuit 11;
  • the data writing circuit 43 is electrically connected to the second scanning line S2, the data line D1 and the first end of the driving circuit 11, and is used to write the data on the data line D1 under the control of the second scanning signal. writing the data voltage into the first end of the driving circuit 11;
  • the energy storage circuit 44 is electrically connected to the control terminal of the driving circuit 11 for storing electric energy.
  • the first light emission control line E1 and the first light emission control line E2 may be the same light emission control line, but not limited thereto.
  • the initial control line S0 may be a second scan line, or the initial control line S0 may be a first light emission control line or a second light emission control line.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second initialization circuit 41, a compensation control circuit 42, a Input circuit 43 and energy storage circuit 44;
  • the second initialization circuit 41 is electrically connected to the initial control line S0, the second initial voltage line and the first pole of the light-emitting element 10 respectively, and is used to set the second initial voltage line under the control of the initial control signal provided by the initial control line S0 Writing the second initial voltage Vi2 provided by the voltage line into the first pole of the light emitting element 10;
  • the compensation control circuit 42 is electrically connected to the second scanning line S2, the connection node N0 and the second end of the driving circuit 11, and is used for controlling the second scanning signal provided on the second scanning line S2. Next, controlling the connection between the connection node N0 and the second end of the driving circuit 11;
  • the data writing circuit 43 is electrically connected to the second scanning line S2, the data line D1 and the first end of the driving circuit 11, and is used to write the data on the data line D1 under the control of the second scanning signal. writing the data voltage into the first end of the driving circuit 11;
  • the energy storage circuit 44 is electrically connected to the control terminal of the driving circuit 11 for storing electric energy.
  • the first light emission control line E1 and the first light emission control line E2 may be the same light emission control line, but not limited thereto.
  • the initial control line S0 may be a second scan line, or the initial control line S0 may be a first light emission control line or a second light emission control line.
  • the first voltage terminal may be a high voltage terminal
  • the second voltage terminal may be a low voltage terminal, but not limited thereto.
  • the first light emission control circuit 14 includes a second transistor T2, and the second light emission control circuit 15 includes a third transistor T3.
  • the control circuit 12 includes a fourth transistor T4; the second initialization circuit 41 includes a fifth transistor T5; the first initialization circuit 13 includes a sixth transistor T6, and the compensation control circuit 42 includes a seventh transistor T7,
  • the data writing circuit 43 includes an eighth transistor T8, the driving circuit 11 includes a driving transistor T0, and the energy storage circuit 44 includes a storage capacitor C; the light emitting element is an organic light emitting diode O1;
  • the gate of T2 is electrically connected to the first light emission control line E1, the source of T2 is electrically connected to the high voltage terminal, and the drain of T2 is electrically connected to the source of T0; the high voltage terminal is used to provide a high voltage VDD;
  • the gate of T3 is electrically connected to the second light emission control line E1, the source of T3 is electrically connected to the drain of T0, and the drain of T3 is electrically connected to the anode of O1;
  • the gate of T4 is electrically connected to the first scanning line S1, the source of T4 is electrically connected to the gate of T0, and the drain of T4 is electrically connected to the connection node N0;
  • the gate of T5 is electrically connected to the second scanning line S2, the source of T5 is electrically connected to the second initial voltage line, and the drain of T5 is electrically connected to the anode of O1; the second initial voltage line is used to provide the second initial Voltage Vi2;
  • the gate of T6 is electrically connected to the reset control line R1, the source of T6 is electrically connected to the first initial voltage line, and the drain of T6 is electrically connected to the connection node N0; the first initial voltage line is used to provide the first initial voltage Vi1;
  • the gate of T7 is electrically connected to the second scanning line S2, the source of T7 is electrically connected to the connection node N0, and the drain of T7 is electrically connected to the drain of T0;
  • the gate of T8 is electrically connected to the second scanning line S2, the source of T8 is electrically connected to the data line D1, and the drain of T8 is electrically connected to the source of T0;
  • the first end of C is electrically connected to the gate of T0, and the second end of C is electrically connected to the high voltage end;
  • the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide the low voltage VSS.
  • the initial control line is the second scan line.
  • T4 is an oxide thin film transistor, and other transistors may be low temperature polysilicon thin film transistors, but not limited thereto.
  • the one labeled N1 is the first node
  • the one labeled N2 is the second node
  • the one labeled N3 is the third node
  • the first node N1 is electrically connected to the gate of T0
  • the second node N2 is connected to T0
  • the source of T0 is electrically connected
  • the third node N3 is electrically connected with the drain of T0.
  • the display cycle includes an initialization phase t1, a data writing phase t2, and a lighting phase t3 which are set successively;
  • E1 provides a high voltage signal
  • E2 provides a low voltage signal
  • S1 provides a high voltage signal
  • S2 provides a high voltage signal
  • R1 provides a low voltage signal
  • T6 is turned on
  • T4 is turned on
  • T3 is turned on
  • T2 is turned off
  • the potential is initialized to Vi1, and the source potential of T0 decreases due to leakage, until the potential of the source of T0 (that is, the potential of N2) becomes Vi1-Vth, and T0 is in an off-bias state, Vth is the threshold voltage of T0;
  • E1 provides a high voltage signal
  • E2 provides a high voltage signal
  • S1 provides a high voltage signal
  • S2 provides a low voltage signal
  • R1 provides a high voltage signal
  • T7, T8 and T4 are turned on, and the data voltage Vdata on D1 Write to N2;
  • T0 is turned on to charge C through Vdata, and the potential of the gate of T0 is changed until T0 is turned off.
  • the potential of N1 is Vdata+Vth;
  • E1 provides a low voltage signal
  • E2 provides a low voltage signal
  • S1 provides a low voltage signal
  • S2 provides a high voltage signal
  • S3 provides a high voltage signal
  • T2 and T3 are turned on
  • T0 is turned on to drive O1 to emit light.
  • At least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure is in operation. Before data is written, T0 is in the off-state bias state to ensure that the driving transistor in each pixel circuit is from the off-state bias state. Starting to charge and compensate without being affected by the data voltage of the previous frame can eliminate the influence of T0 hysteresis and improve afterimage and response time.
  • the pulse width of the first light emission control signal provided by E1 needs to be greater than the pulse width of the first scan signal provided by S1, that is, the potential of the first light emission control signal provided by E1 lasts for a period of time at a high voltage , including the time period in which the potential of the first scanning signal provided by S1 remains at a high voltage, so as to ensure that when T4 is turned on, T2 is turned off.
  • the period during which the potential of the first scan signal provided by S1 continues to be a high voltage needs to include the period during which the potential of the reset control signal provided by R1 continues to be a low voltage, and the period of the second scan signal provided by S2
  • the potential lasts for a period of low voltage to ensure that during the initialization phase and the data writing phase, the first scan signal provided by S1 can control T4 to turn on, so as to initialize the potential of N1 during the initialization phase and facilitate data writing stage compensates the threshold voltage of drive transistor T0.
  • the time period during which the potential of the second light-emitting control signal provided by E2 continues to be a high voltage needs to include the time period during which the potential of the second scanning signal provided by S2 continues to be a low voltage, so as to ensure that during the data writing phase , the second lighting control signal provided by E2 can control T3 to turn off, so as to ensure that O1 does not emit light.
  • the shortest time interval between the rising edge of the first light emission control signal provided by E1 and the rising edge of the first scan signal provided by S1 may be A predetermined time interval
  • the shortest time interval between the rising edge of the first lighting control signal provided by E1 and the falling edge of the reset control signal provided by R1 may be a second predetermined time interval
  • the first predetermined time interval and the The second predetermined time interval may be greater than or equal to 0.5us and less than or equal to 1us, but not limited thereto;
  • the shortest time interval between the rising edge of the second lighting control signal provided by E2 and the falling edge of the second scanning signal provided by S2 may be a third predetermined time interval, and the third predetermined time interval may be greater than or equal to 0.5us and Less than or equal to 1us, but not limited thereto.
  • T0 is turned on at the beginning of the data writing phase, so the voltage difference between the voltage value of Vi1 and the minimum data voltage value needs to be smaller than the threshold voltage Vth of T0.
  • the voltage value of Vi1 may be greater than or equal to -6V and less than or equal to -2V, for example, the voltage value of Vi1 may be -2V, -3V, -4V, -5V or -6V, etc., but not limited thereto;
  • a voltage difference between the voltage value of Vi1 and the minimum data voltage value may be less than a*Vth, where a may be greater than or equal to 2 and less than or equal to 7.
  • a can be 2, 4, 6 or 7.
  • Vth can be greater than or equal to -5V and less than or equal to -2V; for example, Vth can be -2.5V or -3V, etc.;
  • the voltage value of VDD can be greater than or equal to 3V and less than or equal to 6V, for example, the voltage value of VDD can be 4.6V; but not limited thereto;
  • the absolute value of the voltage value of VDD may be greater than 1.5 times the absolute value of Vth, for example, the absolute value of the voltage value of VDD may be 1.6 times, 1.8 times, or 2 times the absolute value of Vth.
  • the voltage value of VSS may be greater than or equal to -6V and less than or equal to -3V; for example, the voltage value of VSS may be -5V, -4V or -3V.
  • the voltage value of Vi2 may be greater than or equal to -7V and less than or equal to 0V.
  • the voltage value of the second initialization voltage may be -6V, -5V, -4V, -3V or -2V; but not limited thereto.
  • the voltage difference between the voltage value of Vi2 and the voltage value of VSS needs to be smaller than the turn-on voltage of the light-emitting element, so that when the first pole of the light-emitting element is connected to Vi2, the light-emitting element does not emit light.
  • the display cycle includes an initialization phase t1, a data writing phase t2, and a light emitting phase t3 which are set successively;
  • E1 provides a low voltage signal
  • E2 provides a high voltage signal
  • S1 provides a high voltage signal
  • S2 provides a high voltage signal
  • R1 provides a low voltage signal
  • T6 is turned on
  • T4 is turned on
  • T2 is turned on
  • T3 is turned off
  • the potential is initialized to Vi1, and the potential of N2 is VDD.
  • the gate-source voltage of T0 is Vi1-VDD, and T0 is in an on-bias state;
  • E1 provides a high voltage signal
  • E2 provides a high voltage signal
  • S1 provides a high voltage signal
  • S2 provides a low voltage signal
  • R1 provides a high voltage signal
  • T7, T8 and T4 are turned on, and the data voltage Vdata on D1 Write N2;
  • T5 is turned on to write Vi2 into the anode of O1, so that O1 does not emit light, and clear the residual charge of the anode of O1;
  • T0 is turned on to charge C through Vdata, and the potential of the gate of T0 is changed until T0 is turned off.
  • the potential of N1 is Vdata+Vth;
  • E1 provides a low voltage signal
  • E2 provides a low voltage signal
  • S1 provides a low voltage signal
  • S2 provides a high voltage signal
  • S3 provides a high voltage signal
  • T2 and T3 are turned on
  • T0 is turned on to drive O1 to emit light.
  • At least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure is in operation.
  • T0 is in the on-state bias state to ensure that the driving transistor in each pixel circuit is from the on-state bias state.
  • Starting to charge and compensate without being affected by the data voltage of the previous frame can eliminate the influence of T0 hysteresis and improve afterimage and response time.
  • the pulse width of the second light emission control signal provided by E2 needs to be greater than the pulse width of the first scan signal provided by S1, that is, the potential of the second light emission control signal provided by E2 lasts for a period of high voltage , including the time period in which the potential of the first scanning signal provided by S1 remains at a high voltage, so as to ensure that when T4 is turned on, T3 is turned off.
  • the period during which the potential of the first scan signal provided by S1 continues to be a high voltage needs to include the period during which the potential of the reset control signal provided by R1 continues to be a low voltage, and the second scan signal provided by S2
  • the potential lasts for a period of low voltage to ensure that during the initialization phase and the data writing phase, the first scan signal provided by S1 can control T4 to turn on, so as to initialize the potential of N1 during the initialization phase and facilitate data writing stage compensates the threshold voltage of drive transistor T0.
  • the time period during which the potential of the first light-emitting control signal provided by E1 continues to be a high voltage needs to include the time period during which the potential of the second scanning signal provided by S2 continues to be a low voltage, so as to ensure that during the data writing phase , the first lighting control signal provided by E1 can control T2 to turn off, so as to ensure that O1 does not emit light.
  • the shortest time interval between the rising edge of the second light emission control signal provided by E2 and the rising edge of the first scan signal provided by S1 may be Four predetermined time intervals, the shortest time interval between the rising edge of the second lighting control signal provided by E2 and the falling edge of the reset control signal provided by R1 may be the fifth predetermined time interval, the fourth predetermined time interval and the The fifth predetermined time interval may be greater than or equal to 0.5us and less than or equal to 1us, but not limited thereto;
  • the shortest time interval between the rising edge of the first lighting control signal provided by E1 and the falling edge of the second scanning signal provided by S2 may be the sixth predetermined time interval, and the sixth predetermined time interval may be greater than or equal to 0.5us and Less than or equal to 1us, but not limited thereto.
  • the first light emission control circuit 14 includes a second transistor T2, and the second light emission control circuit 15 includes a third transistor T3
  • the control circuit 12 includes a fourth transistor T4; the second initialization circuit 41 includes a fifth transistor T5; the first initialization circuit 13 includes a sixth transistor T6, and the compensation control circuit 42 includes a seventh transistor T7,
  • the data writing circuit 43 includes an eighth transistor T8, the driving circuit 11 includes a driving transistor T0, and the energy storage circuit 44 includes a storage capacitor C;
  • the light emitting element is an organic light emitting diode O1;
  • the gate of T2 is electrically connected to the first light emission control line E1, the source of T2 is electrically connected to the high voltage terminal, and the drain of T2 is electrically connected to the source of T0; the high voltage terminal is used to provide a high voltage VDD;
  • the gate of T3 is electrically connected to the second light emission control line E1, the source of T3 is electrically connected to the drain of T0, and the drain of T3 is electrically connected to the anode of O1;
  • the gate of T4 is electrically connected to the first scanning line S1, the source of T4 is electrically connected to the gate of T0, and the drain of T4 is electrically connected to the connection node N0;
  • the gate of T5 is electrically connected to the first light emission control line E1, the source of T5 is electrically connected to the second initial voltage line, and the drain of T5 is electrically connected to the anode of O1; the second initial voltage line is used to provide the second Initial voltage Vi2;
  • the gate of T6 is electrically connected to the reset control line R1, the source of T6 is electrically connected to the first initial voltage line, and the drain of T6 is electrically connected to the connection node N0; the first initial voltage line is used to provide the first initial voltage Vi1;
  • the gate of T7 is electrically connected to the second scanning line S2, the source of T7 is electrically connected to the connection node N0, and the drain of T7 is electrically connected to the drain of T0;
  • the gate of T8 is electrically connected to the second scanning line S2, the source of T8 is electrically connected to the data line D1, and the drain of T8 is electrically connected to the source of T0;
  • the first end of C is electrically connected to the gate of T0, and the second end of C is electrically connected to the high voltage end;
  • the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide the low voltage VSS.
  • T4 and T5 are oxide thin film transistors, and other transistors may be low temperature polysilicon thin film transistors, but not limited thereto.
  • the first node labeled N1 is the first node
  • the labeled N2 is the second node
  • the labeled N3 is the third node
  • the first node N1 is electrically connected to the gate of T0
  • the second node N2 is connected to T0
  • the source of T0 is electrically connected
  • the third node N3 is electrically connected with the drain of T0.
  • T5 is an oxide thin film transistor, the gate of T5 is electrically connected to E1, and when E1 provides a high voltage signal, T5 is turned on to reset the potential of the anode of O1.
  • E1 provides a high voltage signal
  • T5 is turned on to reset the potential of the anode of O1.
  • a high-frequency control signal is required to reset the potential of the anode of O1
  • the first light-emitting control signal provided by E1 itself is a high-frequency signal, which can save the need to change the signal controlling the gate of T5 to high frequency The problem of increased power consumption caused by the signal.
  • the first light emission control circuit 14 includes a second transistor T2, and the second light emission control circuit 15 includes a third transistor T3
  • the control circuit 12 includes a fourth transistor T4; the second initialization circuit 41 includes a fifth transistor T5; the first initialization circuit 13 includes a sixth transistor T6, and the compensation control circuit 42 includes a seventh transistor T7,
  • the data writing circuit 43 includes an eighth transistor T8, the driving circuit 11 includes a driving transistor T0, and the energy storage circuit 44 includes a storage capacitor C; the light emitting element is an organic light emitting diode O1;
  • the gate of T2 is electrically connected to the first light emission control line E1, the source of T2 is electrically connected to the high voltage terminal, and the drain of T2 is electrically connected to the source of T0; the high voltage terminal is used to provide a high voltage VDD;
  • the gate of T3 is electrically connected to the second light emission control line E1, the source of T3 is electrically connected to the drain of T0, and the drain of T3 is electrically connected to the anode of O1;
  • the gate of T4 is electrically connected to the first scanning line S1, the source of T4 is electrically connected to the gate of T0, and the drain of T4 is electrically connected to the connection node N0;
  • the gate of T5 is electrically connected to the second light emission control line E2, the source of T5 is electrically connected to the second initial voltage line, and the drain of T5 is electrically connected to the anode of O1; the second initial voltage line is used to provide the second Initial voltage Vi2;
  • the gate of T6 is electrically connected to the reset control line R1, the source of T6 is electrically connected to the first initial voltage line, and the drain of T6 is electrically connected to the connection node N0; the first initial voltage line is used to provide the first initial voltage Vi1;
  • the gate of T7 is electrically connected to the second scanning line S2, the source of T7 is electrically connected to the connection node N0, and the drain of T7 is electrically connected to the drain of T0;
  • the gate of T8 is electrically connected to the second scanning line S2, the source of T8 is electrically connected to the data line D1, and the drain of T8 is electrically connected to the source of T0;
  • the first end of C is electrically connected to the gate of T0, and the second end of C is electrically connected to the high voltage end;
  • the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide the low voltage VSS.
  • T4 and T5 are oxide thin film transistors, and other transistors may be low temperature polysilicon thin film transistors, but not limited thereto.
  • the first node labeled N1 is the first node
  • the labeled N2 is the second node
  • the labeled N3 is the third node
  • the first node N1 is electrically connected to the gate of T0
  • the second node N2 is connected to T0
  • the source of T0 is electrically connected
  • the third node N3 is electrically connected with the drain of T0.
  • T5 is an oxide thin film transistor, the gate of T5 is electrically connected to E2, and when E2 provides a high voltage signal, T5 is turned on to reset the potential of the anode of O1.
  • E2 provides a high voltage signal
  • T5 is turned on to reset the potential of the anode of O1.
  • a high-frequency control signal is required to reset the potential of the anode of O1
  • the second light-emitting control signal provided by E2 itself is a high-frequency signal, which can save the need to change the signal controlling the gate of T5 to high frequency The problem of increased power consumption caused by the signal.
  • the reset circuit 20 includes a first transistor T1; the first light emission control circuit 14 includes a second transistor T2, the The second light emission control circuit 15 includes a third transistor T3; the control circuit 12 includes a fourth transistor T4; the second initialization circuit 41 includes a fifth transistor T5; the first initialization circuit 13 includes a sixth transistor T6, so
  • the compensation control circuit 42 includes a seventh transistor T7, the data writing circuit 43 includes an eighth transistor T8, the driving circuit 11 includes a driving transistor T0, and the energy storage circuit 44 includes a storage capacitor C; the light emitting element is organic light emitting diode O1;
  • the gate of T1 is electrically connected to the reset control line R1, the source of T1 is electrically connected to the reset voltage line DR, and the drain of T1 is electrically connected to the source of T0; the reset voltage line DR is used to supply a reset voltage;
  • the gate of T2 is electrically connected to the light emission control line E0, the source of T2 is electrically connected to the high voltage terminal, and the drain of T2 is electrically connected to the source of T0; the high voltage terminal is used to provide a high voltage VDD;
  • the gate of T3 is electrically connected to the light emission control line E0, the source of T3 is electrically connected to the drain of T0, and the drain of T3 is electrically connected to the anode of O1;
  • the gate of T4 is electrically connected to the first scanning line S1, the source of T4 is electrically connected to the gate of T0, and the drain of T4 is electrically connected to the connection node N0;
  • the gate of T5 is electrically connected to the second scanning line S2, the source of T5 is electrically connected to the second initial voltage line, and the drain of T5 is electrically connected to the anode of O1; the second initial voltage line is used to provide the second initial Voltage Vi2;
  • the gate of T6 is electrically connected to the reset control line R1, the source of T6 is electrically connected to the first initial voltage terminal, and the drain of T6 is electrically connected to the connection node N0; the first initial voltage terminal is used to provide the first initial voltage Vi1;
  • the gate of T7 is electrically connected to the second scanning line S2, the source of T7 is electrically connected to the connection node N0, and the drain of T7 is electrically connected to the drain of T0;
  • the gate of T8 is electrically connected to the second scanning line S2, the source of T8 is electrically connected to the data line D1, and the drain of T8 is electrically connected to the source of T0;
  • the first end of C is electrically connected to the gate of T0, and the second end of C is electrically connected to the high voltage end;
  • the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide the low voltage VSS.
  • the first light emission control line and the second light emission control line are the same light emission control line E0.
  • T4 is an oxide thin film transistor, and other transistors may be low temperature polysilicon thin film transistors, but not limited thereto.
  • the reset voltage provided by DR may be a low voltage signal, but not limited thereto; for example, the reset voltage may be Vi1, Vi2 or VSS; at this time, reset The voltage value of the voltage may be greater than or equal to -6V and less than or equal to -2V; for example, the voltage value of the reset voltage may be equal to -6V, -5V, -4V, -3V or -2V; but not limited thereto;
  • the reset voltage provided by DR can also be a high voltage signal.
  • the voltage value of the reset voltage can be greater than or equal to 4V and less than or equal to 10V; for example, the voltage value of the reset voltage can be 4V, 5V, 6V, 7V, 8V, 9V or 10V, but not limited thereto.
  • the voltage value of the reset voltage is less than the minimum data voltage value, ensuring that when the first driving circuit When the terminal is connected to all data voltages, it can start working from a lower voltage state;
  • the voltage value of the reset voltage is greater than the maximum data voltage value, so as to ensure that when the first end of the driving circuit is connected to all data voltages, it can start from a higher voltage state Work.
  • the display cycle includes an initialization phase t1, a data writing phase t2, and a lighting phase t3 which are set successively;
  • E0 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a low voltage signal
  • S2 provides a high voltage signal
  • T6, T4 and T1 are all turned on
  • Vi is written into N1
  • the reset voltage is written into N2, T0 in the off-bias state
  • E0 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a high voltage signal
  • S2 provides a low voltage signal
  • T7, T8 and T4 are turned on, and the data voltage Vdata on D1 is written into N2
  • T5 is turned on , to write Vi2 into the anode of O1, so that O1 does not emit light, and remove the residual charge of the anode of O1;
  • T0 is turned on to charge C through Vdata, and the potential of N1 is changed until the potential of N1 becomes Vdata+Vth, and T0 is turned off;
  • E0 provides a low-voltage signal
  • S1 provides a low-voltage signal
  • S2 provides a high-voltage signal
  • R1 provides a high-voltage signal
  • T2 drives O1 to emit light.
  • At least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure is in operation.
  • T0 In the initialization phase t1, T0 is in the off state, ensuring that each pixel circuit is charged and compensated from the off-state bias state, and is not affected by The influence of the data voltage of the previous frame can eliminate the influence of the hysteresis of T0 and improve afterimage and response time.
  • the pulse width of the light emission control signal provided by E0 needs to be greater than the pulse width of the first scan signal provided by S1, that is, the potential of the light emission control signal provided by E0 continues to be a high voltage period, including the time period provided by S1.
  • the potential of the first scanning signal lasts for a period of high voltage, ensuring that when T4 is turned on, T2 and T3 are turned off.
  • the period during which the potential of the first scan signal provided by S1 is continuously at a high voltage needs to include the period during which the potential of the reset control signal provided by R1 is continuously at a low voltage, and the period of time during which the potential of the second scan signal provided by S2 is The potential lasts for a period of low voltage to ensure that during the initialization phase and the data writing phase, the first scan signal provided by S1 can control T4 to turn on, so as to initialize the potential of N1 during the initialization phase and facilitate data writing stage compensates the threshold voltage of drive transistor T0.
  • the time period during which the potential of the light-emitting control signal provided by E0 continues to be a high voltage needs to include the time period during which the potential of the second scanning signal provided by S2 continues to be a low voltage, so as to ensure that during the data writing phase, E0
  • the light emission control signal provided can control T2 and T3 to turn off, so as to ensure that O1 does not emit light.
  • the shortest time interval between the rising edge of the light emission control signal provided by E0 and the rising edge of the first scan signal provided by S1 may be the seventh predetermined Time interval
  • the shortest time interval between the rising edge of the lighting control signal provided by E0 and the falling edge of the reset control signal provided by R1 may be the eighth predetermined time interval
  • the seventh predetermined time interval and the eighth predetermined time interval The interval may be greater than or equal to 0.5us and less than or equal to 1us, but not limited thereto.
  • the light emission control signal provided by E0, the first scan signal provided by S1, the reset control signal provided by R1 and The timing of the second scan signal provided by S2 is set as described above.
  • the reset circuit 20 includes a first transistor T1; the first light emission control circuit 14 includes a second transistor T2, the The second light emission control circuit 15 includes a third transistor T3; the control circuit 12 includes a fourth transistor T4; the second initialization circuit 41 includes a fifth transistor T5; the first initialization circuit 13 includes a sixth transistor T6, so
  • the compensation control circuit 42 includes a seventh transistor T7, the data writing circuit 43 includes an eighth transistor T8, the driving circuit 11 includes a driving transistor T0, and the energy storage circuit 44 includes a storage capacitor C; the light emitting element is organic light emitting diode O1;
  • Both the gate of T1 and the source of T1 are electrically connected to the reset control line R1, and the drain of T1 is electrically connected to the source of T0;
  • the gate of T2 is electrically connected to the light emission control line E0, the source of T2 is electrically connected to the high voltage terminal, and the drain of T2 is electrically connected to the source of T0; the high voltage terminal is used to provide a high voltage VDD;
  • the gate of T3 is electrically connected to the light emission control line E0, the source of T3 is electrically connected to the drain of T0, and the drain of T3 is electrically connected to the anode of O1;
  • the gate of T4 is electrically connected to the first scanning line S1, the source of T4 is electrically connected to the gate of T0, and the drain of T4 is electrically connected to the connection node N0;
  • the gate of T5 is electrically connected to the second scanning line S2, the source of T5 is electrically connected to the second initial voltage line, and the drain of T5 is electrically connected to the anode of O1; the second initial voltage line is used to provide the second initial Voltage Vi2;
  • the gate of T6 is electrically connected to the reset control line R1, the source of T6 is electrically connected to the first initial voltage line, and the drain of T6 is electrically connected to the connection node N0; the first initial voltage line is used to provide the first initial voltage Vi1;
  • the gate of T7 is electrically connected to the second scanning line S2, the source of T7 is electrically connected to the connection node N0, and the drain of T7 is electrically connected to the drain of T0;
  • the gate of T8 is electrically connected to the second scanning line S2, the source of T8 is electrically connected to the data line D1, and the drain of T8 is electrically connected to the source of T0;
  • the first end of C is electrically connected to the gate of T0, and the second end of C is electrically connected to the high voltage end;
  • the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide the low voltage VSS.
  • the first light emission control line and the second light emission control line are the same light emission control line E0.
  • T4 is an oxide thin film transistor, and other transistors may be low temperature polysilicon thin film transistors, but not limited thereto.
  • the display cycle includes an initialization phase t1, a data writing phase t2, and a lighting phase t3 which are set successively;
  • E0 provides a high-voltage signal
  • S1 provides a high-voltage signal
  • R1 provides a low-voltage signal
  • S2 provides a high-voltage signal
  • T6, T4, and T1 are all turned on, Vi1 is written into N1, and a low-voltage signal is written into N2, T0 is in the off-state bias state;
  • E0 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a high voltage signal
  • S2 provides a low voltage signal
  • T7, T8 and T4 are turned on, and the data voltage Vdata on D1 is written into N2
  • T5 is turned on , to write Vi2 into the anode of O1, so that O1 does not emit light, and remove the residual charge of the anode of O1;
  • T0 is turned on to charge C through Vdata, and the potential of N1 is changed until the potential of N1 becomes Vdata+Vth, and T0 is turned off;
  • E0 provides a low-voltage signal
  • S1 provides a low-voltage signal
  • S2 provides a high-voltage signal
  • R1 provides a high-voltage signal
  • T2 drives O1 to emit light.
  • At least one embodiment of the pixel circuit shown in FIG. 14 of the present disclosure is in operation.
  • T0 In the initialization phase t1, T0 is in the off state, ensuring that each pixel circuit is charged and compensated from the off-state bias state, and is not affected by The influence of the data voltage of the previous frame can eliminate the influence of the hysteresis of T0 and improve afterimage and response time.
  • the reset circuit 20 includes a first transistor T1; the first light emission control circuit 14 includes a second transistor T2, the The second light emission control circuit 15 includes a third transistor T3; the control circuit 12 includes a fourth transistor T4; the second initialization circuit 41 includes a fifth transistor T5; the first initialization circuit 13 includes a sixth transistor T6, so
  • the compensation control circuit 42 includes a seventh transistor T7, the data writing circuit 43 includes an eighth transistor T8, the driving circuit 11 includes a driving transistor T0, and the energy storage circuit 44 includes a storage capacitor C; the light emitting element is organic light emitting diode O1;
  • the gate of T1 is electrically connected to the reset control line R1, the source of T1 is electrically connected to the reset voltage line DR, and the drain of T1 is electrically connected to the source of T0; the reset voltage line DR is used to provide a reset voltage;
  • the gate of T2 is electrically connected to the light emission control line E0, the source of T2 is electrically connected to the high voltage terminal, and the drain of T2 is electrically connected to the source of T0; the high voltage terminal is used to provide a high voltage VDD;
  • the gate of T3 is electrically connected to the light emission control line E0, the source of T3 is electrically connected to the drain of T0, and the drain of T3 is electrically connected to the anode of O1;
  • the gate of T4 is electrically connected to the first scanning line S1, the source of T4 is electrically connected to the gate of T0, and the drain of T4 is electrically connected to the connection node N0;
  • the gate of T5 is electrically connected to the light emission control line E0, the source of T5 is electrically connected to the second initial voltage line, and the drain of T5 is electrically connected to the anode of O1; the second initial voltage line is used to provide the second initial voltage Vi2;
  • the gate of T6 is electrically connected to the reset control line R1, the source of T6 is electrically connected to the first initial voltage line, and the drain of T6 is electrically connected to the connection node N0; the first initial voltage line is used to provide the first initial voltage Vi1;
  • the gate of T7 is electrically connected to the second scanning line S2, the source of T7 is electrically connected to the connection node N0, and the drain of T7 is electrically connected to the drain of T0;
  • the gate of T8 is electrically connected to the second scanning line S2, the source of T8 is electrically connected to the data line D1, and the drain of T8 is electrically connected to the source of T0;
  • the first end of C is electrically connected to the gate of T0, and the second end of C is electrically connected to the high voltage end;
  • the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide the low voltage VSS.
  • the first light emission control line and the second light emission control line are the same light emission control line E0.
  • T4 and T5 are oxide thin film transistors, and other transistors may be low temperature polysilicon thin film transistors, but not limited thereto.
  • the first node labeled N1 is the first node
  • the labeled N2 is the second node
  • the labeled N3 is the third node
  • the first node N1 is electrically connected to the gate of T0
  • the second node N2 is connected to the gate of T0
  • the source of T0 is electrically connected
  • the third node N3 is electrically connected with the drain of T0.
  • T5 is an oxide thin film transistor, and the gate of T5 is electrically connected to the light emission control line E0;
  • E0 provides a high voltage signal
  • T5 is turned on to reset the potential of the anode of O1.
  • a high-frequency control signal is required to reset the potential of the anode of O1
  • the second light-emitting control signal provided by E2 itself is a high-frequency signal, which can save the need to change the signal controlling the gate of T5 to high frequency The problem of increased power consumption caused by the signal.
  • the reset circuit 20 includes a first transistor T1; the first light emission control circuit 14 includes a second transistor T2, the The second light emission control circuit 15 includes a third transistor T3; the control circuit 12 includes a fourth transistor T4; the second initialization circuit 41 includes a fifth transistor T5; the first initialization circuit 13 includes a sixth transistor T6, so
  • the compensation control circuit 42 includes a seventh transistor T7, the data writing circuit 43 includes an eighth transistor T8, the driving circuit 11 includes a driving transistor T0, and the energy storage circuit 44 includes a storage capacitor C; the light emitting element is organic light emitting diode O1;
  • the gate of T1 is electrically connected to the reset control line R1, the source of T1 is electrically connected to the reset voltage line DR, and the drain of T1 is electrically connected to the second pole of T0; the reset voltage line DR is used to provide a reset voltage;
  • the gate of T2 is electrically connected to the light emission control line E0, the source of T2 is electrically connected to the high voltage terminal, and the drain of T2 is electrically connected to the first pole of T0; the high voltage terminal is used to provide a high voltage VDD;
  • the gate of T3 is electrically connected to the light emission control line E0, the source of T3 is electrically connected to the second pole of T0, and the drain of T3 is electrically connected to the anode of O1;
  • the gate of T4 is electrically connected to the first scanning line S1, the source of T4 is electrically connected to the gate of T0, and the drain of T4 is electrically connected to the connection node N0;
  • the gate of T5 is electrically connected to the second scanning line S2, the source of T5 is electrically connected to the second initial voltage line, and the drain of T5 is electrically connected to the anode of O1; the second initial voltage line is used to provide the second initial Voltage Vi2;
  • the gate of T6 is electrically connected to the reset control line R1, the source of T6 is electrically connected to the first initial voltage line, and the drain of T6 is electrically connected to the connection node N0; the first initial voltage line is used to provide the first initial voltage Vi1;
  • the gate of T7 is electrically connected to the second scanning line S2, the source of T7 is electrically connected to the connection node N0, and the drain of T7 is electrically connected to the second electrode of T0;
  • the gate of T8 is electrically connected to the second scanning line S2, the source of T8 is electrically connected to the data line D1, and the drain of T8 is electrically connected to the first electrode of T0;
  • the first end of C is electrically connected to the gate of T0, and the second end of C is electrically connected to the high voltage end;
  • the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide the low voltage VSS.
  • the first light emission control line and the second light emission control line are the same light emission control line E0.
  • T4 is an oxide thin film transistor, and other transistors may be low temperature polysilicon thin film transistors, but not limited thereto.
  • the reset voltage provided by DR may be a low voltage signal, but not limited thereto; for example, the reset voltage may be Vi1, Vi2 or VSS.
  • the display cycle includes an initialization phase t1, a data writing phase t2 and a light emitting phase t3 which are set successively;
  • E0 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a low voltage signal
  • S2 provides a high voltage signal
  • T6, T4 and T1 are all turned on
  • Vi is written into N1
  • the reset voltage is written into N3, T0 in the off-bias state
  • E0 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a high voltage signal
  • S2 provides a low voltage signal
  • T7, T8 and T4 are turned on, and the data voltage Vdata on D1 is written into N2
  • T5 is turned on , to write Vi2 into the anode of O1, so that O1 does not emit light, and remove the residual charge of the anode of O1;
  • T0 is turned on to charge C through Vdata, and the potential of N1 is changed until the potential of N1 becomes Vdata+Vth, and T0 is turned off;
  • E0 provides a low-voltage signal
  • S1 provides a low-voltage signal
  • S2 provides a high-voltage signal
  • R1 provides a high-voltage signal
  • T2 drives O1 to emit light.
  • At least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure is in operation.
  • T0 In the initialization phase t1, T0 is in the off state, ensuring that each pixel circuit is charged and compensated from the off-state bias state, and is not affected by The influence of the data voltage of the previous frame can eliminate the influence of the hysteresis of T0 and improve afterimage and response time.
  • the reset circuit 20 includes a first transistor T1; the first light emission control circuit 14 includes a second transistor T2, the The second light emission control circuit 15 includes a third transistor T3; the control circuit 12 includes a fourth transistor T4; the second initialization circuit 41 includes a fifth transistor T5; the first initialization circuit 13 includes a sixth transistor T6, so
  • the compensation control circuit 42 includes a seventh transistor T7, the data writing circuit 43 includes an eighth transistor T8, the driving circuit 11 includes a driving transistor T0, and the energy storage circuit 44 includes a storage capacitor C; the light emitting element is organic light emitting diode O1;
  • Both the gate of T1 and the source of T1 are electrically connected to the reset control line R1, and the drain of T1 is electrically connected to the second pole of T0;
  • the gate of T2 is electrically connected to the light emission control line E0, the source of T2 is electrically connected to the high voltage terminal, and the drain of T2 is electrically connected to the first pole of T0; the high voltage terminal is used to provide a high voltage VDD;
  • the gate of T3 is electrically connected to the light emission control line E0, the source of T3 is electrically connected to the second pole of T0, and the drain of T3 is electrically connected to the anode of O1;
  • the gate of T4 is electrically connected to the first scanning line S1, the source of T4 is electrically connected to the gate of T0, and the drain of T4 is electrically connected to the connection node N0;
  • the gate of T5 is electrically connected to the second scanning line S2, the source of T5 is electrically connected to the second initial voltage line, and the drain of T5 is electrically connected to the anode of O1; the second initial voltage line is used to provide the second initial Voltage Vi2;
  • the gate of T6 is electrically connected to the reset control line R1, the source of T6 is electrically connected to the first initial voltage line, and the drain of T6 is electrically connected to the connection node N0; the first initial voltage line is used to provide the first initial voltage Vi1;
  • the gate of T7 is electrically connected to the second scanning line S2, the source of T7 is electrically connected to the connection node N0, and the drain of T7 is electrically connected to the second electrode of T0;
  • the gate of T8 is electrically connected to the second scanning line S2, the source of T8 is electrically connected to the data line D1, and the drain of T8 is electrically connected to the first electrode of T0;
  • the first end of C is electrically connected to the gate of T0, and the second end of C is electrically connected to the high voltage end;
  • the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide the low voltage VSS.
  • the first light emission control line and the second light emission control line are the same light emission control line E0.
  • T4 is an oxide thin film transistor, and other transistors may be low temperature polysilicon thin film transistors, but not limited thereto.
  • the first node marked N1 is the first node
  • the second node marked N2 is the third node marked N3
  • the first node N1 is electrically connected to the gate of T0
  • the second node N2 is connected to the gate of T0
  • the source of T0 is electrically connected
  • the third node N3 is electrically connected to the second electrode of T0.
  • the reset voltage provided by DR may be a low voltage signal, but not limited thereto; for example, the reset voltage may be Vi1, Vi2 or VSS.
  • the display cycle includes an initialization phase t1, a data writing phase t2 and a light emitting phase t3 which are set successively;
  • E0 provides a high-voltage signal
  • S1 provides a high-voltage signal
  • R1 provides a low-voltage signal
  • S2 provides a high-voltage signal
  • T6, T4, and T1 are all turned on, Vi1 is written into N1, and a low-voltage signal is written into N3, T0 is in the off-state bias state;
  • E0 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a high voltage signal
  • S2 provides a low voltage signal
  • T7, T8 and T4 are turned on, and the data voltage Vdata on D1 is written into N2
  • T5 is turned on , to write Vi2 into the anode of O1, so that O1 does not emit light, and remove the residual charge of the anode of O1;
  • T0 is turned on to charge C through Vdata, and the potential of N1 is changed until the potential of N1 becomes Vdata+Vth, and T0 is turned off;
  • E0 provides a low-voltage signal
  • S1 provides a low-voltage signal
  • S2 provides a high-voltage signal
  • R1 provides a high-voltage signal
  • T2 drives O1 to emit light.
  • At least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure is in operation.
  • T0 In the initialization phase t1, T0 is in the off state, ensuring that each pixel circuit is charged and compensated from the off-state bias state, and is not affected by The influence of the data voltage of the previous frame can eliminate the influence of the hysteresis of T0 and improve afterimage and response time.
  • the reset circuit 20 includes a first transistor T1; the first light emission control circuit 14 includes a second transistor T2, the The second light emission control circuit 15 includes a third transistor T3; the control circuit 12 includes a fourth transistor T4; the second initialization circuit 41 includes a fifth transistor T5; the first initialization circuit 13 includes a sixth transistor T6, so
  • the compensation control circuit 42 includes a seventh transistor T7, the data writing circuit 43 includes an eighth transistor T8, the driving circuit 11 includes a driving transistor T0, and the energy storage circuit 44 includes a storage capacitor C; the light emitting element is organic light emitting diode O1;
  • the gate of T1 is electrically connected to the reset control line R1, the source of T1 is electrically connected to the reset voltage line DR, and the drain of T1 is electrically connected to the second pole of T0; the reset voltage line DR is used to provide a reset voltage;
  • the gate of T2 is electrically connected to the light emission control line E0, the source of T2 is electrically connected to the high voltage terminal, and the drain of T2 is electrically connected to the first pole of T0; the high voltage terminal is used to provide a high voltage VDD;
  • the gate of T3 is electrically connected to the light emission control line E0, the source of T3 is electrically connected to the second pole of T0, and the drain of T3 is electrically connected to the anode of O1;
  • the gate of T4 is electrically connected to the first scanning line S1, the source of T4 is electrically connected to the gate of T0, and the drain of T4 is electrically connected to the connection node N0;
  • the gate of T5 is electrically connected to the light emission control line E0, the source of T5 is electrically connected to the second initial voltage line, and the drain of T5 is electrically connected to the anode of O1; the second initial voltage line is used to provide the second initial voltage Vi2;
  • the gate of T6 is electrically connected to the reset control line R1, the source of T6 is electrically connected to the first initial voltage line, and the drain of T6 is electrically connected to the connection node N0; the first initial voltage line is used to provide the first initial voltage Vi1;
  • the gate of T7 is electrically connected to the second scanning line S2, the source of T7 is electrically connected to the connection node N0, and the drain of T7 is electrically connected to the second electrode of T0;
  • the gate of T8 is electrically connected to the second scanning line S2, the source of T8 is electrically connected to the data line D1, and the drain of T8 is electrically connected to the first electrode of T0;
  • the first end of C is electrically connected to the gate of T0, and the second end of C is electrically connected to the high voltage end;
  • the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide the low voltage VSS.
  • the first light emission control line and the second light emission control line are the same light emission control line E0.
  • T4 and T5 are oxide thin film transistors, and other transistors may be low temperature polysilicon thin film transistors, but not limited thereto.
  • the one labeled N1 is the first node
  • the one labeled N2 is the second node
  • the one labeled N3 is the third node
  • the first node N1 is electrically connected to the gate of T0
  • the second node N2 is connected to T0
  • the first pole of T0 is electrically connected
  • the third node N3 is electrically connected with the second pole of T0.
  • the reset voltage provided by DR may be a low voltage signal, but not limited thereto; for example, the reset voltage may be Vi1, Vi2 or VSS.
  • T5 is an oxide thin film transistor, and the gate of T5 is electrically connected to the light emission control line E0;
  • E0 provides a high voltage signal
  • T5 is turned on to reset the potential of the anode of O1.
  • a high-frequency control signal is required to reset the potential of the anode of O1
  • the second light-emitting control signal provided by E2 itself is a high-frequency signal, which can save the need to change the signal controlling the gate of T5 to high frequency The problem of increased power consumption caused by the signal.
  • FIG. 22 it is a distribution diagram of pixel circuits in a display device according to at least one embodiment of the present disclosure.
  • the display device may include a plurality of pixel circuits P distributed in an array, a first high voltage line VDD11 , a second high voltage line VDD12 , a third high voltage line VDD21 and a fourth high voltage line VDD22 .
  • VDD11, VDD12, VDD21, VDD22 can all be used to provide high voltage.
  • VDD11 and VDD12 extend along the column direction
  • VDD21 and VDD22 extend along the row direction.
  • Pixel circuits in two adjacent rows can be connected to high voltage lines extending in the same row direction.
  • the high-voltage lines extending along the column direction can be connected and intersected with multiple high-voltage lines extending along the row direction, so that the multiple high-voltage lines can form a grid structure.
  • the high voltage line extending along the column direction may be located in the area where the red pixel driving circuit is located.
  • two pixel circuits in adjacent columns can be mirrored to facilitate wiring.
  • the driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display cycle includes an initialization phase; the driving method includes:
  • the first initialization circuit writes the first initial voltage into the connection node under the control of the reset control signal, and the control circuit controls the control terminal of the driving circuit to connect to the connection node under the control of the first scanning signal.
  • the connection node is electrically connected to write a first initial voltage into the control terminal of the driving circuit, and to control the driving transistor in the driving circuit to be in a predetermined bias state when the initialization phase ends.
  • the predetermined bias state may be an on-state bias state or an off-state bias state.
  • the control circuit and the first initialization circuit cooperate with the control of writing the first initial voltage into the driving circuit end, and control the drive transistor in the drive circuit to be in a predetermined bias state at the end of the initialization phase, so as to improve the hysteresis of the drive transistor.
  • the predetermined bias state may be an off-state bias state
  • the driving method may further include:
  • the second light emission control circuit controls the communication between the second terminal of the driving circuit and the first pole of the light emitting element under the control of the second light emission control signal;
  • the driving circuit controls the communication between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of the potential of its control terminal, so as to change the first terminal of the driving circuit.
  • the potential of the terminal until the drive transistor included in the drive circuit is turned off, and the drive transistor is in an off-state bias state.
  • the control circuit and the first initialization circuit cooperate with the control of writing the first initial voltage into the driving circuit terminal
  • the second light emission control circuit initializes the potential of the source of the driving transistor included in the driving circuit, so that at the end of the initialization phase, the driving transistor is in the off-state bias state, ensuring that the The driving transistors are all charged and compensated from the off-state bias state without being affected by the data voltage of the previous frame, so as to improve the hysteresis of the driving transistors.
  • the predetermined bias state may be an open bias state
  • the driving method may further include:
  • the first light emission control circuit controls the connection between the first terminal of the drive circuit and the first voltage terminal, so that the drive transistor in the drive circuit is in the open bias state.
  • the control circuit and the first initialization circuit cooperate with the control of writing the first initial voltage into the driving circuit Terminal, the first light emission control circuit controls the communication between the first terminal of the driving circuit and the first voltage terminal, so that the driving transistor in the driving circuit is in an open bias state, ensuring that each pixel circuit The driving transistors are all charged and compensated from the open bias state, without being affected by the data voltage of the previous frame, so as to improve the hysteresis of the driving transistors.
  • the pixel circuit further includes a data writing circuit
  • the display cycle also includes a data writing phase set after the initialization phase
  • the driving method further includes:
  • the data writing circuit writes the data voltage on the data line into the first terminal of the driving circuit under the control of the second scanning line.
  • the pixel circuit further includes a second initialization circuit; the driving method further includes:
  • the second initialization circuit Under the control of the initial control signal, the second initialization circuit writes a second initial voltage into the first pole of the light-emitting element, so as to control the light-emitting element not to emit light, and clear the residual charge of the first pole of the light-emitting element .
  • the driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the pixel circuit further includes a reset circuit; the first light emission control line and the second light emission control line are the same light emission control line; the display cycle includes initialization stage;
  • the driving method includes:
  • the first initialization circuit writes the first initial voltage into the connection node under the control of the reset control signal
  • the control circuit controls the control terminal of the driving circuit to connect to the connection node under the control of the first scanning signal.
  • the connection node is electrically connected to write the first initial voltage into the control terminal of the drive circuit; the reset circuit controls the potential of the first terminal of the drive circuit or the potential of the drive circuit under the control of the reset control signal
  • the potential of the second terminal is initialized.
  • the control circuit and the first initialization circuit cooperate to write the first initial voltage into the control terminal of the driving circuit.
  • the reset circuit initializes the potential of the first terminal of the driving circuit or the potential of the second terminal of the driving circuit, so as to improve the hysteresis of the driving transistor.
  • the pixel circuit further includes a data writing circuit
  • the display cycle also includes a data writing phase set after the initialization phase
  • the driving method further includes:
  • the data writing circuit writes the data voltage on the data line into the first end of the driving circuit under the control of the second scanning line.
  • the pixel circuit further includes a second initialization circuit; the driving method further includes:
  • the second initialization circuit Under the control of the initial control signal, the second initialization circuit writes a second initial voltage into the first pole of the light-emitting element, so as to control the light-emitting element not to emit light, and clear the residual charge of the first pole of the light-emitting element .
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种像素电路、驱动方法和显示装置。像素电路包括发光元件(10)、驱动电路(11)、控制电路(12)、第一初始化电路(13)、第一发光控制电路(14)和第二发光控制电路(15)，控制电路(12)在第一扫描信号的控制下，控制驱动电路(11)的控制端与连接节点(N0)电连接；第一初始化电路(13)在复位控制信号的控制下，将第一初始电压(Vi1)写入连接节点(N0)；第一发光控制电路(14)在第一发光控制信号的控制下，控制第一电压端(V1)与驱动电路(11)的第一端之间连通；第二发光控制电路(15)在第二发光控制信号的控制下，控制驱动电路(11)的第二端与发光元件(10)的第一极之间连通。

Description

像素电路、驱动方法和显示装置
相关申请的交叉引用
本申请主张在2021年7月30日提交的专利申请号为PCT/CN2021/109890的PCT国际申请，以及，在2021年8月5日在中国提交的中国专利申请号No.202110897272.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。
背景技术
相关的显示面板在工作时，像素电路包括的驱动电路中的驱动晶体管的磁滞会导致驱动晶体管的特性反应较迟钝，从而影响显示。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括发光元件、驱动电路、控制电路、第一初始化电路、第一发光控制电路和第二发光控制电路，其中，
所述控制电路分别与第一扫描线、所述驱动电路的控制端和连接节点电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述驱动电路的控制端与所述连接节点电连接；
所述第一初始化电路分别与复位控制线、所述连接节点和第一初始电压线电连接，用于在所述复位控制线提供的复位控制信号的控制下，将第一初始电压线提供的第一初始电压写入所述连接节点；
所述第一发光控制电路分别与第一发光控制线、第一电压端和所述驱动电路的第一端电连接，用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通；
所述第二发光控制电路分别与第二发光控制线、所述驱动电路的第二端 和发光元件的第一极电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
所述驱动电路用于在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括复位电路；
所述复位电路分别与复位控制线和所述驱动电路的第一端电连接，用于在所述复位控制信号的控制下，对所述驱动电路的第一端的电位进行初始化；或者，
所述复位电路分别与复位控制线和所述驱动电路的第二端电连接，用于在所述复位控制信号的控制下，对所述驱动电路的第二端的电位进行初始化。
可选的，所述复位电路包括第一晶体管；
所述第一晶体管的控制极与所述复位控制线电连接，所述第一晶体管的第一极与复位电压线电连接，所述第一晶体管的第二极与所述驱动电路的第一端或所述驱动电路的第二端电连接；所述复位电压线用于提供复位电压。
可选的，所述复位电路包括第一晶体管；
所述第一晶体管的控制极和所述第一晶体管的第一极与所述复位控制线电连接，所述第一晶体管的第二极与所述驱动电路的第一端或所述驱动电路的第二端电连接。
可选的，所述第一发光控制电路包括第二晶体管，所述第二发光控制电路包括第三晶体管；
所述第二晶体管的控制极与所述第一发光控制线电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接；
所述第三晶体管的控制极与所述第二发光控制线电连接，所述第三晶体管的第一极与所述驱动电路的第二端电连接，所述第三晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第一发光控制线与所述第二发光控制线为不同的发光控制线；或者，
所述第一发光控制线与所述第二发光控制线为相同的发光控制线。
可选的，所述控制电路包括第四晶体管；
所述第四晶体管的控制极与所述第一扫描线电连接，所述第四晶体管的第一极与所述驱动电路的控制端电连接，所述第四晶体管的第二极与所述连接节点电连接；
所述第四晶体管为氧化物薄膜晶体管。
可选的，本公开至少一实施例所述的像素电路还包括第二初始化电路；
所述第二初始化电路分别与初始控制线、第二初始电压线和发光元件的第一极电连接，用于在初始控制线提供的初始控制信号的控制下，将第二初始电压线提供的第二初始电压写入所述发光元件的第一极。
可选的，所述第二初始化电路包括第五晶体管；
所述第五晶体管的控制极与所述初始控制线电连接，所述第五晶体管的第一极与所述第二初始电压线电连接，所述第五晶体管的第二极与所述发光元件的第一极电连接；
所述第五晶体管为氧化物薄膜晶体管；所述初始控制线为所述第一发光控制线或所述第二发光控制线。
可选的，本公开至少一实施例所述的像素电路还包括补偿控制电路、数据写入电路和储能电路；
所述补偿控制电路分别与第二扫描线、所述连接节点和所述驱动电路的第二端电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，控制所述连接节点和所述驱动电路的第二端之间连通；
所述数据写入电路分别与第二扫描线、数据线和所述驱动电路的第一端电连接，用于在所述第二扫描信号的控制下，将数据线上的数据电压写入所述驱动电路的第一端；
所述储能电路与所述驱动电路的控制端电连接，用于储存电能。
可选的，所述第一初始化电路包括第六晶体管，所述补偿控制电路包括第七晶体管，所述数据写入电路包括第八晶体管，所述驱动电路包括驱动晶体管，所述储能电路包括存储电容；
所述第六晶体管的控制极与所述复位控制线电连接，所述第六晶体管的 第一极与第一初始电压线电连接，所述第六晶体管的第二极与所述连接节点电连接；
所述第七晶体管的控制极与所述第二扫描线电连接，所述第七晶体管的第一极与所述连接节点电连接，所述第七晶体管的第二极与所述驱动晶体管的第二极电连接；
所述第八晶体管的控制极与所述第二扫描线电连接，所述第八晶体管的第一极与所述数据线电连接，所述第八晶体管的第二极与所述驱动晶体管的第一极电连接；
所述存储电容的第一端与所述驱动晶体管的控制极电连接，所述存储电容的第二端与所述第一电压端电连接。
在第二个方面中，本公开实施例还提供一种驱动方法，应用于上述的像素电路，显示周期包括初始化阶段；所述驱动方法包括：
在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第一初始电压写入连接节点，控制电路在所述第一扫描信号的控制下，控制驱动电路的控制端与所述连接节点电连接，以将第一初始电压写入所述驱动电路的控制端，并使得在所述初始化阶段结束时，所述驱动电路中的驱动晶体管处于预定偏置状态。
可选的，所述预定偏置状态为关态偏置状态；所述驱动方法还包括：
在所述初始化阶段，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通；
在所述初始化阶段开始时，驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以改变所述驱动电路的第一端的电位，直至驱动电路包括的驱动晶体管关断，所述驱动晶体管处于关态偏置状态。
可选的，所述预定偏置状态为所述驱动方法还包括：
在所述初始化阶段，第一发光控制电路在第一发光控制信号的控制下，控制所述驱动电路的第一端与第一电压端之间连通，以使得所述驱动电路中的驱动晶体管处于开态偏置状态。
可选的，所述像素电路还包括数据写入电路，所述显示周期还包括设置 于所述初始化阶段之后的数据写入阶段；所述驱动方法还包括：
在所述数据写入阶段，数据写入电路在第二扫描线的控制下，将数据线上的数据电压写入所述驱动电路的第一端。
可选的，所述像素电路还包括第二初始化电路；所述驱动方法还包括：
所述第二初始化电路在初始控制信号的控制下，将第二初始电压写入所述发光元件的第一极，以控制发光元件不发光。
在第三个方面中，本公开实施例还提供了一种驱动方法，应用于上述的像素电路，所述像素电路还包括复位电路；第一发光控制线和第二发光控制线为相同的发光控制线；显示周期包括初始化阶段；
所述驱动方法包括：
在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第一初始电压写入连接节点，控制电路在所述第一扫描信号的控制下，控制驱动电路的控制端与所述连接节点电连接，以将第一初始电压写入所述驱动电路的控制端；所述复位电路在复位控制信号的控制下，对所述驱动电路的第一端的电位或所述驱动电路的第二端的电位进行初始化。
可选的，所述像素电路还包括数据写入电路，所述显示周期还包括设置于所述初始化阶段之后的数据写入阶段；所述驱动方法还包括：
在所述数据写入阶段，数据写入电路在第二扫描线的控制下，将数据线上的数据电压写入所述驱动电路的第一端。
可选的，所述像素电路还包括第二初始化电路；所述驱动方法还包括：
所述第二初始化电路在初始控制信号的控制下，将第二初始电压写入所述发光元件的第一极，以控制发光元件不发光。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的像素电路。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的结构图；
图6是本公开至少一实施例所述的像素电路的结构图；
图7是本公开至少一实施例所述的像素电路的电路图；
图8是图7所示的像素电路的至少一实施例的一种工作时序图；
图9是图7所示的像素电路的至少一实施例的另外一种工作时序图；
图10是本公开至少一实施例所述的像素电路的电路图；
图11是本公开至少一实施例所述的像素电路的电路图；
图12是本公开至少一实施例所述的像素电路的电路图；
图13是图12所示的像素电路的至少一实施例的工作时序图；
图14是本公开至少一实施例所述的像素电路的电路图；
图15是图14所示的像素电路的至少一实施例的工作时序图；
图16是本公开至少一实施例所述的像素电路的电路图；
图17是本公开至少一实施例所述的像素电路的电路图；
图18是图17所示的像素电路的至少一实施例的工作时序图；
图19是本公开至少一实施例所述的像素电路的电路图；
图20是图19所示的像素电路的至少一实施例的工作时序图；
图21是本公开至少一实施例所述的像素电路的电路图；
图22是本公开至少一实施例所述的显示装置中的像素电路的分布图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极 可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的像素电路包括发光元件10、驱动电路11、控制电路12、第一初始化电路13、第一发光控制电路14和第二发光控制电路15，其中，
所述控制电路12分别与第一扫描线S1、所述驱动电路11的控制端和连接节点N0电连接，用于在所述第一扫描线S1提供的第一扫描信号的控制下，控制所述驱动电路11的控制端与所述连接节点N0电连接；
所述第一初始化电路13分别与复位控制线R1、所述连接节点N0和第一初始电压线电连接，用于在所述复位控制线R1提供的复位控制信号的控制下，将第一初始电压线提供的第一初始电压Vi1写入所述连接节点N0；
所述第一发光控制电路14分别与第一发光控制线E1、第一电压端V1和所述驱动电路11的第一端电连接，用于在所述第一发光控制线E1提供的第一发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路11的第一端之间连通；
所述第二发光控制电路15分别与第二发光控制线E2、所述驱动电路11的第二端和发光元件10的第一极电连接，用于在所述第二发光控制线E2提供的第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件10的第一极之间连通；
所述驱动电路11用于在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通。
本公开实施例所述的像素电路在工作时，在数据电压写入驱动电路的第一端之前，在初始化阶段，控制电路12和第一初始化电路13配合将第一初始电压Vi1写入驱动电路11的控制端，所述第一发光控制电路14或所述第二发光控制电路15工作以对驱动电路11包括的驱动晶体管的源极的电位进行初始化，以能够改善所述驱动晶体管的磁滞现象。
在一种情况下，本公开实施例所述的像素电路在工作时，显示周期包括初始化阶段；
在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第一 初始电压写入连接节点，控制电路在所述第一扫描信号的控制下，控制驱动电路的控制端与所述连接节点电连接，以将第一初始电压写入所述驱动电路的控制端；第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通；
在所述初始化阶段开始时，驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以改变所述驱动电路的第一端的电位，直至驱动电路包括的驱动晶体管关断，以对所述驱动电路的第一端的电位进行初始化。
在另一种情况下，本公开实施例所述的像素电路在工作时，显示周期包括初始化阶段；
在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第一初始电压写入连接节点，控制电路在所述第一扫描信号的控制下，控制驱动电路的控制端与所述连接节点电连接，以将第一初始电压写入所述驱动电路的控制端；第一发光控制电路在第一发光控制信号的控制下，控制所述驱动电路的第一端与第一电压端之间连通，以对所述驱动电路的第一端的电位进行初始化。
可选的，本公开至少一实施例所述的像素电路还可以包括复位电路；
所述复位电路分别与复位控制线和所述驱动电路的第一端电连接，用于在所述复位控制信号的控制下，对所述驱动电路的第一端的电位进行初始化；或者，
所述复位电路分别与复位控制线和所述驱动电路的第二端电连接，用于在所述复位控制信号的控制下，对所述驱动电路的第二端的电位进行初始化。
在本公开至少一实施例中，在初始化阶段，也可以通过复位电路在复位控制信号的控制下，对所述驱动电路的第一端的电位或所述驱动电路的第二端的电位进行初始化，以改善驱动电路中的驱动晶体管的磁滞现象。
如图2所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括复位电路20；
所述复位电路20分别与复位控制线R1和所述驱动电路11的第一端电连接，用于在所述复位控制信号的控制下，对所述驱动电路11的第一端的电位 进行初始化。
如图3所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括复位电路20；
所述复位电路20分别与复位控制线R1和所述驱动电路11的第二端电连接，用于在所述复位控制信号的控制下，对所述驱动电路11的第二端的电位进行初始化。
可选的，所述复位电路包括第一晶体管；
所述第一晶体管的控制极与所述复位控制线电连接，所述第一晶体管的第一极与复位电压线电连接，所述第一晶体管的第二极与所述驱动电路的第一端或所述驱动电路的第二端电连接；所述复位电压线用于提供复位电压。
可选的，所述复位电路包括第一晶体管；
所述第一晶体管的控制极和所述第一晶体管的第一极与所述复位控制线电连接，所述第一晶体管的第二极与所述驱动电路的第一端或所述驱动电路的第二端电连接。
在本公开至少一实施例中，所述第一发光控制电路包括第二晶体管，所述第二发光控制电路包括第三晶体管；
所述第二晶体管的控制极与所述第一发光控制线电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接；
所述第三晶体管的控制极与所述第二发光控制线电连接，所述第三晶体管的第一极与所述驱动电路的第二端电连接，所述第三晶体管的第二极与所述发光元件的第一极电连接。
在具体实施时，所述第一发光控制线与所述第二发光控制线可以为不同的发光控制线；或者，
所述第一发光控制线与所述第二发光控制线可以为相同的发光控制线。
可选的，所述控制电路包括第四晶体管；
所述第四晶体管的控制极与所述第一扫描线电连接，所述第四晶体管的第一极与所述驱动电路的控制端电连接，所述第四晶体管的第二极与所述连接节点电连接；
所述第四晶体管为氧化物薄膜晶体管，以减少驱动电路的控制端的漏电，能够在低频工作时保证第一节点的电压的稳定性，利于提升显示质量，提升显示均一性，减轻Flicker(闪烁)。
本公开至少一实施例所述的像素电路还可以包括第三初始化电路；
所述第三初始化电路分别与初始控制线、第二初始电压线和发光元件的第一极电连接，用于在初始控制线提供的初始控制信号的控制下，将第二初始电压线提供的第二初始电压写入所述发光元件的第一极，以使得所述发光元件不发光，并清除所述发光元件的第一极残留的电荷。
可选的，所述第二初始化电路包括第五晶体管；
所述第五晶体管的控制极与所述初始控制线电连接，所述第五晶体管的第一极与所述第二初始电压线电连接，所述第五晶体管的第二极与所述发光元件的第一极电连接；
所述第五晶体管为氧化物薄膜晶体管；所述初始控制线为所述第一发光控制线或所述第二发光控制线。
在本公开至少一实施例中，所述第五晶体管可以为p型晶体管，第五晶体管的控制极可以为第一发光控制线或第二发光控制线，由于第一发光控制信号和第二发光控制线本身就是高频信号，可以方便的对发光元件的第一极进行高频复位，解决闪烁问题。
本公开至少一实施例所述的像素电路还可以包括补偿控制电路、数据写入电路和储能电路；
所述补偿控制电路分别与第二扫描线、所述连接节点和所述驱动电路的第二端电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，控制所述连接节点和所述驱动电路的第二端之间连通；
所述数据写入电路分别与第二扫描线、数据线和所述驱动电路的第一端电连接，用于在所述第二扫描信号的控制下，将数据线上的数据电压写入所述驱动电路的第一端；
所述储能电路与所述驱动电路的控制端电连接，用于储存电能。
本公开至少一实施例所述的像素电路在工作时，在设置于初始化阶段之后的数据写入阶段，数据写入电路在第二扫描信号的控制下，将数据电压写 入驱动电路的第一端，补偿控制电路在第二扫描信号的控制下，控制所述连接节点和所述驱动电路的第二端之间连通；控制电路在第一扫描信号的控制下，控制所述驱动电路的控制端与所述连接节点电连接，以将数据电压写入驱动电路的控制端；
并在所述数据写入阶段开始时，驱动电路中的驱动晶体管导通，以改变驱动电路的控制端的电位，直至所述驱动晶体管关断，此时，驱动电路的控制端的电位与驱动晶体管的阈值电压相关。
可选的，所述第一初始化电路包括第六晶体管，所述补偿控制电路包括第七晶体管，所述数据写入电路包括第八晶体管，所述驱动电路包括驱动晶体管，所述储能电路包括存储电容；
所述第六晶体管的控制极与所述复位控制线电连接，所述第六晶体管的第一极与第一初始电压线电连接，所述第六晶体管的第二极与所述连接节点电连接；
所述第七晶体管的控制极与所述第二扫描线电连接，所述第七晶体管的第一极与所述连接节点电连接，所述第七晶体管的第二极与所述驱动晶体管的第二极电连接；
所述第八晶体管的控制极与所述第二扫描线电连接，所述第八晶体管的第一极与所述数据线电连接，所述第八晶体管的第二极与所述驱动晶体管的第一极电连接；
所述存储电容的第一端与所述驱动晶体管的控制极电连接，所述存储电容的第二端与所述第一电压端电连接。
如图4所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第二初始化电路41、补偿控制电路42、数据写入电路43和储能电路44；
所述第二初始化电路41分别与初始控制线S0、第二初始电压线和发光元件10的第一极电连接，用于在初始控制线S0提供的初始控制信号的控制下，将第二初始电压线提供的第二初始电压Vi2写入所述发光元件10的第一极；
所述补偿控制电路42分别与第二扫描线S2、所述连接节点N0和所述驱 动电路11的第二端电连接，用于在所述第二扫描线S2提供的第二扫描信号的控制下，控制所述连接节点N0和所述驱动电路11的第二端之间连通；
所述数据写入电路43分别与第二扫描线S2、数据线D1和所述驱动电路11的第一端电连接，用于在所述第二扫描信号的控制下，将数据线D1上的数据电压写入所述驱动电路11的第一端；
所述储能电路44与所述驱动电路11的控制端电连接，用于储存电能。
在图4所示的像素电路的至少一实施例中，第一发光控制线E1与第二发光控制线E2为不同的发光控制线。
在图4所示的像素电路的至少一实施例中，所述初始控制线S0可以为第二扫描线，或者，所述初始控制线S0可以为第一发光控制线或第二发光控制线。
如图5所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第二初始化电路41、补偿控制电路42、数据写入电路43和储能电路44；
所述第二初始化电路41分别与初始控制线S0、第二初始电压线和发光元件10的第一极电连接，用于在初始控制线S0提供的初始控制信号的控制下，将第二初始电压线提供的第二初始电压Vi2写入所述发光元件10的第一极；
所述补偿控制电路42分别与第二扫描线S2、所述连接节点N0和所述驱动电路11的第二端电连接，用于在所述第二扫描线S2提供的第二扫描信号的控制下，控制所述连接节点N0和所述驱动电路11的第二端之间连通；
所述数据写入电路43分别与第二扫描线S2、数据线D1和所述驱动电路11的第一端电连接，用于在所述第二扫描信号的控制下，将数据线D1上的数据电压写入所述驱动电路11的第一端；
所述储能电路44与所述驱动电路11的控制端电连接，用于储存电能。
在图5所示的像素电路的至少一实施例中，第一发光控制线E1和第一发光控制线E2可以为相同的发光控制线，但不以此为限。
在图5所示的像素电路的至少一实施例中，所述初始控制线S0可以为第二扫描线，或者，所述初始控制线S0可以为第一发光控制线或第二发光控制 线。
如图6所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第二初始化电路41、补偿控制电路42、数据写入电路43和储能电路44；
所述第二初始化电路41分别与初始控制线S0、第二初始电压线和发光元件10的第一极电连接，用于在初始控制线S0提供的初始控制信号的控制下，将第二初始电压线提供的第二初始电压Vi2写入所述发光元件10的第一极；
所述补偿控制电路42分别与第二扫描线S2、所述连接节点N0和所述驱动电路11的第二端电连接，用于在所述第二扫描线S2提供的第二扫描信号的控制下，控制所述连接节点N0和所述驱动电路11的第二端之间连通；
所述数据写入电路43分别与第二扫描线S2、数据线D1和所述驱动电路11的第一端电连接，用于在所述第二扫描信号的控制下，将数据线D1上的数据电压写入所述驱动电路11的第一端；
所述储能电路44与所述驱动电路11的控制端电连接，用于储存电能。
在图6所示的像素电路的至少一实施例中，第一发光控制线E1和第一发光控制线E2可以为相同的发光控制线，但不以此为限。
在图6所示的像素电路的至少一实施例中，所述初始控制线S0可以为第二扫描线，或者，所述初始控制线S0可以为第一发光控制线或第二发光控制线。
在本公开至少一实施例中，第一电压端可以为高电压端，第二电压端可以为低电压端，但不以此为限。
如图7所示，在图4所示的像素电路的至少一实施例的基础上，所述第一发光控制电路14包括第二晶体管T2，所述第二发光控制电路15包括第三晶体管T3；所述控制电路12包括第四晶体管T4；所述第二初始化电路41包括第五晶体管T5；所述第一初始化电路13包括第六晶体管T6，所述补偿控制电路42包括第七晶体管T7，所述数据写入电路43包括第八晶体管T8，所述驱动电路11包括驱动晶体管T0，所述储能电路44包括存储电容C；所述发光元件为有机发光二极管O1；
T2的栅极与第一发光控制线E1电连接，T2的源极与高电压端电连接，T2的漏极与T0的源极电连接；所述高电压端用于提供高电压VDD；
T3的栅极与第二发光控制线E1电连接，T3的源极与T0的漏极电连接，T3的漏极与O1的阳极电连接；
T4的栅极与第一扫描线S1电连接，T4的源极与T0的栅极电连接，T4的漏极与连接节点N0电连接；
T5的栅极与第二扫描线S2电连接，T5的源极与第二初始电压线电连接，T5的漏极与O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
T6的栅极与复位控制线R1电连接，T6的源极与第一初始电压线电连接，T6的漏极与连接节点N0电连接；所述第一初始电压线用于提供第一初始电压Vi1；
T7的栅极与第二扫描线S2电连接,T7的源极与连接节点N0电连接，T7的漏极与T0的漏极电连接；
T8的栅极与第二扫描线S2电连接，T8的源极与数据线D1电连接，T8的漏极与T0的源极电连接；
C的第一端与T0的栅极电连接，C的第二端与所述高电压端电连接；
O1的阴极与低电压端电连接，所述低电压端用于提供低电压VSS。
在图7所示的像素电路的至少一实施例中，初始控制线为第二扫描线。
在图7所示的像素电路的至少一实施例中，T4为氧化物薄膜晶体管，其他晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
在图7中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点；第一节点N1与T0的栅极电连接，第二节点N2与T0的源极电连接，第三节点N3与T0的漏极电连接。
如图8所示，本公开如图7所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3；
在初始化阶段t1，E1提供高电压信号，E2提供低电压信号，S1提供高电压信号，S2提供高电压信号，R1提供低电压信号，T6打开，T4打开，T3打开，T2关断，N1的电位被初始化为Vi1，T0的源极电位由于漏电而降低， 直至T0的源极的电位(也即N2的电位)变为Vi1-Vth，T0处于关态偏置(off-bias)状态，Vth为T0的阈值电压；
在数据写入阶段t2，E1提供高电压信号，E2提供高电压信号，S1提供高电压信号，S2提供低电压信号，R1提供高电压信号，T7、T8和T4打开，D1上的数据电压Vdata写入N2；
在数据写入阶段t2开始时，T0打开，以通过Vdata为C充电，改变T0的栅极的电位，直至T0关断，此时N1的电位为Vdata+Vth；
在发光阶段t3，E1提供低电压信号，E2提供低电压信号，S1提供低电压信号，S2提供高电压信号，S3提供高电压信号，T2和T3打开，T0打开，以驱动O1发光。
本公开如图7所示的像素电路的至少一实施例在工作时，在数据写入之前，T0处于关态偏置状态，确保每个像素电路中的驱动晶体管都是从关态偏置状态开始充电和补偿的，而不受上一帧数据电压的影响，可以消除T0的磁滞的影响，改善残像和响应时间。
如图8所示，E1提供的第一发光控制信号的脉宽需要大于S1提供的第一扫描信号的脉宽，也即，E1提供的第一发光控制信号的电位持续为高电压的时间段，包含S1提供的第一扫描信号的电位持续为高电压的时间段，保证当T4打开时，T2关断。
如图8所示，S1提供的第一扫描信号的电位持续为高电压的时间段需要包含R1提供的复位控制信号的电位持续为低电压的时间段，以及，S2提供的第二扫描信号的电位持续为低电压的时间段，以保证在进行初始化阶段和数据写入阶段，S1提供的第一扫描信号可以控制T4打开，以便在初始化阶段对N1的电位进行初始化，并便于在数据写入阶段补偿驱动晶体管T0的阈值电压。
如图8所示，E2提供的第二发光控制信号的电位持续为高电压的时间段需要包含S2提供的第二扫描信号的电位持续为低电压的时间时间段，以保证在数据写入阶段，E2提供的第二发光控制信号能够控制T3关断，保证O1不发光。
在本公开至少一实施例中，在图8所示的时序图中，E1提供的第一发光 控制信号的上升沿与S1提供的第一扫描信号的上升沿之间的最短时间间隔可以为第一预定时间间隔，E1提供的第一发光控制信号的上升沿与R1提供的复位控制信号的下降沿之间的最短时间间隔可以为第二预定时间间隔，所述第一预定时间间隔和所述第二预定时间间隔可以大于或等于0.5us而小于或等于1us，但不以此为限；
E2提供的第二发光控制信号的上升沿与S2提供的第二扫描信号的下降沿之间的最短时间间隔可以为第三预定时间间隔，所述第三预定时间间隔可以大于或等于0.5us而小于或等于1us，但不以此为限。
本公开至少一实施例所述的像素电路在工作时，在数据写入阶段开始时，T0打开，因此Vi1的电压值与最小数据电压值之间的电压差需要小于T0的阈值电压Vth。
其中，Vi1的电压值可以大于或等于-6V而小于或等于-2V，例如，Vi1的电压值可以为-2V、-3V、-4V、-5V或-6V等，但不以此为限；
Vi1的电压值与最小数据电压值之间的电压差值可以小于a*Vth，其中，a可以大于或等于2而小于或等于7。例如，a可以为2、4、6或7。
Vth可以大于或等于-5V而小于或等于-2V；例如，Vth可以为-2.5V或-3V等；
VDD的电压值可以大于或等于3V而小于或等于6V，例如，VDD的电压值可以为4.6V；但不以此为限；
VDD的电压值的绝对值可以大于Vth的绝对值的1.5倍，例如，VDD的电压值的绝对值可以为Vth的绝对值的1.6倍、1.8倍、2倍等。
可选的，VSS的电压值可以大于或等于-6V而小于或等于-3V；例如，VSS的电压值可以为-5V、-4V或-3V。
在本公开至少一实施例中，Vi2的电压值可以大于或等于-7V而小于或等于0V。例如，所述第二初始化电压的电压值可以为-6V、-5V、-4V、-3V或-2V；但不以此为限。
可选的，Vi2的电压值与VSS的电压值之间的电压差值需要小于发光元件的启亮电压，以使得当发光元件的第一极接入Vi2时，发光元件不发光。
如图9所示，本公开如图7所示的像素电路的至少一实施例在工作时， 显示周期包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3；
在初始化阶段t1，E1提供低电压信号，E2提供高电压信号，S1提供高电压信号，S2提供高电压信号，R1提供低电压信号，T6打开，T4打开，T2打开，T3关断，N1的电位被初始化为Vi1，N2的电位为VDD，此时T0的栅源电压为Vi1-VDD，T0处于开态偏置(on-bias)状态；
在数据写入阶段t2，E1提供高电压信号，E2提供高电压信号，S1提供高电压信号，S2提供低电压信号，R1提供高电压信号，T7、T8和T4打开，D1上的数据电压Vdata写入N2；T5打开，以将Vi2写入O1的阳极，使得O1不发光，并清除O1的阳极残留的电荷；
在数据写入阶段t2开始时，T0打开，以通过Vdata为C充电，改变T0的栅极的电位，直至T0关断，此时N1的电位为Vdata+Vth；
在发光阶段t3，E1提供低电压信号，E2提供低电压信号，S1提供低电压信号，S2提供高电压信号，S3提供高电压信号，T2和T3打开，T0打开，以驱动O1发光。
本公开如图7所示的像素电路的至少一实施例在工作时，在数据写入之前，T0处于开态偏置状态，确保每个像素电路中的驱动晶体管都是从开态偏置状态开始充电和补偿的，而不受上一帧数据电压的影响，可以消除T0的磁滞的影响，改善残像和响应时间。
如图9所示，E2提供的第二发光控制信号的脉宽需要大于S1提供的第一扫描信号的脉宽，也即，E2提供的第二发光控制信号的电位持续为高电压的时间段，包含S1提供的第一扫描信号的电位持续为高电压的时间段，保证当T4打开时，T3关断。
如图9所示，S1提供的第一扫描信号的电位持续为高电压的时间段需要包含R1提供的复位控制信号的电位持续为低电压的时间段，以及，S2提供的第二扫描信号的电位持续为低电压的时间段，以保证在进行初始化阶段和数据写入阶段，S1提供的第一扫描信号可以控制T4打开，以便在初始化阶段对N1的电位进行初始化，并便于在数据写入阶段补偿驱动晶体管T0的阈值电压。
如图9所示，E1提供的第一发光控制信号的电位持续为高电压的时间段 需要包含S2提供的第二扫描信号的电位持续为低电压的时间时间段，以保证在数据写入阶段，E1提供的第一发光控制信号能够控制T2关断，保证O1不发光。
在本公开至少一实施例中，在图9所示的时序图中，E2提供的第二发光控制信号的上升沿与S1提供的第一扫描信号的上升沿之间的最短时间间隔可以为第四预定时间间隔，E2提供的第二发光控制信号的上升沿与R1提供的复位控制信号的下降沿之间的最短时间间隔可以为第五预定时间间隔，所述第四预定时间间隔和所述第五预定时间间隔可以大于或等于0.5us而小于或等于1us，但不以此为限；
E1提供的第一发光控制信号的上升沿与S2提供的第二扫描信号的下降沿之间的最短时间间隔可以为第六预定时间间隔，所述第六预定时间间隔可以大于或等于0.5us而小于或等于1us，但不以此为限。
如图10所示，在图4所示的像素电路的至少一实施例的基础上，所述第一发光控制电路14包括第二晶体管T2，所述第二发光控制电路15包括第三晶体管T3；所述控制电路12包括第四晶体管T4；所述第二初始化电路41包括第五晶体管T5；所述第一初始化电路13包括第六晶体管T6，所述补偿控制电路42包括第七晶体管T7，所述数据写入电路43包括第八晶体管T8，所述驱动电路11包括驱动晶体管T0，所述储能电路44包括存储电容C；所述发光元件为有机发光二极管O1；
T2的栅极与第一发光控制线E1电连接，T2的源极与高电压端电连接，T2的漏极与T0的源极电连接；所述高电压端用于提供高电压VDD；
T3的栅极与第二发光控制线E1电连接，T3的源极与T0的漏极电连接，T3的漏极与O1的阳极电连接；
T4的栅极与第一扫描线S1电连接，T4的源极与T0的栅极电连接，T4的漏极与连接节点N0电连接；
T5的栅极与第一发光控制线E1电连接，T5的源极与第二初始电压线电连接，T5的漏极与O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
T6的栅极与复位控制线R1电连接，T6的源极与第一初始电压线电连接， T6的漏极与连接节点N0电连接；所述第一初始电压线用于提供第一初始电压Vi1；
T7的栅极与第二扫描线S2电连接,T7的源极与连接节点N0电连接，T7的漏极与T0的漏极电连接；
T8的栅极与第二扫描线S2电连接，T8的源极与数据线D1电连接，T8的漏极与T0的源极电连接；
C的第一端与T0的栅极电连接，C的第二端与所述高电压端电连接；
O1的阴极与低电压端电连接，所述低电压端用于提供低电压VSS。
在图10所示的像素电路的至少一实施例中，T4和T5为氧化物薄膜晶体管，其他晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
在图10中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点；第一节点N1与T0的栅极电连接，第二节点N2与T0的源极电连接，第三节点N3与T0的漏极电连接。
图10所示的像素电路的至少一实施例与图7所示的像素电路的至少一实施例的区别在于：
T5为氧化物薄膜晶体管，T5的栅极与E1电连接，在E1提供高电压信号时，T5导通，以对O1的阳极的电位进行复位。通常为了解决闪烁问题，需要高频控制信号对O1的阳极的电位进行复位，而E1提供的第一发光控制信号本身就是高频信号，可以省去将控制T5的栅极的信号变为高频信号带来的功耗增加问题。
如图11所示，在图4所示的像素电路的至少一实施例的基础上，所述第一发光控制电路14包括第二晶体管T2，所述第二发光控制电路15包括第三晶体管T3；所述控制电路12包括第四晶体管T4；所述第二初始化电路41包括第五晶体管T5；所述第一初始化电路13包括第六晶体管T6，所述补偿控制电路42包括第七晶体管T7，所述数据写入电路43包括第八晶体管T8，所述驱动电路11包括驱动晶体管T0，所述储能电路44包括存储电容C；所述发光元件为有机发光二极管O1；
T2的栅极与第一发光控制线E1电连接，T2的源极与高电压端电连接，T2的漏极与T0的源极电连接；所述高电压端用于提供高电压VDD；
T3的栅极与第二发光控制线E1电连接，T3的源极与T0的漏极电连接，T3的漏极与O1的阳极电连接；
T4的栅极与第一扫描线S1电连接，T4的源极与T0的栅极电连接，T4的漏极与连接节点N0电连接；
T5的栅极与第二发光控制线E2电连接，T5的源极与第二初始电压线电连接，T5的漏极与O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
T6的栅极与复位控制线R1电连接，T6的源极与第一初始电压线电连接，T6的漏极与连接节点N0电连接；所述第一初始电压线用于提供第一初始电压Vi1；
T7的栅极与第二扫描线S2电连接,T7的源极与连接节点N0电连接，T7的漏极与T0的漏极电连接；
T8的栅极与第二扫描线S2电连接，T8的源极与数据线D1电连接，T8的漏极与T0的源极电连接；
C的第一端与T0的栅极电连接，C的第二端与所述高电压端电连接；
O1的阴极与低电压端电连接，所述低电压端用于提供低电压VSS。
在图10所示的像素电路的至少一实施例中，T4和T5为氧化物薄膜晶体管，其他晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
在图10中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点；第一节点N1与T0的栅极电连接，第二节点N2与T0的源极电连接，第三节点N3与T0的漏极电连接。
图10所示的像素电路的至少一实施例与图7所示的像素电路的至少一实施例的区别在于：
T5为氧化物薄膜晶体管，T5的栅极与E2电连接，在E2提供高电压信号时，T5导通，以对O1的阳极的电位进行复位。通常为了解决闪烁问题，需要高频控制信号对O1的阳极的电位进行复位，而E2提供的第二发光控制信号本身就是高频信号，可以省去将控制T5的栅极的信号变为高频信号带来的功耗增加问题。
如图12所示，在图5所示的像素电路的至少一实施例的基础上，所述复 位电路20包括第一晶体管T1；所述第一发光控制电路14包括第二晶体管T2，所述第二发光控制电路15包括第三晶体管T3；所述控制电路12包括第四晶体管T4；所述第二初始化电路41包括第五晶体管T5；所述第一初始化电路13包括第六晶体管T6，所述补偿控制电路42包括第七晶体管T7，所述数据写入电路43包括第八晶体管T8，所述驱动电路11包括驱动晶体管T0，所述储能电路44包括存储电容C；所述发光元件为有机发光二极管O1；
T1的栅极与复位控制线R1电连接，T1的源极与复位电压线DR电连接，T1的漏极与T0的源极电连接；所述复位电压线DR用于供复位电压；
T2的栅极与发光控制线E0电连接，T2的源极与高电压端电连接，T2的漏极与T0的源极电连接；所述高电压端用于提供高电压VDD；
T3的栅极与发光控制线E0电连接，T3的源极与T0的漏极电连接，T3的漏极与O1的阳极电连接；
T4的栅极与第一扫描线S1电连接，T4的源极与T0的栅极电连接，T4的漏极与连接节点N0电连接；
T5的栅极与第二扫描线S2电连接，T5的源极与第二初始电压线电连接，T5的漏极与O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
T6的栅极与复位控制线R1电连接，T6的源极与第一初始电压端电连接，T6的漏极与连接节点N0电连接；所述第一初始电压端用于提供第一初始电压Vi1；
T7的栅极与第二扫描线S2电连接,T7的源极与连接节点N0电连接，T7的漏极与T0的漏极电连接；
T8的栅极与第二扫描线S2电连接，T8的源极与数据线D1电连接，T8的漏极与T0的源极电连接；
C的第一端与T0的栅极电连接，C的第二端与所述高电压端电连接；
O1的阴极与低电压端电连接，所述低电压端用于提供低电压VSS。
在图12所示的像素电路的至少一实施例中，第一发光控制线和第二发光控制线为同一发光控制线E0。
在图12所示的像素电路的至少一实施例中，T4为氧化物薄膜晶体管， 其他晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
在图12中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点；第一节点N1与T0的栅极电连接，第二节点N2与T0的源极电连接，第三节点N3与T0的漏极电连接。
在本公开所述的像素电路的至少一实施例中，DR提供的复位电压可以为低电压信号，但不以此为限；例如，所述复位电压可以为Vi1、Vi2或VSS；此时复位电压的电压值可以大于或等于-6V而小于或等于-2V；例如，所述复位电压的电压值可以等于-6V、-5V、-4V、-3V或-2V；但不以此为限；
DR提供的复位电压也可以为高电压信号，此时，复位电压的电压值可以大于或等于4V而小于或等于10V；例如，所述复位电压的电压值可以为4V、5V、6V、7V、8V、9V或10V，但不以此为限。
本公开所述的像素电路的至少一实施例在工作时，当在初始化阶段，T0处于关态偏置状态时，所述复位电压的电压值小于最小数据电压值，确保当驱动电路的第一端接入所有数据电压时，都能从更低的电压状态开始工作；
当在初始化阶段，T0处于开态偏置状态时，所述复位电压的电压值大于最大数据电压值，确保当驱动电路的第一端接入所有数据电压时，能从更高的电压状态开始工作。
如图13所示，本公开图12所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3；
在初始化阶段t1，E0提供高电压信号，S1提供高电压信号，R1提供低电压信号，S2提供高电压信号，T6、T4和T1都开启，Vi写入N1，同时复位电压写入N2，T0处于关态偏置状态；
在数据写入阶段t2，E0提供高电压信号，S1提供高电压信号，R1提供高电压信号，S2提供低电压信号，T7、T8和T4打开，D1上的数据电压Vdata写入N2；T5打开，以将Vi2写入O1的阳极，使得O1不发光，并清除O1的阳极残留的电荷；
在数据写入阶段t2开始时，T0打开，以通过Vdata为C充电，改变N1的电位，直至N1的电位变为Vdata+Vth，T0关断；
在发光阶段t3，E0提供低电压信号，S1提供低电压信号，S2提供高电 压信号，R1提供高电压信号，T2、T0和T3打开，T0驱动O1发光。
本公开图12所示的像素电路的至少一实施例在工作时，在初始化阶段t1，T0处于关断状态，确保每个像素电路都是从关态偏置状态开始充电和补偿的，不受上一帧数据电压的影响，可以消除T0的磁滞的影响，改善残像和响应时间。
如图13所示，E0提供的发光控制信号的脉宽需要大于S1提供的第一扫描信号的脉宽，也即，E0提供的发光控制信号的电位持续为高电压的时间段，包含S1提供的第一扫描信号的电位持续为高电压的时间段，保证当T4打开时，T2和T3关断。
如图13所示，S1提供的第一扫描信号的电位持续为高电压的时间段需要包含R1提供的复位控制信号的电位持续为低电压的时间段，以及，S2提供的第二扫描信号的电位持续为低电压的时间段，以保证在进行初始化阶段和数据写入阶段，S1提供的第一扫描信号可以控制T4打开，以便在初始化阶段对N1的电位进行初始化，并便于在数据写入阶段补偿驱动晶体管T0的阈值电压。
如图13所示，E0提供的发光控制信号的电位持续为高电压的时间段需要包含S2提供的第二扫描信号的电位持续为低电压的时间时间段，以保证在数据写入阶段，E0提供的发光控制信号能够控制T2和T3关断，保证O1不发光。
在本公开至少一实施例中，在图13所示的时序图中，E0提供的发光控制信号的上升沿与S1提供的第一扫描信号的上升沿之间的最短时间间隔可以为第七预定时间间隔，E0提供的发光控制信号的上升沿与R1提供的复位控制信号的下降沿之间的最短时间间隔可以为第八预定时间间隔，所述第七预定时间间隔和所述第八预定时间间隔可以大于或等于0.5us而小于或等于1us，但不以此为限。
在本公开如图14、图17、图19所示的像素电路的至少一实施例工作时，也可以将E0提供的发光控制信号、S1提供的第一扫描信号、R1提供的复位控制信号和S2提供的第二扫描信号的时序设置为如上所述。
如图14所示，在图5所示的像素电路的至少一实施例的基础上，所述复 位电路20包括第一晶体管T1；所述第一发光控制电路14包括第二晶体管T2，所述第二发光控制电路15包括第三晶体管T3；所述控制电路12包括第四晶体管T4；所述第二初始化电路41包括第五晶体管T5；所述第一初始化电路13包括第六晶体管T6，所述补偿控制电路42包括第七晶体管T7，所述数据写入电路43包括第八晶体管T8，所述驱动电路11包括驱动晶体管T0，所述储能电路44包括存储电容C；所述发光元件为有机发光二极管O1；
T1的栅极和T1的源极都与复位控制线R1电连接，T1的漏极与T0的源极电连接；
T2的栅极与发光控制线E0电连接，T2的源极与高电压端电连接，T2的漏极与T0的源极电连接；所述高电压端用于提供高电压VDD；
T3的栅极与发光控制线E0电连接，T3的源极与T0的漏极电连接，T3的漏极与O1的阳极电连接；
T4的栅极与第一扫描线S1电连接，T4的源极与T0的栅极电连接，T4的漏极与连接节点N0电连接；
T5的栅极与第二扫描线S2电连接，T5的源极与第二初始电压线电连接，T5的漏极与O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
T6的栅极与复位控制线R1电连接，T6的源极与第一初始电压线电连接，T6的漏极与连接节点N0电连接；所述第一初始电压线用于提供第一初始电压Vi1；
T7的栅极与第二扫描线S2电连接,T7的源极与连接节点N0电连接，T7的漏极与T0的漏极电连接；
T8的栅极与第二扫描线S2电连接，T8的源极与数据线D1电连接，T8的漏极与T0的源极电连接；
C的第一端与T0的栅极电连接，C的第二端与所述高电压端电连接；
O1的阴极与低电压端电连接，所述低电压端用于提供低电压VSS。
在图14所示的像素电路的至少一实施例中，第一发光控制线和第二发光控制线为同一发光控制线E0。
在图14所示的像素电路的至少一实施例中，T4为氧化物薄膜晶体管， 其他晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
在图14中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点；第一节点N1与T0的栅极电连接，第二节点N2与T0的源极电连接，第三节点N3与T0的漏极电连接。
如图15所示，本公开图14所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3；
在初始化阶段t1，E0提供高电压信号，S1提供高电压信号，R1提供低电压信号，S2提供高电压信号，T6、T4和T1都开启，Vi1写入N1，同时低电压信号写入N2，T0处于关态偏置状态；
在数据写入阶段t2，E0提供高电压信号，S1提供高电压信号，R1提供高电压信号，S2提供低电压信号，T7、T8和T4打开，D1上的数据电压Vdata写入N2；T5打开，以将Vi2写入O1的阳极，使得O1不发光，并清除O1的阳极残留的电荷；
在数据写入阶段t2开始时，T0打开，以通过Vdata为C充电，改变N1的电位，直至N1的电位变为Vdata+Vth，T0关断；
在发光阶段t3，E0提供低电压信号，S1提供低电压信号，S2提供高电压信号，R1提供高电压信号，T2、T0和T3打开，T0驱动O1发光。
本公开图14所示的像素电路的至少一实施例在工作时，在初始化阶段t1，T0处于关断状态，确保每个像素电路都是从关态偏置状态开始充电和补偿的，不受上一帧数据电压的影响，可以消除T0的磁滞的影响，改善残像和响应时间。
如图16所示，在图5所示的像素电路的至少一实施例的基础上，所述复位电路20包括第一晶体管T1；所述第一发光控制电路14包括第二晶体管T2，所述第二发光控制电路15包括第三晶体管T3；所述控制电路12包括第四晶体管T4；所述第二初始化电路41包括第五晶体管T5；所述第一初始化电路13包括第六晶体管T6，所述补偿控制电路42包括第七晶体管T7，所述数据写入电路43包括第八晶体管T8，所述驱动电路11包括驱动晶体管T0，所述储能电路44包括存储电容C；所述发光元件为有机发光二极管O1；
T1的栅极与复位控制线R1电连接，T1的源极与复位电压线DR电连接， T1的漏极与T0的源极电连接；所述复位电压线DR用于提供复位电压；
T2的栅极与发光控制线E0电连接，T2的源极与高电压端电连接，T2的漏极与T0的源极电连接；所述高电压端用于提供高电压VDD；
T3的栅极与发光控制线E0电连接，T3的源极与T0的漏极电连接，T3的漏极与O1的阳极电连接；
T4的栅极与第一扫描线S1电连接，T4的源极与T0的栅极电连接，T4的漏极与连接节点N0电连接；
T5的栅极与发光控制线E0电连接，T5的源极与第二初始电压线电连接，T5的漏极与O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
T6的栅极与复位控制线R1电连接，T6的源极与第一初始电压线电连接，T6的漏极与连接节点N0电连接；所述第一初始电压线用于提供第一初始电压Vi1；
T7的栅极与第二扫描线S2电连接,T7的源极与连接节点N0电连接，T7的漏极与T0的漏极电连接；
T8的栅极与第二扫描线S2电连接，T8的源极与数据线D1电连接，T8的漏极与T0的源极电连接；
C的第一端与T0的栅极电连接，C的第二端与所述高电压端电连接；
O1的阴极与低电压端电连接，所述低电压端用于提供低电压VSS。
在图16所示的像素电路的至少一实施例中，第一发光控制线和第二发光控制线为同一发光控制线E0。
在图16所示的像素电路的至少一实施例中，T4和T5为氧化物薄膜晶体管，其他晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
在图16中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点；第一节点N1与T0的栅极电连接，第二节点N2与T0的源极电连接，第三节点N3与T0的漏极电连接。
图16所示的像素电路的至少一实施例与图12所示的像素电路的至少一实施例的区别仅在于：T5为氧化物薄膜晶体管，T5的栅极与发光控制线E0电连接；在E0提供高电压信号时，T5导通，以对O1的阳极的电位进行复位。 通常为了解决闪烁问题，需要高频控制信号对O1的阳极的电位进行复位，而E2提供的第二发光控制信号本身就是高频信号，可以省去将控制T5的栅极的信号变为高频信号带来的功耗增加问题。
如图17所示，在图6所示的像素电路的至少一实施例的基础上，所述复位电路20包括第一晶体管T1；所述第一发光控制电路14包括第二晶体管T2，所述第二发光控制电路15包括第三晶体管T3；所述控制电路12包括第四晶体管T4；所述第二初始化电路41包括第五晶体管T5；所述第一初始化电路13包括第六晶体管T6，所述补偿控制电路42包括第七晶体管T7，所述数据写入电路43包括第八晶体管T8，所述驱动电路11包括驱动晶体管T0，所述储能电路44包括存储电容C；所述发光元件为有机发光二极管O1；
T1的栅极与复位控制线R1电连接，T1的源极与复位电压线DR电连接，T1的漏极与T0的第二极电连接；所述复位电压线DR用于提供复位电压；
T2的栅极与发光控制线E0电连接，T2的源极与高电压端电连接，T2的漏极与T0的第一极电连接；所述高电压端用于提供高电压VDD；
T3的栅极与发光控制线E0电连接，T3的源极与T0的第二极电连接，T3的漏极与O1的阳极电连接；
T4的栅极与第一扫描线S1电连接，T4的源极与T0的栅极电连接，T4的漏极与连接节点N0电连接；
T5的栅极与第二扫描线S2电连接，T5的源极与第二初始电压线电连接，T5的漏极与O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
T6的栅极与复位控制线R1电连接，T6的源极与第一初始电压线电连接，T6的漏极与连接节点N0电连接；所述第一初始电压线用于提供第一初始电压Vi1；
T7的栅极与第二扫描线S2电连接,T7的源极与连接节点N0电连接，T7的漏极与T0的第二极电连接；
T8的栅极与第二扫描线S2电连接，T8的源极与数据线D1电连接，T8的漏极与T0的第一极电连接；
C的第一端与T0的栅极电连接，C的第二端与所述高电压端电连接；
O1的阴极与低电压端电连接，所述低电压端用于提供低电压VSS。
在图17所示的像素电路的至少一实施例中，第一发光控制线和第二发光控制线为同一发光控制线E0。
在图17所示的像素电路的至少一实施例中，T4为氧化物薄膜晶体管，其他晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
在图17中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点；第一节点N1与T0的栅极电连接，第二节点N2与T0的第一极电连接，第三节点N3与T0的第二极电连接。
在图17所示的像素电路的至少一实施例中，DR提供的复位电压可以为低电压信号，但不以此为限；例如，所述复位电压可以为Vi1、Vi2或VSS。
如图18所示，本公开图17所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3；
在初始化阶段t1，E0提供高电压信号，S1提供高电压信号，R1提供低电压信号，S2提供高电压信号，T6、T4和T1都开启，Vi写入N1，同时复位电压写入N3，T0处于关态偏置状态；
在数据写入阶段t2，E0提供高电压信号，S1提供高电压信号，R1提供高电压信号，S2提供低电压信号，T7、T8和T4打开，D1上的数据电压Vdata写入N2；T5打开，以将Vi2写入O1的阳极，使得O1不发光，并清除O1的阳极残留的电荷；
在数据写入阶段t2开始时，T0打开，以通过Vdata为C充电，改变N1的电位，直至N1的电位变为Vdata+Vth，T0关断；
在发光阶段t3，E0提供低电压信号，S1提供低电压信号，S2提供高电压信号，R1提供高电压信号，T2、T0和T3打开，T0驱动O1发光。
本公开图17所示的像素电路的至少一实施例在工作时，在初始化阶段t1，T0处于关断状态，确保每个像素电路都是从关态偏置状态开始充电和补偿的，不受上一帧数据电压的影响，可以消除T0的磁滞的影响，改善残像和响应时间。
如图19所示，在图6所示的像素电路的至少一实施例的基础上，所述复位电路20包括第一晶体管T1；所述第一发光控制电路14包括第二晶体管 T2，所述第二发光控制电路15包括第三晶体管T3；所述控制电路12包括第四晶体管T4；所述第二初始化电路41包括第五晶体管T5；所述第一初始化电路13包括第六晶体管T6，所述补偿控制电路42包括第七晶体管T7，所述数据写入电路43包括第八晶体管T8，所述驱动电路11包括驱动晶体管T0，所述储能电路44包括存储电容C；所述发光元件为有机发光二极管O1；
T1的栅极与T1的源极都与复位控制线R1电连接，T1的漏极与T0的第二极电连接；
T2的栅极与发光控制线E0电连接，T2的源极与高电压端电连接，T2的漏极与T0的第一极电连接；所述高电压端用于提供高电压VDD；
T3的栅极与发光控制线E0电连接，T3的源极与T0的第二极电连接，T3的漏极与O1的阳极电连接；
T4的栅极与第一扫描线S1电连接，T4的源极与T0的栅极电连接，T4的漏极与连接节点N0电连接；
T5的栅极与第二扫描线S2电连接，T5的源极与第二初始电压线电连接，T5的漏极与O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
T6的栅极与复位控制线R1电连接，T6的源极与第一初始电压线电连接，T6的漏极与连接节点N0电连接；所述第一初始电压线用于提供第一初始电压Vi1；
T7的栅极与第二扫描线S2电连接,T7的源极与连接节点N0电连接，T7的漏极与T0的第二极电连接；
T8的栅极与第二扫描线S2电连接，T8的源极与数据线D1电连接，T8的漏极与T0的第一极电连接；
C的第一端与T0的栅极电连接，C的第二端与所述高电压端电连接；
O1的阴极与低电压端电连接，所述低电压端用于提供低电压VSS。
在图19所示的像素电路的至少一实施例中，第一发光控制线和第二发光控制线为同一发光控制线E0。
在图19所示的像素电路的至少一实施例中，T4为氧化物薄膜晶体管，其他晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
在图19中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点；第一节点N1与T0的栅极电连接，第二节点N2与T0的源极电连接，第三节点N3与T0的第二极电连接。
在图19所示的像素电路的至少一实施例中，DR提供的复位电压可以为低电压信号，但不以此为限；例如，所述复位电压可以为Vi1、Vi2或VSS。
如图20所示，本公开图19所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3；
在初始化阶段t1，E0提供高电压信号，S1提供高电压信号，R1提供低电压信号，S2提供高电压信号，T6、T4和T1都开启，Vi1写入N1，同时低电压信号写入N3，T0处于关态偏置状态；
在数据写入阶段t2，E0提供高电压信号，S1提供高电压信号，R1提供高电压信号，S2提供低电压信号，T7、T8和T4打开，D1上的数据电压Vdata写入N2；T5打开，以将Vi2写入O1的阳极，使得O1不发光，并清除O1的阳极残留的电荷；
在数据写入阶段t2开始时，T0打开，以通过Vdata为C充电，改变N1的电位，直至N1的电位变为Vdata+Vth，T0关断；
在发光阶段t3，E0提供低电压信号，S1提供低电压信号，S2提供高电压信号，R1提供高电压信号，T2、T0和T3打开，T0驱动O1发光。
本公开图19所示的像素电路的至少一实施例在工作时，在初始化阶段t1，T0处于关断状态，确保每个像素电路都是从关态偏置状态开始充电和补偿的，不受上一帧数据电压的影响，可以消除T0的磁滞的影响，改善残像和响应时间。
如图21所示，在图6所示的像素电路的至少一实施例的基础上，所述复位电路20包括第一晶体管T1；所述第一发光控制电路14包括第二晶体管T2，所述第二发光控制电路15包括第三晶体管T3；所述控制电路12包括第四晶体管T4；所述第二初始化电路41包括第五晶体管T5；所述第一初始化电路13包括第六晶体管T6，所述补偿控制电路42包括第七晶体管T7，所述数据写入电路43包括第八晶体管T8，所述驱动电路11包括驱动晶体管T0，所述储能电路44包括存储电容C；所述发光元件为有机发光二极管O1；
T1的栅极与复位控制线R1电连接，T1的源极与复位电压线DR电连接，T1的漏极与T0的第二极电连接；所述复位电压线DR用于提供复位电压；
T2的栅极与发光控制线E0电连接，T2的源极与高电压端电连接，T2的漏极与T0的第一极电连接；所述高电压端用于提供高电压VDD；
T3的栅极与发光控制线E0电连接，T3的源极与T0的第二极电连接，T3的漏极与O1的阳极电连接；
T4的栅极与第一扫描线S1电连接，T4的源极与T0的栅极电连接，T4的漏极与连接节点N0电连接；
T5的栅极与发光控制线E0电连接，T5的源极与第二初始电压线电连接，T5的漏极与O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
T6的栅极与复位控制线R1电连接，T6的源极与第一初始电压线电连接，T6的漏极与连接节点N0电连接；所述第一初始电压线用于提供第一初始电压Vi1；
T7的栅极与第二扫描线S2电连接,T7的源极与连接节点N0电连接，T7的漏极与T0的第二极电连接；
T8的栅极与第二扫描线S2电连接，T8的源极与数据线D1电连接，T8的漏极与T0的第一极电连接；
C的第一端与T0的栅极电连接，C的第二端与所述高电压端电连接；
O1的阴极与低电压端电连接，所述低电压端用于提供低电压VSS。
在图21所示的像素电路的至少一实施例中，第一发光控制线和第二发光控制线为同一发光控制线E0。
在图21所示的像素电路的至少一实施例中，T4和T5为氧化物薄膜晶体管，其他晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
在图21中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点；第一节点N1与T0的栅极电连接，第二节点N2与T0的第一极电连接，第三节点N3与T0的第二极电连接。
在图21所示的像素电路的至少一实施例中，DR提供的复位电压可以为低电压信号，但不以此为限；例如，所述复位电压可以为Vi1、Vi2或VSS。
图21所示的像素电路的至少一实施例与图17所示的像素电路的至少一实施例的区别仅在于：T5为氧化物薄膜晶体管，T5的栅极与发光控制线E0电连接；在E0提供高电压信号时，T5导通，以对O1的阳极的电位进行复位。通常为了解决闪烁问题，需要高频控制信号对O1的阳极的电位进行复位，而E2提供的第二发光控制信号本身就是高频信号，可以省去将控制T5的栅极的信号变为高频信号带来的功耗增加问题。
如图22所示，为本公开至少一实施例所述的显示装置中的像素电路的分布图。该显示装置可以包括多个阵列分布的像素电路P、第一高电压线VDD11、第二高电压线VDD12、第三高电压线VDD21和第四高电压线VDD22。VDD11、VDD12、VDD21、VDD22均可以用于提供高电压。如图22所示，VDD11、VDD12沿列方向延伸，VDD21、VDD22沿行方向延伸，相邻两行像素电路可以与同一行向延伸的高电压线连接，该高电压线可以位于上述相邻两行像素电路之间，沿列方向延伸的高电压线可以连接与其相交的多条沿行方向延伸的高电压线相交，从而多条高电压线可以形成网格结构。其中，沿列方向延伸的高电压线可以位于红色像素驱动电路所在的区域内。此外，在同一像素行中，相邻列的两个像素电路可以镜像设置，以方便布线。
本公开至少一实施例所述的驱动方法，应用于上述的像素电路，显示周期包括初始化阶段；所述驱动方法包括：
在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第一初始电压写入连接节点，控制电路在所述第一扫描信号的控制下，控制驱动电路的控制端与所述连接节点电连接，以将第一初始电压写入所述驱动电路的控制端，并控制在所述初始化阶段结束时，所述驱动电路中的驱动晶体管处于预定偏置状态。
可选的，所述预定偏置状态可以为开态偏置状态或关态偏置状态。
在本公开至少一实施例所述的驱动方法中，在数据电压写入驱动电路的第一端之前，在初始化阶段，控制电路和第一初始化电路配合将第一初始电压写入驱动电路的控制端，并控制在初始化阶段结束时，所述驱动电路中的驱动晶体管处于预定偏置状态，以能够改善所述驱动晶体管的磁滞现象。
在本公开至少一实施例中，所述预定偏置状态可以为关态偏置状态，所 述驱动方法还可以包括：
在所述初始化阶段，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通；
在所述初始化阶段开始时，驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以改变所述驱动电路的第一端的电位，直至驱动电路包括的驱动晶体管关断，所述驱动晶体管处于关态偏置状态。
在本公开至少一实施例所述的驱动方法中，在数据电压写入驱动电路的第一端之前，在初始化阶段，控制电路和第一初始化电路配合将第一初始电压写入驱动电路的控制端，所述第二发光控制电路对驱动电路包括的驱动晶体管的源极的电位进行初始化，以使得在初始化阶段结束时，所述驱动晶体管处于关态偏置状态，确保每个像素电路中的驱动晶体管都是从关态偏置状态开始充电和补偿的，而不受上一帧数据电压的影响，以能够改善所述驱动晶体管的磁滞现象。
在本公开至少一实施例中，所述预定偏置状态可以为开态偏置状态，所述驱动方法还可以包括：
在所述初始化阶段，第一发光控制电路在第一发光控制信号的控制下，控制所述驱动电路的第一端与第一电压端之间连通，以使得所述驱动电路中的驱动晶体管处于开态偏置状态。
在本公开至少一实施例所述的驱动方法中，在数据电压写入驱动电路的第一端之前，在初始化阶段，控制电路和第一初始化电路配合将第一初始电压写入驱动电路的控制端，所述第一发光控制电路控制所述驱动电路的第一端与第一电压端之间连通，以使得所述驱动电路中的驱动晶体管处于开态偏置状态，确保每个像素电路中的驱动晶体管都是从开态偏置状态开始充电和补偿的，而不受上一帧数据电压的影响，以能够改善所述驱动晶体管的磁滞现象。
可选的，所述像素电路还包括数据写入电路，所述显示周期还包括设置于所述初始化阶段之后的数据写入阶段；所述驱动方法还包括：
在所述数据写入阶段，数据写入电路在第二扫描线的控制下，将数据线 上的数据电压写入所述驱动电路的第一端。
可选的，所述像素电路还包括第二初始化电路；所述驱动方法还包括：
所述第二初始化电路在初始控制信号的控制下，将第二初始电压写入所述发光元件的第一极，以控制发光元件不发光，并清除所述发光元件的第一极残留的电荷。
本公开至少一实施例所述的驱动方法，应用于上述的像素电路，所述像素电路还包括复位电路；第一发光控制线和第二发光控制线为相同的发光控制线；显示周期包括初始化阶段；
所述驱动方法包括：
在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第一初始电压写入连接节点，控制电路在所述第一扫描信号的控制下，控制驱动电路的控制端与所述连接节点电连接，以将第一初始电压写入所述驱动电路的控制端；所述复位电路在复位控制信号的控制下，对所述驱动电路的第一端的电位或所述驱动电路的第二端的电位进行初始化。
在本公开实施例所述的驱动方法中，在数据电压写入驱动电路的第一端之前，在初始化阶段，控制电路和第一初始化电路配合将第一初始电压写入驱动电路的控制端，复位电路在复位控制信号的控制下，对所述驱动电路的第一端的电位或所述驱动电路的第二端的电位进行初始化，以能够改善所述驱动晶体管的磁滞现象。
可选的，所述像素电路还包括数据写入电路，所述显示周期还包括设置于所述初始化阶段之后的数据写入阶段；所述驱动方法还包括：
在所述数据写入阶段，数据写入电路在第二扫描线的控制下，将数据线上的数据电压写入所述驱动电路的第一端。
可选的，所述像素电路还包括第二初始化电路；所述驱动方法还包括：
所述第二初始化电路在初始控制信号的控制下，将第二初始电压写入所述发光元件的第一极，以控制发光元件不发光，并清除所述发光元件的第一极残留的电荷。
本公开实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示 器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种像素电路，包括发光元件、驱动电路、控制电路、第一初始化电路、第一发光控制电路和第二发光控制电路，其中，
    所述控制电路分别与第一扫描线、所述驱动电路的控制端和连接节点电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述驱动电路的控制端与所述连接节点电连接；
    所述第一初始化电路分别与复位控制线、所述连接节点和第一初始电压线电连接，用于在所述复位控制线提供的复位控制信号的控制下，将第一初始电压线提供的第一初始电压写入所述连接节点；
    所述第一发光控制电路分别与第一发光控制线、第一电压端和所述驱动电路的第一端电连接，用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通；
    所述第二发光控制电路分别与第二发光控制线、所述驱动电路的第二端和发光元件的第一极电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
    所述驱动电路用于在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通。
  2. 如权利要求1所述的像素电路，其中，还包括复位电路；
    所述复位电路分别与复位控制线和所述驱动电路的第一端电连接，用于在所述复位控制信号的控制下，对所述驱动电路的第一端的电位进行初始化；或者，
    所述复位电路分别与复位控制线和所述驱动电路的第二端电连接，用于在所述复位控制信号的控制下，对所述驱动电路的第二端的电位进行初始化。
  3. 如权利要求2所述的像素电路，其中，所述复位电路包括第一晶体管；
    所述第一晶体管的控制极与所述复位控制线电连接，所述第一晶体管的第一极与复位电压线电连接，所述第一晶体管的第二极与所述驱动电路的第一端或所述驱动电路的第二端电连接；所述复位电压线用于提供复位电压。
  4. 如权利要求2所述的像素电路，其中，所述复位电路包括第一晶体管；
    所述第一晶体管的控制极和所述第一晶体管的第一极与所述复位控制线电连接，所述第一晶体管的第二极与所述驱动电路的第一端或所述驱动电路的第二端电连接。
  5. 如权利要求1所述的像素电路，其中，所述第一发光控制电路包括第二晶体管，所述第二发光控制电路包括第三晶体管；
    所述第二晶体管的控制极与所述第一发光控制线电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接；
    所述第三晶体管的控制极与所述第二发光控制线电连接，所述第三晶体管的第一极与所述驱动电路的第二端电连接，所述第三晶体管的第二极与所述发光元件的第一极电连接。
  6. 如权利要求1至5中任一权利要求所述的像素电路，其中，所述第一发光控制线与所述第二发光控制线为不同的发光控制线；或者，
    所述第一发光控制线与所述第二发光控制线为相同的发光控制线。
  7. 如权利要求1至5中任一权利要求所述的像素电路，其中，所述控制电路包括第四晶体管；
    所述第四晶体管的控制极与所述第一扫描线电连接，所述第四晶体管的第一极与所述驱动电路的控制端电连接，所述第四晶体管的第二极与所述连接节点电连接；
    所述第四晶体管为氧化物薄膜晶体管。
  8. 如权利要求1至5中任一权利要求所述的像素电路，其中，还包括第二初始化电路；
    所述第二初始化电路分别与初始控制线、第二初始电压线和发光元件的第一极电连接，用于在初始控制线提供的初始控制信号的控制下，将第二初始电压线提供的第二初始电压写入所述发光元件的第一极。
  9. 如权利要求8所述的像素电路，其中，所述第二初始化电路包括第五晶体管；
    所述第五晶体管的控制极与所述初始控制线电连接，所述第五晶体管的 第一极与所述第二初始电压线电连接，所述第五晶体管的第二极与所述发光元件的第一极电连接；
    所述第五晶体管为氧化物薄膜晶体管；所述初始控制线为所述第一发光控制线或所述第二发光控制线。
  10. 如权利要求1至5中任一权利要求所述的像素电路，其中，还包括补偿控制电路、数据写入电路和储能电路；
    所述补偿控制电路分别与第二扫描线、所述连接节点和所述驱动电路的第二端电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，控制所述连接节点和所述驱动电路的第二端之间连通；
    所述数据写入电路分别与第二扫描线、数据线和所述驱动电路的第一端电连接，用于在所述第二扫描信号的控制下，将数据线上的数据电压写入所述驱动电路的第一端；
    所述储能电路与所述驱动电路的控制端电连接，用于储存电能。
  11. 如权利要求10所述的像素电路，其中，所述第一初始化电路包括第六晶体管，所述补偿控制电路包括第七晶体管，所述数据写入电路包括第八晶体管，所述驱动电路包括驱动晶体管，所述储能电路包括存储电容；
    所述第六晶体管的控制极与所述复位控制线电连接，所述第六晶体管的第一极与第一初始电压线电连接，所述第六晶体管的第二极与所述连接节点电连接；
    所述第七晶体管的控制极与所述第二扫描线电连接，所述第七晶体管的第一极与所述连接节点电连接，所述第七晶体管的第二极与所述驱动晶体管的第二极电连接；
    所述第八晶体管的控制极与所述第二扫描线电连接，所述第八晶体管的第一极与所述数据线电连接，所述第八晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述存储电容的第一端与所述驱动晶体管的控制极电连接，所述存储电容的第二端与所述第一电压端电连接。
  12. 一种驱动方法，应用于如权利要求1至11中任一权利要求所述的像素电路，显示周期包括初始化阶段；所述驱动方法包括：
    在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第一初始电压写入连接节点，控制电路在所述第一扫描信号的控制下，控制驱动电路的控制端与所述连接节点电连接，以将第一初始电压写入所述驱动电路的控制端，并使得在所述初始化阶段结束时，所述驱动电路中的驱动晶体管处于预定偏置状态。
  13. 如权利要求12所述的驱动方法，其中，所述预定偏置状态为关态偏置状态；所述驱动方法还包括：
    在所述初始化阶段，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通；
    在所述初始化阶段开始时，驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以改变所述驱动电路的第一端的电位，直至驱动电路包括的驱动晶体管关断，所述驱动晶体管处于关态偏置状态。
  14. 如权利要求12所述的驱动方法，其中，所述预定偏置状态为所述驱动方法还包括：
    在所述初始化阶段，第一发光控制电路在第一发光控制信号的控制下，控制所述驱动电路的第一端与第一电压端之间连通，以使得所述驱动电路中的驱动晶体管处于开态偏置状态。
  15. 如权利要求13或14所述的驱动方法，其中，所述像素电路还包括数据写入电路，所述显示周期还包括设置于所述初始化阶段之后的数据写入阶段；所述驱动方法还包括：
    在所述数据写入阶段，数据写入电路在第二扫描线的控制下，将数据线上的数据电压写入所述驱动电路的第一端。
  16. 如权利要求13或14所述的驱动方法，其中，所述像素电路还包括第二初始化电路；所述驱动方法还包括：
    所述第二初始化电路在初始控制信号的控制下，将第二初始电压写入所述发光元件的第一极，以控制发光元件不发光。
  17. 一种驱动方法，应用于如权利要求1至11中任一权利要求所述的像素电路，所述像素电路还包括复位电路；第一发光控制线和第二发光控制线 为相同的发光控制线；显示周期包括初始化阶段；
    所述驱动方法包括：
    在所述初始化阶段，第一初始化电路在复位控制信号的控制下，将第一初始电压写入连接节点，控制电路在所述第一扫描信号的控制下，控制驱动电路的控制端与所述连接节点电连接，以将第一初始电压写入所述驱动电路的控制端；所述复位电路在复位控制信号的控制下，对所述驱动电路的第一端的电位或所述驱动电路的第二端的电位进行初始化。
  18. 如权利要求17所述的驱动方法，其中，所述像素电路还包括数据写入电路，所述显示周期还包括设置于所述初始化阶段之后的数据写入阶段；所述驱动方法还包括：
    在所述数据写入阶段，数据写入电路在第二扫描线的控制下，将数据线上的数据电压写入所述驱动电路的第一端。
  19. 如权利要求17所述的驱动方法，其中，所述像素电路还包括第二初始化电路；所述驱动方法还包括：
    所述第二初始化电路在初始控制信号的控制下，将第二初始电压写入所述发光元件的第一极，以控制发光元件不发光。
  20. 一种显示装置，包括如权利要求1至11中任一权利要求所述的像素电路。
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