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WO2023005695A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2023005695A1
WO2023005695A1 PCT/CN2022/106020 CN2022106020W WO2023005695A1 WO 2023005695 A1 WO2023005695 A1 WO 2023005695A1 CN 2022106020 W CN2022106020 W CN 2022106020W WO 2023005695 A1 WO2023005695 A1 WO 2023005695A1
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WO
WIPO (PCT)
Prior art keywords
circuit
transistor
reset
terminal
light emission
Prior art date
Application number
PCT/CN2022/106020
Other languages
English (en)
French (fr)
Inventor
袁长龙
曹席磊
朱莉
王本莲
张振华
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/278,552 priority Critical patent/US12322335B2/en
Publication of WO2023005695A1 publication Critical patent/WO2023005695A1/zh

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Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display panel.
  • Organic light emitting diode Organic Light Emitting Diode, OLED
  • OLED Organic Light Emitting Diode
  • Pixel circuits in OLED display devices generally adopt a matrix driving method, which is divided into active matrix (Active Matrix, AM) driving and passive matrix (Passive Matrix, PM) driving according to whether switching components are introduced into each pixel unit.
  • PMOLED has a simple process and low cost, it cannot meet the needs of high-resolution and large-size displays due to shortcomings such as crosstalk, high power consumption, and low lifespan.
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. Through the driving control of the thin film transistors and storage capacitors, the control of the current flowing through the OLED is realized, so that the OLED glow.
  • AMOLED Compared with PMOLED, AMOLED requires less driving current, lower power consumption, and longer life, which can meet the needs of large-size display with high resolution and multiple gray scales. At the same time, AMOLED has obvious advantages in terms of viewing angle, color reproduction, power consumption, and response time, and is suitable for display devices with high information content and high resolution.
  • At least one embodiment of the present disclosure provides a pixel circuit, including: a drive circuit, a data writing circuit, a compensation storage circuit, a first light emission control circuit, and a second light emission control circuit;
  • the drive circuit includes a control terminal, a first terminal and The second terminal is configured to control the driving current flowing through the first terminal and the second terminal for driving the light emitting element to emit light;
  • the data writing circuit is connected with the first terminal and the second terminal of the driving circuit
  • a scanning signal line is connected and configured to write a data signal into the first end of the driving circuit in response to the first scanning signal provided by the first scanning signal line;
  • the control of the compensation storage circuit and the driving circuit connected to the second terminal and the second terminal and connected to the second scanning signal line and the first power supply line, and configured to store the data written by the data writing circuit in response to the second scanning signal provided by the second scanning signal line.
  • the first lighting control circuit is connected to the first end of the driving circuit, the first power supply line and the first scanning signal line, and is configured to respond to the The first scanning signal provided by the first scanning signal line applies the first voltage of the first power supply line to the first end of the driving circuit, wherein the data writing circuit and the first light emitting Under the control of the first scan signal, the control circuit is turned on and repelled;
  • the second light emission control circuit is connected to the second end of the driving circuit, the light emission control signal line and the first end of the light emitting element, And configured to apply the drive current to the light emitting element in response to a light emission control signal provided by the light emission control signal line.
  • the drive circuit includes a drive transistor; the gate of the drive transistor serves as the control terminal of the drive circuit, and the first pole of the drive transistor serves as the The first terminal of the driving circuit, the second pole of the driving transistor serves as the second terminal of the driving circuit.
  • the data writing circuit includes a data writing transistor; the gate of the data writing transistor is connected to the first scanning signal line to receive the first scanning signal line.
  • a scan signal, the first pole of the data writing transistor is connected to the data line to receive the data signal, and the second pole of the data writing transistor is connected to the first terminal of the driving circuit.
  • the first light emission control circuit includes a first light emission control transistor; the gate of the first light emission control transistor is connected to the first scanning signal line to receive For the first scanning signal, the first electrode of the first light emission control transistor is connected to the first power line to receive the first voltage, and the second electrode of the first light emission control transistor is connected to the drive circuit The first end connection.
  • the type of the data write transistor is different from the type of the first light emission control transistor.
  • the first light emission control transistor is an N-type transistor
  • the data writing transistor is a P-type transistor
  • the gate of the first light emission control transistor includes a first sub-gate and a second sub-gate located in different layers, and the gate of the first light emission control transistor The active layer is located between the first sub-gate and the second sub-gate, and the layer where the first sub-gate is located is located between the layer where the gate of the data writing transistor is located and the second sub-gate.
  • the first sub-gate and the second sub-gate of the first light emission control transistor and the gate of the data writing transistor are respectively connected to the first scanning signal line through connecting electrodes, so
  • the layer where the connection electrode is located is located on a side of the layer where the second sub-gate is located away from the layer where the first sub-gate is located and the layer where the gate of the data writing transistor is located.
  • the compensation storage circuit includes a compensation transistor and a storage capacitor; the gate of the compensation transistor is connected to the second scan signal line to receive the second scan signal, the first pole of the compensation transistor is connected to the second terminal of the driving circuit, and the second pole of the compensation transistor is connected to the control terminal of the driving circuit;
  • the first pole of the storage capacitor is connected to the control terminal of the drive circuit, and the second pole of the storage capacitor is connected to the first power line.
  • the first scan signal line and the second scan signal line are the same or different, and the first scan signal and the second scan signal are the same or different .
  • the type of the data writing transistor is different from the type of the compensation transistor, so The type of the compensation transistor is the same as that of the first light emission control transistor.
  • the pixel circuit provided in at least one embodiment of the present disclosure further includes a reset circuit, the reset circuit is connected to the initial voltage terminal, the first terminal of the light-emitting element, and the control terminal of the driving circuit, and is configured to respond to The reset signal applies the reset voltage provided by the initial voltage terminal to the first terminal of the light emitting element and the control terminal of the driving circuit.
  • the reset circuit includes a first reset transistor and a second reset transistor; the gate of the first reset transistor is connected to the first reset signal line to receive the first A reset signal is used as the reset signal, the first pole of the first reset transistor is connected to the initial voltage terminal to receive the reset voltage, the second pole of the first reset transistor is connected to the control terminal of the driving circuit connected; the gate of the second reset transistor is connected to the second reset signal line to receive the second reset signal as the reset signal, and the first pole of the second reset transistor is connected to the initial voltage terminal to receive the The reset voltage, the second pole of the second reset transistor is connected to the first end of the light emitting element.
  • the first reset signal line and the second reset signal line are the same or different, and the first reset signal and the second reset signal are the same or different .
  • the second light emission control circuit includes a second light emission control transistor
  • the gate of the second light emission control transistor is connected to the light emission control line to receive the light emission control signal
  • the first pole of the second light emission control transistor is connected to the second terminal of the driving circuit
  • the first electrode of the second light emission control transistor is connected to the second terminal of the driving circuit.
  • the second poles of the two light-emitting control transistors are connected to the first end of the light-emitting element.
  • At least one embodiment of the present disclosure also provides a driving method for a pixel circuit, including: a reset phase, a data writing and compensation phase, and a light emitting phase; Scanning the first level of the signal to turn on the first light emitting control circuit, applying the first voltage to the first end of the driving circuit through the turned on first light emitting control circuit;
  • the second level of the first scan signal is input through the first scan signal line to turn on the data writing circuit, and the second scan signal is input through the second scan signal line to Turn on the compensation storage circuit, input the data signal through the data line, write the data signal into the first end of the driving circuit through the turned on data writing circuit to turn on the driving circuit, and turn on the driving circuit through the turned on
  • the compensation storage circuit stores the data signal, and compensates the driving circuit through the turned-on compensation storage circuit; in the light-emitting phase, the first scanning signal is input through the first scanning signal line to Turn on the first light emission control circuit and the driving circuit, input the light emission control signal through the light emission control signal
  • the pixel circuit further includes a reset circuit connected to the initial voltage terminal, the first terminal of the light-emitting element and the control terminal of the driving circuit , and configured to apply a reset voltage to the first terminal of the light emitting element and the control terminal of the driving circuit in response to a reset signal; the method further includes: in the reset phase, inputting the reset signal to turn on the The reset circuit, the reset voltage is applied to the first end of the light emitting element and the control end of the driving circuit through the turned on reset circuit.
  • At least one embodiment of the present disclosure further provides a display panel, including the pixel circuit provided by any embodiment of the present disclosure.
  • FIG. 1A is a schematic diagram of an image 1 displayed by a display device
  • FIG. 1B is a schematic diagram of an image 2 to be displayed by the display device
  • FIG. 1C is a schematic diagram of an image 2 actually displayed by the display device
  • Fig. 2 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic block diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • 4A, 5A, 6A, and 7A are circuit diagrams of a specific implementation example of the pixel circuit shown in FIG. 3 ;
  • 4B, 5B, 6B, and 7B are timing diagrams of driving methods of the pixel circuits shown in FIGS. 4A, 5A, 6A, and 7A, respectively;
  • FIG. 8A to 8C are circuit schematic diagrams of the pixel circuit shown in FIG. 4A corresponding to the three stages in FIG. 4B;
  • 9A is a cross-sectional view of the first light emission control transistor, the driving transistor and the second light emission control transistor in the pixel circuit shown in FIG. 4A;
  • 9B to 9I are cross-sectional views of the first light emission control transistor, the data writing transistor and the compensation transistor in the pixel circuit shown in FIG. 4A;
  • FIG. 10 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • the compensation memory circuit is used to compensate for threshold voltage variations (or deviations) of drive transistors included in pixels of an AMOLED display.
  • the compensation memory circuit is used to display images, due to hysteresis, the response speed of pixels varies according to the increase/decrease of the data voltage applied to the driving transistor, making it difficult to correctly display gray scales.
  • driving an AMOLED display to express brightness from black to white there is a delay in response speed, and when text is scrolled on the screen, this problem causes sticking, ie, an afterimage.
  • Figure 1A is a schematic diagram of image 1 displayed by a display device
  • Figure 1B is a schematic diagram of image 2 to be displayed by the display device
  • Figure 1C is a schematic diagram of image 2 actually displayed by the display device .
  • the display device displays an image such as a black and white checkerboard image as shown in Figure 1A for a period of time
  • a new image 2 such as an image with a gray scale of 48 as shown in Figure 1B
  • the Part of the checkerboard image of Image 1 shown in Figure 1A remains, as shown in Figure 1C.
  • a black-and-white grid image (as shown in Figure 1A) is displayed on the OLED for a short time (eg, 10s), and then the residual image phenomenon is observed in the grayscale image (such as the 48-level grayscale image shown in Figure 1C) , after a few seconds or minutes, the residual image shown in Figure 1C fades out of sight and appears as the image shown in Figure 1B.
  • a short time eg, 10s
  • the residual image phenomenon is observed in the grayscale image (such as the 48-level grayscale image shown in Figure 1C)
  • the residual image shown in Figure 1C fades out of sight and appears as the image shown in Figure 1B.
  • the cause of the afterimage phenomenon has been proved to be related to the hysteresis characteristics of the driving transistor in the pixel circuit. Due to the hysteresis effect of the drive transistor, when a display device displays the same image for a period of time, when the previous display image is switched to the next image, the original previous display image will partially remain and appear in the next image for a period of time. After the afterimage disappears, this phenomenon is called short-term afterimage.
  • the hysteresis effect is mainly caused by the threshold voltage (Vth) shift caused by the residual mobile ions in the driving transistor.
  • the V GS (the voltage between the gate and the source of the drive transistor) in the initialization phase (that is, the reset phase) may be different when different screens are switched, so it may cause different degrees of threshold voltage shift of the drive transistor, resulting in short-term afterimage.
  • a separate transistor and corresponding gate scanning signal are usually added to control the source voltage of the driving transistor, so as to keep the source voltage of the driving transistor at a stable potential during the initialization stage, thereby driving the
  • the gate voltage Vg and source voltage Vs of the transistor are reset at the same time, so that the drive transistor is in the On-Bias state, so no matter whether the data voltage of the image displayed in the previous frame is black or white, the drive transistor starts to process data from the On-Bias state Writing and compensation, so it can improve the problem of short-term afterimage.
  • this solution to the afterimage problem needs to introduce additional transistors and signals, which is not conducive to the realization and layout of the pixel circuit.
  • At least one embodiment of the present disclosure provides a pixel circuit, including a driving circuit, a data writing circuit, a compensation storage circuit, a first light emission control circuit and a second light emission control circuit.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control the driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light; the data writing circuit and the first terminal and the second terminal of the driving circuit
  • a scanning signal line is connected and configured to write a data signal into the first terminal of the driving circuit in response to the first scanning signal provided by the first scanning signal line;
  • the compensation storage circuit is connected to the control terminal and the second terminal of the driving circuit and is connected to the The second scanning signal line is connected to the first power supply line, and configured to store the data signal written by the data writing circuit in response to the second scanning signal provided by the second scanning signal line and compensate the driving circuit; the first lighting control circuit connected to the first end of the driving circuit, the first power supply line and the first scanning signal line,
  • At least one embodiment of the present disclosure further provides a driving method and a display panel corresponding to the above pixel circuit.
  • the pixel circuit provided by at least one embodiment of the present disclosure can solve the afterimage problem without adding transistors and control signal lines, which is beneficial to the realization and layout of the pixel circuit and the promotion of products.
  • an example of an embodiment of the present disclosure provides a pixel circuit 10 , for example, the pixel circuit 10 is used for a sub-pixel of an OLED display device.
  • the pixel circuit 10 includes a driving circuit 100 , a data writing circuit 200 , a compensation storage circuit 300 , a first light emission control circuit 400 , and a second light emission control circuit 600 .
  • the pixel circuit 10 is used to drive the light emitting element 500 to emit light.
  • the driving circuit 100 includes a first terminal 110, a second terminal 120 and a control terminal 130 configured to control the driving current for driving the light-emitting element 500 to emit light, and the control terminal 130 of the driving circuit 100 is connected to the first node N1, and the driving circuit The first terminal 110 of the driving circuit 100 is connected to the second node N2, and the second terminal 120 of the driving circuit 100 is connected to the third node N3.
  • the driving circuit 100 can provide a driving current to the light-emitting element 500 to drive the light-emitting element 500 to emit light, and can emit light according to the required "gray scale".
  • the light emitting element 500 may adopt OLED and be configured to be connected to the third node N3 and the second power line VSS (for example, providing a low level, such as ground).
  • Embodiments of the present disclosure include but are not limited to this situation.
  • the light emitting element 500 can be connected to the third node N3 through the second light emission control circuit 600, so that the light emitting element 500 can be avoided.
  • the non-luminous stage current flows to emit light.
  • Embodiments of the present disclosure include, but are not limited to, this scenario.
  • the data writing circuit 200 is connected to the first terminal 110 (second node N2) of the driving circuit 100 and the first scanning signal line G1, and is configured to write the data in response to the first scanning signal provided by the first scanning signal line G1.
  • the signal is written into the first end 110 of the driving circuit 100 .
  • the data writing circuit 200 is connected to the data signal terminal Vdata (for example, as shown in FIG. 4A , the data signal terminal Vdata is connected to the data line DL), the second node N2 and the first scanning signal line G1.
  • the first scan signal from the first scan signal line G1 is applied to the data writing circuit 200 to control whether the data writing circuit 200 is turned on or not.
  • the data writing circuit 200 can be turned on in response to the first scanning signal, so that the data signal can be written into the first terminal 110 (the second node N2) of the driving circuit 100, and the data signal can be stored
  • a driving current for driving the light emitting element 500 to emit light can be generated according to the data signal during, for example, the light emitting phase.
  • the compensation storage circuit 300 is connected to the control terminal 130 (the first node N1) and the second terminal 120 (the third node N3) of the drive circuit, and is connected to the second scanning signal line G2 and the first power supply line VDD, configured to respond to The second scanning signal provided on the second scanning line G2 stores the data signal written by the data writing circuit 200 and compensates the driving circuit 100 .
  • the compensation storage circuit 300 may be connected to the second scan signal line G2, the first power line VDD, the first node N1 and the third node N3.
  • the second scan signal from the second scan signal line G2 is applied to the compensation storage circuit 300 to control whether it is turned on or not.
  • the compensation storage circuit 300 includes a capacitor
  • the compensation storage circuit 300 can be turned on in response to the second scanning signal, so that the data signal written by the data writing circuit 200 can be stored. in this capacitor.
  • the compensation storage circuit 300 can electrically connect the control terminal 130 of the driving circuit 100 to the second terminal 120, so that the relevant information of the threshold voltage of the driving circuit 100 can also be stored in the corresponding In the capacitance, for example, the stored data signal and the threshold voltage can be used to control the driving circuit 100 during the light emitting stage, so that the output of the driving circuit 100 is compensated.
  • the first light emission control circuit 400 is connected to the first terminal 110 (second node N2) of the driving circuit 100, the first power supply line VDD and the first scanning signal line G1, and is configured to provide The first scan signal applies the first voltage of the first power line VDD to the first terminal 110 of the driving circuit 100 .
  • the first light emission control circuit 400 is connected to the first scanning signal line G1 , the first power supply line VDD and the second node N2 .
  • the first light emission control circuit 400 can be turned on in response to the first scanning signal, so that the first voltage VDD can be applied to the first terminal 110 of the driving circuit 100, so that the voltage of the second node N2 is the first
  • the voltage VDD is used to keep the source voltage of the driving transistor at a stable potential during the initialization phase. Therefore, at the initial stage, the gate voltage Vg and the source voltage Vs of the driving transistor of the driving circuit are reset at the same time, so that the driving transistor is in the On-Bias state, so regardless of whether the data voltage of the previous frame display image is black or white, the driving Transistors start data writing and compensation from the On-Bias state, so the problem of short-term afterimage can be improved.
  • the first light-emitting control circuit 400 can be turned on in response to the first scanning signal, so that the first voltage VDD can be applied to the first terminal 110 of the driving circuit 100.
  • the driving circuit 100 can control the driving current flowing according to the data signal stored in the compensation memory circuit, and apply the driving current to the light emitting element 500 when the second light emitting control circuit 600 is turned on, so as to drive the light emitting element to emit light.
  • the first voltage VDD may be a high voltage (eg, higher than the second voltage VSS).
  • the data write-in circuit 200 and the first light emission control circuit 400 are in mutually exclusive conduction states under the control of the first scanning signal.
  • the types of the data writing transistor implemented by the data writing circuit 200 and the first light emitting control transistor implemented by the first light emitting control circuit 400 are different, so that when the data writing transistor is turned off in response to the first level of the first scan signal , the first light emission control circuit 400 is turned on in response to the first level of the first scan signal, and when the first light emission control circuit 400 is turned off in response to the second level of the first scan signal, the data writing transistor responds to the first The second level of the scanning signal is turned on, so that the voltage control of the second node N2 can be realized by turning on the first light emission control circuit 400 in the initialization stage, so that afterimages can be avoided without adding additional transistors and control signals the emergence of the phenomenon.
  • the data writing circuit 200 may include a P-type transistor, and the first light emission control circuit 400 may include an N-type transistor; or the data writing circuit 200 may include an N-type transistor, and the first light emission control circuit 400 may include a P-type transistor.
  • the turn-on voltages of the N-type transistor and the P-type transistor are different, for example, the P-type transistor is turned on in response to a low-level signal, and the N-type transistor is turned on in response to a high-level signal (higher than the aforementioned low-level signal).
  • the voltage control of the second node N2 can be realized by turning on the first light emission control circuit 400 in the initialization stage, so that the data writing circuit 200 and the first light emission control circuit 400 can share the gate signal,
  • the voltage control of the second node N2 in the initial stage can be realized without adding additional transistors and gate signals.
  • the compensation storage circuit 300 and the data writing circuit 200 may respectively include P-type transistors, and the first light emission control circuit 400 may include N-type transistors; or the compensation storage circuit 300 and the data writing circuit 200 may respectively include An N-type transistor, the first light emission control circuit 400 includes a P-type transistor.
  • the turn-on voltages of the N-type transistor and the P-type transistor are different, for example, the P-type transistor is turned on in response to a low-level signal, and the N-type transistor is turned on in response to a high-level signal (higher than the aforementioned low-level signal).
  • the voltage control of the second node N2 can be realized by turning on the first light emission control circuit 400 in the initialization stage, so that the compensation storage circuit 300, the data writing circuit 200 and the first light emission control circuit 400 can By sharing the gate signal, the voltage control of the second node N2 can be realized in the initial stage without adding additional transistors and gate signals.
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • LTPS Low Temperature Poly Silicon, low temperature polysilicon
  • amorphous silicon such as Hydrogenated amorphous silicon
  • the second light emission control circuit 600 is connected to the light emission control signal line EM, the first end 510 of the light emitting element 500, and the second end 120 of the driving circuit 100, and is configured to respond to the light emission control signal provided by the light emission control signal line EM.
  • a drive current is applied to the light emitting element 500 .
  • the second light-emitting control circuit 600 is turned on in response to the light-emitting control signal provided by the light-emitting control signal line EM, so that the driving circuit 100 can apply a driving current to the light-emitting element 500 through the second light-emitting control circuit 600 to make it
  • the second light-emitting control circuit 600 is turned off in response to the light-emitting control signal, so as to avoid current flowing through the light-emitting element 500 and make it emit light, which can improve the contrast of the corresponding display device.
  • the first scan signal and the light emission control signal are both turn-on signals at least part of the time period.
  • the two light-emitting control circuits 600 are simultaneously turned on during the light-emitting stage, so that the light-emitting element 500 can emit light.
  • the light emitting element 500 includes a first end 510 and a second end 520, the first end 510 of the light emitting element 500 is configured to receive a driving current from the second end 120 of the driving circuit 100 through the second light emitting control circuit 600, the light emitting element 500
  • the second end 520 is configured to be connected to the second power line VSS.
  • the first end 510 of the light emitting element 500 can also be connected to the fourth node N4, and through the second light emission control circuit
  • the circuit 600 is connected to the third node N3.
  • Embodiments of the present disclosure include, but are not limited to, this scenario.
  • the pixel circuit 10 further includes a reset circuit 700 .
  • the reset circuit 700 is connected to the initial voltage terminal Vinit and the first terminal 510 of the light emitting element 500 and the control terminal 130 (first node N1) of the driving circuit 100, and is configured to reset the initial voltage terminal Vinit provided by the initial voltage terminal Vinit in response to a reset signal.
  • the voltage is applied to the first terminal 510 of the light emitting element 500 and the control terminal 130 (the first node N1 ) of the driving circuit 100 .
  • the reset circuit 700 is respectively connected to the fourth node N4, the first node N1, the initial voltage terminal Vinit, the first terminal 510 of the light emitting element 500 and the reset control terminal RST (reset control line).
  • the reset circuit 700 can be turned on in response to a reset signal, so that a reset voltage can be applied to the first terminal 510 (the fourth node N4) of the light emitting element 500 and the control terminal 130 (the first node N4) of the driving circuit 100. N1), so that the drive circuit 100, the compensation storage circuit 300 and the light emitting element 500 can be reset to eliminate the influence of the previous light emitting stage.
  • the pixel circuit provided by at least one embodiment of the present disclosure can solve the afterimage problem without adding transistors and control signal lines, which is beneficial to the realization and layout of the pixel circuit and the promotion of products.
  • the driving circuit 100 when the driving circuit 100 is implemented as a driving transistor, for example, the gate of the driving transistor can be used as the control terminal 130 (connected to the first node N1) of the driving circuit 100, and the first pole (such as the source) can be used as the driving circuit.
  • the first end 110 of the driving circuit 100 (connected to the second node N2 ), and the second pole (for example, the drain) can serve as the second end 120 of the driving circuit 100 (connected to the third node N3 ).
  • the first power line VDD for example, maintains the input of a DC high level signal, and the DC high level is called the first voltage
  • the second power line VSS for example, maintains the input of a DC low level signal.
  • the DC low level is referred to as a second voltage, which is lower than the first voltage.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not represent actual components, but represent a collection of related circuit connections in the circuit diagram point.
  • the symbol Vdata can represent both the data signal terminal and the level of the data signal.
  • the symbol Vinit can represent both the initial voltage terminal and the reset voltage.
  • the symbol VDD can represent both the first power line and the first voltage
  • the symbol VSS can represent both the second power line and the second voltage.
  • the initial voltage terminal Vinit is connected to the initial voltage line VL to receive the reset voltage.
  • the pixel circuit 10 shown in FIG. 3 can be embodied as the pixel circuit structure shown in FIG. 4A .
  • the pixel circuit 10 includes: transistors T1 , T2 , T3 , T4 , T5 , T6 , and includes a storage capacitor Cst and a light emitting element OLED.
  • transistor T1 is used as a driving transistor
  • other transistors T2-T7 are used as switching transistors.
  • the light-emitting element OLED can be various types of OLEDs, such as top emission, bottom emission, double-side emission, etc., and can emit red, green, blue, or white light, which is not limited by embodiments of the present disclosure.
  • the driving circuit 100 may be implemented as a driving transistor T3.
  • the gate of the driving transistor T3 is used as the control terminal 130 of the driving circuit 100 and is connected to the first node N1; the first pole of the driving transistor T3 is used as the first terminal 110 of the driving circuit 100 and is connected to the second node N2; The second pole serves as the second terminal 120 of the driving circuit 100 and is connected to the third node N3.
  • the driving transistor T3 is a P-type transistor.
  • the P-type transistor is turned on in response to a low-level signal, and the following embodiments are the same and will not be repeated here. It should be noted that, it is not limited thereto, and the driving circuit 100 may also be a circuit composed of other components.
  • the data writing circuit 200 may be implemented as a data writing transistor T4.
  • the gate of the data writing transistor T4 is connected to the first scanning signal line G1 to receive the first scanning signal, and the first pole of the data writing transistor T4 is connected to the data line DL (connected to the data signal terminal Vdata) to receive the data signal,
  • the second pole of the data writing transistor T4 is connected to the first terminal 110 (the second node N2 ) of the driving circuit 100 .
  • the compensation storage circuit 300 may be implemented as a compensation transistor T2 and a storage capacitor Cst.
  • the gate of the compensation transistor T2 is configured to be connected to the second scan signal line G2 to receive the scan signal, the first pole of the compensation transistor T2 is connected to the control terminal 130 (first node N1) of the driving circuit 100, and the second pole of the compensation transistor T2
  • the first pole of the storage capacitor Cst is connected to the control terminal 130 of the drive circuit 100, and the second pole of the storage capacitor Cst is connected to the first power line VDD.
  • the first light emission control circuit 400 may be implemented as a first light emission control transistor T5.
  • the gate of the first light emission control transistor T5 is connected to the first scanning signal line G1 to receive the first light emission control signal, and the first pole of the first light emission control transistor T5 is connected to the first power line VDD to receive the first voltage.
  • the second pole of the light emission control transistor T5 is connected to the first terminal 110 (second node N2 ) of the driving transistor.
  • the second light emission control circuit 600 may be implemented as a second light emission control transistor T6.
  • the gate of the second light emission control transistor T6 is connected to the second light emission control line (emission control signal line EM) to receive the light emission control signal, and the first electrode of the second light emission control transistor T6 is connected to the second terminal 120 of the driving circuit 100 (the The three nodes N3) are connected, and the second pole of the second light emission control transistor T6 is connected to the first terminal 510 (fourth node N4) of the light emitting element OLED.
  • the first terminal 510 (here, the anode) of the light-emitting element OLED is connected to the fourth node N4 and configured to receive a driving current from the second terminal 120 of the driving circuit 100 through the second light-emitting control circuit 600, and the second terminal 520 of the light-emitting element OLED ( Here, the cathode) is configured to be connected to the second power supply line VSS to receive the second voltage.
  • the second power line can be grounded, that is, VSS can be 0V.
  • the reset circuit 400 may be implemented as a first reset transistor T1 and a second reset transistor T7.
  • the gate of the first reset transistor T1 is configured to be connected to the first reset signal line RST to receive the first reset signal as a reset signal, and the first pole of the first reset transistor T1 is connected to the initial voltage terminal Vinit to receive the reset voltage.
  • the second pole of the reset transistor T1 is configured to be connected to the control terminal 130 of the driving circuit 100 .
  • the gate of the second reset transistor T7 is connected to the second reset signal line RST to receive the second reset signal as a reset signal, the first pole of the second reset transistor T7 is connected to the initial voltage terminal Vinit to receive the reset voltage, and the second reset transistor The second pole of T7 is connected to the first end 510 of the light emitting element 500 .
  • the type of the data writing transistor T4 and the type of the first light emission control transistor T5 are different.
  • the data writing transistor T4 is a P-type transistor, such as a thin film transistor whose active layer is low-temperature doped polysilicon.
  • the first light emission control transistor T5 is an N-type transistor.
  • IGZO can be used as the active layer of the thin film transistor to reduce the size of the driving transistor and prevent leakage current.
  • the N-type transistor is turned on in response to a high-level signal, and the following embodiments are the same and will not be repeated here.
  • the first reset transistor T1 , the second reset transistor T7 , the compensation transistor T2 , and the second light emission control transistor T6 are all P-type transistors, such as thin film transistors whose active layers are low-temperature doped polysilicon.
  • both the data writing transistor T4 and the compensation transistor T2 are N-type transistors
  • the first light emission control transistor T5 is a P-type transistor.
  • the first reset transistor T1, the second reset transistor T7, and the second light emission control transistor T6 are all P-type transistors.
  • the data writing transistor T4 is a P-type transistor
  • the first light emission control transistor T5 and the compensation transistor T2 are both N-type transistors.
  • the first reset transistor T1, the second reset transistor T7, and the second light emission control transistor T6 are all P-type transistors.
  • the data writing transistor T4 is a P-type transistor
  • the first reset transistor T1 , the first light emission control transistor T5 and the compensation transistor T2 are all N-type transistors.
  • both the second reset transistor T7 and the second light emission control transistor T6 are P-type transistors.
  • the width-to-length ratio of the N-type transistors in each of the above embodiments may be 2.5/3.5, for example, its width ranges from 1.5 to 4 ⁇ m (micrometer), for example, it may be 1.5, 2, 2.5, 3, 3.5, 4, etc. , the length ranges from 3 to 5 ⁇ m, for example, it can be 3, 3.5, 4, 4.5, 5, etc.;
  • the aspect ratio of P-type transistors can be 2.2/3.0 (except for driving transistors), for example, its width ranges from 1.5 to 4 ⁇ m
  • it may be 1.5, 2, 2.5, 3, 3.5, 4, etc.
  • the length ranges from 2 to 6 ⁇ m, such as 2, 3, 4, 5, 6, etc., which are not limited by embodiments of the present disclosure.
  • the pixel circuit needs to turn on the driving transistor T3 during the data writing and compensation phases. Therefore, the voltage difference Vinit-VDD between the initial signal terminal Vinit and the first power supply terminal VDD needs to be smaller than the threshold value of the driving transistor T3
  • the voltage Vth wherein Vinit is the voltage of the initial signal terminal
  • VDD is the voltage of the first power line VDD.
  • Vinit may be -2 ⁇ -6V (volts), for example, -2V, -3V, -4V, -5V, -6V and so on.
  • Vinit-VDD can be less than a*Vth, a can be 2 ⁇ 7, for example, a can be 2, 4, 6, 7; Vth can be -2 ⁇ -5V, for example -2V, -3V, -5V and so on. VDD may be greater than 1.5 times Vth, for example, VDD may be 1.6 times, 1.8 times, 2 times, etc. of Vth.
  • the display panel may include a plurality of pixel driving circuits P distributed in an array, and each of the plurality of first power lines VDD may be used to provide a first voltage.
  • a part of the first power line VDD extends along the column direction, and another part of the first power line VDD extends along the row direction.
  • Pixel circuits in two adjacent rows can be connected to the first power line extending in the same row direction.
  • the first power line VDD can be located at Between the two adjacent rows of pixel circuits, the first power lines extending along the column direction can be connected to intersect with multiple first power lines extending along the row direction, so that the multiple power lines can form a grid structure.
  • the first power line extending along the column direction may be located in the area where the red pixel circuit is located.
  • two pixel circuits in adjacent columns can be mirrored to facilitate wiring.
  • the absolute value of the second reset signal is greater than 1.5 times the threshold voltage of the driving sub-circuit.
  • the magnitude of the second reset signal is greater than zero.
  • the second reset signal is generally a reset voltage of 4-10V
  • the first reset signal is generally a reset voltage of -2V--6V.
  • the voltage value of the first voltage may be greater than 0V and less than or equal to 5V, for example, the voltage value of the first voltage may be 4.6V, but not limited thereto.
  • the reset voltage can be a DC voltage, and the voltage value of the reset voltage can be greater than or equal to -7V and less than or equal to 0V; for example, the voltage value of the reset voltage can be -6V, -5V, -4V, -3V or -2V , but not limited to this.
  • the threshold voltage Vth of the driving transistor in the driving circuit may be greater than or equal to -5V and less than or equal to -2V, for example, Vth may be greater than or equal to -4V and less than or equal to -2.5V; for example , Vth can be -4V, -3.5V, -3V or -2.5V, but not limited thereto.
  • the absolute value of the voltage value of the reset signal may be greater than 1.5 times the absolute value of the threshold voltage, so as to ensure that the bias effect can be quickly achieved in a relatively short period of time.
  • the absolute value of the voltage value of the reset signal may be greater than 2 times, 2.5 times or 3 times the absolute value of the threshold voltage, but not limited thereto.
  • the channel width W of the second reset transistor T7 is 1.5-3.5, such as 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it may be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.
  • the width-to-length ratio W/L of the first light emission control transistor T8 may be greater than the width-to-length ratio W/L of the first reset transistor T1, so that the reset capability of the N2 node can be improved.
  • the channel width W of the first light emission control transistor T8 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; For example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of the first reset transistor T1 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; The channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0 and so on.
  • the display process of each frame of image includes three stages, namely initialization stage t1, data writing and compensation stage t2, and lighting stage t3, and the figure shows the timing waveforms of each signal in each stage .
  • FIG. 8A is a schematic diagram when the pixel circuit shown in FIG. 4A is in the initialization phase t1
  • FIG. 8B is a schematic diagram when the pixel circuit shown in FIG. 4A is in the data writing and compensation phase t2
  • FIG. 8C is The schematic diagram of the pixel circuit shown in FIG. 4A is in the light-emitting phase t3.
  • the transistors marked with dotted lines in FIG. 8A to FIG. 8C all indicate that they are in the off state in the corresponding phase
  • the dotted lines with arrows in FIG. 8A to FIG. 8C indicate the current direction of the pixel circuit in the corresponding phase.
  • the drive transistor T3 and the first reset transistor T1 are all described by taking the drive transistor T3 and the first reset transistor T1 as N-type transistors, and the other transistors as P-type transistors for example, that is, the gates of each N-type transistor are connected to a high voltage. It is usually turned on, and it is turned off when it is connected to a low level, and the gate of each P-type transistor is turned on when it is connected to a low level, and it is turned off when it is connected to a high level.
  • the following embodiments are the same as this and will not be repeated here.
  • the first level of the first scanning signal (for example, the low level shown in FIG.
  • the first light emission control circuit 400 is applied to the first end of the driving circuit 100; the reset signal is input to turn on the reset circuit 700, and the reset voltage is applied to the first end of the light emitting element OLED and the control of the driving circuit 100 through the turned on reset circuit 700 End 130.
  • the first reset transistor T1 and the second reset transistor T7 are P-type transistors, and the first light emission control transistor T5 is an N-type transistor
  • the first reset transistor T1 and the second reset transistor T7 Turned on by the low level of the reset signal, the first light emission control transistor T5 is turned on by the low level of the first scanning signal; at the same time, the compensation transistor T2 and the data writing transistor T4 are turned off by the high level of the first scanning signal,
  • the second light emission control transistor T6 is turned off by the high level of the light emission control signal.
  • the voltage of the second node N2 is charged through the first light emission control transistor T5, thereby stabilizing the voltage of the second node N2 at a stable voltage. Therefore, after the initialization phase t1, the potentials of the first node N1, the third node N3, and the fourth node N4 are reset voltage Vinit (a low-level signal, such as grounding or other low-level signals), and the potential of the second node is the first voltage VDD.
  • Vinit a low-level signal, such as grounding or other low-level signals
  • the second node N2 maintains a stable potential, which resets the Vg and Vs voltages of the drive transistor at the same time, so that the drive transistor is in a fixed bias open state (that is, the On-Bias state), so no matter whether the data voltage of the previous frame display image is black or white, the drive transistor starts from the On-Bias state to write the data voltage of the current frame and the compensation stage t2, so it can improve the short-term afterimage question.
  • the potential of the first node N1 is the reset voltage Vinit, and the potential of the second node N2 is VDD.
  • the storage capacitor Cst is reset to discharge the voltage stored in the storage capacitor Cst, so that the data signal in the subsequent stage can be stored in the storage capacitor Cst more quickly and reliably; at the same time, the light-emitting element OLED (that is, the fourth node N4) is also reset, so that the light-emitting element OLED can be displayed in a black state and not emit light before the light-emitting period t3, and the display effect such as contrast ratio of the display device using the above-mentioned pixel circuit can be improved.
  • the second level of the first scanning signal is input through the first scanning signal line G1 to turn on the data writing circuit 200, and the second scanning signal is input through the second scanning signal line G2 to turn on the compensation memory.
  • the circuit 300 inputs a data signal through the data lines DL to Dm, writes the data signal into the first end 110 of the driving circuit 100 through the data writing circuit 200 that is turned on to turn on the driving circuit 100, and stores the data signal through the turned-on compensation storage circuit 300 , and the driving circuit 100 is compensated by the turned-on compensation storage circuit 300 .
  • the data writing transistor T4 is turned on by the second level of the first scanning signal (for example, the high level shown in FIG. 5B), and the compensation transistor T2 is turned on by the high level of the second scan signal (in this example, the first scan signal and the second scan signal are the same signal), and at the same time, the first light emission control transistor T5 is turned off by the high level of the first scan signal , the second light emission control transistor T6 is turned off by the high level of the light emission control signal, and the first reset transistor T1 and the second reset transistor T7 are turned off by the high level of the reset signal.
  • the second level of the first scanning signal for example, the high level shown in FIG. 5B
  • the compensation transistor T2 is turned on by the high level of the second scan signal (in this example, the first scan signal and the second scan signal are the same signal)
  • the first light emission control transistor T5 is turned off by the high level of the first scan signal
  • the second light emission control transistor T6 is turned off by the high level of the light emission control signal
  • a data writing and compensation path (as shown by the dotted line with arrows in Figure 8B) is formed, and the data signal passes through the data writing transistor T4, the driving transistor T3 and the compensation
  • the transistor T2 then charges the first node N1 (that is, charges the storage capacitor Cst), that is, the potential of the first node N1 rises. It is easy to understand that the potential of the second node N2 remains at Vdata, and according to the characteristics of the driving transistor T3, when the potential of the first node N1 increases to Vdata+Vth, the driving transistor T3 is turned off, and the charging process ends.
  • Vdata represents the voltage value of the data signal
  • Vth represents the threshold voltage of the first transistor. Since in this embodiment, the drive transistor T3 is described using a P-type transistor as an example, the threshold voltage Vth here can be is a negative value.
  • the potentials of the first node N1 and the third node N3 are both Vdata+Vth, that is to say, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst for use
  • grayscale display data is provided and the threshold voltage of the driving transistor T3 is compensated.
  • the first scanning signal is input through the first scanning signal line G1 to turn on the first light-emitting control circuit 400 and the driving circuit 100
  • the light-emitting control signal is input through the light-emitting control signal line EM to turn on the second light-emitting control circuit 600.
  • a driving current is applied to the light emitting element 500 to emit light through the turned-on first light emission control circuit 400 , the driving circuit 100 and the second light emission control circuit 600 .
  • the first light-emitting control transistor T5 is turned on by the high level of the first scanning signal
  • the second light-emitting control transistor T6 is turned on by the low level of the light-emitting control signal
  • the data writing transistor T4 is turned off by the high level of the first scan signal
  • the compensation transistor T2 is turned off by the high level of the second scan signal (ie, the first scan signal)
  • the first reset transistor T1 and the second reset transistor T7 are turned off
  • the low level of the reset signal is cut off.
  • the potential of the first node N1 is Vdata+Vth
  • the potential of the second node N2 is VDD, so the driving transistor T3 is also kept turned on at this stage.
  • a driving light-emitting path is formed (shown by the dotted line with an arrow in FIG. 8C ).
  • the light emitting element OLED can emit light under the action of the driving current flowing through the driving transistor T3.
  • the value of the driving current I L1 flowing through the light emitting element OLED can be obtained according to the following formula:
  • I L1 K(V GS -Vth) 2
  • K W*C OX *U/L.
  • Vth represents the threshold voltage of the driving transistor T3
  • V GS represents the voltage between the gate and the source (here, the first electrode) of the driving transistor T3
  • K is a constant value related to the driving transistor itself.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the embodiments of the present disclosure in order to distinguish the two poles of the transistor except the gate, it is directly described that one pole is the first pole and the other pole is the second pole.
  • the transistors in the pixel circuit 10 shown in FIG. can be the drain, and the second pole can be the source.
  • the cathode of the light emitting element OLED in the pixel circuit 10 is connected to the second power line VSS to receive the second voltage.
  • the cathodes of the light-emitting elements OLED can be electrically connected to the same voltage terminal, that is, a common cathode connection is adopted.
  • first scan signal line and the second scan signal line are the same or different, and the first scan signal and the second scan signal are the same or different.
  • the first scanning signal line and the second scanning signal line are the same, denoted as G1 , and correspondingly, the first scanning signal and the second scanning signal are the same.
  • the type of the data write transistor T4 is different from the type of the compensation transistor T2, and the type of the compensation transistor T2 is different from the first scan signal.
  • the types of the light emission control transistors T5 are the same, for example, the data writing transistor T4 is a P-type transistor, and the compensation transistor T2 and the first light emission control transistor T5 are N-type transistors.
  • first reset signal line and the second reset signal line are the same or different, and the first reset signal and the second reset signal are the same or different.
  • the first reset transistor T1 and the second reset transistor T7 are of the same type, for example, both are P-type transistors, and the first reset signal line is the same as the second reset signal line.
  • RST Denoted as RST, correspondingly, the first reset signal and the second reset signal are also the same.
  • the types of the first reset transistor T1 and the second reset transistor T7 are different, for example, the first reset transistor T1 is an N-type transistor, the second reset transistor T7 is a P-type transistor, and the first reset transistor T7 is a P-type transistor.
  • the signal line RST1 is different from the second reset signal line RST2 , for example, as shown in FIG. 7B , the first reset signal and the second reset signal are opposite signals.
  • Fig. 5B is a working timing diagram of the pixel circuit shown in Fig. 5A;
  • Fig. 6B is a working timing diagram shown in Fig. 6A,
  • Fig. 7B is a working timing diagram shown in Fig. 7A, and
  • Fig. 5A, Fig. 6A and Fig. 7A show The working process of the pixel circuit is similar to the working process of the pixel circuit shown in Figure 4A, and only the timing is adjusted according to the adjustment of the transistor type.
  • the introduction of the working process of the pixel circuit shown in Figure 4A which will not Let me repeat.
  • the first light emission control transistor T5 is used to control the voltage of the second node N2 in the initial stage, so that the voltage of the second node N2 can maintain a stable potential in the initial stage, so that the Improves short-term image retention without adding additional transistors.
  • FIG. 9A is a cross-sectional view of the first light emission control transistor, the driving transistor and the second light emission control transistor in the pixel circuit shown in FIG. 4A or FIG. 5A .
  • 9B and 9I are cross-sectional views of the first light emission control transistor, the data write transistor and the compensation transistor in the pixel circuit shown in FIG. 4A or FIG. 5A .
  • the gate of the first light emission control transistor T5 includes a first sub-gate G51 and a second sub-gate G52 located in different layers, and the active layer A5 of the first light emission control transistor is located in the first sub-gate G52. Between the gate G51 and the second sub-gate G52.
  • the layer where the first sub-gate G51 is located is located between the layer where the gate G4 of the data writing transistor T4 is located and the layer where the second sub-gate G52 is located.
  • the first sub-gate G51 and the second sub-gate of the first light emission control transistor T5 and the gate G4 of the data writing transistor T4 are respectively connected to the first scanning signal line G1 (not shown in FIG. 9B ) through the connection electrode E.
  • the layer where the connecting electrode E is located is located on a side where the layer where the second sub-gate G52 is located away from the layer where the first sub-gate G51 is located and the layer where the gate G4 of the data writing transistor T4 is located.
  • insulating layers 1001 to 1008 are sequentially formed on the base substrate 1000, and the first semiconductor layer, the first gate layer, the second gate layer, the second gate layer, and the first semiconductor layer are sequentially formed between the insulating layers.
  • the anode 510 of the light-emitting element is located on the third conductive layer, and is connected to the second pole of the sixth transistor T6 through a via hole penetrating the insulating layer 1008, for example, the second pole of the sixth transistor T6 is located on the second conductive layer or the first
  • the conductive layer is not limited in the embodiments of the present disclosure.
  • the first power line VDD may be located on the second conductive layer; as shown in FIGS. 9G-9H , the first power line VDD may also be located on the first conductive layer.
  • Embodiments of the disclosure address No limit.
  • the first power line VDD when the first power line VDD is located on the second conductive layer, it can be connected to the first electrode of the first light emission control transistor T5 through the first conductive layer, and the second electrode of the first light emission control transistor T5 is located on the first conductive layer
  • the connecting electrode is connected to the first electrode of the driving transistor T3, and the active layer A3 of the driving transistor T3 is integrally formed with the active layer A6 of the second light emission control transistor T6, and is located on the first semiconductor layer.
  • the second sub-gate G52 is located in the third gate layer
  • the first sub-gate G51 is located in the second gate layer
  • the gates of other transistors for example, G4, G2, G3, G6 are located in the first gate layer.
  • the active layer A5 of the first light emission control transistor is located on the second semiconductor layer
  • the active layers of other transistors for example, A4 , A2 , A3 , A6 ) are located on the first semiconductor layer.
  • connection electrode E can be connected to each gate (G51, G52, G4, G2) in the manner shown in FIG. 9B, for example, as shown in FIG.
  • the electrodes on the first conductive layer and/or the second conductive layer connect the connection electrodes and each gate, which can form a buffer and avoid the need for larger via holes.
  • each gate ( G51 , G52 , G4 , G2 ) can also be connected to the connection electrode E through a via hole in the manner shown in FIG. 9C and FIG. 9D , which is not limited in the embodiments of the present disclosure.
  • connection electrode can be arranged on the same layer as the anode 510 of the light-emitting element, and can also be arranged on the same layer as the first power line VDD (as shown in Figures 9B to 9D);
  • the connection electrode can also be located on the first conductive layer, which is not limited in the embodiments of the present disclosure, as long as the data writing transistor T4 and the first light emission control transistor T5 can be connected, but the first light emission control transistor T5 The transistor T5 is not in the same layer as the gate of the compensation transistor T2 and the data writing transistor T4.
  • the gate G51 and the second sub-gate G52 are connected to the gate G4 of the data writing transistor T4, and then the gate G4 of the data writing transistor T4 is electrically connected to the gate G2 of the compensation transistor T2 through a jumper connection.
  • the embodiments of the present disclosure do not limit this.
  • the jumper connection part is not shown in FIG. 9I , and details may refer to designs in the field, and details are not repeated here.
  • connection electrode E can also be located on the second conductive layer, and be connected to the electrode on the first conductive layer through the via hole penetrating the insulating layer 1007, and then connect to the electrode on the first conductive layer through the electrode on the first conductive layer.
  • Other gate connections may also be directly connected to each gate through via holes in each insulating layer (as shown in FIG. 9H ).
  • the first power line VDD is located on the first conductive layer.
  • the base substrate 1000 may be made of glass, plastic, quartz or other suitable materials, which are not limited in the embodiments of the present disclosure.
  • the materials of the insulating layers 1001-1008 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, etc., organic insulating materials such as organic resin, or other suitable materials, which are not limited in the embodiments of the present disclosure.
  • the material of the semiconductor layer may include oxide semiconductor, organic semiconductor or amorphous silicon, polysilicon, etc.
  • the oxide semiconductor includes metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polysilicon includes low-temperature polysilicon or high-temperature polysilicon. etc., which are not limited by the embodiments of the present disclosure.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, which is not limited in the embodiments of the present disclosure.
  • first conductive layer, second conductive layer, and third conductive layer may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy or any other suitable composite material.
  • first gate layer and the second gate layer may be the same as that of the first conductive layer, which will not be repeated here.
  • At least one embodiment of the present disclosure further provides a display panel, including a plurality of pixel units arranged in an array, and each of the plurality of pixel units includes the pixel circuit provided by any embodiment of the present disclosure.
  • FIG. 10 is a schematic block diagram of a display panel provided by an embodiment of the present disclosure. As shown in FIG. 10 , the display panel 11 is disposed in the display device 1 and is electrically connected to the gate driver 12 , the timing controller 13 and the data driver 14 .
  • the display panel 11 includes a pixel unit P defined by intersections of multiple scan lines GL and multiple data lines DL; a gate driver 12 is used to drive multiple scan lines GL; a data driver 14 is used to drive multiple data lines DL; timing
  • the controller 13 is used for processing the image data RGB input from the outside of the display device 1, providing the processed image data RGB to the data driver 14, and outputting the scan control signal GCS and the data control signal DCS to the gate driver 12 and the data driver 14, so as to control
  • the gate driver 12 and the data driver 14 perform control.
  • the display panel 11 includes a plurality of pixel units P, and the pixel units P include any pixel circuit 10 provided in the above-mentioned embodiments.
  • the pixel circuit 10 shown in FIG. 3 is included.
  • the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL.
  • the plurality of scanning lines are correspondingly connected to the data writing circuit 200 in the pixel circuit 10 of each row of pixel units to provide the first scanning signal, and the plurality of scanning lines are also correspondingly connected to the pixel circuit 10 of each row of pixel units
  • the compensation storage circuit 300 and the reset circuit 700 in the second scan signal are used as reset signals.
  • the pixel unit P is disposed at the intersection area of the scan line GL and the data line DL.
  • each pixel unit P is connected to a plurality of scanning lines GL (respectively providing a first scanning signal, a second scanning signal, a first reset signal, a second reset signal, and an emission control signal), a data line DL, a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a reset voltage line for supplying a reset voltage.
  • the first power line or the second power line can be replaced by a corresponding plate-shaped common electrode (such as a common anode or a common cathode).
  • each pixel unit P Can be connected to only 3 scanning lines GL. It should be noted that the following embodiments are the same as this and will not be repeated here.
  • the plurality of pixel units P are arranged in multiple rows, and the compensation storage circuit 300, the data writing circuit 200, and the first light emission control circuit 400 of the pixel circuit of each row of pixel units P are connected to the same scanning line GL, the embodiments of the present disclosure do not limit this.
  • the data line DL of each column is connected to the data writing circuit 200 in the pixel circuit 10 of this column to provide a data signal.
  • the gate driver 12 supplies a plurality of gate signals to a plurality of scan lines GL according to a plurality of scan control signals GCS from the timing controller 13 .
  • the plurality of gating signals include a first scan signal, a second scan signal, a light emission control signal, and a reset signal. These signals are supplied to each pixel unit P through a plurality of scan lines GL.
  • the data driver 14 converts digital image data RGB input from the timing controller 13 into data signals according to a plurality of data control signals DCS from the timing controller 13 using a reference gamma voltage.
  • the data driver 14 supplies converted data signals to a plurality of data lines DL.
  • the timing controller 13 processes externally input image data RGB to match the size and resolution of the display panel 11 , and then supplies the processed image data to the data driver 14 .
  • the timing controller 13 generates a plurality of scanning control signals GCS and a plurality of data control signals DCS using synchronous signals (such as dot clock DCLK, data enable signal DE, horizontal synchronous signal Hsync, and vertical synchronous signal Vsync) input from the display device.
  • the timing controller 13 provides the generated scan control signal GCS and data control signal DCS to the gate driver 12 and the data driver 14 respectively for controlling the gate driver 12 and the data driver 14 .
  • the data driver 14 can be connected to a plurality of data lines DL to provide a data signal Vdata; meanwhile, it can also be connected to a plurality of first power lines, a plurality of second power lines and a plurality of reset voltage lines to provide first voltage, a second voltage and a reset voltage.
  • the gate driver 12 and the data driver 14 may be implemented as semiconductor chips.
  • the display device 1 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may be existing conventional components, and will not be described in detail here.
  • the display panel 11 provided in this embodiment can be applied to any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.
  • a display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.
  • the embodiment of the present disclosure also provides a driving method, which can be used to drive the pixel circuit 10 provided by the embodiment of the present disclosure.
  • the driving method includes a reset phase, a data writing and compensation phase, and a light emitting phase.
  • the first level of the first scanning signal is input through the first scanning signal line to turn on the first light emitting control circuit, and the first voltage is applied to the first terminal of the driving circuit through the turned on first light emitting control circuit.
  • the second level of the first scanning signal is input through the first scanning signal line to open the data writing circuit, and the second scanning signal is input through the second scanning signal line to open the compensation storage circuit.
  • the data signal is input through the line, and the data signal is written into the first end of the driving circuit through the turned-on data writing circuit to turn on the driving circuit, the data signal is stored through the turned-on compensation storage circuit, and the driving circuit is compensated through the turned-on compensation storage circuit .
  • the first scan signal is input through the first scan signal line to turn on the first light-emitting control circuit and the driving circuit
  • the light-emitting control signal is input through the light-emitting control signal line to turn on the second light-emitting control circuit
  • the driving current is passed through the turned-on first light-emitting control circuit.
  • a light emission control circuit, a driving circuit and a second light emission control circuit are applied to the light emitting element to cause it to emit light.
  • the driving method includes the following operations:
  • a reset signal is input to turn on the reset circuit, and a reset voltage is applied to the first end of the light emitting element and the control end of the driving circuit through the turned on reset circuit.

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Abstract

一种像素电路及其驱动方法、显示面板。该像素电路(10)包括驱动电路(100)、数据写入电路(200)、补偿存储电路(300)、第一发光控制电路(400)和第二发光控制电路(600)。驱动电路(100)包括控制端(130)、第一端(110)和第二端(120)，且配置为控制流经第一端(110)和第二端(120)的用于驱动发光元件(500)发光的驱动电流；数据写入电路(200)与第一扫描信号线(G1)连接，且配置为响应于第一扫描信号线(G1)提供的第一扫描信号将数据信号写入驱动电路(100)的第一端(110)；第一发光控制电路(400)与第一扫描信号线(G1)连接，且配置为响应于第一扫描信号线(G1)提供的第一扫描信号将第一电源线(VDD)的第一电压施加至驱动电路(100)的第一端(110)，数据写入电路(200)和第一发光控制电路(400)在第一扫描信号的控制下导通状态相斥。该像素电路可以解决残像问题。

Description

像素电路及其驱动方法、显示面板
本申请要求于2021年7月30日递交的PCT专利申请PCT/CN2021/109890及2021年8月5日递交的中国专利申请第202110898658.9号的优先权，在此全文引用上述专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示面板。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。由于上述特点，有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。PMOLED虽然工艺简单、成本较低，但因存在交叉串扰、高功耗、低寿命等缺点，不能满足高分辨率大尺寸显示的需求。相比之下，AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。相比PMOLED，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
发明内容
本公开至少一实施例提供一种像素电路，包括：驱动电路、数据写入电路、补偿存储电路、第一发光控制电路和第二发光控制电路；所述驱动电路包括控制端、第一端和第二端，且配置为控制流经所述第一端和所述第二端 的用于驱动所述发光元件发光的驱动电流；所述数据写入电路与所述驱动电路的第一端和第一扫描信号线连接，且配置为响应于所述第一扫描信号线提供的第一扫描信号将数据信号写入所述驱动电路的第一端；所述补偿存储电路与所述驱动电路的控制端以及第二端连接且与第二扫描信号线和第一电源线连接，且配置为响应于所述第二扫描信号线提供的第二扫描信号存储所述数据写入电路写入的所述数据信号并对所述驱动电路进行补偿；所述第一发光控制电路与所述驱动电路的第一端、所述第一电源线以及所述第一扫描信号线连接，且配置为响应于所述第一扫描信号线提供的所述第一扫描信号将所述第一电源线的第一电压施加至所述驱动电路的第一端，其中，所述数据写入电路和所述第一发光控制电路在所述第一扫描信号的控制下导通状态相斥；所述第二发光控制电路与所述驱动电路的第二端、发光控制信号线以及所述发光元件的第一端连接，且配置为响应于所述发光控制信号线提供的发光控制信号将所述驱动电流施加至所述发光元件。
例如，在本公开至少一实施例提供的像素电路中，所述驱动电路包括驱动晶体管；所述驱动晶体管的栅极作为所述驱动电路的控制端，所述驱动晶体管的第一极作为所述驱动电路的第一端，所述驱动晶体管的第二极作为所述驱动电路的第二端。
例如，在本公开至少一实施例提供的像素电路中，所述数据写入电路包括数据写入晶体管；所述数据写入晶体管的栅极和所述第一扫描信号线连接以接收所述第一扫描信号，所述数据写入晶体管的第一极和数据线连接以接收所述数据信号，所述数据写入晶体管的第二极和所述驱动电路的第一端连接。
例如，在本公开至少一实施例提供的像素电路中，所述第一发光控制电路包括第一发光控制晶体管；所述第一发光控制晶体管的栅极和所述第一扫描信号线连接以接收所述第一扫描信号，所述第一发光控制晶体管的第一极和所述第一电源线连接以接收所述第一电压，所述第一发光控制晶体管的第二极和所述驱动电路的第一端连接。
例如，在本公开至少一实施例提供的像素电路中，所述数据写入晶体管的类型和所述第一发光控制晶体管的类型不同。
例如，在本公开至少一实施例提供的像素电路中，所述第一发光控制晶 体管为N型晶体管，所述数据写入晶体管为P型晶体管。
例如，在本公开至少一实施例提供的像素电路中，所述第一发光控制晶体管的栅极包括位于不同层的第一子栅极和第二子栅极，所述第一发光控制晶体管的有源层位于所述第一子栅极和所述第二子栅极之间，所述第一子栅极所在层位于所述数据写入晶体管的栅极所在层和所述第二子栅极所在层之间，所述第一发光控制晶体管的第一子栅极和第二子栅极以及所述数据写入晶体管的栅极分别通过连接电极与所述第一扫描信号线连接，所述连接电极所在层位于所述第二子栅极所在层远离所述第一子栅极所在层和所述数据写入晶体管的栅极所在层的一侧。
例如，在本公开至少一实施例提供的像素电路中，所述补偿存储电路包括补偿晶体管和存储电容；所述补偿晶体管的栅极和所述第二扫描信号线连接以接收所述第二扫描信号，所述补偿晶体管的第一极和所述驱动电路的第二端连接，所述补偿晶体管的第二极和所述驱动电路的控制端连接；
所述存储电容的第一极和所述驱动电路的控制端连接，所述存储电容的第二极和所述第一电源线连接。
例如，在本公开至少一实施例提供的像素电路中，所述第一扫描信号线和所述第二扫描信号线相同或不同，所述第一扫描信号和所述第二扫描信号相同或不同。
例如，在本公开至少一实施例提供的像素电路中，当所述第一扫描信号和所述第二扫描信号不同时，所述数据写入晶体管的类型和所述补偿晶体管的类型不同，所述补偿晶体管的类型和所述第一发光控制晶体管的类型相同。
例如，本公开至少一实施例提供的像素电路，还包括复位电路，所述复位电路与初始电压端、所述发光元件的第一端和所述驱动电路的控制端连接，且配置为响应于复位信号将所述初始电压端提供的复位电压施加至所述发光元件的第一端和所述驱动电路的控制端。
例如，在本公开至少一实施例提供的像素电路中，所述复位电路包括第一复位晶体管和第二复位晶体管；所述第一复位晶体管的栅极和第一复位信号线连接以接收第一复位信号作为所述复位信号，所述第一复位晶体管的第一极和所述初始电压端连接以接收所述复位电压，所述第一复位晶体管的第二极和所述驱动电路的控制端连接；所述第二复位晶体管的栅极和第二复位 信号线连接以接收第二复位信号作为所述复位信号，所述第二复位晶体管的第一极和所述初始电压端连接以接收所述复位电压，所述第二复位晶体管的第二极和所述发光元件的第一端连接。
例如，在本公开至少一实施例提供的像素电路中，所述第一复位信号线和所述第二复位信号线相同或不同，所述第一复位信号和所述第二复位信号相同或不同。
例如，在本公开至少一实施例提供的像素电路中，所述第二发光控制电路包括第二发光控制晶体管；
所述第二发光控制晶体管的栅极和所述发光控制线连接以接收所述发光控制信号，所述第二发光控制晶体管的第一极和所述驱动电路的第二端连接，所述第二发光控制晶体管的第二极和所述发光元件的第一端连接。
本公开至少一实施例还提供一种像素电路的驱动方法，包括：复位阶段、数据写入及补偿阶段以及发光阶段；在所述复位阶段，通过所述第一扫描信号线输入所述第一扫描信号的第一电平的以开启所述第一发光控制电路，将所述第一电压通过开启的所述第一发光控制电路施加至所述驱动电路的第一端；在所述数据写入及补偿阶段，通过所述第一扫描信号线输入所述第一扫描信号的第二电平以开启所述数据写入电路，通过所述第二扫描信号线输入所述第二扫描信号以开启所述补偿存储电路，通过数据线输入所述数据信号，将所述数据信号通过开启的所述数据写入电路写入所述驱动电路的第一端以开启所述驱动电路，通过开启的所述补偿存储电路存储所述数据信号，且通过开启的所述补偿存储电路对所述驱动电路进行补偿；在所述发光阶段，通过所述第一扫描信号线输入所述第一扫描信号以开启所述第一发光控制电路和所述驱动电路，通过所述发光控制信号线输入所述发光控制信号以开启所述第二发光控制电路，将所述驱动电流通过开启的所述第一发光控制电路、所述驱动电路和所述第二发光控制电路施加至所述发光元件以使其发光。
例如，在本公开至少一实施例提供的驱动方法中，所述像素电路还包括复位电路，所述复位电路与初始电压端、所述发光元件的第一端和所述驱动电路的控制端连接，且配置为响应于复位信号将复位电压施加至所述发光元件的第一端和所述驱动电路的控制端；所述方法还包括：在所述复位阶段，输入所述复位信号以开启所述复位电路，将所述复位电压通过开启的所述复 位电路施加至所述发光元件的第一端和所述驱动电路的控制端。
本公开至少一实施例还提供一种显示面板，包括本公开任一实施例提供的像素电路。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一显示装置显示的图像一的示意图；
图1B为该显示装置要显示的图像二的示意图；
图1C为该显示装置实际显示的图像二的示意图；
图2为本公开至少一实施例提供的一种像素电路的示意框图；
图3为本公开一实施例提供的另一种像素电路的示意框图；
图4A、5A、6A、7A分别为图3中所示的像素电路的一种具体实现示例的电路图；
图4B、5B、6B、7B分别为图4A、5A、6A、7A所示的像素电路的驱动方法的时序图；
图8A至图8C分别为图4A中所示的像素电路对应于图4B中三个阶段的电路示意图；
图9A为图4A所示的像素电路中的第一发光控制晶体管、驱动晶体管和第二发光控制晶体管的截面图；
图9B至图9I为图4A所示的像素电路中的第一发光控制晶体管、数据写入晶体管和补偿晶体管的截面图；以及
图10为本公开一实施例提供的一种显示面板的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面，将参照附图详细描述根据本公开的各个实施例。需要注意的是，在附图中，将相同的附图标记赋予基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
补偿存储电路用于对包含在AMOLED显示器的像素中的驱动晶体管的阈值电压变化(或偏差)进行补偿。然而，当补偿存储电路被用于显示图像时，由于滞后现象，像素的响应速度根据施加到驱动晶体管的数据电压的增大/减小而变化，使得难以正确地显示灰度级。当驱动AMOLED显示器以表达从黑到白的亮度时，会产生响应速度的延迟，并且当在屏幕上滚动文本时，这个问题会导致残留影象(sticking)，即残像。
残像现象如图1A-1C所示，图1A为一显示装置显示的图像一的示意图，图1B为该显示装置要显示的图像二的示意图，图1C为该显示装置实际显示的图像二的示意图。在该显示装置显示图像一例如如图1A所示的黑白棋盘图像一段时间后，当显示装置显示的图像切换到新的图像二例如如图1B所示的灰阶为48的图像时，仍然会部分残留图1A所示图像一的棋盘图像，如图1C所示。例如，首先，在OLED上短时间(如10s)显示黑白格子图像(如图1A所示)，然后在灰度图(图1C所示的例如48级灰度图)中观察到残差图像现象，几秒钟或几分钟后，图1C中所示的残余图像逐渐消失看不见的，显示为图1B所示的图像。
残像现象形成的原因被证明与像素电路中驱动晶体管的磁滞特性相关。 由于驱动晶体管的迟滞效应，当一显示装置显示同一个图像一段时间后，在把前一个显示图像切换到下一个图像时，原先的前一个显示图像会部分残留而浮现在下一个图像中，一段时间后残像会消失，这种现象称为短期残像。迟滞效应主要是因为驱动晶体管中残留的可移动离子造成阈值电压(Vth)偏移所导致的。在不同画面切换时其初始化阶段(即复位阶段)的V GS(驱动晶体管的栅极和源极之间的电压)可能不同，所以可能会造成驱动晶体管不同程度的阈值电压偏移，从而造成短期残像。
为了避免出现残像现象，通常增加一个单独的晶体管以及对应的栅极扫描信号来控制驱动晶体管的源极的电压，以在初始化阶段使得驱动晶体管的源极电压保持在稳定的电位，由此将驱动晶体管的栅极电压Vg和源极电压Vs同时进行复位，使驱动晶体管处于On-Bias状态，因此不论前帧显示图像的数据电压为黑或是白，驱动晶体管皆由On-Bias状态开始进行数据写入与补偿，故可改善短期残像问题。但是，该解决残像问题的方案需要引入额外的晶体管和信号，不利于像素电路的实现和布局。
本公开至少一实施例提供一种像素电路，包驱动电路、数据写入电路、补偿存储电路、第一发光控制电路和第二发光控制电路。驱动电路包括控制端、第一端和第二端，且配置为控制流经第一端和第二端的用于驱动发光元件发光的驱动电流；数据写入电路与驱动电路的第一端和第一扫描信号线连接，且配置为响应于第一扫描信号线提供的第一扫描信号将数据信号写入驱动电路的第一端；补偿存储电路与驱动电路的控制端以及第二端连接且与第二扫描信号线和第一电源线连接，且配置为响应于第二扫描信号线提供的第二扫描信号存储数据写入电路写入的数据信号并对驱动电路进行补偿；第一发光控制电路与驱动电路的第一端、第一电源线以及第一扫描信号线连接，且配置为响应于第一扫描信号线提供的第一扫描信号将第一电源线的第一电压施加至驱动电路的第一端，数据写入电路和第一发光控制电路在第一扫描信号的控制下导通状态相斥；第二发光控制电路与驱动电路的第二端、发光控制信号线以及发光元件的第一端连接，且配置为响应于发光控制信号线提供的发光控制信号将驱动电流施加至发光元件。
本公开至少一实施例还提供了一种对应于上述像素电路的驱动方法和显示面板。
本公开至少一实施例提供的像素电路，可以在不增加晶体管和控制信号线的情况下解决残像问题，有利于像素电路的实现和布局，有利于产品的推广。
下面结合附图对本公开的实施例进行详细说明。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开实施例的一个示例提供一种像素电路10，该像素电路10例如用于OLED显示装置的子像素。如图2所示，该像素电路10包括驱动电路100、数据写入电路200、补偿存储电路300、第一发光控制电路400、第二发光控制电路600。例如，该像素电路10用于驱动发光元件500发光。
例如，驱动电路100包括第一端110、第二端120和控制端130，其配置为控制驱动发光元件500发光的驱动电流，且驱动电路100的控制端130和第一节点N1连接，驱动电路100的第一端110和第二节点N2连接，驱动电路100的第二端120和第三节点N3连接。例如，在发光阶段，驱动电路100可以向发光元件500提供驱动电流以驱动发光元件500进行发光，且可以根据需要的“灰度”发光。例如，发光元件500可以采用OLED，且配置为和第三节点N3以及第二电源线VSS(例如，提供低电平，例如接地)连接，本公开的实施例包括但不限于此情形。
例如，如图2所示的示例中，在像素电路10包括第二发光控制电路600的情形下，发光元件500可以通过第二发光控制电路600与第三节点N3连接，从而可以避免发光元件500在非发光阶段有电流流过而发光。本公开的实施例包括但不限于此情形。
例如，数据写入电路200与驱动电路100的第一端110(第二节点N2)和第一扫描信号线G1连接，且配置为响应于第一扫描信号线G1提供的第一扫描信号将数据信号写入驱动电路100的第一端110。例如，数据写入电路200和数据信号端Vdata(例如，如图4A所示，该数据信号端Vdata与数据线DL连接)、第二节点N2以及第一扫描信号线G1连接。例如，来自第一扫描信号线G1的第一扫描信号被施加至数据写入电路200以控制数据写入电路200开启与否。
例如，在数据写入阶段，数据写入电路200可以响应于第一扫描信号而开启，从而可以将数据信号写入驱动电路100的第一端110(第二节点N2)， 并将数据信号存储在补偿存储电路300中，以在例如发光阶段时可以根据该数据信号生成驱动发光元件500发光的驱动电流。
例如，补偿存储电路300与驱动电路的控制端130(第一节点N1)以及第二端120(第三节点N3)连接且与第二扫描信号线G2和第一电源线VDD连接，配置为响应于第二扫描线G2提供的第二扫描信号存储数据写入电路200写入的所述数据信号并对驱动电路100进行补偿。例如，补偿存储电路300可以与第二扫描信号线G2、第一电源线VDD、第一节点N1以及第三节点N3连接。例如，来自第二扫描信号线G2的第二扫描信号被施加至补偿存储电路300以控制其开启与否。例如，在补偿存储电路300包括电容的情形下，例如在数据写入和补偿阶段，补偿存储电路300可以响应于第二扫描信号而开启，从而可以将数据写入电路200写入的数据信号存储在该电容中。例如，同时在数据写入和补偿阶段，补偿存储电路300可以将驱动电路100的控制端130和第二端120电连接，从而可以使驱动电路100的阈值电压的相关信息也相应地存储在该电容中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动电路100进行控制，使得驱动电路100的输出得到补偿。
例如，第一发光控制电路400与驱动电路100的第一端110(第二节点N2)、第一电源线VDD以及第一扫描信号线G1连接，且配置为响应于第一扫描信号线G1提供的第一扫描信号将第一电源线VDD的第一电压施加至驱动电路100的第一端110。例如，如图2所示，第一发光控制电路400和第一扫描信号线G1、第一电源线VDD以及第二节点N2连接。
例如，在初始阶段，第一发光控制电路400可以响应于第一扫描信号而开启，从而可以将第一电压VDD施加至驱动电路100的第一端110，使得第二节点N2的电压为第一电压VDD，以在初始化阶段使得驱动晶体管的源极电压保持在稳定的电位。由此在初始阶段将驱动电路的驱动晶体管的栅极电压Vg和源极电压Vs同时进行复位，使驱动晶体管处于On-Bias状态，因此不论前帧显示图像的数据电压为黑或是白，驱动晶体管皆由On-Bias状态开始进行数据写入与补偿，故可改善短期残像问题。
例如，在发光阶段，第一发光控制电路400可以响应于第一扫描信号而开启，从而可以将第一电压VDD施加至驱动电路100的第一端110，在驱动 电路100导通时，驱动电路100可以根据存储在补偿存储电路中的数据信号控制流经的驱动电流，并在第二发光控制电路600开启时，将此驱动电流施加至发光元件500，从而驱动发光元件发光。例如，第一电压VDD可以是高电压(例如，高于第二电压VSS)。
例如，数据写入电路200和第一发光控制电路400在第一扫描信号的控制下导通状态相斥。例如，数据写入电路200实现的数据写入晶体管和第一发光控制电路400实现的第一发光控制晶体管的类型不同，从而使得数据写入晶体管响应于第一扫描信号的第一电平截止时，第一发光控制电路400响应于第一扫描信号的第一电平导通，当第一发光控制电路400响应于第一扫描信号的第二电平截止时，数据写入晶体管响应于第一扫描信号的第二电平导通，从而在初始化阶段通过导通第一发光控制电路400实现对第二节点N2的电压控制，从而可以在不增加额外的晶体管和控制信号的情形下，避免残像现象的出现。
例如，在一些示例中，数据写入电路200可以包括P型晶体管，第一发光控制电路400包括N型晶体管；或者数据写入电路200可以包括N型晶体管，第一发光控制电路400包括P型晶体管。例如，该N型晶体管和P型晶体管的开启电压不同，例如，P型晶体管响应于低电平信号开启，N型晶体管响应于高电平信号(高于前述低电平信号)开启。因此，通过这种设置，可以在初始化阶段通过导通第一发光控制电路400实现对第二节点N2的电压控制，从而可以使得数据写入电路200和第一发光控制电路400共用栅极信号，无需再增加额外的晶体管和栅极信号即可实现在初始阶段对第二节点N2的电压控制。
例如，在另一些示例中，补偿存储电路300和数据写入电路200可以分别包括P型晶体管，第一发光控制电路400包括N型晶体管；或者补偿存储电路300和数据写入电路200可以分别包括N型晶体管，第一发光控制电路400包括P型晶体管。例如，该N型晶体管和P型晶体管的开启电压不同，例如，P型晶体管响应于低电平信号开启，N型晶体管响应于高电平信号(高于前述低电平信号)开启。因此，通过这种设置，可以在初始化阶段通过导通第一发光控制电路400实现对第二节点N2的电压控制，从而可以使得补偿存储电路300、数据写入电路200和第一发光控制电路400共用栅极信号，无 需再增加额外的晶体管和栅极信号即可实现在初始阶段对第二节点N2的电压控制。
例如，采用N型晶体管时，其可以采用IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)作为薄膜晶体管的有源层，相对于采用LTPS(Low Temperature Poly Silicon，低温多晶硅)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流，从而在使得该像素电路的可以适用于低频驱动的同时，还可以增加显示面板的分辨率，以下实施例与此相同，不再赘述。
例如，第二发光控制电路600和发光控制信号线EM、发光元件500的第一端510以及驱动电路100的第二端120连接，且配置为响应于发光控制信号线EM提供的发光控制信号将驱动电流施加至发光元件500。
例如，在发光阶段，第二发光控制电路600响应于发光控制信号线EM提供的发光控制信号而开启，从而驱动电路100可以通过第二发光控制电路600将驱动电流施加至发光元件500以使其发光；而在非发光阶段，第二发光控制电路600响应于发光控制信号而截止，从而避免有电流流过发光元件500而使其发光，可以提高相应的显示装置的对比度。
例如，第一扫描信号和发光控制信号至少部分时间段内同时为开启信号，例如在发光阶段，可以使第一扫描信号和发光控制信号同时为开启信号，以使得第一发光控制电路400和第二发光控制电路600在发光阶段同时导通，以使得发光元件500可发光。
例如，发光元件500包括第一端510和第二端520，发光元件500的第一端510配置为从驱动电路100的第二端120通过第二发光控制电路600接收驱动电流，发光元件500的第二端520配置为与第二电源线VSS连接。例如，在如图2所示的示例中，在像素电路10包括第二发光控制电路600的情形下，发光元件500的第一端510还可以和第四节点N4连接，且通过第二发光控制电路600与第三节点N3连接。本公开的实施例包括但不限于此情形。
例如，如图3所示，在图2所示的示例的基础上，像素电路10还包括复位电路700。
例如，复位电路700与初始电压端Vinit以及发光元件500的第一端510和驱动电路100的控制端130(第一节点N1)连接，且配置为响应于复位信 号将初始电压端Vinit提供的复位电压施加至发光元件500的第一端510和驱动电路100的控制端130(第一节点N1)。例如，如图3所示，该复位电路700分别和第四节点N4、第一节点N1、初始电压端Vinit、发光元件500的第一端510以及复位控制端RST(复位控制线)连接。例如，在初始化阶段，复位电路700可以响应于复位信号而开启，从而可以将复位电压施加至发光元件500的第一端510(第四节点N4)以及驱动电路100的控制端130(第一节点N1)，从而可以对驱动电路100、补偿存储电路300以及发光元件500进行复位操作，消除之前的发光阶段的影响。
本公开至少一实施例提供的像素电路，可以在不增加晶体管和控制信号线的情况下解决残像问题，有利于像素电路的实现和布局，有利于产品的推广。
例如，在驱动电路100实现为驱动晶体管的情形时，例如驱动晶体管的栅极可以作为驱动电路100的控制端130(连接到第一节点N1)，第一极(例如源极)可以作为驱动电路100的第一端110(连接到第二节点N2)，第二极(例如漏极)可以作为驱动电路100的第二端120(连接到第三节点N3)。
需要说明的是，本公开的实施例中的第一电源线VDD例如保持输入直流高电平信号，将该直流高电平称为第一电压；第二电源线VSS例如保持输入直流低电平信号，将该直流低电平称为第二电压，低于第一电压。以下各实施例与此相同，不再赘述。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3以及第四节点N4并非表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vdata既可以表示数据信号端又可以表示数据信号的电平，同样地，符号Vinit既可以表示初始电压端又可以表示复位电压，符号VDD既可以表示第一电源线又可以表示第一电压，符号VSS既可以表示第二电源线又可以表示第二电压。以下各实施例与此相同，不再赘述。
例如，初始电压端Vinit与初始电压线VL连接以接收复位电压。
例如，图3中所示的像素电路10可以具体实现为图4A所示的像素电路结构。如图4A所示，该像素电路10包括：晶体管T1、T2、T3、T4、T5、 T6以及包括存储电容Cst和发光元件OLED。例如，晶体管T1被用作驱动晶体管，其他的晶体管T2-T7被用作开关晶体管。例如，发光元件OLED可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图4A所示，更详细地，驱动电路100可以实现为驱动晶体管T3。驱动晶体管T3的栅极作为驱动电路100的控制端130，和第一节点N1连接；驱动晶体管T3的第一极作为驱动电路100的第一端110，和第二节点N2连接；驱动晶体管T3的第二极作为驱动电路100的第二端120，和第三节点N3连接。例如，该驱动晶体管T3为P型晶体管。例如，P型晶体管响应于低电平信号开启，以下实施例与此相同，不再赘述。需要注意的是，不限于此，驱动电路100也可以是由其他的组件组成的电路。
数据写入电路200可以实现为数据写入晶体管T4。数据写入晶体管T4的栅极和第一扫描信号线G1连接以接收第一扫描信号，数据写入晶体管T4的第一极和数据线DL(与数据信号端Vdata连接)连接以接收数据信号，数据写入晶体管T4的第二极和驱动电路100的第一端110(第二节点N2)连接。
补偿存储电路300可以实现为补偿晶体管T2和存储电容Cst。补偿晶体管T2的栅极配置为和第二扫描信号线G2连接以接收扫描信号，补偿晶体管T2的第一极和驱动电路100的控制端130(第一节点N1)连接，补偿晶体管T2的第二极和驱动电路100的第二端120(第三节点N3)连接；存储电容Cst的第一极和驱动电路100的控制端130连接，存储电容Cst的第二极和第一电源线VDD连接。
第一发光控制电路400可以实现为第一发光控制晶体管T5。第一发光控制晶体管T5的栅极和第一扫描信号线G1连接以接收第一发光控制信号，第一发光控制晶体管T5的第一极和第一电源线VDD连接以接收第一电压，第一发光控制晶体管T5的第二极和驱动晶体管的第一端110(第二节点N2)连接。
第二发光控制电路600可以实现为第二发光控制晶体管T6。第二发光控制晶体管T6的栅极和第二发光控制线(发光控制信号线EM)连接以接收发光控制信号，第二发光控制晶体管T6的第一极和驱动电路100的第二端120(第三节点N3)连接，第二发光控制晶体管T6的第二极和发光元件OLED 的第一端510(第四节点N4)连接。
发光元件OLED的第一端510(这里为阳极)和第四节点N4连接配置为通过第二发光控制电路600从驱动电路100的第二端120接收驱动电流，发光元件OLED的第二端520(这里为阴极)配置为和第二电源线VSS连接以接收第二电压。例如第二电源线可以接地，即VSS可以为0V。
复位电路400可以实现为第一复位晶体管T1和第二复位晶体管T7。第一复位晶体管T1的栅极配置为和第一复位信号线RST连接以接收第一复位信号作为复位信号，第一复位晶体管T1的第一极和初始电压端Vinit连接以接收复位电压，第一复位晶体管T1的第二极配置为和驱动电路100的控制端130连接。
第二复位晶体管T7的栅极和第二复位信号线RST连接以接收第二复位信号作为复位信号，第二复位晶体管T7的第一极和初始电压端Vinit连接以接收复位电压，第二复位晶体管T7的第二极和发光元件500的第一端510连接。
例如，在一些示例中，数据写入晶体管T4的类型和第一发光控制晶体管T5的类型不同。
例如，在图4A所示的示例中，该数据写入晶体管T4为P型晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。该第一发光控制晶体管T5为N型晶体管，例如，采用N型晶体管时，其可以采用IGZO作为薄膜晶体管的有源层，以减小驱动晶体管的尺寸以及防止漏电流。例如，N型晶体管响应于高电平信号开启，以下实施例与此相同，不再赘述。例如，该第一复位晶体管T1、第二复位晶体管T7、补偿晶体管T2、第二发光控制晶体管T6均为P型晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。
例如，在图5A所示的示例中，该数据写入晶体管T4和补偿晶体管T2均为N型晶体管，该第一发光控制晶体管T5为P型晶体管。例如，该第一复位晶体管T1、第二复位晶体管T7、第二发光控制晶体管T6均为P型晶体管。
例如，在图6A所示的示例中，该数据写入晶体管T4为P型晶体管，该第一发光控制晶体管T5和补偿晶体管T2均为N型晶体管。例如，该第一复位晶体管T1、第二复位晶体管T7、第二发光控制晶体管T6均为P型晶体管。
例如，在图7A所示的示例中，该数据写入晶体管T4为P型晶体管，该第一复位晶体管T1、第一发光控制晶体管T5和补偿晶体管T2均为N型晶体管。例如，该第二复位晶体管T7、第二发光控制晶体管T6均为P型晶体管。
例如，上述各个实施例中的N型晶体管的宽长比可以是2.5/3.5，例如，其宽度范围在1.5～4μm(微米)，例如，可以是1.5、2、2.5、3、3.5、4等，长度范围在3～5μm，例如，可以是3、3.5、4、4.5、5等；P型晶体管的宽长比可以是2.2/3.0(驱动晶体管除外)，例如，其宽度范围在1.5～4μm，例如，可以是1.5、2、2.5、3、3.5、4等，长度范围在2～6μm，例如可以是2、3、4、5、6等，本公开的实施例对此不作限制。
如图12、14所示，该像素电路需要在数据写入及补偿阶段导通驱动晶体管T3，因此，初始信号端Vinit与第一电源端VDD的电压差Vinit-VDD需要小于驱动晶体管T3的阈值电压Vth，其中，Vinit为初始信号端的电压，VDD为第一电源线VDD的电压。其中，Vinit可以为-2～-6V(伏特)，例如，-2V、-3V、-4V、-5V、-6V等。Vinit-VDD可以小于a*Vth，a可以为2～7，例如，a可以为2、4、6、7；Vth可以为-2～-5V，例如-2V、-3V、-5V等。VDD可以大于1.5倍的Vth，例如，VDD可以为Vth的1.6倍、1.8倍、2倍等。
该显示面板可以包括多个阵列分布的像素驱动电路P，多条第一电源线VDD均可以用于提供第一电压。一部分第一电源线VDD沿列方向延伸，另一部分第一电源线VDD沿行方向延伸，相邻两行像素电路可以与同一行向延伸的第一电源线连接，该第一电源线VDD可以位于上述相邻两行像素电路之间，沿列方向延伸的第一电源线可以连接与其相交的多条沿行方向延伸的第一电源线相交，从而多条电源线可以形成网格结构。其中，沿列方向延伸的第一电源线可以位于红色像素电路所在的区域内。此外，在同一像素行中，相邻列的两个像素电路可以镜像设置，以方便布线。
例如，当第一复位信号和第二复位信号不同时，例如，第二复位信号的绝对值大于驱动子电路的阈值电压的1.5倍。在一些示例性实施方式中，第二复位信号的幅值大于0。示例性的，第二复位信号一般为4～10V的复位电压，第一复位信号一般为-2V～-6V的复位电压。
例如，第一电压的电压值可以大于0V而小于或等于5V，例如，第一电压的电压值可以为4.6V，但不以此为限。例如，复位电压可以为直流电压， 复位电压的电压值可以在大于或等于-7V而小于或等于0V；例如，复位电压的电压值可以为-6V、-5V、-4V、-3V或-2V，但不以此为限。
在本公开至少一实施例中，驱动电路中的驱动晶体管的阈值电压Vth可以大于或等于-5V而小于或等于-2V，例如，Vth可以大于或等于-4V而小于或等于-2.5V；例如，Vth可以为-4V、-3.5V、-3V或-2.5V，但不以此为限。
例如，复位信号的电压值的绝对值可以大于阈值电压的绝对值的1.5倍，以保证在较短时间内能够快速达到偏置效果。例如，复位信号的电压值的绝对值可以大于阈值电压的绝对值的2倍、2.5倍或3倍，但不以此为限。
第二复位晶体管T7的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等。
第一发光控制晶体管T8的宽长比W/L可以大于第一复位晶体管T1的宽长比W/L，如此可以提升N2节点复位能力。
本公开实施例中，第一发光控制晶体管T8的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等；第一复位晶体管T1的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等。
下面结合图4B所示的信号时序图，对图4A所示的像素电路10的工作原理进行说明。
如图4A所示，每一帧图像的显示过程包括3个阶段，分别为初始化阶段t1、数据写入及补偿阶段t2和发光阶段t3，图中示出了每个阶段中各个信号的时序波形。
需要说明的是，图8A为图4A中所示的像素电路处于初始化阶段t1时的示意图，图8B为图4A中所示的像素电路处于数据写入及补偿阶段t2时的示意图，图8C为图4A中所示的像素电路处于发光阶段t3时的示意图。另外图8A至图8C中用虚线标识的晶体管均表示在对应阶段内处于截止状态，图8A至图8C中带箭头的虚线表示像素电路在对应阶段内的电流方向。图8A至图8C中所示的晶体管均以驱动晶体管T3和第一复位晶体管T1为N型晶体管，其他晶体管为P型晶体管为例进行说明，即各个N型晶体管的栅极在接入高 电平时导通，而在接入低电平时截止，各个P型晶体管的栅极在接入低电平时导通，而在接入高电平时截止。以下实施例与此相同，不再赘述。
在初始化阶段t1，通过第一扫描信号线输入第一扫描信号的第一电平(例如，图5B所示的低电平)的以开启第一发光控制电路400，将第一电压VDD通过开启的第一发光控制电路400施加至驱动电路100的第一端；输入复位信号以开启复位电路700，将复位电压通过开启的复位电路700施加至发光元件OLED的第一端和驱动电路100的控制端130。
如图8A所示，在初始化阶段t1，由于第一复位晶体管T1和第二复位晶体管T7是P型晶体管，第一发光控制晶体管T5是N型晶体管，第一复位晶体管T1和第二复位晶体管T7被复位信号的低电平导通，第一发光控制晶体管T5被第一扫描信号的低电平导通；同时，补偿晶体管T2和数据写入晶体管T4被第一扫描信号的高电平截止，第二发光控制晶体管T6被发光控制信号的高电平截止。
如图5所示，在初始化阶段t1，形成一条第一节点N1和第四节点N4的复位路径(如图8A中带箭头的虚线所示)以及第二节点N2的复位路径(如图8A中带箭头的虚线所示)。所以在此阶段，存储电容Cst以及驱动晶体管T3的栅极通过第一复位晶体管T1放电，驱动晶体管T3和发光元件OLED通过第二复位晶体管T7放电，发光元件OLED通过第二复位晶体管T7放电，从而将第一节点N1和发光元件OLED(即第四节点N4)复位。第二节点N2的电压通过第一发光控制晶体管T5充电，从而将第二节点N2的电压稳定在稳定电压。所以，经过初始化阶段t1后第一节点N1、第三节点N3以及第四节点N4的电位为复位电压Vinit(低电平信号，例如可以接地或为其他低电平信号)，第二节点的电位为第一电压VDD。在此阶段，由于驱动晶体管T3和第一发光控制晶体管T5导通，第二节点N2保持稳定的电位，此将驱动晶体管的Vg、Vs电压同时进行复位，使驱动晶体管处于固定偏置的开启状态(即On-Bias状态)，因此不论前帧显示图像的数据电压为黑或是白，驱动晶体管皆由On-Bias状态开始进行当前帧数据电压的写入及补偿阶段t2，故可改善短期残像问题。
经过初始化阶段t1后，第一节点N1的电位为复位电压Vinit，第二节点N2的电位为VDD。在初始化阶段t1，存储电容Cst被复位，使存储在存储电 容Cst中的电压放电，从而使后续阶段中的数据信号可以被更迅速、更可靠地存储在存储电容Cst中；同时，发光元件OLED(即第四节点N4)也被复位，从而可以使发光元件OLED在发光阶段t3之前显示为黑态不发光，改善采用上述像素电路的显示装置的对比度等显示效果。
在数据写入及补偿阶段t2，通过第一扫描信号线G1输入第一扫描信号的第二电平以开启数据写入电路200，通过第二扫描信号线G2输入第二扫描信号以开启补偿存储电路300，通过数据线DL～Dm输入数据信号，将数据信号通过开启的数据写入电路200写入驱动电路100的第一端110以开启驱动电路100，通过开启的补偿存储电路300存储数据信号，且通过开启的补偿存储电路300对驱动电路100进行补偿。
如图4A和图8B所示，在数据写入及补偿阶段t2，数据写入晶体管T4被第一扫描信号的第二电平(例如，图5B所示的高电平)导通，补偿晶体管T2被第二扫描信号的高电平(在该实例中，第一扫描信号和第二扫描信号为同一信号)导通，同时，第一发光控制晶体管T5被第一扫描信号的高电平截止，第二发光控制晶体管T6被发光控制信号的高电平截止，第一复位晶体管T1和第二复位晶体管T7被复位信号的高电平截止。
如图8B所示，在数据写入及补偿阶段t2，形成一条数据写入及补偿路径(如图8B中带箭头的虚线所示)，数据信号经过数据写入晶体管T4、驱动晶体管T3和补偿晶体管T2后对第一节点N1进行充电(即对存储电容Cst充电)，也就是说第一节点N1的电位升高。容易理解，第二节点N2的电位保持为Vdata，同时根据驱动晶体管T3的自身特性，当第一节点N1的电位增大到Vdata+Vth时，驱动晶体管T3截止，充电过程结束。需要说明的是，Vdata表示数据信号的电压值，Vth表示第一晶体管的阈值电压，由于在本实施例中，驱动晶体管T3是以P型晶体管为例就行说明的，所以此处阈值电压Vth可以是个负值。
经过数据写入阶段2后，第一节点N1和第三节点N3的电位均为Vdata+Vth，也就是说将带有数据信号和阈值电压Vth的电压信息存储在了存储电容Cst中，以用于后续在发光阶段时，提供灰度显示数据和对驱动晶体管T3自身的阈值电压进行补偿。
在发光阶段t3，通过第一扫描信号线G1输入第一扫描信号以开启第一发 光控制电路400和驱动电路100，通过发光控制信号线EM输入发光控制信号以开启第二发光控制电路600，将驱动电流通过开启的第一发光控制电路400、驱动电路100和第二发光控制电路600施加至发光元件500以使其发光。
如图4A和图8C所示，在发光阶段t3，第一发光控制晶体管T5被第一扫描信号的高电平导通，第二发光控制晶体管T6被发光控制信号的低电平导通；同时，数据写入晶体管T4被第一扫描信号的高电平截止，补偿晶体管T2被第二扫描信号(即第一扫描信号)的高电平截止，第一复位晶体管T1和第二复位晶体管T7被复位信号的低电平截止。同时，第一节点N1的电位Vdata+Vth，第二节点N2的电位为VDD，所以在此阶段驱动晶体管T3也保持导通。
如图8C所示，在发光阶段t3，形成一条驱动发光路径(如图8C中带箭头的虚线所示)。发光元件OLED可以在流经驱动晶体管T3的驱动电流的作用下发光。
具体地，流经发光元件OLED的驱动电流I L1的值可以根据下述公式得出：
I L1＝K(V GS-Vth) 2
＝K[(Vdata+Vth-VDD)-Vth] 2
＝K(Vdata-VDD) 2
其中，K＝W*C OX*U/L。
在上述公式中，Vth表示驱动晶体管T3的阈值电压，V GS表示驱动晶体管T3的栅极和源极(这里为第一极)之间的电压，K为与驱动晶体管本身相关的一常数值。从上述I L1的计算公式可以看出，流经发光元件OLED的驱动电流I L1不再与驱动晶体管T3的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为驱动晶体管T3)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流I L1的影响，从而可以改善采用其的显示装置的显示效果。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第 二极。
另外，需要说明的是，图4A中所示的像素电路10中的晶体管是以第一发光控制晶体管T5为N型晶体管，其它晶体管为P型晶体管为例进行说明的，此时，第一极可以是漏极，第二极可以是源极。如图5所示，该像素电路10中的发光元件OLED的阴极和第二电源线VSS连接以接收第二电压。例如，在一个显示面板中，当图5中所示的像素电路10呈阵列排布时，发光元件OLED的阴极可以电连接到同一个电压端，即采用共阴极连接方式。
例如，第一扫描信号线和第二扫描信号线相同或不同，所述第一扫描信号和所述第二扫描信号相同或不同。
例如，在图4A和图5A所示的示例中，第一扫描信号线和第二扫描信号线相同，均表示为G1，对应地，第一扫描信号和第二扫描信号相同。
例如，在图6A和图7A所示的示例中，当第一扫描信号和第二扫描信号不同时，数据写入晶体管T4的类型和补偿晶体管T2的类型不同，补偿晶体管T2的类型和第一发光控制晶体管T5的类型相同，例如，数据写入晶体管T4为P型晶体管，补偿晶体管T2和第一发光控制晶体管T5是N型晶体管。
例如，第一复位信号线和第二复位信号线相同或不同，第一复位信号和第二复位信号相同或不同。
例如，在图4A、5A、6A所示的示例中，第一复位晶体管T1和第二复位晶体管T7的类型相同，例如均为P型晶体管，第一复位信号线和第二复位信号线相同，表示为RST，对应地，第一复位信号和第二复位信号也相同。
例如，在图7A所示的示例中，第一复位晶体管T1和第二复位晶体管T7的类型不同，例如第一复位晶体管T1为N型晶体管，第二复位晶体管T7为P型晶体管，第一复位信号线RST1和第二复位信号线RST2不同，例如，如图7B所示，第一复位信号和第二复位信号为相反的信号。
图5B为图5A所示的像素电路的工作时序图；图6B为图6A所示的工作时序图，图7B为图7A所示的工作时序图，图5A、图6A和图7A所示的像素电路的工作过程和图4A所示的像素电路的工作过程类似，仅根据晶体管类型的调整对时序做了对应调整，具体可参考图4A所示的像素电路的工作过程的介绍，在此不再赘述。
在本公开上述各实施例中，均利用了第一发光控制晶体管T5实现在初始 阶段对第二节点N2的电压的控制，使第二节点N2的电压在初阶段保持稳定的电位，从而可在不增加额外的晶体管的情形下改善短期残像的问题。
图9A为图4A或图5A所示的像素电路中的第一发光控制晶体管、驱动晶体管和第二发光控制晶体管的截面图。图9B和图9I为图4A或图5A所示的像素电路中的第一发光控制晶体管、数据写入晶体管和补偿晶体管的截面图。
例如，如图9A所示，第一发光控制晶体管T5的栅极包括位于不同层的第一子栅极G51和第二子栅极G52，第一发光控制晶体管的有源层A5位于第一子栅极G51和第二子栅极G52之间。
例如，如图9B所示，第一子栅极G51所在层位于数据写入晶体管T4的栅极G4所在层和第二子栅极G52所在层之间。
第一发光控制晶体管T5的第一子栅极G51和第二子栅极以及数据写入晶体管T4的栅极G4分别通连接电极E与第一扫描信号线G1(图9B中未示出)连接，连接电极E所在层位于第二子栅极G52所在层远离第一子栅极G51所在层和数据写入晶体管T4的栅极G4所在层的一侧。
例如，如图9A所示，在衬底基板1000上依次形成绝缘层1001至1008，以及位于绝缘层之间的依次形成的第一半导体层、第一栅极层、第二栅极层、第二半导体层、第三栅极层、第一导电层、第二导电层和第三导电层。
例如，发光元件的阳极510位于第三导电层，且通过贯穿绝缘层1008的过孔与第六晶体管T6的第二极连接，例如第六晶体管T6的第二极位于第二导电层或第一导电层，本公开的实施例对此不作限制。
例如，如图9A-9F所示，第一电源线VDD可以位于第二导电层；如图9G-9H所示，第一电源线VDD还可以位于第一导电层，本公开的实施例对此不作限制。
例如，当第一电源线VDD位于第二导电层时，可以通过第一导电层与第一发光控制晶体管T5的第一极连接，第一发光控制晶体管T5的第二极通过位于第一导电层的连接电极与驱动晶体管T3的第一极连接，驱动晶体管T3的有源层A3与第二发光控制晶体管T6的有源层A6一体形成，且位于第一半导体层。
例如，第二子栅极G52位于第三栅极层，第一子栅极G51位于第二栅极 层，其余各个晶体管的栅极(例如，G4、G2、G3、G6)位于第一栅极层。例如，第一发光控制晶体管的有源层A5位于第二半导体层，其余各个晶体管的有源层(例如，A4、A2、A3、A6)位于第一半导体层。
例如，连接电极E可通过图9B所示的方式与各个栅极(G51、G52、G4、G2)连接，例如，如图9B所示，通过位于连接电极和第二子栅极G52之间的第一导电层和/或第二导电层上的电极将连接电极和各个栅极连接起来，可以形成缓冲，避免需要较大的过孔。
当然，也可通过图9C和图9D中所示的方式将各个栅极(G51、G52、G4、G2)分别通过1个过孔与连接电极E连接，本公开的实施例对此不作限制。
例如，如图9E和9F所示，该连接电极可以与发光元件的阳极510同层设置，也可以与第一电源线VDD同层设置(如图9B至图9D所示)；例如，如图9I所示，该连接电极还可以位于第一导电层，本公开的实施例对此不作限制，只要能将数据写入晶体管T4和第一发光控制晶体管T5连起来即可，但第一发光控制晶体管T5与补偿晶体管T2和数据写入晶体管T4的栅极不处于同一层，例如，如图9I所示，可以使用位于第一导电层的连接电极E将第一发光控制晶体管T5的第一子栅极G51和第二子栅极G52与数据写入晶体管T4的栅极G4连接，再通过跳线连接的方式将数据写入晶体管T4的栅极G4与补偿晶体管T2的栅极G2电连接在一起，本公开的实施例对此不作限制。需要注意的是，图9I中未示出该跳线连接部分，具体可参考本领域的设计，在此不再赘述。
例如，如图9G所示，该连接电极E还可以位于第二导电层，并通过贯穿绝缘层1007的过孔与第一导电层上的电极连接，进而通过该第一导电层上的电极与其他各个栅极连接，也可以直接通过各个绝缘层的过孔与各个栅极连接(如图9H所示)。在该示例中，第一电源线VDD位于第一导电层。
例如，该衬底基板1000可以采用例如玻璃、塑料、石英或其他适合的材料，本公开的实施例对此不作限制。
例如，绝缘层1001-1008的材料可以包括例如SiNx、SiOx、SiNxOy等无机绝缘材料、例如有机树脂等有机绝缘材料，或其它适合的材料，本公开的实施例对此不作限定。
例如，半导体层的材料可以包括氧化物半导体、有机半导体或非晶硅、多晶硅等，例如，氧化物半导体包括金属氧化物半导体(例如氧化铟镓锌(IGZO))，多晶硅包括低温多晶硅或者高温多晶硅等，本公开的实施例对此不作限定。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域，本公开的实施例对此不作限制。
例如，上述第一导电层、第二导电层、第三导电层的材料可以包括钛、钛合金、铝、铝合金、铜、铜合金或其他任意适合的复合材料，本公开的实施例对此不作限定。例如，第一栅极层和第二栅极层的材料可以与第一导电层的材料相同，在此不再赘述。
本公开至少一个实施例还提供一种显示面板，包括阵列布置的多个像素单元，该多个像素单元每个包括本公开任一实施例提供的像素电路。
图10为本公开一实施例提供的一种显示面板的示意框图。如图10所示显示面板11设置在显示装置1中，并与栅极驱动器12、定时控制器13和数据驱动器14电连接。该显示面板11包括根据多条扫描线GL和多条数据线DL交叉限定的像素单元P；栅极驱动器12用于驱动多条扫描线GL；数据驱动器14用于驱动多条数据线DL；定时控制器13用于处理从显示装置1外部输入的图像数据RGB、向数据驱动器14提供处理的图像数据RGB以及向栅极驱动器12和数据驱动器14输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器12和数据驱动器14进行控制。
例如，该显示面板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路10。例如，包括图3所示像素电路10。如图10所示，显示面板11还包括多条扫描线GL和多条数据线DL。例如，该多条扫描线对应连接到每行像素单元的像素电路10中的数据写入电路200以提供第一扫描信号，并且该多条扫描线还对应连接到每行像素单元的像素电路10中的补偿存储电路300和复位电路700以将第二扫描信号作为复位信号。
例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图10所示，每个像素单元P连接到多条扫描线GL(分别提供第一扫描信号、第二扫描信号、第一复位信号、第二复位信号以及发光控制信号)、一条数据线DL、用于提供第一电压的第一电源线、用于提供第二电压的第二电源线以及用于提供复位电压的复位电压线。例如，第一电源线或第二电源线可以用 相应的板状公共电极(例如公共阳极或公共阴极)替代。需要说明的是，在图10中仅示出了部分的像素单元P、扫描线GL、数据线DL。需要注意的是，在本公开实施例中，由于第二扫描信号线提供的第二扫描信号可以和第一扫描信号相同，第一复位信号可以和第二复位信号相同，所以每个像素单元P可以仅连接到3条扫描线GL。需要注意的是，以下实施例与此相同，不再赘述。
例如，在一些示例中，该多个像素单元P排列为多行，每一行像素单元P的像素电路的补偿存储电路300、数据写入电路200以及第一发光控制电路400连接到同一条扫描线GL，本公开的实施例对此不作限制。例如，每一列的数据线DL和本列像素电路10中的数据写入电路200连接以提供数据信号。
例如，栅极驱动器12根据源自定时控制器13的多个扫描控制信号GCS向多个扫描线GL提供多个选通信号。多个选通信号包括第一扫描信号、第二扫描信号、发光控制信号以及复位信号。这些信号通过多个扫描线GL提供给每个像素单元P。
例如，数据驱动器14使用参考伽玛电压根据源自定时控制器13的多个数据控制信号DCS将从定时控制器13输入的数字图像数据RGB转换成数据信号。数据驱动器14向多条数据线DL提供转换的数据信号。
例如，定时控制器13对外部输入的图像数据RGB进行处理以匹配显示面板11的大小和分辨率，然后向数据驱动器14提供处理的图像数据。定时控制器13使用从显示装置外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器13分别向栅极驱动器12和数据驱动器14提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器12和数据驱动器14的控制。
例如，数据驱动电器14可以与多条数据线DL连接，以提供数据信号Vdata；同时还可以与多条第一电源线、多条第二电源线和多条复位电压线连接以分别提供第一电压、第二电压和复位电压。
例如，栅极驱动器12和数据驱动器14可以实现为半导体芯片。该显示装置1还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，本实施例提供的显示面板11可以应用于电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
关于显示面板11的技术效果可以参考本公开的实施例中提供的像素电路10的技术效果，这里不再赘述。
本公开的实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的像素电路10。例如，在图2所示的示例中，该驱动方法包括复位阶段、数据写入及补偿阶段以及发光阶段。
在复位阶段，通过第一扫描信号线输入第一扫描信号的第一电平的以开启第一发光控制电路，将第一电压通过开启的第一发光控制电路施加至驱动电路的第一端。
在数据写入及补偿阶段，通过第一扫描信号线输入第一扫描信号的第二电平以开启数据写入电路，通过第二扫描信号线输入第二扫描信号以开启补偿存储电路，通过数据线输入数据信号，将数据信号通过开启的数据写入电路写入驱动电路的第一端以开启驱动电路，通过开启的补偿存储电路存储数据信号，且通过开启的补偿存储电路对驱动电路进行补偿。
在发光阶段，通过第一扫描信号线输入第一扫描信号以开启第一发光控制电路和驱动电路，通过发光控制信号线输入发光控制信号以开启第二发光控制电路，将驱动电流通过开启的第一发光控制电路、驱动电路和第二发光控制电路施加至发光元件以使其发光。
例如，在图3所示的示例中，在像素电路还包括复位电路的情况下，该驱动方法包括如下操作：
在复位阶段，输入复位信号以开启复位电路，将复位电压通过开启的复位电路施加至发光元件的第一端和驱动电路的控制端。
需要说明的是，关于该驱动方法的详细描述可以参考本公开的实施例中对于像素电路10的工作原理的描述，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组 合以得到新的实施例。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (17)

  1. 一种像素电路，包括：驱动电路、数据写入电路、补偿存储电路、第一发光控制电路和第二发光控制电路；其中，
    所述驱动电路包括控制端、第一端和第二端，且配置为控制流经所述第一端和所述第二端的用于驱动所述发光元件发光的驱动电流；
    所述数据写入电路与所述驱动电路的第一端和第一扫描信号线连接，且配置为响应于所述第一扫描信号线提供的第一扫描信号将数据信号写入所述驱动电路的第一端；
    所述补偿存储电路与所述驱动电路的控制端以及第二端连接且与第二扫描信号线和第一电源线连接，且配置为响应于所述第二扫描信号线提供的第二扫描信号存储所述数据写入电路写入的所述数据信号并对所述驱动电路进行补偿；
    所述第一发光控制电路与所述驱动电路的第一端、所述第一电源线以及所述第一扫描信号线连接，且配置为响应于所述第一扫描信号线提供的所述第一扫描信号将所述第一电源线的第一电压施加至所述驱动电路的第一端，其中，所述数据写入电路和所述第一发光控制电路在所述第一扫描信号的控制下导通状态相斥；
    所述第二发光控制电路与所述驱动电路的第二端、发光控制信号线以及所述发光元件的第一端连接，且配置为响应于所述发光控制信号线提供的发光控制信号将所述驱动电流施加至所述发光元件。
  2. 根据权利要求1所述的像素电路，其中，所述驱动电路包括驱动晶体管；
    所述驱动晶体管的栅极作为所述驱动电路的控制端，所述驱动晶体管的第一极作为所述驱动电路的第一端，所述驱动晶体管的第二极作为所述驱动电路的第二端。
  3. 根据权利要求1或2所述的像素电路，其中，所述数据写入电路包括数据写入晶体管；
    所述数据写入晶体管的栅极和所述第一扫描信号线连接以接收所述第一扫描信号，所述数据写入晶体管的第一极和数据线连接以接收所述数据信号， 所述数据写入晶体管的第二极和所述驱动电路的第一端连接。
  4. 根据权利要求3所述的像素电路，其中，所述第一发光控制电路包括第一发光控制晶体管；
    所述第一发光控制晶体管的栅极和所述第一扫描信号线连接以接收所述第一扫描信号，所述第一发光控制晶体管的第一极和所述第一电源线连接以接收所述第一电压，所述第一发光控制晶体管的第二极和所述驱动电路的第一端连接。
  5. 根据权利要求4所述的像素电路，其中，所述数据写入晶体管的类型和所述第一发光控制晶体管的类型不同。
  6. 根据权利要求4或5所述的像素电路，其中，所述第一发光控制晶体管为N型晶体管，所述数据写入晶体管为P型晶体管。
  7. 根据权利要求6所述的像素电路，其中，所述第一发光控制晶体管的栅极包括位于不同层的第一子栅极和第二子栅极，所述第一发光控制晶体管的有源层位于所述第一子栅极和所述第二子栅极之间，
    所述第一子栅极所在层位于所述数据写入晶体管的栅极所在层和所述第二子栅极所在层之间，
    所述第一发光控制晶体管的第一子栅极和第二子栅极以及所述数据写入晶体管的栅极分别通过连接电极与所述第一扫描信号线连接，所述连接电极所在层位于所述第二子栅极所在层远离所述第一子栅极所在层和所述数据写入晶体管的栅极所在层的一侧。
  8. 根据权利要求4-7任一所述的像素电路，其中，所述补偿存储电路包括补偿晶体管和存储电容；
    所述补偿晶体管的栅极和所述第二扫描信号线连接以接收所述第二扫描信号，所述补偿晶体管的第一极和所述驱动电路的第二端连接，所述补偿晶体管的第二极和所述驱动电路的控制端连接；
    所述存储电容的第一极和所述驱动电路的控制端连接，所述存储电容的第二极和所述第一电源线连接。
  9. 根据权利要求1-8任一所述的像素电路，其中，所述第一扫描信号线和所述第二扫描信号线相同或不同，所述第一扫描信号和所述第二扫描信号相同或不同。
  10. 根据权利要求8所述的像素电路，其中，当所述第一扫描信号和所述第二扫描信号不同时，所述数据写入晶体管的类型和所述补偿晶体管的类型不同，所述补偿晶体管的类型和所述第一发光控制晶体管的类型相同。
  11. 根据权利要求1-10任一所述的像素电路，还包括复位电路，其中，
    所述复位电路与初始电压端、所述发光元件的第一端和所述驱动电路的控制端连接，且配置为响应于复位信号将所述初始电压端提供的复位电压施加至所述发光元件的第一端和所述驱动电路的控制端。
  12. 根据权利要求11所述的像素电路，其中，所述复位电路包括第一复位晶体管和第二复位晶体管；
    所述第一复位晶体管的栅极和第一复位信号线连接以接收第一复位信号作为所述复位信号，所述第一复位晶体管的第一极和所述初始电压端连接以接收所述复位电压，所述第一复位晶体管的第二极和所述驱动电路的控制端连接；
    所述第二复位晶体管的栅极和第二复位信号线连接以接收第二复位信号作为所述复位信号，所述第二复位晶体管的第一极和所述初始电压端连接以接收所述复位电压，所述第二复位晶体管的第二极和所述发光元件的第一端连接。
  13. 根据权利要求12所述的像素电路，其中，所述第一复位信号线和所述第二复位信号线相同或不同，所述第一复位信号和所述第二复位信号相同或不同。
  14. 根据权利要求1-13任一所述的像素电路，其中，所述第二发光控制电路包括第二发光控制晶体管；
    所述第二发光控制晶体管的栅极和所述发光控制线连接以接收所述发光控制信号，所述第二发光控制晶体管的第一极和所述驱动电路的第二端连接，所述第二发光控制晶体管的第二极和所述发光元件的第一端连接。
  15. 一种如权利要求1所述的像素电路的驱动方法，包括：复位阶段、数据写入及补偿阶段以及发光阶段；其中，
    在所述复位阶段，通过所述第一扫描信号线输入所述第一扫描信号的第一电平的以开启所述第一发光控制电路，将所述第一电压通过开启的所述第一发光控制电路施加至所述驱动电路的第一端；
    在所述数据写入及补偿阶段，通过所述第一扫描信号线输入所述第一扫描信号的第二电平以开启所述数据写入电路，通过所述第二扫描信号线输入所述第二扫描信号以开启所述补偿存储电路，通过数据线输入所述数据信号，将所述数据信号通过开启的所述数据写入电路写入所述驱动电路的第一端以开启所述驱动电路，通过开启的所述补偿存储电路存储所述数据信号，且通过开启的所述补偿存储电路对所述驱动电路进行补偿；
    在所述发光阶段，通过所述第一扫描信号线输入所述第一扫描信号以开启所述第一发光控制电路和所述驱动电路，通过所述发光控制信号线输入所述发光控制信号以开启所述第二发光控制电路，将所述驱动电流通过开启的所述第一发光控制电路、所述驱动电路和所述第二发光控制电路施加至所述发光元件以使其发光。
  16. 根据权利要求15所述的驱动方法，其中，所述像素电路还包括复位电路，其中，
    所述复位电路与初始电压端、所述发光元件的第一端和所述驱动电路的控制端连接，且配置为响应于复位信号将复位电压施加至所述发光元件的第一端和所述驱动电路的控制端；
    所述方法还包括：
    在所述复位阶段，输入所述复位信号以开启所述复位电路，将所述复位电压通过开启的所述复位电路施加至所述发光元件的第一端和所述驱动电路的控制端。
  17. 一种显示面板，包括如权利要求1-14任一所述的像素电路。
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