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WO2023245438A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023245438A1
WO2023245438A1 PCT/CN2022/100197 CN2022100197W WO2023245438A1 WO 2023245438 A1 WO2023245438 A1 WO 2023245438A1 CN 2022100197 W CN2022100197 W CN 2022100197W WO 2023245438 A1 WO2023245438 A1 WO 2023245438A1
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WO
WIPO (PCT)
Prior art keywords
transistor
control
scan
area
signal
Prior art date
Application number
PCT/CN2022/100197
Other languages
English (en)
French (fr)
Inventor
刘松
周洋
白露
代俊秀
李灵通
魏立恒
陈天赐
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP22947218.8A priority Critical patent/EP4421791A4/en
Priority to US18/029,356 priority patent/US20240363066A1/en
Priority to PCT/CN2022/100197 priority patent/WO2023245438A1/zh
Priority to CN202280001848.9A priority patent/CN117716414A/zh
Publication of WO2023245438A1 publication Critical patent/WO2023245438A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G2300/0421—Structural details of the set of electrodes
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Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and specifically relates to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including: a substrate and a circuit structure layer disposed on the substrate, where the circuit structure layer includes: a pixel circuit, a scan driving circuit, a control driving circuit and a buffer driving circuit;
  • the pixel circuit includes: a node reset transistor, a write transistor, a reset signal line, a scan signal line and a control signal line.
  • the reset signal line is connected to the control electrode of the node reset transistor, and the scan signal line is connected to the write The control electrode connection of the transistor;
  • the scanning signal lines of the pixel circuits in the first to Nth rows are electrically connected to the scan driving circuit, and the control signal lines of the pixel circuits in the first to Nth rows are electrically connected to the control driving circuit. connect;
  • it includes: a display area and a non-display area, wherein the non-display area includes: a frame area surrounding the display area and a bounding area located on the side of the frame area away from the display area. defined area;
  • the scan driving circuit, control driving circuit and buffer driving circuit are located in the display area and/or non-display area;
  • the scan drive circuit, the control drive circuit and the buffer drive circuit are located in the non-display area, the scan drive circuit and the control drive circuit are located on the first side and the second side of the display area opposite to each other, so
  • the buffer driving circuit is located on the third side or the fourth side of the display area, the third side is located on the side of the display area away from the binding area, and the fourth side is located on the display area close to the binding area. side.
  • the pixel circuit further includes: a light-emitting driving circuit, the pixel circuit further includes: a light-emitting transistor and a light-emitting signal line; the light-emitting signal line is electrically connected to the control electrode of the light-emitting transistor; the light-emitting driving circuit is located at the The control drive circuit is on the side away from the display area;
  • the light-emitting signal lines of the first row to the N-th row of pixel circuits are electrically connected to the light-emitting driving circuit;
  • the difference between the start time of the effective level signal of the light-emitting signal line of the pixel circuit and the end time of the effective level signal of the reset signal line is greater than the threshold time and the effective level of the signal of the scanning signal line.
  • the pixel circuit also includes: a test circuit and a multiplexing circuit; the pixel circuit also includes: a data signal line extending along a second direction, where the first direction intersects the second direction, and the third One direction is the extension direction of the reset signal line, scanning signal line and control signal line;
  • the data signal line is electrically connected to the first pole of the write transistor, the test circuit and the multiplexing circuit respectively;
  • the test circuit is located on the first side and the third side of the display area, and the multiplexing circuit is located on the first side and/or the second side of the display area.
  • the buffer driving circuit when the reset signal lines of the K+1th to Nth row pixel circuits are electrically connected to the scan driving circuit, includes: K cascaded buffer shift registers ;
  • the scan drive circuit includes: N cascaded scan shift registers;
  • the control drive circuit includes: N/2 cascaded control shift registers, and the output end of the last buffer shift register is connected to the first The input terminal of the stage scan shift register is electrically connected;
  • the a-th level buffer shift register is electrically connected to the reset signal line of the a-th row pixel circuit, 1 ⁇ a ⁇ K;
  • the b-th stage scanning shift register is electrically connected to the scanning signal line of the b-th row pixel circuit, 1 ⁇ b ⁇ N;
  • the c-th stage scanning shift register is electrically connected to the reset signal line of the K+c-th row pixel circuit, 1 ⁇ c ⁇ N-K;
  • the first stage to the N-Kth scan shift register includes: a first signal output line and a second signal output line connected to each other, and the second signal output line is located at the first signal output line.
  • the output line is away from the side of the substrate;
  • the first signal output line of the c-th scan shift register is electrically connected to the scan signal line of the c-th row pixel circuit, and the second signal output line of the c-th scan shift register is electrically connected to the reset signal of the K+c-th row pixel circuit. wired electrical connection;
  • the first to K-th level buffer shift registers include: a third signal output line arranged on the same layer as the second signal output line, the third signal of the a-th level buffer shift register The output line is electrically connected to the reset signal line of the a-th row pixel circuit;
  • the N-K+1 to Nth level scan shift registers include: a fourth signal output line arranged on the same layer as the first signal output line; a fourth signal output line of the sth level scan shift register Electrically connected to the scanning signal line of the s-th row pixel circuit, N-K+1 ⁇ s ⁇ N;
  • the third signal output line and the fourth signal output line are located between the scan driving circuit and the display area.
  • the buffer drive circuit when the reset signal lines of the K+1th to Nth row pixel circuits are electrically connected to the control drive circuit, includes: K/2 cascaded buffer shifters. bit register; the scan drive circuit includes: N cascaded scan shift registers; the control drive circuit includes: N/2 cascaded control shift registers; the output end of the last level buffer shift register and The input terminal of the first stage control shift register is electrically connected;
  • the i-th level buffer shift register is electrically connected to the reset signal lines of the 2i-1th row pixel circuit and the 2i-th row pixel circuit respectively, 1 ⁇ i ⁇ K/2;
  • the b-th stage scanning shift register is electrically connected to the scanning signal line of the b-th row pixel circuit, 1 ⁇ b ⁇ N;
  • the nth stage control shift register is electrically connected to the reset signal lines of the K+2n-1th row pixel circuit and the K+2nth row pixel circuit respectively, 1 ⁇ n ⁇ (N-K)/2.
  • the first to (N-K)/2nd stage control shift registers include: a first signal output line and a second signal output line connected to each other, and the second signal output line is located at The first signal output line is on a side away from the substrate;
  • the first signal output line of the n-th level control shift register is electrically connected to the control signal line of the 2n-1th row pixel circuit and the 2n-th row pixel circuit respectively, and the second signal output line of the n-th level control shift register is respectively connected to The reset signal lines of the K+2n-1th row pixel circuit and the K+2nth row pixel circuit are electrically connected;
  • first signal output line and the second signal output line are located between the control drive circuit and the display area, and the extension direction of the first signal output line is in the same direction as the second signal output line.
  • the extension directions intersect.
  • the first to K/2th level buffer shift registers include: a third signal output line arranged on the same layer as the second signal output line, the third signal of the i-th level buffer shift register The output lines are electrically connected to the reset signal lines of the 2i-1th row pixel circuit and the 2ith row pixel circuit respectively;
  • the third signal output line and the fourth signal output line are located between the control driving circuit and the display area.
  • the light-emitting driving circuit includes: an N/2-level light-emitting shift register;
  • the shape of the boundary of the display area includes: a rounded rectangle, the rounded rectangle includes: four rounded corners and four borders, the border area includes: located outside the first rounded corner The first rounded corner area, the second rounded corner area located outside the second rounded corner, the third rounded corner area located outside the third rounded corner, the fourth rounded corner area located outside the fourth rounded corner, located at the first border A first frame area outside, a second frame area located outside the second frame, a third frame area located outside the third frame, and a fourth frame area located outside the fourth frame;
  • the scan driving circuit is located in the first frame area, the first rounded corner area and the second rounded corner area, and the control driving circuit and the light emitting driving circuit are located in the second frame area, the third rounded corner area. area and the fourth fillet area;
  • the scan shift register located in the second rounded corner area is arranged along the second rounded corner;
  • the control shift registers located in the fourth rounded corner area are arranged along the fourth rounded corner.
  • K is greater than or equal to 14;
  • K is greater than or equal to 7.
  • the boundary of the display area includes a circle;
  • the frame area includes: a first area to a fourth area, and the first area and the second area are located in the third area and between the fourth areas,
  • the center line extending along the first direction of the display area passes through the third area and the fourth area;
  • the first area and the second area are respectively located on both sides of a centerline extending along the first direction of the display area;
  • the first area is located on the first side of the display substrate, the second area is located on the second side of the display area, the third area is located on the third side of the display area, and the fourth area Located on the fourth side of the display area;
  • the scan driving circuit is located in the first area, and the control driving circuit and the light emitting driving circuit are located in the second area,
  • the scan shift registers located in the first area are arranged along the circular boundary;
  • the light-emitting shift registers located in the second area are arranged along a circular boundary.
  • the buffer driving circuit is located in the fourth area, and the plurality of cascaded buffer shift registers in the buffer driving circuit are arranged along the first direction.
  • the multiplexing circuit is located in the first area and/or the second area, and is interspersed between the scan shift register and/or the control shift register.
  • K is greater than or equal to 10;
  • K is greater than or equal to 5.
  • the circuit structure of the buffer shift register and the scan shift register Both include: a plurality of scanning transistors and a plurality of scanning capacitors, and the scanning capacitors include: a first plate and a second plate;
  • the display substrate also includes: a control initial signal line, a first control clock signal line and a second control clock signal line, a first control power supply line and a second control power supply line; a first-level buffer shift register and a control initial signal line Electrically connected, the buffer drive circuit and the control drive circuit are electrically connected to the first control clock signal line and the second control clock signal line, the first control power supply line and the second control power supply line respectively.
  • the circuit structure layer when the reset signal lines of the K+1th to Nth row pixel circuits are electrically connected to the scan driving circuit, includes: sequentially stacked on the substrate. a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer and a planarization layer;
  • the second conductive layer includes: a plurality of second plates of scanning capacitors
  • the third conductive layer includes: first poles and second poles of a plurality of scan transistors, first signal output lines of the first to N-Kth level scan shift registers, and N-K+1 to Nth levels. Scan the fourth signal output line of the shift register;
  • the third conductive layer includes: first poles and second poles of a plurality of control transistors, first signal output lines of the first to (N-K)/2-th control shift registers, and the (N-K)th )/2+1 to Nth stage control the fourth signal output line of the shift register;
  • Figure 3A is an equivalent circuit schematic diagram of a pixel circuit
  • Figure 5 is a cascade diagram of multiple drive circuits of a display substrate
  • Figure 9 is a schematic diagram of the arrangement of multiple drive circuits on another display substrate
  • Figure 12A is an equivalent circuit diagram of a control shift register provided by an exemplary embodiment
  • Figure 16A is a schematic diagram of the first conductive layer pattern
  • Figure 16B is a schematic diagram after forming the first conductive layer pattern
  • Figure 17A is a schematic diagram of the second conductive layer pattern
  • Figure 18 is a schematic diagram after the third insulating layer pattern is formed
  • Figure 19A is a schematic diagram of the third conductive layer pattern
  • Figure 19B is a schematic diagram after the third conductive layer pattern is formed
  • Figure 20 is a schematic diagram after the fourth insulating layer pattern is formed
  • Figure 21A is a schematic diagram of the fourth conductive layer pattern
  • FIG. 21B is a schematic diagram after the fourth conductive layer pattern is formed.
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • the "same layer arrangement" used refers to structures formed by patterning two (or more than two) structures through the same patterning process, and their materials may be the same or different.
  • the precursor materials used to form multiple structures arranged in the same layer are the same, and the final materials formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • LTPS Low Temperature Poly-Silicon
  • LTPS technology has the advantages of high resolution, high response speed, high brightness, and high aperture ratio. Although welcomed by the market, LTPS technology also has some shortcomings, such as high production costs and high power consumption. At this time, the Low Temperature Polycrystalline Oxide (LTPO) technical solution emerged as the times require. . Compared with LTPS technology, LTPO technology has smaller leakage current and faster pixel response. An extra layer of oxide is added to the display substrate, which reduces the energy consumption required to excite pixels, thereby reducing power consumption during screen display. However, compared to display products using LTPS technology, display products using LTPO technology will cause afterimages due to the bias of the threshold voltage of the driving transistor in the pixel circuit, reducing the display effect of the display product.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes: a substrate and a circuit structure layer provided on the substrate.
  • the circuit structure layer includes: pixel circuit P, scan driving circuit, control driving circuit and buffer driving circuit.
  • the pixel circuit P includes: a writing transistor, a node reset transistor, a reset signal line, a scanning signal line and a control signal line.
  • the reset signal line is connected to the control electrode of the node reset transistor, and the scanning signal line is connected to the control electrode of the writing transistor.
  • Figures 1 and 2 take N rows and M columns of pixel circuits as an example.
  • the display substrate may include a display area 100 and a non-display area.
  • the pixel circuit P is located in the display area 100, and the scan driving circuit, the control driving circuit and the buffer driving circuit can be located in the display area 100 and/or the non-display area, and this disclosure does not impose any limitation on this.
  • FIG. 1 and FIG. 2 illustrate using the example that the scan driving circuit, the control driving circuit and the buffer driving circuit are located in the non-display area.
  • the reset signal lines RL 1 to RL K of the pixel circuits in the first row to the Kth row are electrically connected to the buffer drive circuit, and the reset signal lines RL of the pixel circuits in the K+1 to Nth rows are electrically connected.
  • K+1 to RL N are electrically connected to the scan drive circuit or the control drive circuit, where K makes the start time of the effective level signal of the scan signal line or the control signal line of the pixel circuit and the signal of the reset signal line to be the effective level. The difference between the end times of the flat signals is greater than the threshold time.
  • Figure 1 illustrates the electrical connection between the reset signal lines RL K+1 to RL N of the pixel circuits in the K+1 to Nth rows and the scan drive circuit as an example.
  • Figure 2 takes the K+1 to Nth rows as an example. The electrical connection of the reset signal lines RL K+1 to RL N of the row pixel circuit to control the driving circuit is explained as an example.
  • K is such that the start time of the effective level signal of the scan signal line or the control signal line of the x-th row pixel circuit and the end time of the effective level signal of the signal of the reset signal line of the x-th row pixel circuit are between The difference is greater than or equal to the threshold time, 1 ⁇ x ⁇ N.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal chips; the flexible substrate may be, but is not limited to, polyparaphenylene.
  • the display substrate may further include: a light-emitting structure layer located on a side of the circuit structure layer away from the substrate;
  • the light-emitting structure layer includes: light-emitting elements located in the display area and arranged in an array;
  • the light-emitting elements include: One electrode (anode), an organic light-emitting layer and a second electrode (cathode), the anode is located on the side of the organic light-emitting layer close to the substrate, and the cathode is located on the side of the organic light-emitting layer away from the substrate; the light-emitting element is electrically connected to the pixel circuit.
  • the display substrate may further include a timing controller and a source driving circuit.
  • the timing controller and source driver circuit can be located in the non-display area.
  • the timing controller may provide grayscale values and control signals suitable for specifications of the source driving circuit to the source driving circuit, and may provide clock signals, scan signals suitable for specifications of the scan driving circuit.
  • the start signal and the like are supplied to the scan drive circuit.
  • a clock signal, a control start signal, etc. suitable for the specifications of the control drive circuit can be supplied to the control drive circuit.
  • a clock signal and emission stop signal suitable for the specifications of the light-emitting drive circuit can be supplied to the control drive circuit. etc. are provided to the light-emitting driving circuit.
  • the source driving circuit may utilize the gray value and the control signal received from the timing controller to generate the signal to be provided to the data signal lines D 1 , D 2 , D 3 , . . . and DM data voltage.
  • the source driving circuit may sample a grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal lines D 1 to DM in units of pixel rows.
  • the scan driving circuit may generate a signal to be provided to the scan signal lines GL 1 , GL 2 , GL 3 , ... and GLM by receiving a clock signal, a scan start signal, etc. from a timing controller. Scan signal.
  • the scan driving circuit may sequentially supply scan signals having on-level pulses to the scan signal lines GL 1 to GL M .
  • the scan driving circuit may be configured in the form of a shift register, and the scan may be generated in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal. Signal.
  • the light emitting driving circuit may generate the emission to be provided to the light emitting signal lines EL 1 , EL 2 , EL 3 , ... and ELM by receiving a clock signal, an emission stop signal, or the like from a timing controller. Signal.
  • the light-emitting driving circuit may sequentially supply emission signals with off-level pulses to the light-emitting signal lines EL 1 to ELM .
  • the light-emitting driving circuit may be configured in the form of a shift register, and may generate the light-emitting signal in a manner that sequentially transmits a light-emitting stop signal provided in the form of an off-level pulse to a next-stage circuit under the control of a clock signal.
  • the display substrate provided by the embodiment of the present disclosure includes: a substrate and a circuit structure layer provided on the substrate.
  • the circuit structure layer includes: a pixel circuit, a scan driving circuit, a control driving circuit and a buffer driving circuit; the pixel circuit includes: a writing transistor, a node The reset transistor, the reset signal line, the scan signal line and the control signal line.
  • the reset signal line is connected to the control electrode of the node reset transistor, and the scan signal line is connected to the control electrode of the write transistor; the reset of the pixel circuits in the first row to the Kth row
  • the signal line is electrically connected to the buffer drive circuit, and the reset signal line of the K+1 to Nth row pixel circuit is electrically connected to the scan drive circuit or the control drive circuit, so that the signal of the pixel circuit scan signal line or control signal line is valid.
  • the difference between the start time of the level signal and the end time when the signal on the reset signal line is a valid level signal is greater than the threshold time.
  • the present disclosure can lengthen the difference between the time when the reset signal line of the pixel circuit is a valid level signal and the time when the pixel circuit scan signal line or the control signal line is a valid level signal by arranging a buffer driving circuit, so that the control of the driving transistor of the pixel circuit is The pole can be fully reset, and the threshold voltage can be recovered from the bias state, thereby improving the afterimage of the display substrate and improving the display effect of the display substrate.
  • the display substrate provided by an exemplary embodiment may further include: a light-emitting driving circuit, and the pixel circuit further includes: a light-emitting transistor and a light-emitting signal line; the light-emitting signal line is electrically connected to the control electrode of the light-emitting transistor. ;
  • the light-emitting driving circuit is located on the side of the control driving circuit away from the display area 100.
  • the light-emitting signal lines of the first row to the N-th row of pixel circuits are electrically connected to the light-emitting driving circuit.
  • EL i refers to the light-emitting signal line of the i-th row pixel circuit.
  • the difference between the start time of the effective level signal of the signal of the pixel circuit's light-emitting signal line and the end time of the effective level signal of the signal of the reset signal line is greater than the threshold time and
  • the signal of the scanning signal line is the sum of the durations of the effective level signals.
  • the difference between the start time of the effective level signal of the signal of the light-emitting signal line of the pixel circuit and the end time of the effective level signal of the signal of the reset signal line is equal to the threshold time and
  • the signal of the scanning signal line is the sum of the durations of the effective level signals.
  • a display substrate provided by an exemplary embodiment may further include: a test circuit and a multiplexing circuit (not shown in the figure); the pixel circuit may further include: a pixel extending along the second direction.
  • the first direction of the data signal line D intersects with the second direction, and the first direction is the extension direction of the reset signal line, the scanning signal line and the control signal line.
  • Di refers to the data signal line of the i-th column pixel circuit.
  • the data signal line is electrically connected to the first pole of the writing transistor, the test circuit and the multiplexing circuit respectively; the test circuit is located on the first and third sides of the display area, and the multiplexing circuit is located on the first side of the display area. side and/or second side.
  • the reset signal lines of the K+1th to Nth row pixel circuits are electrically connected to the scan driving circuit.
  • the pixel circuit may also include: a compensation transistor and a compensation reset transistor; the transistor type of the compensation reset transistor is opposite to the transistor type of the driving transistor, the node reset transistor, the writing transistor, and the compensation transistor; the scanning signal line is also connected to the control of the compensation transistor.
  • the control signal line is electrically connected to the control electrode of the compensation reset transistor.
  • the reset signal lines of the K+1th to Nth row pixel circuits are electrically connected to the control driving circuit, and the pixel
  • the circuit also includes: a compensation transistor; the node reset transistor and the compensation transistor have transistor types that are opposite to the transistor types of the drive transistor and the write transistor; and the control signal line is electrically connected to the control electrode of the compensation transistor.
  • FIG. 3A is an equivalent circuit schematic diagram of a pixel circuit.
  • the pixel circuit may include 8 transistors (first transistor T1 to eighth transistor T8), 1 capacitor C, and 8 signal lines (data signal line D, control signal line SL, scanning signal line GL, reset signal line RL, light emitting signal line EL, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD and second power supply line VSS).
  • FIG. 3A illustrates an example when the node reset transistor and the write transistor have the same transistor type.
  • the first plate of the capacitor C is connected to the first power line VDD, and the second plate of the capacitor C is connected to the first node N1.
  • the control electrode of the first transistor T1 is connected to the reset signal line RL, the first electrode of the first transistor T1 is connected to the first initial signal line Vinit1, and the second electrode of the first transistor is connected to the fourth node N4.
  • the control electrode of the second transistor T2 is connected to the scanning signal line GL, the first electrode of the second transistor T2 is connected to the fourth node N4, and the second electrode of the second transistor T2 is connected to the second node N2.
  • the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the control electrode of the fourth transistor T4 is connected to the scanning signal line GL, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the third node N3.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line EL, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line EL, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element L.
  • the control electrode of the seventh transistor T7 is connected to the reset signal line RL, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element L, and emits light.
  • the second pole of element L is connected to the second power supply line VSS.
  • the control electrode of the eighth transistor T8 is connected to the control signal line SL, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is connected to the fourth node N4.
  • control electrode of the seventh transistor T7 may also be connected to the scan signal line GL, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 It is connected to the first electrode of the light-emitting element L, and the second electrode of the light-emitting element L is connected to the second power supply line VSS.
  • the first transistor T1 may be called a node reset transistor.
  • the reset signal line RL inputs a valid level signal
  • the first transistor T1 transmits the initialization voltage to the first node N1 so that the first The charge amount of node N1 is initialized.
  • the eighth transistor T8 may be called a compensation reset transistor.
  • the eighth transistor T8 transmits the signal of the fourth node N4 to the first node N1. Not only can the charge amount of the first node be initialized, but also the threshold value of the third transistor T3 can be compensated.
  • the second transistor T2 may be called a compensation transistor.
  • the second transistor T2 causes the signal of the second node N2 to be written to the fourth node N4.
  • the third transistor T3 may be called a driving transistor.
  • the third transistor T3 determines a position between the first power supply terminal VDD and the second power supply terminal VSS according to the potential difference between the control electrode and the first electrode. the driving current flowing between them.
  • the fourth transistor T4 may be called a write transistor.
  • the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel circuit.
  • the fifth transistor T5 and the sixth transistor T6 may be called light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 cause the light-emitting element to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the signal of the first power line VDD continuously provides a high-level signal
  • the signal of the second power line VSS is a low-level signal
  • the eighth transistor T8 is a metal oxide transistor and is an N-type transistor
  • the first to seventh transistors T1 to T7 are low-temperature polysilicon transistors and are P-type transistors.
  • the eighth transistor T8 is an oxide transistor, which can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.
  • FIG. 3B is an operating timing diagram of the pixel circuit provided in FIG. 3A.
  • the following describes exemplary embodiments of the present disclosure through the working process of the pixel circuit illustrated in FIG. 3B.
  • the working process of the pixel circuit can include:
  • the first stage A1 is called the reset stage.
  • the signals of the control signal line SL, the light-emitting signal line EL and the scanning signal line GL are all high-level signals, and the signal of the reset signal line RL is a low-level signal.
  • the signal of the reset signal line RL is a low-level signal, the first transistor T1 is turned on, the signal of the first initial signal line Vinit1 is provided to the fourth node N4, the seventh transistor T7 is turned on, and the initial voltage of the second initial signal line Vinit2 Provide to the first pole of the light-emitting element L to initialize (reset) the first pole of the light-emitting element L, for example, clear the pre-stored voltage inside it to complete the initialization and ensure that the light-emitting element L does not emit light.
  • the signal of the control signal line SL is a high-level signal
  • the eighth transistor T8 is turned on
  • the signal of the fourth node N4 is provided to the first node N1 to initialize the capacitor C and clear the original data voltage in the capacitor C.
  • the signals of the scanning signal line GL and the light-emitting signal line EL are high-level signals.
  • the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the light-emitting element L does not emit light. .
  • the second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned on so that the data voltage output by the data signal line D passes through the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor.
  • T2, the fourth node N4 and the turned-on eighth transistor T8 are provided to the first node N1, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the capacitor C until the first node
  • the voltage of N1 is Vd-
  • the third stage A3 is called the light-emitting stage.
  • the signals of the control signal line SL and the light-emitting signal line EL are both low-level signals, and the signals of the scanning signal line GL and the reset signal line RL are high-level signals.
  • the signal of the reset signal line RL is a low-level signal, and the first transistor T1 and the seventh transistor T7 are turned off.
  • the control signal line SL is a low-level signal
  • the signals of the scanning signal line GL and the reset signal line RL are high-level signals, and the second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned off.
  • the signal of the light-emitting signal line EL is a low-level signal
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply terminal VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor.
  • T6 provides a driving voltage to the first pole of the light-emitting element L to drive the light-emitting element L to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • the first plate of the capacitor C is connected to the first power line VDD, and the second plate of the capacitor C is connected to the first node N1.
  • the control electrode of the first transistor T1 is connected to the reset signal line RL, the first electrode of the first transistor T1 is connected to the first initial signal line Vinit1, and the second electrode of the first transistor T1 is connected to the first node N1;
  • the control electrode is connected to the control signal line SL, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the second node N2.
  • the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the control electrode of the fourth transistor T4 is connected to the scanning signal line GL, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the third node N3.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line EL, the first electrode of the fifth transistor T5 is connected to the first power line VDD, the second electrode of the fifth transistor T5 is connected to the third node N3;
  • the control electrode is connected to the light-emitting signal line EL, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device.
  • the control electrode of the seventh transistor T7 is connected to the scanning signal line GL, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device.
  • the second pole is connected to the second power line VSS.
  • the first transistor T1 may be called a node reset transistor.
  • the reset signal line RL inputs a valid level signal
  • the first transistor T1 transmits the initialization voltage to the first node N1 so that the first The charge amount of node N1 is initialized.
  • the second transistor T2 may be called a compensation transistor.
  • the second transistor T2 transmits the signal of the second node N2 to the first node N1, so as to The signal of the first node N1 is compensated.
  • the third transistor T3 may be called a driving transistor.
  • the third transistor T3 determines the position between the first power line VDD and the second power line VSS according to the potential difference between the control electrode and the first electrode. the driving current flowing between them.
  • the fourth transistor T4 may be called a write transistor or the like.
  • the fourth transistor T4 causes the data voltage of the data signal line D to be input to the third node. N3.
  • the signals of the scanning signal line GL and the light-emitting signal line EL are high-level signals
  • the signals of the control signal line SL are low-level signals
  • the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the The seventh transistor T7 is turned off, and the OLED does not emit light at this stage.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the first through the third node N3, the turned-on third transistor T3, the second node N2 and the turned-on second transistor T2.
  • Node N1 and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the data voltage, Vth is the threshold voltage of the third transistor T3.
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the scan drive circuit and the control drive circuit are located in the non-display area, as shown in Figures 1 and 2
  • the scan drive circuit and the control drive circuit can be located on the first and second sides of the display area
  • the buffer The driving circuit may be located on the third side or the fourth side of the display area.
  • the third side is located on the side of the display area away from the binding area
  • the fourth side is located on the side of the display area close to the binding area.
  • FIG. 5 is a cascade diagram of multiple driving circuits of a display substrate.
  • the buffer drive circuit includes: K cascaded buffer shift registers GateB (1 ) to GateB(K);
  • the scan drive circuit includes: N cascaded scan shift registers GateG(1) to GateG(N);
  • the control drive circuit includes: N/2 cascaded control shift registers GateS(1 ) to GateS(N/2), the output terminal of the last stage buffer shift register GateB(K) is electrically connected to the input terminal of the first stage scanning shift register GateG(1).
  • R(i) in Figure 5 refers to the i-th row pixel circuit.
  • the a-th level buffer shift register GateB(a) is electrically connected to the reset signal line of the a-th row pixel circuit, 1 ⁇ a ⁇ K.
  • the b-th stage scanning shift register GateG(b) is electrically connected to the scanning signal line of the b-th row pixel circuit, 1 ⁇ b ⁇ N.
  • the c-th scanning shift register GateG(c) is electrically connected to the reset signal line of the K+c-th row pixel circuit, 1 ⁇ c ⁇ N-K.
  • the d-th stage control shift register GateS(d) is electrically connected to the control signal lines of the pixel circuits of the 2d-1 row and the pixel circuit of the 2d row respectively, 1 ⁇ d ⁇ N/2.
  • FIG. 6 is a schematic diagram of the connection between a driving circuit and a pixel circuit in a display substrate.
  • the first to N-Kth scanning shift registers GateG(1) to GateG(N-K) include: a first signal output line OL1 and a second signal output line OL2 connected to each other.
  • the second signal output line OL2 Located on the side of the first signal output line OL1 away from the substrate.
  • the first signal output line of the c-th scan shift register is electrically connected to the scan signal line GL(c) of the c-th row pixel circuit
  • the second signal output line of the c-th scan shift register is electrically connected to the K+c-th row pixels.
  • the reset signal line RL (K+c) of the circuit is electrically connected.
  • the first signal output line OL1 and the second signal output line OL2 are located between the scan driving circuit and the display area, and the extension direction of the first signal output line OL1 is in line with the first signal output line OL1 .
  • the extending directions of the two signal output lines OL2 intersect.
  • the N-K+1 to N-th stage scanning shift registers GateG(N-K+1) to GateG(N) include: and the first signal output
  • the fourth signal output line OL4 is provided on the same layer as line OL1; the fourth signal output line of the s-th level scanning shift register GateS(s) is electrically connected to the scanning signal line GL(s) of the s-th row pixel circuit, N-K +1 ⁇ s ⁇ N.
  • the third signal output line OL3 and the fourth signal output line OL4 are located between the scan driving circuit and the display area.
  • FIG. 7 is a cascade diagram of multiple driving circuits of another display substrate.
  • the buffer drive circuit includes: K/2 cascaded buffer shift registers GateB (1) to GateB(K/2);
  • the scan drive circuit includes: N cascaded scan shift registers GateG(1) to GateG(N);
  • the control drive circuit includes: N/2 cascaded control shifts Registers GateS(1) to GateS(N/2); the output terminal of the last stage buffer shift register GateB(K/2) is electrically connected to the input terminal of the first stage control shift register GateS(1).
  • the m-th level control shift register GateS(m) is electrically connected to the control signal lines of the 2m-1th row pixel circuit and the 2m-th row pixel circuit respectively, 1 ⁇ m ⁇ N/2.
  • the nth stage control shift register GateS(n) is electrically connected to the reset signal line of the K+2n-1th row pixel circuit and the K+2nth row pixel circuit respectively, 1 ⁇ n ⁇ (N-K)/2.
  • the first signal output line and the second signal output line are located between the control driving circuit and the display area, and the extending direction of the first signal output line intersects the extending direction of the second signal output line.
  • the first frame area LR1, the first rounded corner area CR1 and the second rounded corner area CR2 are located on the first side of the display area 100
  • the second frame area LR2 the third rounded corner area CR3 and the fourth rounded corner area CR4 are located on the first side of the display area 100
  • the third frame area LR3 is located on the third side of the display area 100
  • the fourth frame area LR4 is located on the second side of the display area 100 .
  • the test circuit CT includes: multiple test sub-circuits, some of which are located in the third frame area LR3 and interspersed between the buffer shift registers, and the other part
  • the test sub-circuit is located in the first rounded corner area CR1 and is interspersed between the scan shift registers located in the first rounded corner area CR1.
  • the multiplexing circuit MUX is interspersed between the scan shift register located in the first frame area LR1 and/or the control shift register located in the second frame area LR2 between.
  • a scan driving circuit including multiple cascaded scan shift registers GateG(1) to GateG(N) is located in the first region R1 and includes multiple stages.
  • the control drive circuit of the connected shift registers GateS(1) to GateS(N/2) and the light-emitting drive circuit including multiple cascaded light-emitting shift registers EM(1) to EM(N/2) are located in the second Area R2.
  • the length of the bending region along the first direction is greater than the average length of the composite circuit region along the first direction.
  • the length of the composite circuit area along the first direction gradually changes along the second direction, and the length of the composite circuit area close to the bending area along the first direction is smaller than the length of the composite circuit area away from the bending area along the first direction.
  • the scan shift register may include: a plurality of scan transistors and a plurality of scan capacitors.
  • the circuit structure of the scan shift register may be 8T2C, which is not limited in this disclosure.
  • the control electrode of the fifth light-emitting transistor ET5 is electrically connected to the fourth node E4, the first electrode of the fifth light-emitting transistor ET5 is electrically connected to the fifth node E5, and the second electrode of the fifth light-emitting transistor ET5 is electrically connected to the first power terminal VGH. .
  • the control electrode of the sixth light-emitting transistor ET6 is electrically connected to the fourth node E4, the first electrode of the sixth light-emitting transistor ET6 is electrically connected to the first clock signal terminal ECK1, and the second electrode of the sixth light-emitting transistor ET6 is electrically connected to the sixth node E6. connect.
  • the control electrode of the ninth light-emitting transistor ET9 is electrically connected to the seventh node E7, the first electrode of the ninth light-emitting transistor ET9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth light-emitting transistor ET9 is electrically connected to the output terminal EOUT.
  • the control electrode of the tenth light-emitting transistor ET10 is electrically connected to the third node E3, the first electrode of the tenth light-emitting transistor ET10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth light-emitting transistor ET10 is electrically connected to the output terminal EOUT.
  • the first power terminal VGH continuously provides a high-level signal
  • the second power terminal VGL continuously provides a low-level signal. Since the second power terminal VGL continues to provide a low-level signal, the eleventh light-emitting transistor ET11 and the twelfth light-emitting transistor ET12 continue to be turned on.
  • the flat signal is transmitted to the first node E1, so that the level of the first node E1 becomes a high level signal, and the turned-on twelfth light-emitting transistor ET12 transmits the high level signal of the first node E1 to the third node E2 , the second light-emitting transistor ET2, the fourth light-emitting transistor ET4, the eighth light-emitting transistor ET8 and the tenth light-emitting transistor ET10 are turned off.
  • the turned-on third light-emitting transistor ET3 transmits the low-level signal of the third power terminal VGL to the second node E2, thereby causing the level of the second node E2 to become low-level, and the turned-on eleventh light-emitting transistor ET3
  • the transistor ET11 transmits the low-level signal of the second node E2 to the fourth node E4, so that the level of the fourth node E4 becomes a low level, and the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on.
  • the signal of the first clock signal terminal ECK1 is a high-level signal, and the seventh light-emitting transistor ET7 is turned off.
  • the ninth light-emitting transistor ET9 is turned off.
  • the signal at the output terminal EOUT maintains the previous low level.
  • the signal of the first clock signal terminal ECK1 is a low-level signal
  • the signal of the third clock signal terminal ECK3 is a high-level signal.
  • the signal of the first clock signal terminal ECK1 is a low-level signal
  • the seventh light-emitting transistor ET7 is turned on.
  • the signal of the third clock signal terminal ECK3 is a high-level signal, and the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned off. Under the action of the third light-emitting capacitor EC3, the first node E1 and the third node E3 can continue to maintain the high level signal of the previous stage.
  • the fourth node E4 can continue to maintain the high level signal of the previous stage. phase is low, so the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on.
  • the second light-emitting transistor ET2, the fourth light-emitting transistor ET4, the eighth light-emitting transistor ET8 and the tenth light-emitting transistor ET10 are turned off.
  • the low-level signal of the first clock signal terminal ECK1 is transmitted to the seventh node E7 through the sixth light-emitting transistor ET6 and the seventh light-emitting transistor ET7 that are turned on, the ninth light-emitting transistor ET9 is turned on, and the ninth light-emitting transistor ET9 that is turned on
  • the light-emitting transistor ET9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal EOUT is a high-level signal.
  • the signal of the first clock signal terminal ECK1 is a low-level signal
  • the signal of the third clock signal terminal ECK3 is a high-level signal
  • the signal of the third clock signal terminal ECK3 is a high-level signal, and the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned off.
  • the signal of the first clock signal terminal ECK1 is low level, and the seventh light-emitting transistor ET7 is turned on.
  • the levels of the first node E1 and the third node E3 maintain the high-level signal of the previous stage, thereby causing the second light-emitting transistor ET2, the fourth light-emitting transistor ET4, and the eighth light-emitting transistor to emit light.
  • the transistor ET8 and the tenth light-emitting transistor ET10 are turned off.
  • the fourth node E4 continues to maintain the low level of the previous stage, so that the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on.
  • the low-level signal of the first clock signal terminal ECK1 is transmitted to the seventh node E7 through the turned-on sixth light-emitting transistor ET6 and the seventh light-emitting transistor ET7, and the turned-on ninth light-emitting transistor ET9 switches the first power terminal VGH
  • the high-level signal is output, so the signal at the output terminal EOUT is still a high-level signal.
  • the first light-emitting transistor ET1 that is turned on transmits the low-level signal of the input terminal EIN to the first node E1, so that the level of the first node E1 becomes low level
  • the twelfth light-emitting transistor ET12 that is turned on transmits the low-level signal of the input terminal EIN to the first node E1.
  • the low level signal of a node E1 is transmitted to the third node E3, so that the level of the third node E3 becomes a low level
  • the light-emitting transistor ET10 is turned on.
  • the turned-on second light-emitting transistor ET2 transmits the low-level signal of the third clock signal terminal ECK3 to the second node E2, thereby further pulling down the level of the second node E2, so the second node E2 and the fourth node E4 continues to maintain the low level of the previous stage, so that the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on.
  • the signal of the first clock signal terminal ECK1 is a high-level signal
  • the seventh light-emitting transistor ET7 is turned off.
  • the turned-on eighth light-emitting transistor ET8 transmits the high-level signal of the first power terminal VGH to the seventh node E7
  • the ninth light-emitting transistor ET9 is turned off.
  • the turned-on tenth light-emitting transistor ET10 outputs the low-level signal of the second power supply terminal VGL, so the signal of the output terminal EOUT becomes low-level.
  • the display substrate may further include: a light-emitting initial signal line extending along the second direction, first to third light-emitting clock signal lines, a first high-level power supply line and a first light-emitting clock signal line. Low level power cord.
  • the input end of the first-level light-emitting shift register is electrically connected to the light-emitting initial signal line, and the output end of the i-th level light-emitting shift register is electrically connected to the input end of the i+1-th level light-emitting shift register; the i-th level light-emitting shift register
  • the first clock signal terminal of the register is electrically connected to the first luminescent clock signal line
  • the second clock signal terminal is electrically connected to the second luminescent clock signal line
  • the third clock signal terminal is electrically connected to the third luminescent clock signal line
  • the first clock signal terminal of the level 1 light-emitting shift register is electrically connected to the third light-emitting clock signal line
  • the second clock signal terminal is electrically connected to the second light-emitting clock signal line
  • the third clock signal terminal is electrically connected to the first light-emitting clock signal line.
  • the first power terminal of the i-th stage light-emitting shift register is electrically connected to the first light-emitting power line
  • the second power terminal of the i-th stage light-emitting shift register is electrically connected to the second light-emitting power line.
  • FIG. 11A is an equivalent circuit diagram of a scan shift register provided in an exemplary embodiment
  • FIG. 11B is a timing diagram of the scan shift register provided in FIG. 11A
  • the scan shift register includes: first to eighth scan transistors GT1 to GT8 , a first scan capacitor GC1 and a second scan capacitor GC2 .
  • the scan electrode of the first scan transistor GT1 is electrically connected to the first clock signal terminal CK
  • the first electrode of the first scan transistor GT1 is electrically connected to the input terminal GIN
  • the first scan electrode of the first scan transistor GT1 is electrically connected to the input terminal GIN.
  • the second pole of the scan transistor GT3 is electrically connected to the second node G2; the scan pole of the fourth scan transistor GT4 is electrically connected to the second node G2; the first pole of the fourth scan transistor GT4 is electrically connected to the first power terminal VGH.
  • the second pole of the fourth scan transistor GT4 is electrically connected to the output terminal GOUT; the scan pole of the fifth scan transistor GT5 is electrically connected to the third node G3; the first pole of the fifth scan transistor GT5 is electrically connected to the second clock signal terminal GCK2.
  • the second pole of the fifth scan transistor GT5 is electrically connected to the output terminal GOUT; the scan pole of the sixth scan transistor GT6 is electrically connected to the second node G2; the first pole of the sixth scan transistor GT6 is electrically connected to the first power terminal VGH.
  • the second pole of the sixth scan transistor GT6 is electrically connected to the first pole of the seventh scan transistor GT7; the scan pole of the seventh scan transistor GT7 is electrically connected to the second clock signal terminal GCK2, and the second pole of the seventh scan transistor GT7 is electrically connected to The first node G1 is electrically connected; the scan electrode of the eighth scan transistor GT8 is electrically connected to the second power terminal VGL, the first electrode of the eighth scan transistor GT8 is electrically connected to the first node G1, and the second electrode of the eighth scan transistor GT8 is electrically connected to the third node G3; one end of the first scanning capacitor GC1 is electrically connected to the first power terminal VGH, and the other end of the first scanning capacitor GC1 is electrically connected to the second node G2; the first plate of the second scanning capacitor GC2 GC21 is electrically connected to the output terminal GOUT, and the second plate GC22 of the second scanning capacitor GC2 is electrically connected to the third node G3.
  • the first power terminal VGH continuously provides a high-level signal
  • the second power terminal VGL continuously provides a low-level signal
  • the signals of the first clock signal terminal GCK1 and the input terminal GIN are low-level signals, and the signal of the second clock signal terminal GCK2 is a high-level signal. Since the signal at the first clock signal terminal GCK1 is a low-level signal, the first scan transistor GT1 is turned on, and the signal at the input terminal GIN is transmitted to the first node G1 through the first scan transistor GT1. Since the signal of the eighth scan transistor GT8 receives the low level signal of the second power terminal VGL, the eighth scan transistor GT8 is in an on state. The level of the third node G3 can be scanned and the fifth scan transistor GT5 is turned on. The signal of the second clock signal terminal GCK2 is transmitted to the output terminal GOUT through the fifth scan transistor GT5.
  • the output terminal GOUT is high level.
  • the third scan transistor GT3 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted to the second node G2 via the third scan transistor GT3.
  • both the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are turned on. Since the signal at the second clock signal terminal GCK2 is a high-level signal, the seventh scanning transistor GT7 is turned off.
  • the signal of the first clock signal terminal GCK1 is a high-level signal
  • the signal of the second clock signal terminal GCK2 is a low-level signal
  • the signal of the input terminal GIN is a high-level signal.
  • the fifth scan transistor GT5 is turned on, and the signal of the second clock signal terminal GCK2 is used as the signal of the output terminal GOUT through the fifth scan transistor GT5.
  • the level of one end of the second scanning capacitor GC2 connected to the output terminal OUT becomes the signal of the second power terminal VGL. Due to the bootstrap effect of the second scanning capacitor GC2, the eighth scanning transistor GT8 is turned off, and the fifth scanning transistor GT8 is turned off.
  • the scan transistor GT5 can be turned on better, and the signal at the output terminal GOUT is a low-level signal.
  • the signal at the first clock signal terminal GCK1 is a high-level signal, so that the first scanning transistor GT1 and the third scanning transistor GT3 are both turned off.
  • the second scan transistor GT2 is turned on, and the high-level signal of the first clock signal terminal GCK1 is transmitted to the second node G2 via the second scan transistor GT2. Therefore, the fourth scan transistor GT4 and the sixth scan transistor GT6 are both turned off. Since the signal at the second clock signal terminal GCK2 is a low-level signal, the seventh scanning transistor GT7 is turned on.
  • the signals of the first clock signal terminal GCK1 and the second clock signal terminal GCK2 are both high-level signals
  • the signal of the input terminal GIN is a high-level signal
  • the fifth scan transistor GT5 is turned on
  • the terminal GCK2 serves as the output signal GOUT via the fifth scan transistor GT5. Due to the bootstrapping effect of the second scan capacitor C2, the level of the first node G1 becomes VGL-VthN1.
  • the signal of the first clock signal terminal GCK1 is a high-level signal, so that the first scanning transistor GT1 and the third scanning transistor GT3 are both turned off, the eighth scanning transistor GT8 is turned on, the second scanning transistor GT2 is turned on, and the first clock
  • the high-level signal at the signal terminal GCK1 is transmitted to the second node G2 via the second scan transistor GT2, whereby both the fourth scan transistor GT4 and the sixth scan transistor GT6 are turned off. Since the signal at the second clock signal terminal GCK2 is a high-level signal, the seventh scanning transistor GT7 is turned off.
  • the signal of the first clock signal terminal GCK1 is a low-level signal
  • the signals of the second clock signal terminal GCK2 and the input terminal GIN are high-level signals. Since the signal at the first clock signal terminal GCK1 is a low-level signal, the first scan transistor GT1 is turned on, the signal at the input terminal GIN is transmitted to the first node G1 through the first scan transistor GT1, and the second scan transistor GT2 is turned off. Since the eighth scan transistor GT8 is in the on state, the fifth scan transistor GT5 is turned off.
  • the third scanning transistor GT3 is turned on, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned on, and the high level signal of the first power supply terminal VGH passes through the fourth The scan transistor GT4 is transmitted to the output terminal GOUT, that is, the signal at the output terminal GOUT is a high-level signal.
  • the signal of the first clock signal terminal GCK1 is a high-level signal
  • the signal of the second clock signal terminal GCK2 is a low-level signal
  • the signal of the input terminal GIN is a high-level signal.
  • the fifth scan transistor GT5 and the second scan transistor GT2 are both turned off.
  • the signal of the first clock signal terminal GCK1 is a high-level signal, so the first scan transistor GT1 and the third scan transistor GT3 are both turned off.
  • the fourth scan transistor GT4 and the sixth scan transistor Both GT6 are turned on, and the high-level signal is transmitted to the output terminal GOUT through the fourth scan transistor GT4, that is, the signal at the output terminal GOUT is a high-level signal.
  • the seventh scan transistor GT7 is turned on, so that the high-level signal is transmitted via the sixth scan transistor GT6 and the seventh scan transistor GT7. to the third node G3 and the first node G1, so that the signals of the third node G3 and the first node G1 remain as high-level signals.
  • the signals of the first clock signal terminal GCK1 and the second clock signal GCK2 are both high-level signals, and the signal of the input terminal GIN is a high-level signal.
  • the fifth scan transistor GT5 and the second scan transistor GT2 are turned off.
  • the signal at the first clock signal terminal GCK1 is a high-level signal, so that the first scan transistor GT1 and the third scan transistor GT3 are both turned off, and the fourth scan transistor GT4 and the sixth scan transistor GT6 are both turned on.
  • the high-level signal is transmitted to the output terminal GOUT through the fourth scan transistor GT4, that is, the signal at the output terminal GOUT is a high-level signal.
  • the input end of the first-level scanning shift register is electrically connected to the scanning initial signal line, and the output end of the i-th level scanning shift register is connected to the input end of the i+1-th level scanning shift register.
  • Electrical connection; the first clock signal terminal of the i-th level scan shift register is electrically connected to the first scan clock signal line, the second clock signal end is electrically connected to the second scan clock signal line, and the i+1-level scan shift register
  • the first clock signal end is electrically connected to the second scan clock signal line, the second clock signal end is electrically connected to the first scan clock signal line, and the first power end of the i-th stage scan shift register is electrically connected to the first scan power line.
  • the second power terminal of the i-th stage scan shift register is electrically connected to the second scan power line power line.
  • FIG. 12A is an equivalent circuit diagram of a control shift register provided by an exemplary embodiment
  • FIG. 12B is a timing diagram of the control shift register provided in FIG. 12A
  • the control shift register includes: first control transistors ST1 to eighth control transistors ST8, first control capacitor SC1 and second control capacitor SC2.
  • control electrode of the first control transistor ST1 is electrically connected to the first clock signal terminal CK
  • first electrode of the first control transistor ST1 is electrically connected to the input terminal SIN
  • first control electrode of the first control transistor ST1 is electrically connected to the input terminal SIN.
  • the two poles are electrically connected to the first node S1; the control pole of the second control transistor ST2 is electrically connected to the first node S1; the first pole of the second control transistor ST2 is electrically connected to the first clock signal terminal CK; the second control transistor ST2
  • the second pole of the third control transistor ST3 is electrically connected to the second node S2; the control pole of the third control transistor ST3 is electrically connected to the first clock signal terminal SSCK11; the first pole of the third control transistor ST3 is electrically connected to the second power supply terminal VGL; the third control transistor ST3 is electrically connected to the second power terminal VGL.
  • the second pole of the control transistor ST3 is electrically connected to the second node S2; the control pole of the fourth control transistor ST4 is electrically connected to the second node S2; the first pole of the fourth control transistor ST4 is electrically connected to the first power terminal VGH.
  • the second pole of the fourth control transistor ST4 is electrically connected to the output terminal SOUT; the control pole of the fifth control transistor ST5 is electrically connected to the third node S3, and the first pole of the fifth control transistor ST5 is electrically connected to the second clock signal terminal SCK2.
  • the second pole of the fifth control transistor ST5 is electrically connected to the output terminal SOUT; the control pole of the sixth control transistor ST6 is electrically connected to the second node S2; the first pole of the sixth control transistor ST6 is electrically connected to the first power terminal VGH.
  • the second pole of the sixth control transistor ST6 is electrically connected to the first pole of the seventh control transistor ST7; the control pole of the seventh control transistor ST7 is electrically connected to the second clock signal terminal SCK2, and the second pole of the seventh control transistor ST7 is electrically connected to The first node S1 is electrically connected; the control electrode of the eighth control transistor ST8 is electrically connected to the second power terminal VGL, the first electrode of the eighth control transistor ST8 is electrically connected to the first node S1, and the second electrode of the eighth control transistor ST8 It is electrically connected to the third node S3; the first plate SC11 of the first control capacitor SC1 is electrically connected to the first power terminal VGH, and the second plate SC13 of the first control capacitor SC1 is electrically connected to the second node S2; the second control The first plate SC21 of the capacitor SC2 is electrically connected to the output terminal SOUT, and the second plate SC22 of the second control capacitor SC2 is electrically connected to the third node S3.
  • the first to eighth control transistors ST1 to ST8 may be P-type transistors or may be N-type transistors.
  • the first power terminal VGH continuously provides a high-level signal
  • the second power terminal VGL continuously provides a low-level signal
  • the signals of the first clock signal terminal SCK1 and the input terminal SIN are low-level signals, and the signal of the second clock signal terminal SCK2 is a high-level signal. Since the signal at the first clock signal terminal SCK1 is a low-level signal, the first control transistor ST1 is turned on, and the signal at the input terminal SIN is transmitted to the first node S1 through the first control transistor ST1. Since the signal of the eighth control transistor ST8 receives the low level signal of the second power terminal VGL, the eighth control transistor ST8 is in an on state. The level of the third node S3 can control the fifth control transistor ST5 to turn on, and the signal of the second clock signal terminal SCK2 is transmitted to the output terminal SOUT through the fifth control transistor ST5.
  • the output terminal SOUT is high level.
  • the second clock signal terminal SCK2 signal.
  • the third control transistor ST3 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted to the second node S2 through the third control transistor ST3.
  • both the fourth control transistor ST4 and the sixth control transistor ST6 are turned on. Since the signal of the second clock signal terminal SCK2 is a high-level signal, the seventh control transistor ST7 is turned off.
  • the signals of the first clock signal terminal SCK1 and the second clock signal terminal SCK2 are both high-level signals
  • the signal of the input terminal SIN is a high-level signal
  • the fifth control transistor ST5 is turned on
  • the terminal SCK2 serves as the output signal SOUT via the fifth control transistor ST5. Due to the bootstrapping effect of the second control capacitor C2, the level of the first node S1 becomes VGL-VthN1.
  • the signal of the first clock signal terminal SCK1 is a high-level signal, so that the first control transistor ST1 and the third control transistor ST3 are both turned off, the eighth control transistor ST8 is turned on, the second control transistor ST2 is turned on, and the first clock
  • the high-level signal of the signal terminal SCK1 is transmitted to the second node S2 via the second control transistor ST2, whereby both the fourth control transistor ST4 and the sixth control transistor ST6 are turned off. Since the signal of the second clock signal terminal SCK2 is a high-level signal, the seventh control transistor ST7 is turned off.
  • the third control transistor ST3 is turned on, the fourth control transistor ST4 and the sixth control transistor ST6 are both turned on, and the high level signal of the first power supply terminal VGH passes through the fourth The control transistor ST4 is transmitted to the output terminal SOUT, that is, the signal at the output terminal SOUT is a high-level signal.
  • the signal of the first clock signal terminal SCK1 is a high-level signal
  • the signal of the second clock signal terminal SCK2 is a low-level signal
  • the signal of the input terminal SIN is a high-level signal.
  • Both the fifth control transistor ST5 and the second control transistor ST2 are turned off.
  • the signal of the first clock signal terminal SCK1 is a high-level signal, so the first control transistor ST1 and the third control transistor ST3 are both turned off.
  • the fourth control transistor ST4 and the sixth control transistor ST6 is both turned on, and the high-level signal is transmitted to the output terminal SOUT through the fourth control transistor ST4, that is, the signal at the output terminal SOUT is a high-level signal.
  • the seventh control transistor ST7 is turned on, so that the high-level signal is transmitted via the sixth control transistor ST6 and the seventh control transistor ST7. to the third node S3 and the first node S1, so that the signals of the third node S3 and the first node S1 remain as high-level signals.
  • the signals of the first clock signal terminal SCK1 and the second clock signal SCK2 are both high-level signals, and the signal of the input terminal SIN is a high-level signal.
  • the fifth control transistor ST5 and the second control transistor ST2 are turned off.
  • the signal at the first clock signal terminal SCK1 is a high-level signal, so that the first control transistor ST1 and the third control transistor ST3 are both turned off, and the fourth control transistor ST4 and the sixth control transistor ST6 are both turned on.
  • the high-level signal is transmitted to the output terminal SOUT through the fourth control transistor ST4, that is, the signal at the output terminal SOUT is a high-level signal.
  • the input terminal of the first-stage control shift register is electrically connected to the control initial signal line, and the output terminal of the i-th stage control shift register is connected to the input terminal of the i+1-th stage control shift register.
  • Electrical connection; the first clock signal terminal of the i-th stage control shift register is electrically connected to the first control clock signal line, the second clock signal terminal is electrically connected to the second control clock signal line, and the i+1-th stage control shift register
  • the first clock signal terminal is electrically connected to the second control clock signal line, the second clock signal terminal is electrically connected to the first control clock signal line, and the first power supply terminal of the i-th stage control shift register is electrically connected to the first control power supply line.
  • connection, the second power terminal of the i-th stage control shift register is electrically connected to the second control power line power line.
  • FIG. 13 is a schematic structural diagram of a scan shift register provided by an exemplary embodiment.
  • the circuit structure layer when the reset signal lines of the K+1th to Nth row pixel circuits When electrically connected to the scan driving circuit, the circuit structure layer includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third insulating layer which are stacked on the substrate in sequence. a conductive layer, a fourth insulating layer, a fourth conductive layer and a flat layer;
  • the semiconductor layer includes: an active layer of a plurality of scanning transistors;
  • the first conductive layer includes: control electrodes of a plurality of scanning transistors and first plates of a plurality of scanning capacitors;
  • the second conductive layer includes: a plurality of second plates of scanning capacitors
  • the third conductive layer includes: first poles and second poles of a plurality of scan transistors, first signal output lines OL1 of the first to N-Kth level scan shift registers, and N-K+1 to Nth level scans.
  • the fourth conductive layer includes: scan initial signal line GSTV, first scan clock signal line GCLK1, second scan clock signal line GCLK2, first scan power line GVGH, second scan power line GVGL, first to N-Kth level scans
  • FIG. 14 is a schematic structural diagram of a control shift register provided by an exemplary embodiment.
  • the circuit structure layer when the reset signal lines of the K+1th to Nth row pixel circuits When electrically connected to the control drive circuit, the circuit structure layer includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third insulating layer which are sequentially stacked on the substrate. a conductive layer, a fourth insulating layer, a fourth conductive layer and a flat layer;
  • the semiconductor layer includes: an active layer that controls a plurality of transistors;
  • the first conductive layer includes: a plurality of control electrodes of the control transistors and a plurality of first plates of the control capacitors;
  • the second conductive layer includes: a plurality of second plates controlling capacitance
  • the third conductive layer includes: first and second poles of a plurality of control transistors, the first signal output line OL1 of the first to (N-K)/2th-level control shift registers, and the (N-K)/2+1th level.
  • the fourth conductive layer includes: control initial signal line SSTV, first control clock signal line SCLK1, second control clock signal line SCLK2, first control power supply line SVGH, second control power supply line SVGL, first to (N-K)th levels
  • the following takes the electrical connection between the reset signal lines of the K+1 to Nth row pixel circuits and the scan driving circuit as an example to go through the preparation process of the scan shift register including the first signal output line and the second signal output line in the display substrate.
  • the "patterning process” mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a "layer” after the patterning process. The "layer” after the patterning process contains at least one "pattern".
  • FIGS. 15 to 21 illustrate using a display substrate including the two-stage scanning shift register provided in FIG. 11A as an example.
  • Forming a semiconductor layer pattern on a substrate includes: depositing a semiconductor film on the substrate, patterning the semiconductor film through a patterning process, and forming a semiconductor layer pattern. As shown in FIG. 15 , FIG. 15 is a schematic diagram after the semiconductor layer pattern is formed.
  • the semiconductor layer pattern may include: an active layer T11 of the first scan transistor to an active layer T81 of the eighth scan transistor of the shift register.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal chips; the flexible substrate may be, but is not limited to, polyparaphenylene.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer.
  • the first and second flexible material layers can be made of polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • the first and second inorganic materials The material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., used to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the materials of the semiconductor layer Amorphous silicon (a-si) can be used.
  • the preparation process may include: first coating a layer of polyimide on a glass substrate, and then curing to form a film.
  • a first flexible (PI1) layer then deposit a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then deposit a layer of amorphous silicon on the first barrier layer Thin film to form an amorphous silicon (a-si) layer covering the first barrier layer; then apply a layer of polyimide on the amorphous silicon layer, and solidify the film to form a second flexible (PI2) layer; then Deposit a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, completing the preparation of the substrate.
  • the semiconductor layer may use amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si) , polycrystalline silicon (p-Si), hexathiophene, polythiophene and other various materials, that is, the present disclosure is applicable to transistors manufactured based on oxide Oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene polythiophene
  • polythiophene polythiophene and other various materials
  • the active layer T41 of the fourth scanning transistor and the active layer T51 of the fifth scanning transistor may be an integrally formed structure
  • the active layer T61 of the sixth scanning transistor and The active layer T71 of the seventh scanning transistor may be an integrally formed structure.
  • the active layer T11 of the first scanning transistor may be of an inverted "n" type, and the active layer T21 of the second scanning transistor may extend along the second direction, and may be In a strip-like structure, the active layer T31 of the third scanning transistor extends along the second direction and may be in a strip-like structure.
  • the integrated structure of the active layer T41 of the fourth scanning transistor and the active layer T51 of the fifth scanning transistor extends along the second direction.
  • the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh scanning transistor extends along the second direction and may have a stripe structure.
  • the eighth scanning The active layer T81 of the transistor extends along the second direction and may have a stripe structure.
  • Figure 16A is a schematic diagram of the first conductive layer pattern
  • Figure 16B is a diagram of forming the first conductive layer pattern. Schematic diagram after.
  • the first conductive layer pattern may include: control electrodes T12 to T82 of the first scan transistor, and a first plate of the first scan capacitor. C11 and the first plate C21 of the second scanning capacitor.
  • the first conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • Various or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the first insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, Multiple or composite layers.
  • the first insulating layer may be called a first gate insulating layer.
  • control electrode T12 of the first scan transistor and the control electrode T32 of the third scan transistor are integrally formed structures.
  • the integrated structure of the control electrode T12 of the first scan transistor and the control electrode T32 of the third scan transistor extends along the first direction and may be in a strip shape.
  • the first plate C11 of the first scan capacitor, the control electrode T42 of the fourth scan transistor, and the control electrode T62 of the sixth scan transistor are an integrally formed structure. , and extend along the first direction.
  • the first plate C21 of the second scanning capacitor and the control electrode T52 of the fifth scanning transistor have an integrally formed structure.
  • the integrated structure of the first plate C21 of the second scanning capacitor and the control electrode T52 of the fifth scanning transistor is a comb structure, the first plate C21 of the second scanning capacitor is a comb back, and the control electrode of the fifth scanning transistor T52 is the comb tooth.
  • control electrode T22 of the second scan transistor and the control electrode T82 of the eighth scan transistor extend along the first direction and may be strip-shaped.
  • the control electrode T12 of the first scan transistor is disposed across the active layer of the first scan transistor
  • the control electrode T22 of the second scan transistor is disposed across the active layer of the first scan transistor.
  • the control electrode T32 of the third scan transistor is arranged across the active layer of the third scan transistor
  • the control electrode T42 of the fourth scan transistor is arranged across the active layer of the fourth scan transistor.
  • control electrode T52 of the fifth scan transistor is disposed across the active layer of the fifth scan transistor
  • control electrode T62 of the sixth scan transistor is disposed across the active layer of the sixth scan transistor
  • control electrode of the seventh scan transistor is The electrode T72 is disposed across the active layer of the seventh scan transistor
  • control electrode T82 of the eighth scan transistor is disposed across the active layer of the eighth scan transistor. That is to say, the extending direction of the control electrode of at least one scan transistor The extension direction of the active layer is perpendicular to each other.
  • this process also includes a conductorization process.
  • the conductorization process is to use the semiconductor layer in the control electrode shielding area of multiple scanning transistors (that is, the area where the semiconductor layer overlaps the control electrode) after forming the first conductive layer as the channel area of the scanning transistor, which is not covered by the first conductive layer.
  • the semiconductor layer in the layer shielding area is processed into a conductive layer to form the electrode connection portion of the scanning transistor.
  • the interconnected electrode connection portions of the active layer of the sixth scan transistor and the active layer of the seventh scan transistor in the present disclosure are processed into a conductive layer to form a sixth scan transistor that can be multiplexed.
  • the second pole of the seventh scan transistor and the conductive structure of the first pole of the seventh scan transistor are processed into a conductive layer to form a sixth scan transistor that can be multiplexed.
  • FIG. 17A is a schematic diagram of the second conductive layer pattern.
  • Figure 17B after forming the second conductive layer pattern schematic diagram.
  • the second conductive layer pattern may include: a second plate C12 of the first scanning capacitor, a second plate C22 of the second scanning capacitor, and a first connection. Line VL1.
  • the second conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • Various or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the second insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, Multiple or composite layers.
  • the first insulating layer may be called a second gate insulating layer.
  • the orthographic projection of the second plate C12 of the first scanning capacitor on the substrate is the same as the orthogonal projection of the first plate C11 of the first scanning capacitor on the substrate.
  • the projections at least partially overlap.
  • the orthographic projection of the second plate C22 of the second scanning capacitor on the substrate is the same as the orthogonal projection of the first plate C21 of the second scanning capacitor on the substrate.
  • the projections at least partially overlap.
  • the orthographic projection of the first connection line on the substrate is located between the orthographic projection of the control electrode of the second scan transistor on the substrate and the control electrode of the eighth scan transistor. between orthographic projections on the substrate.
  • FIG. 18 is a schematic diagram after the third insulating layer pattern is formed.
  • the plurality of via hole patterns may include: first via holes V1 to eighth via holes V8 opened on the first to third insulating layers,
  • the ninth to fourteenth via holes V9 to V14 are on the second insulating layer and the third insulating layer, and the fifteenth to seventeenth via holes V15 to V17 are opened on the third insulating layer.
  • the first via V1 exposes the active layer of the first scanning transistor
  • the second via V2 exposes the active layer of the second scanning transistor
  • the third via V3 exposes the active layer of the third scanning transistor.
  • the fourth via V4 exposes the active layer T41 of the fourth scan transistor
  • the fifth via V5 exposes the active layer T51 of the fifth scan transistor
  • the sixth via V6 exposes the active layer T61 of the sixth scan transistor.
  • the seventh via hole V7 exposes the active layer T71 of the seventh scan transistor
  • the eighth via hole V8 exposes the active layer T81 of the eighth scan transistor
  • the ninth via hole V9 exposes the control electrode of the first scan transistor and The integrated structure of the control electrode of the third scan transistor.
  • the tenth via hole V10 exposes the control electrode of the second scan transistor.
  • the eleventh via hole V11 exposes the control electrode of the fifth scan transistor.
  • the twelfth via hole V12 exposes the control electrode of the third scan transistor.
  • control electrode of the fourth scan transistor and the control electrode of the sixth scan transistor is exposed, the thirteenth via hole V13 exposes the control electrode of the seventh scan transistor, and the fourteenth via hole V14 exposes the control electrode of the eighth scan transistor.
  • the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, Multiple or composite layers.
  • the first insulating layer may be called a second gate insulating layer.
  • the number of fourth via holes V4 is multiple, and the plurality of fourth via holes V4 are arranged in an array.
  • the number of fifth via holes V5 is multiple, and the plurality of fifth via holes V5 are arranged in an array.
  • the number of ninth via holes V9 is two, and a virtual straight line extending in the second direction passes through the two ninth via holes.
  • the number of the thirteenth via holes V13 is two.
  • One of the thirteenth via holes V13 is located in the middle of the control electrode of the seventh scan transistor, and the other thirteenth via hole V13 is located in the middle of the control electrode of the seventh scan transistor.
  • the overdrive is located at an end of the control electrode of the seventh scan transistor close to the control electrode of the fifth transistor.
  • the number of the fifteenth via holes V15 is two, and the two fifteenth via holes are respectively located at both ends of the first connection line.
  • the number of sixteenth via holes V16 is multiple, and the plurality of sixteenth via holes V16 may be arranged along the first direction.
  • the number of the seventeenth via holes V17 is multiple, and the multiple seventeenth via holes V17 may be arranged along the second direction.
  • FIG. 19A is a schematic diagram of the third conductive layer pattern
  • FIG. 19B is a schematic diagram after the third conductive layer pattern is formed.
  • the third conductive layer pattern may include: a first electrode T13 and a second electrode T14 of the first scan transistor to a first electrode T53 of the fifth scan transistor. and the second pole T54, the first pole T63 of the sixth scan transistor, the second pole T74 of the seventh scan transistor, the first pole T83 and the second pole T84 of the eighth scan transistor, the first signal output line OL1, the second The connection line VL2, the third connection line VL3 and the fourth connection line VL4.
  • the fourth conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • Various or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the second pole T14 of the first scan transistor, the second pole T74 of the seventh scan transistor, and the first pole T83 of the eighth scan transistor are integrally formed.
  • structure, the second pole T24 of the second scanning transistor and the second pole T34 of the third scanning transistor are an integrally formed structure
  • the first pole T43 of the fourth scanning transistor and the first pole T63 of the sixth scanning transistor T63 are an integrally formed structure.
  • the second pole T44 of the fourth scanning transistor, the second pole T54 of the fifth scanning transistor, and the first signal output line OL1 have an integrally formed structure.
  • the first signal output line OL1 extends along the first direction, and the orthographic projection on the substrate partially overlaps with the orthographic projection of the second scanning capacitor on the substrate. .
  • the orthographic projection of the second connection line on the substrate and the integrated structure of the control electrode of the first scan transistor and the control electrode of the third scan transistor are on the substrate.
  • the orthographic projections above partially overlap.
  • the orthographic projection of the third connection line VL3 on the substrate is connected to the first connection line, the first plate C11 of the first scan capacitor, and the fourth scan transistor.
  • the control electrode T42 and the control electrode T62 of the sixth scanning transistor are integrally formed structures and partially overlap with each other in orthographic projection on the substrate.
  • the first electrode T13 and the second electrode T14 of the first scan transistor are connected to the active layer of the first scan transistor through a first via hole, and the second electrode T14 is connected to the active layer of the first scan transistor through a first via hole.
  • the first electrode T23 of the scan transistor and the second electrode T24 of the second scan transistor are connected to the active layer of the second scan transistor through a second via hole, and the first electrode of the second scan transistor is also connected to the active layer of the second scan transistor through a ninth via hole.
  • the control electrode of the first scan transistor is electrically connected to the integrated structure of the control electrode of the third scan transistor.
  • the first electrode T33 and the second electrode T34 of the third scan transistor are respectively connected to the active terminal of the third scan transistor through the third via hole.
  • layer connection, the first electrode T43 and the second electrode T44 of the fourth scan transistor are connected to the active layer exposing the fourth scan transistor through the fourth via hole, and the first electrode T53 and the second electrode T55 of the fifth scan transistor are connected through
  • the fifth via hole is connected to the active layer of the fifth scan transistor
  • the first electrode T63 of the sixth scan transistor is connected to the active layer of the sixth scan transistor through the sixth via hole
  • the second electrode T74 of the seventh scan transistor passes through
  • the seventh via hole is connected to the active layer of the seventh scan transistor
  • the first electrode T83 and the second electrode T84 of the eighth scan transistor are connected to the active layer of the eighth scan transistor through the eighth via hole
  • the second electrode T84 is electrically connected to the control electrode of the fifth scan transistor through the eleventh via hole.
  • the integrated structure of the second pole T24 of the second scan transistor and the second pole T34 of the third scan transistor is electrically connected to the first connection line through the fifteenth via hole.
  • the second pole T14 of the first transistor and the second pole T14 of the seventh transistor are The integrated structure of the second electrode T74 and the first electrode T83 of the eighth transistor is electrically connected to the control electrode of the second transistor through the tenth via hole.
  • the first electrode T43 of the fourth transistor and the first electrode T63 of the sixth transistor T63 The integrated structure of the second electrode of the fourth transistor T44, the second electrode of the fifth transistor T54 and the first signal output line OL1 is electrically connected to the second plate of the first capacitor through the sixteenth via hole.
  • the first electrode T53 of the fifth transistor is electrically connected to the control electrode of the seventh transistor through the thirteenth via hole, and the second connection line VL2 passes through another
  • the ninth via hole is electrically connected to the integrated structure of the control electrode of the first transistor and the control electrode of the third transistor.
  • the third connection line VL3 is electrically connected to the first connection line through another fifteenth via hole and passes through the tenth via hole.
  • the two via holes are electrically connected to the integrated structure of the control electrode of the fourth transistor and the control electrode of the sixth transistor, and the fourth connection line VL4 is electrically connected to the control electrode of the eighth transistor through the fourteenth via hole.
  • the integrated structure of the second pole T44 of the fourth transistor, the second pole T54 of the fifth transistor and the first signal output line OL1 is connected with the next stage.
  • the first electrode of the first transistor of the scan shift register is electrically connected.
  • Forming a fourth insulating layer pattern includes: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern. As shown in FIG. 20 , FIG. 20 is a schematic diagram after the fourth insulating layer pattern is formed.
  • the plurality of via hole patterns may include: eighteenth to twenty-third via holes V18 to V23 opened on the fourth insulating layer.
  • the eighteenth via V18 exposes the first pole of the third transistor
  • the nineteenth via V19 exposes the fourth connection line
  • the twentieth via V20 exposes the second connection line
  • the twenty-first via V20 exposes the second connection line
  • V21 exposes the integrated structure of the first pole of the fourth transistor and the first pole of the sixth transistor
  • the twenty-second via V22 exposes the first pole of the fifth transistor
  • the twenty-third via V23 exposes the first pole of the fifth transistor.
  • a signal output line is the eighteenth to twenty-third via holes V18 to V23 opened on the fourth insulating layer.
  • the eighteenth via V18 exposes the first pole of the third transistor
  • the nineteenth via V19 exposes the fourth connection line
  • the twentieth via V20 exposes the second connection line
  • the twenty-first via V20 exposes the second connection line
  • V21 exposes
  • the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, Multiple or composite layers.
  • the first insulating layer may be called a second gate insulating layer.
  • Forming a fourth conductive layer pattern includes: depositing a fourth metal film on the substrate on which the foregoing pattern is formed, patterning the fourth metal film through a patterning process, and forming a fourth metal layer pattern, as shown in Figure 21A and Figure 21A.
  • FIG. 21A is a schematic diagram of the fourth conductive layer pattern
  • FIG. 21B is a schematic diagram after the fourth conductive layer pattern is formed.
  • the fourth conductive layer pattern may include: a scan initial signal line GSTV, a first scan clock signal line GCLK1, a second scan clock signal line GCLK2, a first The scanning power supply line GVGH, the second scanning power supply line GVGL and the second signal output line OL2.
  • the fourth conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or more.
  • Various or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the second scan power line GVGL is located on a side of the first scan clock signal line GCLK1 away from the display area, and the second scan clock signal line GCLK2 is located on a side of the first scan clock signal line GCLK1.
  • the clock signal line GCLK1 is located on the side close to the display area
  • the scanning initial signal line GSTV is located on the side of the second scanning clock signal line GCLK2 close to the display area
  • the first scanning power line GVGH is located on the side of the scanning initial signal line GSTV close to the display area.
  • the second signal output line OL2 is located on the side of the first scanning power line GVGH close to the display area.
  • the orthographic projection of the first electrode and the fourth connection line of the third transistor on the substrate is the same as the orthographic projection of the second scanning power line GVGL on the substrate. overlap.
  • the orthographic projection of the second connection line on the substrate is the same as the orthographic projection of the scan clock signal line connected to the first clock signal terminal of the scan shift register on the substrate. Orthographic projections partially overlap.
  • the orthographic projection of the first pole of the fifth transistor on the substrate is at the scan clock signal line connected to the second clock signal terminal of the scan shift register.
  • the orthographic projections on the base partially overlap.
  • the orthographic projection of the second signal output line on the substrate of the same scan shift register partially overlaps with the orthographic projection of the first signal output line on the substrate.
  • the second scanning power line is electrically connected to the first electrode of the third transistor through the eighteenth via hole, and is connected to the fourth through the nineteenth via hole. Cable connection.
  • the second connection line is electrically connected to the scan clock signal line connected to the first clock signal terminal of the scan shift register through the twentieth via hole.
  • the first pole of the fifth transistor is electrically connected to the scan clock signal line connected to the second clock signal terminal of the scan shift register through the 22nd via hole.
  • the first scanning power line GVGH is electrically connected to the integrated structure of the first pole of the fourth transistor and the first pole of the sixth transistor through the twenty-first via hole.
  • the second signal output line OL2 is electrically connected to the first signal output line through the twenty-third via hole.
  • 21A and 21B show that the first electrode of the fifth transistor of the upper scan shift register is electrically connected to the first scan clock signal line GCLK1, and the second connection line is electrically connected to the second scan clock signal line GCLK2.
  • the first electrode of the fifth transistor of the lower scan shift register is electrically connected to the second scan clock signal line GCLK2, and the second connection line is electrically connected to the first scan clock signal line GCLK1 for explanation.
  • Forming the light-emitting structure layer includes: coating a flat film on the substrate with the aforementioned pattern, patterning the flat film by etching to form a flat layer, and depositing a transparent conductive film on the substrate with the flat layer formed, The transparent conductive film is patterned through a patterning process to form an anode, a pixel defining film is deposited on the substrate with the anode formed, the pixel defining film is patterned through the patterning process to form a pixel defining layer, and the pixel defining layer is formed A cathode film is deposited on the substrate, and the cathode film is patterned through a patterning process to form a cathode.
  • the flat layer may be made of organic material.
  • the anode film may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the display substrate adopted in the embodiments of the present disclosure can be applied to display products with any resolution.
  • An embodiment of the present disclosure also provides a display device, including: a display substrate.
  • the display device may be a monitor, a television, a mobile phone, a tablet, a navigator, a digital photo frame, a wearable display product, a product or component with any display function.
  • the display substrate is the display substrate provided in any of the foregoing embodiments.
  • the implementation principles and implementation effects are similar and will not be described again here.

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Abstract

一种显示基板和显示装置，显示基板包括：基底及设置在基底上的电路结构层，电路结构层包括：像素电路（P）、扫描驱动电路、控制驱动电路和缓冲驱动电路；像素电路（P）包括：节点复位晶体管（T1）、写入晶体管（T4）以及复位信号线（RL）、扫描信号线（GL）和控制信号线（SL），复位信号线（RL）与节点复位晶体管（T1）的控制极连接，扫描信号线（GL）与写入晶体管（T4）的控制极连接；第一行至第K行像素电路（P）的复位信号线（RL1-RLK）与缓冲驱动电路电连接，第K+1行至第N行像素电路（P）的复位信号线（RLK+1-RLN）与扫描驱动电路或者控制驱动电路电连接，K使得像素电路（P）扫描信号线（GL）或者控制信号线（SL）的信号的有效电平信号的开始时间与复位信号线的信号为有效电平信号的结束时间之差大于或等于阈值时间。

Description

显示基板和显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：基底以及设置在所述基底上的电路结构层，所述电路结构层包括：像素电路、扫描驱动电路、控制驱动电路和缓冲驱动电路；所述像素电路包括：节点复位晶体管、写入晶体管以及复位信号线、扫描信号线和控制信号线，所述复位信号线与所述节点复位晶体管的控制极连接，所述扫描信号线与写入晶体管的控制极连接；
第一行至第K行像素电路的复位信号线与所述缓冲驱动电路电连接，第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路或者所述控制驱动电路电连接，其中，K使得像素电路的扫描信号线或者控制信号线的信号的有效电平信号的开始时间与复位信号线的信号为有效电平信号的结束时间之差大于或等于阈值时间，N为像素电路的总行数。
在一些可能的实现方式中，所述像素电路还包括：驱动晶体管，所述阈值时间t约等于K*(1/f)/N，或者K*(1/f)/(N+N0)，或者Tstress， 其中，f为显示基板的刷新频率，N为像素电路的总行数，N0为显示基板在N行像素电路工作之前和/或之后的所执行的空白行数之和，N0为大于或者等于0的正整数，Tstress为偏置的驱动晶体管的阈值电压的恢复时间。
在一些可能的实现方式中，第一行至第N行像素电路的扫描信号线与所述扫描驱动电路电连接，第一行至第N行像素电路的控制信号线与所述控制驱动电路电连接；
当节点复位晶体管与写入晶体管的晶体管类型相同时，第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接；所述像素电路还包括：补偿晶体管和补偿复位晶体管；补偿复位晶体管的晶体管类型与驱动晶体管、节点复位晶体管、写入晶体管和补偿晶体管的晶体管类型相反；扫描信号线还与补偿晶体管的控制极电连接，控制信号线与补偿复位晶体管的控制极电连接；
当节点复位晶体管与写入晶体管的晶体管类型相反时，第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接，所述像素电路还包括：补偿晶体管；节点复位晶体管和补偿晶体管的晶体管类型与驱动晶体管和写入晶体管的晶体管类型相反；控制信号线与补偿晶体管的控制极电连接。
在一些可能的实现方式中，包括：显示区域和非显示区域，其中，所述非显示区域包括：围设在所述显示区域外围的边框区域和位于所述边框区域远离显示区域一侧的绑定区域；
所述扫描驱动电路、控制驱动电路和缓冲驱动电路位于所述显示区域和/或非显示区域；
当所述扫描驱动电路、控制驱动电路和缓冲驱动电路位于所述非显示区域时，所述扫描驱动电路和所述控制驱动电路位于所述显示区域相对设置的第一侧和第二侧，所述缓冲驱动电路位于所述显示区域的第三侧或第四侧，所述第三侧位于显示区域远离所述绑定区域的一侧，所述第四侧位于显示区域靠近所述绑定区域的一侧。
在一些可能的实现方式中，还包括：发光驱动电路，所述像素电路还包括：发光晶体管和发光信号线；所述发光信号线与发光晶体管的控制极电连接；所述发光驱动电路位于所述控制驱动电路远离显示区域的一侧；
第一行至第N行像素电路的发光信号线与所述发光驱动电路电连接；
对于同一行像素电路，像素电路的发光信号线的信号的有效电平信号的开始时间与复位信号线的信号为有效电平信号的结束时间之差大于阈值时间和扫描信号线的信号为有效电平信号的持续时间之和。
在一些可能的实现方式中，还包括：测试电路和多路复用电路；所述像素电路还包括：沿第二方向延伸的数据信号线，第一方向与第二方向相交，，所述第一方向为复位信号线、扫描信号线和控制信号线的延伸方向；
所述数据信号线，分别与写入晶体管的第一极、所述测试电路与所述多路复用电路电连接；
所述测试电路位于所述显示区域的第一侧和第三侧，所述多路复用电路位于所述显示区域的第一侧和/或第二侧。
在一些可能的实现方式中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，所述缓冲驱动电路包括：K个级联的缓冲移位寄存器；所述扫描驱动电路包括：N个级联的扫描移位寄存器；所述控制驱动电路包括：N/2个级联的控制移位寄存器，最后一级缓冲移位寄存器的输出端与第一级扫描移位寄存器的输入端电连接；
第a级缓冲移位寄存器与第a行像素电路的复位信号线电连接，1≤a≤K；
第b级扫描移位寄存器与第b行像素电路的扫描信号线电连接，1≤b≤N；
第c级扫描移位寄存器与第K+c行像素电路的复位信号线电连接，1≤c≤N-K；
第d级控制移位寄存器分别与第2d-1行像素电路和第2d行像素电路的控制信号线电连接，1≤d≤N/2。
在一些可能的实现方式中，所述第一级至第N-K扫描移位寄存器包括：相互连接的第一信号输出线和第二信号输出线，所述第二信号输出线位于所述第一信号输出线远离基底的一侧；
第c级扫描移位寄存器的第一信号输出线与第c行像素电路的扫描信号线电连接，第c级扫描移位寄存器的第二信号输出线与第K+c行像素电路的复位信号线电连接；
其中，所述第一信号输出线和所述第二信号输出线位于所述扫描驱动电路和所述显示区域之间，且所述第一信号输出线的延伸方向与所述第二信号输出线的延伸方向相交。
在一些可能的实现方式中，第一级至第K级缓冲移位寄存器包括：与所述第二信号输出线同层设置的第三信号输出线，第a级缓冲移位寄存器的第三信号输出线与第a行像素电路的复位信号线电连接；
所述第N-K+1级至第N级扫描移位寄存器包括：与所述第一信号输出线同层设置的第四信号输出线；第s级扫描移位寄存器的第四信号输出线与第s行像素电路的扫描信号线电连接，N-K+1≤s≤N；
所述第三信号输出线和所述第四信号输出线位于所述扫描驱动电路和所述显示区域之间。
在一些可能的实现方式中，当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，所述缓冲驱动电路包括：K/2个级联的缓冲移位寄存器；所述扫描驱动电路包括：N个级联的扫描移位寄存器；所述控制驱动电路包括：N/2个级联的控制移位寄存器；最后一级缓冲移位寄存器的输出端与第一级控制移位寄存器的输入端电连接；
第i级缓冲移位寄存器分别与第2i-1行像素电路和第2i行像素电路的复位信号线电连接，1≤i≤K/2；
第b级扫描移位寄存器与第b行像素电路的扫描信号线电连接，1≤b≤N；
第m级控制移位寄存器分别与第2m-1行像素电路和第2m行像素电路的控制信号线电连接，1≤m≤N/2；
第n级控制移位寄存器分别与第K+2n-1行像素电路和第K+2n行像素电路的复位信号线电连接，1≤n≤(N-K)/2。
在一些可能的实现方式中，所述第一级至第(N-K)/2级控制移位寄存器包括：相互连接的第一信号输出线和第二信号输出线，所述第二信号输出线位于所述第一信号输出线远离基底的一侧；
第n级控制移位寄存器的第一信号输出线分别与第2n-1行像素电路和第2n行像素电路的控制信号线电连接，第n级控制移位寄存器的第二信号输出 线分别与第K+2n-1行像素电路和第K+2n行像素电路的复位信号线电连接；
其中，所述第一信号输出线和所述第二信号输出线位于所述控制驱动电路和所述显示区域之间，且所述第一信号输出线的延伸方向与所述第二信号输出线的延伸方向相交。
在一些可能的实现方式中，第一级至第K/2级缓冲移位寄存器包括：与第二信号输出线同层设置的第三信号输出线，第i级缓冲移位寄存器的第三信号输出线分别与第2i-1行像素电路和第2i行像素电路的复位信号线电连接；
第(N-K)/2+1级至第N级控制移位寄存器包括：与第一信号输出线同层设置的第四信号输出线；第t级控制移位寄存器的第四信号输出线分别与第2t-1行像素电路和第2t行像素电路的控制信号线电连接，(N-K)/2+1≤t≤N；
所述第三信号输出线和所述第四信号输出线位于所述控制驱动电路和所述显示区域之间。
在一些可能的实现方式中，所述发光驱动电路包括：N/2级发光移位寄存器；
第d级发光移位寄存器分别与第2d-1行像素电路和第2d行像素电路的发光信号线电连接，1≤d≤N/2。
在一些可能的实现方式中，所述显示区域的边界的形状包括：圆角矩形，所述圆角矩形包括：四个圆角和四个边框，所述边框区域包括：位于第一圆角外侧的第一圆角区域、位于第二圆角外侧的第二圆角区域、位于第三圆角外侧的第三圆角区域，位于第四圆角外侧的第四圆角区域、位于第一边框外侧的第一边框区域、位于第二边框外侧的第二边框区域、位于第三边框外侧的第三边框区域，位于第四边框外侧的第四边框区域；
所述第一边框区域、所述第一圆角区域和所述第二圆角区域位于所述显示区域的第一侧，所述第二边框区域、所述第三圆角区域和所述第四圆角区域位于所述显示区域的第二侧，所述第三边框区域位于所述显示区域的第三侧，所述第四边框区域位于所述显示区域的第二侧；
第一行像素电路靠近第三边框区域，第N行像素电路靠近第四边框区域；
扫描驱动电路位于所述第一边框区域、所述第一圆角区域和所述第二圆 角区域，控制驱动电路和发光驱动电路位于所述所述第二边框区域、所述第三圆角区域和所述第四圆角区域；
位于所述第一圆角区域的扫描移位寄存器沿第一圆角排布；
位于所述第二圆角区域的扫描移位寄存器沿第二圆角排布；
位于所述第三圆角区域的控制移位寄存器沿第三圆角排布；
位于所述第四圆角区域的控制移位寄存器沿第四圆角排布。
在一些可能的实现方式中，所述缓冲驱动电路位于所述第三边框区域，且所述缓冲驱动电路中的级联的缓冲移位寄存器沿第一方向排布。
在一些可能的实现方式中，所述测试电路包括：多个测试子电路，部分测试子电路位于所述第三边框区域，且穿插设置在缓冲移位寄存器之间，另一部分测试子电路位于所述第一圆角区域，且穿插设置在位于第一圆角区域的扫描移位寄存器之间；
多路复用电路穿插设置在位于第一边框区域的所述扫描移位寄存器和/或位于所述第二边框区域的所述控制移位寄存器之间。
在一些可能的实现方式中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，K大于或者等于14；
当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，K大于或者等于7。
在一些可能的实现方式中，所述显示区域的边界包括圆形；所述边框区域包括：第一区域至第四区域，所述第一区域和所述第二区域位于所述第三区域和所述第四区域之间，
所述显示区域的沿第一方向延伸中线穿过所述第三区域和所述第四区域；
所述第一区域和所述第二区域分别位于所述显示区域的沿第一方向延伸中线的两侧；
所述第一区域位于所述显示基板的第一侧，所述第二区域位于所述显示区域的第二侧，所述第三区域位于所述显示区域的第三侧，所述第四区域位于所述显示区域的第四侧；
第一行像素电路靠近第四区域，第N行像素电路靠近第三区域；
扫描驱动电路位于所述第一区域，控制驱动电路和发光驱动电路位于所述所述第二区域，
位于所述第一区域的扫描移位寄存器沿圆形边界排布；
位于所述第二区域的控制移位寄存器沿圆形边界排布；
位于所述第二区域的发光移位寄存器沿圆形边界排布。
在一些可能的实现方式中，所述缓冲驱动电路位于所述第四区域，且缓冲驱动电路中的级联的多个缓冲移位寄存器沿第一方向排布。
在一些可能的实现方式中，测试电路位于所述第一区域和所述第三区域；
多路复用电路位于所述第一区域和/或第二区域，且穿插设置在所述扫描移位寄存器和/或所述控制移位寄存器之间。
在一些可能的实现方式中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，K大于或者等于10；
当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，K大于或者等于5。
在一些可能的实现方式中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，所述缓冲移位寄存器和所述扫描移位寄存器的电路结构相同均包括：多个扫描晶体管和多个扫描电容，扫描电容包括：第一极板和第二极板；
所述显示基板还包括：扫描初始信号线、第一扫描时钟信号线和第二扫描时钟信号线、第一扫描电源线和第二扫描电源线；第一级缓冲移位寄存器与扫描初始信号线电连接，所述缓冲驱动电路和所述扫描驱动电路分别与第一扫描时钟信号线和第二扫描时钟信号线、第一扫描电源线和第二扫描电源线电连接；
当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，所述缓冲移位寄存器和所述控制移位寄存器的电路结构相同均包括：多个控制晶体管和多个控制电容，控制电容包括：第一极板和第二极板；
所述显示基板还包括：控制初始信号线、第一控制时钟信号线和第二控制时钟信号线、第一控制电源线和第二控制电源线；第一级缓冲移位寄存器与控制初始信号线电连接，所述缓冲驱动电路和所述控制驱动电路分别与第一控制时钟信号线和第二控制时钟信号线、第一控制电源线和第二控制电源线电连接。
在一些可能的实现方式中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，所述电路结构层包括：依次叠设在所述基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层和平坦层；
所述半导体层包括：多个扫描晶体管的有源层；
所述第一导电层包括：多个扫描晶体管的控制极以及多个扫描电容的第一极板；
所述第二导电层包括：多个扫描电容的第二极板；
所述第三导电层包括：多个扫描晶体管的第一极和第二极、第一级至第N-K级扫描移位寄存器的第一信号输出线以及第N-K+1级至第N级扫描移位寄存器的第四信号输出线；
所述第四导电层包括：扫描初始信号线、第一扫描时钟信号线、第二扫描时钟信号线、第一扫描电源线、第二扫描电源线、第一级至第N-K级扫描移位寄存器的第二信号输出线以及第一级至第K级缓冲移位寄存器的第三输出信号线。
在一些可能的实现方式中，当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，所述电路结构层包括：依次叠设在所述基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层和平坦层；
所述半导体层包括：多个控制晶体管的有源层；
所述第一导电层包括：多个控制晶体管的控制极以及多个控制电容的第一极板；
所述第二导电层包括：多个控制电容的第二极板；
所述第三导电层包括：多个控制晶体管的第一极和第二极、所述第一级至第(N-K)/2级控制移位寄存器的第一信号输出线以及所述第(N-K)/2+1级至第N级控制移位寄存器的第四信号输出线；
所述第四导电层包括：控制初始信号线、第一控制时钟信号线、第二控制时钟信号线、第一控制电源线、第二控制电源线、第一级至第(N-K)/2级控制移位寄存器的第二信号输出线以及第一级至第K/2级缓冲移位寄存器的第三输出信号线。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的显示基板的结构示意图一；
图2为本公开实施例提供的显示基板的结构示意图二；
图3A为一种像素电路的等效电路示意图；
图3B为图3A提供的像素电路的工作时序图
图4A为另一像素电路的等效电路示意图；
图4B为图4A提供的像素电路的工作时序图；
图5为一种显示基板的多个驱动电路的级联示意图；
图6为一种显示基板中的驱动电路与像素电路的连接示意图；
图7为另一显示基板的多个驱动电路的级联示意图；
图8为一种显示基板的多个驱动电路的排布示意图；
图9为另一显示基板的多个驱动电路的排布示意图；
图10A为一种示例性实施例提供的发光移位寄存器的等效电路图；
图10B为图10A提供的发光移位寄存器的时序图；
图11A为一种示例性实施例提供的扫描移位寄存器的等效电路图；
图11B为图11A提供的扫描移位寄存器的时序图；
图12A为一种示例性实施例提供的控制移位寄存器的等效电路图；
图12B为图12A提供的控制移位寄存器的时序图；
图13为一种示例性实施例提供的扫描移位寄存器的结构示意图；
图14为一种示例性实施例提供的控制移位寄存器的结构示意图；
图15为形成半导体层图案后的示意图；
图16A为第一导电层图案的示意图；
图16B为形成第一导电层图案后的示意图；
图17A为第二导电层图案的示意图；
图17B形成第二导电层图案后的示意图；
图18为形成第三绝缘层图案后的示意图；
图19A为第三导电层图案的示意图；
图19B形成第三导电层图案后的示意图；
图20为形成第四绝缘层图案后的示意图；
图21A为第四导电层图案的示意图；
图21B形成第四导电层图案后的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到 的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
显示基板中所用的是低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)技术，LTPS技术拥有高分辨率、高反应速度、高亮度、高开口率等优势。尽管受到了市场欢迎，但LTPS技术也存在一些缺陷，如生产成本较高，所需功耗较大等，此时，低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)技术方案应运而生。相比于LTPS技术，LTPO技术的漏电流更小，像素点反应更快，显示基板多加了一层氧化物，降低了激发像素点所需的能耗，从而降低屏幕显示时的功耗。但是，相比采用LTPS技术的显示产品，采用LTPO技术的显示产品由于像素电路中的驱动晶体管的阈值电压的偏压会造成残像，降低了显示产品的显示效果。
图1为本公开实施例提供的显示基板的结构示意图一，图2为本公开实施例提供的显示基板的结构示意图二。如图1和图2所示，显示基板包括：基底以及设置在基底上的电路结构层，电路结构层包括：像素电路P、扫描驱动电路、控制驱动电路和缓冲驱动电路。像素电路P包括：写入晶体管、节点复位晶体管以及复位信号线、扫描信号线和控制信号线，复位信号线与节点复位晶体管的控制极连接，扫描信号线与写入晶体管的控制极连接。图1和图2是以N行M列像素电路为例进行说明的，RL i指的是第i行像素电路的复位信号线，GL i指的是第i行像素电路的扫描信号线，SL i指的是第i行像素电路的控制信号线。
在一种示例性实施例中，显示基板可以包括：显示区域100和非显示区域。其中，像素电路P位于显示区域100，扫描驱动电路、控制驱动电路和缓冲驱动电路可以位于显示区域100和/或非显示区域，本公开对此不做任何限定。图1和图2是以扫描驱动电路、控制驱动电路和缓冲驱动电路位于非显示区域为例进行说明的。
如图1和图2所示，第一行至第N行像素电路的扫描信号线GL 1至GL N可以与扫描驱动电路电连接，第一行至第N行像素电路的控制信号线SL 1至SL N可以与控制驱动电路电连接，N为像素电路的总行数。
如图1和图2所示，第一行至第K行像素电路的复位信号线RL 1至RL K与缓冲驱动电路电连接，第K+1行至第N行像素电路的复位信号线RL K+1至RL N与扫描驱动电路或者控制驱动电路电连接，其中，K使得像素电路的扫描信号线或者控制信号线的信号的有效电平信号的开始时间与复位信号线的信号为有效电平信号的结束时间之差大于阈值时间。图1是以第K+1行至第N行像素电路的复位信号线RL K+1至RL N与扫描驱动电路电连接为例进行说明的，图2是以第K+1行至第N行像素电路的复位信号线RL K+1至RL N控制驱动电路电连接为例进行说明的。
本公开中，K使得第x行像素电路的扫描信号线或者控制信号线的信号的有效电平信号的开始时间与第x行像素电路的复位信号线的信号为有效电平信号的结束时间之差大于或等于阈值时间，1≤x≤N。
在一种示例性实施例中，像素电路还包括：驱动晶体管。其中，阈值时 间t约等于至少两行像素电路的驱动时间，或者K*(1/f)/N，或者K*(1/f)/(N+N0)，或者Tstress，其中，f为显示基板的刷新频率，N为像素电路的总行数，N0为显示基板在N行像素电路工作之前和/或之后的所执行的空白行数之和，N0为大于或者等于0的正整数，Tstress为偏置的驱动晶体管的阈值电压的恢复时间。
K*(1/f)/N，或者(1/f)/(N+N0)为一行像素电路的驱动时间。以显示基板包括：496行378列像素电路，且刷新率为60Hz以及显示基板在像素电路工作之前所执行的24个空白行数，显示之后包括20个空白行数为例，(1/f)/(N+N0)＝1/60/(496+44)＝30.8us。以显示基板包括：466行466列像素电路，且刷新率为60Hz以及显示之前包括24个空白阶段，显示之后包括20个空白阶段为例，(1/f)/(N+N0)＝1/60/(466+44)＝32.7us。
在一种示例性实施例中，阈值时间t约等于至少两行像素电路的驱动时间。例如：阈值时间t约等于至少3～6行像素电路的驱动时间。
在一种示例性实施例中，驱动晶体管的阈值电压一般偏置0.3伏特。
在一种示例性实施例中，偏置的驱动晶体管的阈值电压的恢复时间约为250微秒至300微秒。
在一种示例性实施例中，显示基板可以为LTPO显示基板。
在一种示例性实施例中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，显示基板还可以包括：位于电路结构层远离基底一侧的发光结构层，发光结构层包括：位于显示区域，且阵列排布的发光元件，发光元件包括：第一极(阳极)、有机发光层和第二极(阴极)，阳极位于有机发光层靠近基底的一侧，阴极位于有机发光层远离基底的一侧；发光元件与像素电路电连接。
在一种示例性实施例中，电路结构层还可以包括：位于非显示区域的低 电平电源线，低电平电源线与发光元件的阴极电连接。
在一种示例性实施例中，发光元件可以是有机电致发光二极管(OLED)或者量子点发光二极管(QLED)。其中，OLED可以包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
在一种示例性实施例中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在一种示例性实施例中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在一种示例性实施例中，如图1和图2所示，显示基板还可以包括位于时序控制器和源极驱动电路。时序控制器和源极驱动电路可以位于非显示区域。
在一种示例性实施例中，时序控制器可以将适合于源极驱动电路的规格的灰度值和控制信号提供到源极驱动电路，可以将适合于扫描驱动电路的规格的时钟信号、扫描起始信号等提供到扫描驱动电路，可以将适合于控制驱动电路的规格的时钟信号、控制起始信号等提供到控制驱动电路，可以将适合于发光驱动电路的规格的时钟信号、发射停止信号等提供到发光驱动电路。
在一种示例性实施例中，源极驱动电路可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D 1、D 2、D 3、……和D M的数据电压。例如，源极驱动电路可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D 1至D M。
在一种示例性实施例中，扫描驱动电路可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线GL 1、GL 2、GL 3、……和 GL M的扫描信号。例如，扫描驱动电路可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线GL 1至GL M。例如，扫描驱动电路可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。
在一种示例性实施例中，控制驱动电路可以通过从时序控制器接收时钟信号、控制起始信号等来产生将提供到控制信号线SL 1、SL 2、SL 3、……和SL M的控制信号。例如，控制驱动电路可以将具有导通电平脉冲的控制信号顺序地提供到控制信号线SL 1至SL M。例如，控制驱动电路可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的控制起始信号传输到下一级电路的方式产生控制信号。
在一种示例性实施例中，发光驱动电路可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线EL 1、EL 2、EL 3、……和EL M的发射信号。例如，发光驱动电路可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线EL 1至EL M。例如，发光驱动电路可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号。
本公开实施例提供的显示基板包括：基底以及设置在基底上的电路结构层，电路结构层包括：像素电路、扫描驱动电路、控制驱动电路和缓冲驱动电路；像素电路包括：写入晶体管、节点复位晶体管以及复位信号线、扫描信号线和控制信号线，复位信号线与节点复位晶体管的控制极连接，扫描信号线与写入晶体管的控制极连接；第一行至第K行像素电路的复位信号线与缓冲驱动电路电连接，第K+1行至第N行像素电路的复位信号线与扫描驱动电路或者控制驱动电路电连接，以使得像素电路扫描信号线或者控制信号线的信号的有效电平信号的开始时间与复位信号线的信号为有效电平信号的结束时间之差大于阈值时间。本公开通过设置缓冲驱动电路可以拉长像素电路复位信号线为有效电平信号的时间与像素电路扫描信号线或者控制信号线为有效电平信号的时间之差，使得像素电路的驱动晶体管的控制极可以充分的复位，阈值电压可以从偏置状态恢复，从而改善显示基板的残像，提升显示基板的显示效果。
如图1和图2所示，一种示例性实施例提供的显示基板还可以包括：发光驱动电路，像素电路还包括：发光晶体管和发光信号线；发光信号线与发光晶体管的控制极电连接；发光驱动电路位于所述控制驱动电路远离显示区域100的一侧。第一行至第N行像素电路的发光信号线与发光驱动电路电连接。图1和图2中EL i指的是第i行像素电路的发光信号线。
一种示例性实施例中，对于同一行像素电路，像素电路的发光信号线的信号的有效电平信号的开始时间与复位信号线的信号为有效电平信号的结束时间之差大于阈值时间和扫描信号线的信号为有效电平信号的持续时间之和。
一种示例性实施例中，对于同一行像素电路，像素电路的发光信号线的信号的有效电平信号的开始时间与复位信号线的信号为有效电平信号的结束时间之差等于阈值时间和扫描信号线的信号为有效电平信号的持续时间之和。
如图1和图2所示，一种示例性实施例提供的显示基板还可以包括：测试电路和多路复用电路(图中未示出)；像素电路还包括：沿第二方向延伸的数据信号线D，第一方向与第二方向相交，第一方向为复位信号线、扫描信号线和控制信号线的延伸方向。如图1和图2中的Di指的是第i列像素电路的数据信号线。数据信号线，分别与写入晶体管的第一极、测试电路与多路复用电路电连接；测试电路位于显示区域的第一侧和第三侧，多路复用电路位于显示区域的第一侧和/或第二侧。
在一种示例性实施例中，当节点复位晶体管与写入晶体管的晶体管类型相同时，第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接。此时，像素电路还可以包括：补偿晶体管和补偿复位晶体管；补偿复位晶体管的晶体管类型与驱动晶体管、节点复位晶体管、写入晶体管和补偿晶体管的晶体管类型相反；扫描信号线还与补偿晶体管的控制极电连接，控制信号线与补偿复位晶体管的控制极电连接。
在一种示例性实施例中，当节点复位晶体管与写入晶体管的晶体管类型相反时，第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接，所述像素电路还包括：补偿晶体管；节点复位晶体管和补偿晶体管的晶体管类型与驱动晶体管和写入晶体管的晶体管类型相反；控制信号线与补偿晶体管的控制极电连接。
在一种示例性实施例中，图3A为一种像素电路的等效电路示意图。如图3A所示，像素电路可以包括8个晶体管(第一晶体管T1到第八晶体管T8)、1个电容C和8个信号线(数据信号线D、控制信号线SL、扫描信号线GL、复位信号线RL、发光信号线EL、第一初始信号线Vinit1、第二初始信号线Vinit2、第一电源线VDD和第二电源线VSS)。图3A是以当节点复位晶体管与写入晶体管的晶体管类型相同为例进行说明的。
在一种示例性实施例中，电容C的第一极板与第一电源线VDD连接，电容C的第二极板与第一节点N1连接。第一晶体管T1的控制极与复位信号线RL连接，第一晶体管T1的第一极与第一初始信号线Vinit1连接，第一晶体管的第二极与第四节点N4连接。第二晶体管T2的控制极与扫描信号线GL连接，第二晶体管T2的第一极与第四节点N4连接，第二晶体管T2的第二极与第二节点N2连接。第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的控制极与扫描信号线GL连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第三节点N3连接。第五晶体管T5的控制极与发光信号线EL连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第三节点N3连接。第六晶体管T6的控制极与发光信号线EL连接，第六晶体管T6的第一极与第二节点N2连接，第六晶体管T6的第二极与发光元件L的第一极连接。第七晶体管T7的控制极与复位信号线RL连接，第七晶体管T7的第一极与第二初始信号线Vinit2连接，第七晶体管T7的第二极与发光元件L的第一极连接，发光元件L的第二极与第二电源线VSS连接。第八晶体管T8的控制极与控制信号线SL连接，第八晶体管T8的第一极与第一节点N1连接，第八晶体管T8的第二极与第四节点N4连接。
在一种示例性实施例中，第七晶体管T7的控制极还可以与扫描信号线GL连接，第七晶体管T7的第一极与第二初始信号线Vinit2连接，第七晶体管T7的第二极与发光元件L的第一极连接，发光元件L的第二极与第二电源线VSS连接。
在一种示例性实施例中，第一晶体管T1可以称为节点复位晶体管，当 复位信号线RL输入有效电平信号时，第一晶体管T1将初始化电压传输到第一节点N1，以使第一节点N1的电荷量初始化。
在一种示例性实施例中，第八晶体管T8可以称为补偿复位晶体管，当控制信号线SL输入有效电平信号时，第八晶体管T8将第四节点N4的信号传输至第一节点N1，不仅可以将第一节点的电荷量初始化，还可以对第三晶体管T3进行阈值补偿。
在一种示例性实施例中，第二晶体管T2可以称为补偿晶体管，当扫描信号线GL输入有效电平信号时，第二晶体管T2使第二节点N2的信号写入至第四节点N4。
在一种示例性实施例中，第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据控制极与第一极之间的电位差来确定在第一电源端VDD与第二电源端VSS之间流动的驱动电流。
在一种示例性实施例中，第四晶体管T4可以称为写入晶体管，当扫描信号线GL输入有效电平信号时，第四晶体管T4使数据信号线D的数据电压输入到像素电路。
在一种示例性实施例中，第五晶体管T5和第六晶体管T6可以称为发光晶体管。当发光信号线EL输入有效电平信号时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光元件发光。
在一种示例性实施例中，第一电源线VDD的信号为持续提供高电平信号，第二电源线VSS的信号为低电平信号。
在一种示例性实施例中，第八晶体管T8为金属氧化物晶体管，且为N型晶体管，第一晶体管T1至第七晶体管T7为低温多晶硅晶体管，且为P型晶体管。
在一种示例性实施例中，第八晶体管T8为氧化物晶体管可以减少漏电流，提升像素电路的性能，可以降低像素电路的功耗。
图3B为图3A提供的像素电路的工作时序图。下面通过图3B示例的像素电路的工作过程说明本公开示例性实施例。像素电路的工作过程可以包括：
第一阶段A1，称为复位阶段，控制信号线SL、发光信号线EL和扫描信号线GL的信号均为高电平信号，复位信号线RL的信号为低电平信号。复位信号线RL的信号为低电平信号，第一晶体管T1导通，第一初始信号线Vinit1的信号提供至第四节点N4，第七晶体管T7导通，第二初始信号线Vinit2的初始电压提供至发光元件L的第一极，对发光元件L的第一极进行初始化(复位)，例如：清空其内部的预存电压，完成初始化，确保发光元件L不发光。控制信号线SL的信号为高电平信号，第八晶体管T8导通，第四节点N4的信号提供至第一节点N1，对电容C进行初始化，清除电容C中原有数据电压。扫描信号线GL和发光信号线EL的信号为高电平信号，第二晶体管T2、第四晶体管T4、第五晶体管T5和第六晶体管T6第七晶体管T7截止，此阶段，发光元件L不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线GL的信号为低电平信号，复位信号线RL、发光信号线EL和控制信号线SL的信号为高电平信号，数据信号线D输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管T3导通。扫描信号线GL的信号为低电平信号，第二晶体管T2和第四晶体管T4导通，控制信号线SL的信号为高电平信号，第八晶体管T8导通。第二晶体管T2、第四晶体管T4和第八晶体管T8导通使得数据信号线D输出的数据电压经过第三节点N3、导通的第三晶体管T3、第二节点N2、导通的第二晶体管T2、第四节点N4和导通的第八晶体管T8提供至第一节点N1，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。复位信号线RL的信号为低电平信号，第一晶体管T1和第七晶体管T7断开。发光信号线EL的信号为高电平信号，第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，控制信号线SL和发光信号线EL的信号均为低电平信号，扫描信号线GL和复位信号线RL的信号为高电平信号。复位信号线RL的信号为低电平信号，第一晶体管T1和第七晶体管T7截止。控制信号线SL为低电平信号、扫描信号线GL和复位信号线RL的信号为高电平信号，第二晶体管T2、第四晶体管T4和第八晶体管T8截止。发光信 号线EL的信号为低电平信号，第五晶体管T5和第六晶体管T6导通，第一电源端VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件L的第一极提供驱动电压，驱动发光元件L发光。
在像素电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的控制极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源端VDD输出的电源电压。
在一种示例性实施例中，图4A为另一像素电路的等效电路示意图。如图4A所示，像素电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个电容C和9个信号线(数据信号线D、控制信号线SL、扫描信号线GL、复位信号线RL、发光信号线EL、第一初始信号线Vinit1、第二初始信号线Vinit2、第一电源线VDD和第二电源线VSS)。图4A是以当节点复位晶体管与写入晶体管的晶体管类型相反为例进行说明的。
如图4A所示，电容C的第一极板与第一电源线VDD连接，电容C的第二极板与第一节点N1连接。第一晶体管T1的控制极与复位信号线RL连接，第一晶体管T1的第一极与第一初始信号线Vinit1连接，第一晶体管的第二极与第一节点N1连接；第二晶体管T2的控制极与控制信号线SL连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第二节点N2连接。第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的控制极与扫描信号线GL连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第三节点N3连接。第五晶体管T5的控制极与发光信号线EL连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第三节点N3连接；第六晶体管T6的控制极与发光信号线EL连接，第六晶体管T6的第一极与第二 节点N2连接，第六晶体管T6的第二极与发光器件的第一极连接。第七晶体管T7的控制极与扫描信号线GL连接，第七晶体管T7的第一极与第二初始信号线Vinit2连接，第七晶体管T7的第二极与发光器件的第一极连接，发光器件的第二极与第二电源线VSS连接。
在一种示例性实施例中，第一晶体管T1可以称为节点复位晶体管，当复位信号线RL输入有效电平信号时，第一晶体管T1将初始化电压传输到第一节点N1，以使第一节点N1的电荷量初始化。
在一种示例性实施例中，第二晶体管T2可以称为补偿晶体管，当控制信号线SL输入有效电平信号时，第二晶体管T2将第二节点N2的信号传输到第一节点N1，以对第一节点N1的信号进行补偿。
在一种示例性实施例中，第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流。
在一种示例性实施例中，第四晶体管T4可以称为写入晶体管等，当扫描信号线GL输入有效电平信号时，第四晶体管T4使数据信号线D的数据电压输入到第三节点N3。
在一种示例性实施例中，第五晶体管T5和第六晶体管T6可以称为发光控制晶体管。当发光信号线EL输入有效电平信号时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
在一种示例性实施例中，第一电源线VDD的信号为持续提供高电平信号，第二电源线VSS的信号为低电平信号。
在一种示例性实施例中，第一晶体管T1和第二晶体管T2为金属氧化物晶体管，且为N型晶体管，第三晶体管T3至第七晶体管T7为低温多晶硅晶体管，且为P型晶体管。
在一种示例性实施例中，第一晶体管T1和第二晶体管T2为氧化物晶体管可以减少漏电流，提升像素电路的性能，可以降低像素电路的功耗。
图4B为图4A提供的像素电路的工作时序图。下面通过图4B示例的像 素电路的工作过程说明本公开示例性实施例。在一种示例性实施例中，像素电路的工作过程可以包括：
第一阶段A1，称为复位阶段，复位信号线RL、扫描信号线GL和发光信号线EL的信号均为高电平信号，控制信号线SL的信号为低电平信号。复位信号线RL的信号为高电平信号，第一晶体管T1导通，第一初始信号线Vinit1的信号提供至第一节点N1，对电容C进行初始化，清除电容C中原有数据电压。扫描信号线GL和发光信号线EL的信号为高电平信号，控制信号线SL的信号为低电平信号，第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线GL和复位信号线RL的信号为低电平信号，发光信号线EL和控制信号线SL的信号为高电平信号，数据信号线D输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管T3导通。扫描信号线GL的信号为低电平信号，第四晶体管T4和第七晶体管T7导通，控制信号线SL的信号为高电平信号，第二晶体管T2导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第三节点N3、导通的第三晶体管T3、第二节点N2和导通的第二晶体管T2提供至第一节点N1，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得第二初始信号线Vinit2的初始电压提供至发光元件L的第一极，对发光元件L的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件L不发光。复位信号线RL的信号为低电平信号，第一晶体管T1断开。发光信号线EL的信号为高电平信号，第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，扫描信号线GL的信号为高电平信号，控制信号线SL、发光信号线EL和复位信号线RL的信号均为低电平信号。发光信号线EL的信号为低电平信号，第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件L的第一极提供驱动电压，驱动发光元件L发 光。
在像素电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的控制极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
在一种示例性实施例中，非显示区域可以包括：围设在显示区域外围的边框区域和位于边框区域远离显示区域一侧的绑定区域。
当扫描驱动电路、控制驱动电路和缓冲驱动电路位于非显示区域时，如图1和图2所示，扫描驱动电路和控制驱动电路可以位于显示区域相对设置的第一侧和第二侧，缓冲驱动电路可以位于显示区域的第三侧或第四侧，第三侧位于显示区域远离绑定区域的一侧，第四侧位于显示区域靠近绑定区域的一侧。
图5为一种显示基板的多个驱动电路的级联示意图。结合图1和图5所示，当第K+1行至第N行像素电路的复位信号线与扫描驱动电路电连接时，缓冲驱动电路包括：K个级联的缓冲移位寄存器GateB(1)至GateB(K)；扫描驱动电路包括：N个级联的扫描移位寄存器GateG(1)至GateG(N)；控制驱动电路包括：N/2个级联的控制移位寄存器GateS(1)至GateS(N/2)，最后一级缓冲移位寄存器GateB(K)的输出端与第一级扫描移位寄存器GateG(1)的输入端电连接。图5中的R(i)指的是第i行像素电路。
如图1和图5所示，第a级缓冲移位寄存器GateB(a)与第a行像素电路的复位信号线电连接，1≤a≤K。
如图1和图5所示，第b级扫描移位寄存器GateG(b)与第b行像素电路的扫描信号线电连接，1≤b≤N。
如图1和图5所示，第c级扫描移位寄存器GateG(c)与第K+c行像素 电路的复位信号线电连接，1≤c≤N-K。
如图1和图5所示，第d级控制移位寄存器GateS(d)分别与第2d-1行像素电路和第2d行像素电路的控制信号线电连接，1≤d≤N/2。
图6为一种显示基板中的驱动电路与像素电路的连接示意图。如图6所示，第一级至第N-K扫描移位寄存器GateG(1)至GateG(N-K)包括：相互连接的第一信号输出线OL1和第二信号输出线OL2，第二信号输出线OL2位于第一信号输出线OL1远离基底的一侧。第c级扫描移位寄存器的第一信号输出线与第c行像素电路的扫描信号线GL(c)电连接，第c级扫描移位寄存器的第二信号输出线与第K+c行像素电路的复位信号线RL(K+c)电连接。
在一种示例性实施例中，如图6所示，第一信号输出线OL1和第二信号输出线OL2位于扫描驱动电路和显示区域之间，且第一信号输出线OL1的延伸方向与第二信号输出线OL2的延伸方向相交。
如图6所示，第一级至第K级缓冲移位寄存器GateB(1)至GateB(K)包括：与第二信号输出线OL2同层设置的第三信号输出线OL3，第a级缓冲移位寄存器GateB(a)的第三信号输出线与第a行像素电路的复位信号线RL(a)电连接。
在一种示例性实施例中，如图6所示，第N-K+1级至第N级扫描移位寄存器GateG(N-K+1)至GateG(N)包括：与第一信号输出线OL1同层设置的第四信号输出线OL4；第s级扫描移位寄存器GateS(s)的第四信号输出线与第s行像素电路的扫描信号线GL(s)电连接，N-K+1≤s≤N。
在一种示例性实施例中，如图6所示，第三信号输出线OL3和第四信号输出线OL 4位于扫描驱动电路和显示区域之间。
图7为另一显示基板的多个驱动电路的级联示意图。如图2和图7所示，当第K+1行至第N行像素电路的复位信号线与控制驱动电路电连接时，缓冲驱动电路包括：K/2个级联的缓冲移位寄存器GateB(1)至GateB(K/2)；扫描驱动电路包括：N个级联的扫描移位寄存器GateG(1)至GateG(N)；控制驱动电路包括：N/2个级联的控制移位寄存器GateS(1)至GateS(N/2)；最后一级缓冲移位寄存器GateB(K/2)的输出端与第一级控制移位寄存器 GateS(1)的输入端电连接。
如图2和图7所示，第i级缓冲移位寄存器GateB(i)分别与第2i-1行像素电路和第2i行像素电路的复位信号线电连接，1≤i≤K/2。
如图2和图7所示，第b级扫描移位寄存器GateG(b)与第b行像素电路的扫描信号线电连接，1≤b≤N。
如图2和图7所示，第m级控制移位寄存器GateS(m)分别与第2m-1行像素电路和第2m行像素电路的控制信号线电连接，1≤m≤N/2。
如图2和图7所示，第n级控制移位寄存器GateS(n)分别与第K+2n-1行像素电路和第K+2n行像素电路的复位信号线电连接，1≤n≤(N-K)/2。
在一种示例性实施例中，第一级至第(N-K)/2级控制移位寄存器包括：相互连接的第一信号输出线和第二信号输出线，第二信号输出线位于第一信号输出线远离基底的一侧。第n级控制移位寄存器的第一信号输出线分别与第2n-1行像素电路和第2n行像素电路的控制信号线电连接，第n级控制移位寄存器的第二信号输出线分别与第K+2n-1行像素电路和第K+2n行像素电路的复位信号线电连接。
在一种示例性实施例中，第一信号输出线和第二信号输出线位于控制驱动电路和显示区域之间，且第一信号输出线的延伸方向与第二信号输出线的延伸方向相交。
在一种示例性实施例中，第一级至第K/2级缓冲移位寄存器包括：与第二信号输出线同层设置的第三信号输出线，第i级缓冲移位寄存器的第三信号输出线分别与第2i-1行像素电路和第2i行像素电路的复位信号线电连接。
在一种示例性实施例中，第(N-K)/2+1级至第N级控制移位寄存器包括：与第一信号输出线同层设置的第四信号输出线；第t级控制移位寄存器的第四信号输出线分别与第2t-1行像素电路和第2t行像素电路的控制信号线电连接，(N-K)/2+1≤t≤N。
在一种示例性实施例中，第三信号输出线和第四信号输出线位于控制驱动电路和显示区域之间。
如图5和图7所示，发光驱动电路可以包括：N/2级发光移位寄存器EM (1)至EM(N/2)。第d级发光移位寄存器分别与第2d-1行像素电路和第2d行像素电路的发光信号线电连接，1≤d≤N/2。
图8为一种显示基板的多个驱动电路的排布示意图。如图8所示，显示区域100的边界的形状包括：圆角矩形，圆角矩形包括：四个圆角和四个边框，边框区域200包括：位于第一圆角外侧的第一圆角区域CR1、位于第二圆角外侧的第二圆角区域CR2、位于第三圆角外侧的第三圆角区域CR3，位于第四圆角外侧的第四圆角区域CR4、位于第一边框外侧的第一边框区域LR1、位于第二边框外侧的第二边框区域LR2、位于第三边框外侧的第三边框区域LR3，位于第四边框外侧的第四边框区域LR4。其中，第一边框区域LR1、第一圆角区域CR1和第二圆角区域CR2位于显示区域100的第一侧，第二边框区域LR2、第三圆角区域CR3和第四圆角区域CR4位于显示区域100的第二侧，第三边框区域LR3位于显示区域100的第三侧，第四边框区域LR4位于显示区域100的第二侧。
在一种示例性实施例中，第一行像素电路靠近第三边框区域LR3，第N行像素电路靠近第四边框区域LR4。
在一种示例性实施例中，第一圆角区域至第四圆角区域的宽度可以约为1300微米至1400微米。示例性地，第一圆角区域至第四圆角区域的宽度可以约为1345微米。
在一种示例性实施例中，如图8所示，包括多个级联的扫描移位寄存器GateG(1)至GateG(N)的扫描驱动电路位于第一边框区域LR1、第一圆角区域CR1和第二圆角区域CR2，包括多个级联的控制移位寄存器GateS(1)至GateS(N/2)的控制驱动电路和包括多个级联的发光移位寄存器EM(1)至EM(N/2)的发光驱动电路位于第二边框区域LR2、第三圆角区域CR3和第四圆角区域CR4。
在一种示例性实施例中，如图8所示，位于第一圆角区域CR1的扫描移位寄存器沿第一圆角排布；位于第二圆角区域CR2的扫描移位寄存器沿第二圆角排布；位于第三圆角区域CR3的控制移位寄存器沿第三圆角排布；位于第四圆角区域CR4的控制移位寄存器沿第四圆角排布。
在一种示例性实施例中，如图8所示，包括：多个级联的缓冲移位寄存 器的缓冲驱动电路位于第三边框区域LR3，且缓冲驱动电路中的级联的缓冲移位寄存器沿第一方向排布。
在一种示例性实施例中，如图8所示，测试电路CT包括：多个测试子电路，部分测试子电路位于第三边框区域LR3，且穿插设置在缓冲移位寄存器之间，另一部分测试子电路位于第一圆角区域CR1，且穿插设置在位于第一圆角区域CR1的扫描移位寄存器之间。
在一种示例性实施例中，如图8所示，多路复用电路MUX穿插设置在位于第一边框区域LR1的扫描移位寄存器和/或位于第二边框区域LR2的控制移位寄存器之间。
在一种示例性实施例中，显示区域的边界为圆角矩形时，当第K+1行至第N行像素电路的复位信号线与扫描驱动电路电连接时，K大于或者等于14；当第K+1行至第N行像素电路的复位信号线与控制驱动电路电连接时，K大于或者等于7。
图9为另一显示基板的多个驱动电路的排布示意图。如图9所示，显示区域的边界包括圆形；边框区域200包括：第一区域R1至第四区域R4，第一区域R1和第二区域R2位于第三区域R3和第四区域R4之间。显示区域100的沿第一方向延伸中线穿过第三区域R3和第四区域R4；第一区域R1和第二区域R2分别位于显示区域100的沿第一方向延伸中线的两侧；第一区域R1位于显示基板的第一侧，第二区域R2位于显示区域100的第二侧，第三区域R3位于显示区域100的第三侧，第四区域R4位于显示区域100的第四侧。
在一种示例性实施例中，第一区域至第四区域的宽度可以约为1100微米至1300微米，示例性地，第一区域至第四区域的宽度可以约为1200微米。
在一种示例性实施例中，当显示区域100的边界为圆形时，第一行像素电路靠近第四区域R4，第N行像素电路靠近第三区域R3。
在一种示例性实施例中，如图9所示，包括：包括多个级联的扫描移位寄存器GateG(1)至GateG(N)的扫描驱动电路位于第一区域R1，包括多个级联的控制移位寄存器GateS(1)至GateS(N/2)的控制驱动电路和包括多个级联的发光移位寄存器EM(1)至EM(N/2)的发光驱动电路位于第二区域 R2。
在一种示例性实施例中，如图9所示，位于第一区域R1的扫描移位寄存器沿圆形边界排布；位于第二区域R2的控制移位寄存器沿圆形边界排布；位于第二区域R2的发光移位寄存器沿圆形边界排布。
在一种示例性实施例中，如图9所示，包括多个级联的缓冲移位寄存器的缓冲驱动电路位于第四区域R4，且缓冲驱动电路中的级联的多个缓冲移位寄存器沿第一方向排布。
在一种示例性实施例中，如图9所示，测试电路CT位于第一区域R1和第三区域R3。位于第一区域R1的测试电路CT穿插设置在位于第一区域R1的扫描移位寄存器之间。
在一种示例性实施例中，如图9所示，多路复用电路位于第一区域R1和/或第二区域R2，且穿插设置在扫描移位寄存器和/或控制移位寄存器之间。
在一种示例性实施例中，当显示区域100的边界为圆形时，当第K+1行至第N行像素电路的复位信号线与扫描驱动电路电连接时，K大于或者等于10；当第K+1行至第N行像素电路的复位信号线与控制驱动电路电连接时，K大于或者等于5。
如图8和图9所示，绑定区域300可以包括：弯折区301和复合电路区302。在示例性实施方式中，弯折区301可以以一曲率弯曲，可以将复合电路区302的表面反转，即复合电路区302朝向上方的表面可以通过弯折区302的弯曲转换成面朝向下方。在示例性实施方式中，当弯折区301被弯曲时，复合电路区302可以与显示区域100重叠。
在一种示例性实施例中，弯折区沿第一方向的长度大于复合电路区沿第一方向的平均长度。复合电路区沿第一方向的长度沿着第二方向逐渐变化，且复合电路区靠近弯折区的沿第一方向的长度小于复合电路区远离弯折区的沿第一方向的长度。
在示例性实施方式中，复合电路区302可以包括防静电区、驱动芯片区和绑定引脚区，集成电路(Integrate Circuit，简称IC)可以绑定连接在驱动芯片区，柔性电路板(Flexible Printed Circuit，简称FPC)可以绑定连接在绑 定引脚区。在示例性实施方式中，集成电路可以产生用于驱动子像素所需的驱动信号，并且可以将驱动信号提供给在显示区域100中的子像素。例如，驱动信号可以是驱动子像素发光亮度的数据信号。在示例性实施方式中，集成电路可以通过各向异性导电膜或者其它方式绑定连接在驱动芯片区。在示例性实施方式中，绑定引脚区可以设置包括多个引脚(PIN)的焊盘，柔性电路板可以绑定连接到焊盘上。
在一种示例性实施例中，当第K+1行至第N行像素电路的复位信号线与扫描驱动电路电连接时，缓冲移位寄存器和扫描移位寄存器的电路结构相同均包括：多个扫描晶体管和多个扫描电容，扫描电容包括：第一极板和第二极板。显示基板还包括：扫描初始信号线、第一扫描时钟信号线和第二扫描时钟信号线、第一扫描电源线和第二扫描电源线；第一级缓冲移位寄存器与扫描初始信号线电连接，缓冲驱动电路和扫描驱动电路分别与第一扫描时钟信号线和第二扫描时钟信号线、第一扫描电源线和第二扫描电源线电连接。
在一种示例性实施例中，当第K+1行至第N行像素电路的复位信号线与控制驱动电路电连接时，缓冲移位寄存器和控制移位寄存器的电路结构相同均包括：多个控制晶体管和多个控制电容，控制电容包括：第一极板和第二极板；显示基板还包括：控制初始信号线、第一控制时钟信号线和第二控制时钟信号线、第一控制电源线和第二控制电源线；第一级缓冲移位寄存器与控制初始信号线电连接，缓冲驱动电路和控制驱动电路分别与第一控制时钟信号线和第二控制时钟信号线、第一控制电源线和第二控制电源线电连接。
在一种示例性实施例中，发光移位寄存器可以包括：多个发光晶体管和多个发光电容。发光移位寄存器的电路结构可以为13T3C或者10T3C，本公开对此不作任何限定。
在一种示例性实施例中，扫描移位寄存器可以包括：多个扫描晶体管和多个扫描电容。扫描移位寄存器的电路结构可以为8T2C，本公开对此不作任何限定。
在一种示例性实施例中，控制移位寄存器包括：多个控制晶体管和多个控制电容，控制移位寄存器的电路结构可以为8T2C，本公开对此不作任何限定。
图10A为一种示例性实施例提供的发光移位寄存器的等效电路图，图10B为图10A提供的发光移位寄存器的时序图。如图10A和图10B所示，在一种示例性实施例中，发光移位寄存器可以包括：第一发光晶体管ET1至第十三发光晶体管ET13以及第一发光电容EC1至第三发光电容EC3。
在一种示例性实施例中，第一发光晶体管ET1的控制极与第三时钟信号端ECK3电连接，第一发光晶体管ET1的第一极与输入端EIN电连接，第一发光晶体管ET1的第二极与第一节点E1电连接。第二发光晶体管ET2的控制极与第一节点E1电连接，第二发光晶体管ET2的第一极与第三时钟信号端ECK3电连接，第二发光晶体管ET2的第二极与第二节点E2电连接。第三发光晶体管ET3的控制极与第三时钟信号端ECK3电连接，第三发光晶体管ET3的第一极与第二电源端VGL电连接，第三发光晶体管ET3的第二极与第二节点E2电连接。第四发光晶体管ET4的控制极与第三节点E3电连接，第四发光晶体管ET4的第一极与第一时钟信号端ECK1电连接，第四发光晶体管ET4的第二极与第五节点E5电连接。第五发光晶体管ET5的控制极与第四节点E4电连接，第五发光晶体管ET5的第一极与第五节点E5电连接，第五发光晶体管ET5的第二极与第一电源端VGH电连接。第六发光晶体管ET6的控制极与第四节点E4电连接，第六发光晶体管ET6的第一极与第一时钟信号端ECK1电连接，第六发光晶体管ET6的第二极与第六节点E6电连接。第七发光晶体管ET7的控制极与第一时钟信号端ECK1电连接，第七发光晶体管ET7的第一极与第六节点E6电连接，第七发光晶体管ET7的第二极与第七节点E7电连接。第八发光晶体管ET8的控制极与第一节点E1电连接，第八发光晶体管ET8的第一极与第一电源端VGH电连接，第八发光晶体管ET8的第二极与第七节点E7电连接。第九发光晶体管ET9的控制极与第七节点E7电连接，第九发光晶体管ET9的第一极与第一电源端VGH电连接，第九发光晶体管ET9的第二极与输出端EOUT电连接。第十发光晶体管ET10的控制极与第三节点E3电连接，第十发光晶体管ET10的第一极与第二电源端VGL电连接，第十发光晶体管ET10的第二极与输出端EOUT电连接。第十一发光晶体管ET11的控制极与第二电源端VGL电连接，第十一发光晶体管ET11的第一极与第二节点E2电连接，第十一发光晶体管ET11的第二极与第四节点E4电连接。第十二发光晶体管ET12的控制极与第二电 源端VGL电连接，第十二发光晶体管ET12的第一极与第一节点E1电连接，第十二发光晶体管ET12的第二极与第三节点E3电连接。第十三发光晶体管ET13的控制极与第二时钟信号端ECK2电连接，第十三发光晶体管ET13的第一极与第一节点E1电连接，第十三发光晶体管ET13的第二极与第一电源端VGH电连接。第一发光电容EC1的第一极板EC11与第四节点E4电连接，第一发光电容EC1的第二极板EC12与第六节点E6电连接。第二发光电容EC2的第一极板EC21与第七节点E7电连接，第二发光电容EC2的第二极板EC22与第一电源端VGH电连接。第三发光电容EC3的第一极板EC31与第三节点E3电连接，第三发光电容EC3的第二极板EC32与第五节点E5电连接。
在一种示例性实施例中，第一发光晶体管ET1至第十三发光晶体管ET13可以为P型晶体管或者可以为N型晶体管。
在一种示例性实施例中，第一电源端VGH持续提供高电平信号，第二电源端VGL持续提供低电平信号。由于第二电源端VGL持续提供低电平信号，第十一发光晶体管ET11和第十二发光晶体管ET12持续导通。
在一种示例性实施例中，第二时钟信号端ECK2在开机初始化阶段为低电平信号，防止最后一发光移位寄存器的第九发光晶体管ET9和第十发光晶体管ET10因输出信号的延迟同时导通，或者在异常关机阶段为低电平信号，防止第九发光晶体管ET9和第十发光晶体管ET10同时导通。第二时钟信号端ECK2在正常显示阶段持续提供高电平信号，即在正常显示阶段，第十三发光晶体管ET13持续截止。
以第一发光晶体管ET1至第十三发光晶体管ET13为P型晶体管为例，如图10B所示，一种示例性实施例提供的发光移位寄存器的工作过程包括以下阶段：
在第一阶段B1，第一时钟信号端ECK1的信号为高电平信号，第三时钟信号端ECK3的信号为低电平信号。第三时钟信号端ECK3的信号为低电平信号，第一发光晶体管ET1、第三发光晶体管ET3和第十二发光晶体管ET12导通，导通的第一发光晶体管ET1将输入端EIN的高电平信号传输至第一节点E1，从而使得第一节点E1的电平变为高电平信号，导通的第十二发光晶 体管ET12将第一节点E1的高电平信号传输至第三节点E2，第二发光晶体管ET2、第四发光晶体管ET4、第八发光晶体管ET8以及第十发光晶体管ET10被截止。另外，导通的第三发光晶体管ET3将第三电源端VGL的低电平信号传输至第二节点E2，从而使得第二节点E2的电平变为低电平，导通的第十一发光晶体管ET11将第二节点E2的低电平信号传输至第四节点E4，从而使得第四节点E4的电平变为低电平，第五发光晶体管ET5和第六发光晶体管ET6被导通。第一时钟信号端ECK1的信号为高电平信号，第七发光晶体管ET7截止。另外，在第三发光电容EC3的作用下，第九发光晶体管ET9被截止。在第一阶段P1中，由于第九发光晶体管ET9以及第十发光晶体管ET10均被截止，输出端EOUT的信号保持之前的低电平。
在第二阶段B2，第一时钟信号端ECK1的信号为低电平信号，第三时钟信号端ECK3的信号为高电平信号。第一时钟信号端ECK1的信号为低电平信号，第七发光晶体管ET7导通。第三时钟信号端ECK3的信号为高电平信号，第一发光晶体管ET1和第三发光晶体管ET3被截止。在第三发光电容EC3的作用下，第一节点E1和第三节点E3可以继续保持上一阶段的高电平信号，在第一发光电容EC1作用下，所以第四节点E4可以继续保持上一阶段的低电平，所以第五发光晶体管ET5以及第六发光晶体管ET6被导通。第二发光晶体管ET2、第四发光晶体管ET4、第八发光晶体管ET8以及第十发光晶体管ET10被截止。另外，第一时钟信号端ECK1的低电平信号通过导通的第六发光晶体管ET6以及第七发光晶体管ET7被传输至第七节点E7，第九发光晶体管ET9被导通，导通的第九发光晶体管ET9将第一电源端VGH的高电平信号输出，所以输出端EOUT的信号为高电平信号。另外，
在第三阶段B3，第三时钟信号端ECK3的信号为低电平信号，第一时钟信号端ECK1的信号为高电平信号。第一时钟信号端ECK1的信号为高电平信号，第七发光晶体管ET7被截止。第二发光晶体管ET2、第四发光晶体管ET4、第八发光晶体管ET8以及第十发光晶体管ET10被截止。第三时钟信号端ECK3的信号为低电平信号，第一发光晶体管ET1以及第三发光晶体管ET3被导通。在第二发光电容EC3的作用下，第九发光晶体管ET9保持导通状态，导通的第九发光晶体管ET9将第一电源端VGH的高电平信号输出， 所以输出端EOUT的信号仍然为高电平信号。
在第四阶段B4，第一时钟信号端ECK1的信号为低电平信号，第三时钟信号端ECK3的信号为高电平信号。第三时钟信号端ECK3的信号为高电平信号，第一发光晶体管ET1以及第三发光晶体管ET3被截止。第一时钟信号端ECK1的信号为低电平，第七发光晶体管ET7被导通。由于第三发光电容EC3的存储作用，所以第一节点E1和第三节点E3的电平保持上一阶段的高电平信号，从而使得第二发光晶体管ET2、第四发光晶体管ET4、第八发光晶体管ET8以及第十发光晶体管ET10被截止。由于第一发光电容EC1的存储作用，第四节点E4继续保持上一阶段的低电平，从而使得第五发光晶体管ET5以及第六发光晶体管ET6被导通。另外，第一时钟信号端ECK1的低电平信号通过导通的第六发光晶体管ET6以及第七发光晶体管ET7被传输至第七节点E7，导通的第九发光晶体管ET9将第一电源端VGH的高电平信号输出，所以输出端EOUT的信号仍然为高电平信号。
在第五阶段B5，第一时钟信号端ECK1的信号为高电平信号，第三时钟信号端ECK3的信号为低电平信号。第三时钟信号端ECK3的信号为低电平信号，第一发光晶体管ET1以及第三发光晶体管ET3被导通。第一时钟信号端ECK1的信号为高电平信号，第七发光晶体管ET7被截止。导通的第一发光晶体管ET1将输入端EIN的低电平信号传输至第一节点E1，从而使得第一节点E1的电平变为低电平，导通的第十二发光晶体管ET12将第一节点E1的低电平信号传输至第三节点E3，从而使得第三节点E3的电平变为低电平，第二发光晶体管ET2、第四发光晶体管ET4、第八发光晶体管ET8以及第十发光晶体管ET10被导通。导通的第二发光晶体管ET2将低电平的第三时钟信号端ECK3的信号传输至第二节点E2，从而可以进一步拉低第二节点E2的电平，所以第二节点E2和第四节点E4继续保持上一阶段的低电平，从而使得第五发光晶体管ET5以及第六发光晶体管ET6被导通。第一时钟信号端ECK1的信号为高电平信号，第七发光晶体管ET7被截止。另外，导通的第八发光晶体管ET8将第一电源端VGH的高电平信号传输至第七节点E7，第九发光晶体管ET9被截止。导通的第十发光晶体管ET10将第二电源端VGL的低电平信号输出，所以输出端EOUT的信号变为低电平。
在一种示例性实施例中，显示基板还可以包括：沿第二方向延伸的发光初始信号线、第一发光时钟信号线至第三发光时钟信号线、第一高电平电源线和第一低电平电源线。
第一级发光移位寄存器的输入端与发光初始信号线电连接，第i级发光移位寄存器的输出端与第i+1级发光移位寄存器的输入端电连接；第i级发光移位寄存器的第一时钟信号端与第一发光时钟信号线电连接，第二时钟信号端与第二发光时钟信号线电连接，第三时钟信号端与第三发光时钟信号线电连接，第i+1级发光移位寄存器的第一时钟信号端与第三发光时钟信号线电连接，第二时钟信号端与第二发光时钟信号线电连接，第三时钟信号端与第一发光时钟信号线电连接，第i级发光移位寄存器的第一电源端与第一发光电源线电连接，第i级发光移位寄存器的第二电源端与第二发光电源线电连接。
图11A为一种示例性实施例提供的扫描移位寄存器的等效电路图，图11B为图11A提供的扫描移位寄存器的时序图。如图11A和图11B所示，如图11B所示，扫描移位寄存器包括：第一扫描晶体管GT1至第八扫描晶体管GT8、第一扫描电容GC1和第二扫描电容GC2。
在一种示例性实施例中，第一扫描晶体管GT1的扫描极与第一时钟信号端CK电连接，第一扫描晶体管GT1的第一极与输入端GIN电连接，第一扫描晶体管GT1的第二极与第一节点G1电连接；第二扫描晶体管GT2的扫描极与第一节点G1电连接，第二扫描晶体管GT2的第一极与第一时钟信号端CK电连接，第二扫描晶体管GT2的第二极与第二节点G2电连接；第三扫描晶体管GT3的扫描极与第一时钟信号端GGCK11电连接，第三扫描晶体管GT3的第一极与第二电源端VGL电连接，第三扫描晶体管GT3的第二极与第二节点G2电连接；第四扫描晶体管GT4的扫描极与第二节点G2电连接，第四扫描晶体管GT4的第一极与第一电源端VGH电连接，第四扫描晶体管GT4的第二极与输出端GOUT电连接；第五扫描晶体管GT5的扫描极与第三节点G3电连接，第五扫描晶体管GT5的第一极与第二时钟信号端GCK2电连接，第五扫描晶体管GT5的第二极与输出端GOUT电连接；第六扫描晶体管GT6的扫描极与第二节点G2电连接，第六扫描晶体管GT6的第 一极与第一电源端VGH电连接，第六扫描晶体管GT6的第二极与第七扫描晶体管GT7的第一极电连接；第七扫描晶体管GT7的扫描极与第二时钟信号端GCK2电连接，第七扫描晶体管GT7的第二极与第一节点G1电连接；第八扫描晶体管GT8的扫描极与第二电源端VGL电连接，第八扫描晶体管GT8的第一极与第一节点G1电连接，第八扫描晶体管GT8的第二极与第三节点G3电连接；第一扫描电容GC1的一端与第一电源端VGH电连接，第一扫描电容GC1的另一端与第二节点G2电连接；第二扫描电容GC2的第一极板GC21与输出端GOUT电连接，第二扫描电容GC2的第二极板GC22与第三节点G3电连接。
在一种示例性实施例中，第一扫描晶体管GT1至第八扫描晶体管GT8可以为P型晶体管或者可以为N型晶体管。
在一种示例性实施例中，第一电源端VGH持续提供高电平信号，第二电源端VGL持续提供低电平信号。
以第一扫描晶体管GT1至第八扫描晶体管GT8为P型晶体管为例，如图11B所示，一种示例性实施例提供的扫描移位寄存器的工作过程包括以下阶段：
在输入阶段C1，第一时钟信号端GCK1和输入端GIN的信号为低电平信号，第二时钟信号端GCK2的信号为高电平信号。由于第一时钟信号端GCK1的信号为低电平信号，第一扫描晶体管GT1导通，输入端GIN的信号经由第一扫描晶体管GT1传输至第一节点G1。由于第八扫描晶体管GT8的信号接收第二电源端VGL的低电平信号，从而第八扫描晶体管GT8处于开启状态。第三节点G3的电平可以扫描第五扫描晶体管GT5导通，第二时钟信号端GCK2的信号经由第五扫描晶体管GT5传输至输出端GOUT，即在输入阶段C1，输出端GOUT为高电平信号的第二时钟信号端GCK2的信号。另外，由于第一时钟信号端GCK1的信号为低电平信号，第三扫描晶体管GT3导通，第二电源端VGL的低电平信号经由第三扫描晶体管GT3传输至第二节点G2。此时，第四扫描晶体管GT4和第六扫描晶体管GT6均导通。由于第二时钟信号端GCK2的信号为高电平信号，第七扫描晶体管GT7截止。
在输出阶段C2，第一时钟信号端GCK1的信号为高电平信号，第二时 钟信号端GCK2的信号为低电平信号，输入端GIN的信号为高电平信号。第五扫描晶体管GT5导通，第二时钟信号端GCK2的信号经由第五扫描晶体管GT5作为输出端GOUT的信号。在输出阶段C2，第二扫描电容GC2的连接输出端OUT的一端的电平变为第二电源端VGL的信号，由于第二扫描电容GC2的自举作用，第八扫描晶体管GT8截止，第五扫描晶体管GT5可以更好地打开，输出端GOUT的信号为低电平信号。另外，第一时钟信号端GCK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止。第二扫描晶体管GT2导通，第一时钟信号端GCK1的高电平信号经由第二扫描晶体管GT2传输至第二节点G2，由此，第四扫描晶体管GT4和第六扫描晶体管GT6均截止。由于第二时钟信号端GCK2的信号为低电平信号，第七扫描晶体管GT7导通。
在缓冲阶段C3，第一时钟信号端GCK1和第二时钟信号端GCK2的信号均为高电平信号，输入端GIN的信号为高电平信号，第五扫描晶体管GT5导通，第二时钟信号端GCK2经由第五扫描晶体管GT5作为输出信号GOUT。由于第二扫描电容C2的自举作用，第一节点G1的电平变为VGL-VthN1。另外，第一时钟信号端GCK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止，第八扫描晶体管GT8导通，第二扫描晶体管GT2导通，第一时钟信号端GCK1的高电平信号经由第二扫描晶体管GT2传输至第二节点G2，由此，第四扫描晶体管GT4和第六扫描晶体管GT6均截止。由于第二时钟信号端GCK2的信号为高电平信号，第七扫描晶体管GT7截止。
在稳定阶段C4的第一子阶段C41中，第一时钟信号端GCK1的信号为低电平信号，第二时钟信号端GCK2和输入端GIN的信号为高电平信号。由于第一时钟信号端GCK1的信号为低电平信号，第一扫描晶体管GT1导通，输入端GIN的信号经由第一扫描晶体管GT1传输至第一节点G1，第二扫描晶体管GT2截止。由于第八扫描晶体管GT8处于开启状态，第五扫描晶体管GT5截止。由于第一时钟信号端GCK1的信号为低电平，第三扫描晶体管GT3导通，第四扫描晶体管GT4和第六扫描晶体管GT6均导通，第一电源端VGH的高电平信号经由第四扫描晶体管GT4传输至输出端GOUT，即输 出端GOUT的信号为高电平信号。
在稳定阶段C4的第二子阶段C42中，第一时钟信号端GCK1的信号为高电平信号，第二时钟信号端GCK2的信号为低电平信号，输入端GIN的信号为高电平信号。第五扫描晶体管GT5和第二扫描晶体管GT2均截止。第一时钟信号端GCK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止，由于第一扫描电容GC1的保持作用下，第四扫描晶体管GT4和第六扫描晶体管GT6均导通，高电平信号经由第四扫描晶体管GT4传输至输出端GOUT，即输出端GOUT的信号为高电平信号。
在第二子阶段C42中，由于第二时钟信号端GCK2的信号为低电平信号，第七扫描晶体管GT7导通，从而高电平信号经由第六扫描晶体管GT6和第七扫描晶体管GT7被传输至第三节点G3和第一节点G1，以使第三节点G3和第一节点G1的信号保持为高电平信号。
在第三子阶段C43中，第一时钟信号端GCK1和第二时钟信号GCK2的信号均为高电平信号，输入端GIN的信号为高电平信号。第五扫描晶体管GT5和第二扫描晶体管GT2截止。第一时钟信号端GCK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止，第四扫描晶体管GT4和第六扫描晶体管GT6均导通。高电平信号经由第四扫描晶体管GT4传输至输出端GOUT，即输出端GOUT的信号为高电平信号。
在一种示例性实施例中，第一级扫描移位寄存器的输入端与扫描初始信号线电连接，第i级扫描移位寄存器的输出端与第i+1级扫描移位寄存器的输入端电连接；第i级扫描移位寄存器的第一时钟信号端与第一扫描时钟信号线电连接，第二时钟信号端与第二扫描时钟信号线电连接，第i+1级扫描移位寄存器的第一时钟信号端与第二扫描时钟信号线电连接，第二时钟信号端与第一扫描时钟信号线电连接，第i级扫描移位寄存器的第一电源端与第一扫描电源线电连接，第i级扫描移位寄存器的第二电源端与第二扫描电源线电源线电连接。
图12A为一种示例性实施例提供的控制移位寄存器的等效电路图，图12B为图12A提供的控制移位寄存器的时序图。如图12A和图12B所示，如图12B所示，控制移位寄存器包括：第一控制晶体管ST1至第八控制晶体 管ST8、第一控制电容SC1和第二控制电容SC2。
在一种示例性实施例中，第一控制晶体管ST1的控制极与第一时钟信号端CK电连接，第一控制晶体管ST1的第一极与输入端SIN电连接，第一控制晶体管ST1的第二极与第一节点S1电连接；第二控制晶体管ST2的控制极与第一节点S1电连接，第二控制晶体管ST2的第一极与第一时钟信号端CK电连接，第二控制晶体管ST2的第二极与第二节点S2电连接；第三控制晶体管ST3的控制极与第一时钟信号端SSCK11电连接，第三控制晶体管ST3的第一极与第二电源端VGL电连接，第三控制晶体管ST3的第二极与第二节点S2电连接；第四控制晶体管ST4的控制极与第二节点S2电连接，第四控制晶体管ST4的第一极与第一电源端VGH电连接，第四控制晶体管ST4的第二极与输出端SOUT电连接；第五控制晶体管ST5的控制极与第三节点S3电连接，第五控制晶体管ST5的第一极与第二时钟信号端SCK2电连接，第五控制晶体管ST5的第二极与输出端SOUT电连接；第六控制晶体管ST6的控制极与第二节点S2电连接，第六控制晶体管ST6的第一极与第一电源端VGH电连接，第六控制晶体管ST6的第二极与第七控制晶体管ST7的第一极电连接；第七控制晶体管ST7的控制极与第二时钟信号端SCK2电连接，第七控制晶体管ST7的第二极与第一节点S1电连接；第八控制晶体管ST8的控制极与第二电源端VGL电连接，第八控制晶体管ST8的第一极与第一节点S1电连接，第八控制晶体管ST8的第二极与第三节点S3电连接；第一控制电容SC1的第一极板SC11与第一电源端VGH电连接，第一控制电容SC1的第二极板SC13与第二节点S2电连接；第二控制电容SC2的第一极板SC21与输出端SOUT电连接，第二控制电容SC2的第二极板SC22与第三节点S3电连接。
在一种示例性实施例中，第一控制晶体管ST1至第八控制晶体管ST8可以为P型晶体管或者可以为N型晶体管。
在一种示例性实施例中，第一电源端VGH持续提供高电平信号，第二电源端VGL持续提供低电平信号。
以第一控制晶体管ST1至第八控制晶体管ST8为P型晶体管为例，如图12B所示，一种示例性实施例提供的控制移位寄存器的工作过程包括以下阶 段：
在输入阶段D1，第一时钟信号端SCK1和输入端SIN的信号为低电平信号，第二时钟信号端SCK2的信号为高电平信号。由于第一时钟信号端SCK1的信号为低电平信号，第一控制晶体管ST1导通，输入端SIN的信号经由第一控制晶体管ST1传输至第一节点S1。由于第八控制晶体管ST8的信号接收第二电源端VGL的低电平信号，从而第八控制晶体管ST8处于开启状态。第三节点S3的电平可以控制第五控制晶体管ST5导通，第二时钟信号端SCK2的信号经由第五控制晶体管ST5传输至输出端SOUT，即在输入阶段D1，输出端SOUT为高电平信号的第二时钟信号端SCK2的信号。另外，由于第一时钟信号端SCK1的信号为低电平信号，第三控制晶体管ST3导通，第二电源端VGL的低电平信号经由第三控制晶体管ST3传输至第二节点S2。此时，第四控制晶体管ST4和第六控制晶体管ST6均导通。由于第二时钟信号端SCK2的信号为高电平信号，第七控制晶体管ST7截止。
在输出阶段D2，第一时钟信号端SCK1的信号为高电平信号，第二时钟信号端SCK2的信号为低电平信号，输入端SIN的信号为高电平信号。第五控制晶体管ST5导通，第二时钟信号端SCK2的信号经由第五控制晶体管ST5作为输出端SOUT的信号。在输出阶段D2，第二控制电容SC2的连接输出端OUT的一端的电平变为第二电源端VGL的信号，由于第二控制电容SC2的自举作用，第八控制晶体管ST8截止，第五控制晶体管ST5可以更好地打开，输出端SOUT的信号为低电平信号。另外，第一时钟信号端SCK1的信号为高电平信号，从而第一控制晶体管ST1和第三控制晶体管ST3均截止。第二控制晶体管ST2导通，第一时钟信号端SCK1的高电平信号经由第二控制晶体管ST2传输至第二节点S2，由此，第四控制晶体管ST4和第六控制晶体管ST6均截止。由于第二时钟信号端SCK2的信号为低电平信号，第七控制晶体管ST7导通。
在缓冲阶段D3，第一时钟信号端SCK1和第二时钟信号端SCK2的信号均为高电平信号，输入端SIN的信号为高电平信号，第五控制晶体管ST5导通，第二时钟信号端SCK2经由第五控制晶体管ST5作为输出信号SOUT。由于第二控制电容C2的自举作用，第一节点S1的电平变为VGL-VthN1。 另外，第一时钟信号端SCK1的信号为高电平信号，从而第一控制晶体管ST1和第三控制晶体管ST3均截止，第八控制晶体管ST8导通，第二控制晶体管ST2导通，第一时钟信号端SCK1的高电平信号经由第二控制晶体管ST2传输至第二节点S2，由此，第四控制晶体管ST4和第六控制晶体管ST6均截止。由于第二时钟信号端SCK2的信号为高电平信号，第七控制晶体管ST7截止。
在稳定阶段D4的第一子阶段D41中，第一时钟信号端SCK1的信号为低电平信号，第二时钟信号端SCK2和输入端SIN的信号为高电平信号。由于第一时钟信号端SCK1的信号为低电平信号，第一控制晶体管ST1导通，输入端SIN的信号经由第一控制晶体管ST1传输至第一节点S1，第二控制晶体管ST2截止。由于第八控制晶体管ST8处于开启状态，第五控制晶体管ST5截止。由于第一时钟信号端SCK1的信号为低电平，第三控制晶体管ST3导通，第四控制晶体管ST4和第六控制晶体管ST6均导通，第一电源端VGH的高电平信号经由第四控制晶体管ST4传输至输出端SOUT，即输出端SOUT的信号为高电平信号。
在稳定阶段t4的第二子阶段t42中，第一时钟信号端SCK1的信号为高电平信号，第二时钟信号端SCK2的信号为低电平信号，输入端SIN的信号为高电平信号。第五控制晶体管ST5和第二控制晶体管ST2均截止。第一时钟信号端SCK1的信号为高电平信号，从而第一控制晶体管ST1和第三控制晶体管ST3均截止，由于第一控制电容SC1的保持作用下，第四控制晶体管ST4和第六控制晶体管ST6均导通，高电平信号经由第四控制晶体管ST4传输至输出端SOUT，即输出端SOUT的信号为高电平信号。
在第二子阶段t42中，由于第二时钟信号端SCK2的信号为低电平信号，第七控制晶体管ST7导通，从而高电平信号经由第六控制晶体管ST6和第七控制晶体管ST7被传输至第三节点S3和第一节点S1，以使第三节点S3和第一节点S1的信号保持为高电平信号。
在第三子阶段t43中，第一时钟信号端SCK1和第二时钟信号SCK2的信号均为高电平信号，输入端SIN的信号为高电平信号。第五控制晶体管ST5和第二控制晶体管ST2截止。第一时钟信号端SCK1的信号为高电平信号， 从而第一控制晶体管ST1和第三控制晶体管ST3均截止，第四控制晶体管ST4和第六控制晶体管ST6均导通。高电平信号经由第四控制晶体管ST4传输至输出端SOUT，即输出端SOUT的信号为高电平信号。
在一种示例性实施例中，第一级控制移位寄存器的输入端与控制初始信号线电连接，第i级控制移位寄存器的输出端与第i+1级控制移位寄存器的输入端电连接；第i级控制移位寄存器的第一时钟信号端与第一控制时钟信号线电连接，第二时钟信号端与第二控制时钟信号线电连接，第i+1级控制移位寄存器的第一时钟信号端与第二控制时钟信号线电连接，第二时钟信号端与第一控制时钟信号线电连接，第i级控制移位寄存器的第一电源端与第一控制电源线电连接，第i级控制移位寄存器的第二电源端与第二控制电源线电源线电连接。
在一种示例性实施例中，图13为一种示例性实施例提供的扫描移位寄存器的结构示意图，如图13所示，当第K+1行至第N行像素电路的复位信号线与扫描驱动电路电连接时，电路结构层包括：依次叠设在基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层和平坦层；
半导体层包括：多个扫描晶体管的有源层；
第一导电层包括：多个扫描晶体管的控制极以及多个扫描电容的第一极板；
第二导电层包括：多个扫描电容的第二极板；
第三导电层包括：多个扫描晶体管的第一极和第二极、第一级至第N-K级扫描移位寄存器的第一信号输出线OL1以及第N-K+1级至第N级扫描移位寄存器的第四信号输出线；
第四导电层包括：扫描初始信号线GSTV、第一扫描时钟信号线GCLK1、第二扫描时钟信号线GCLK2、第一扫描电源线GVGH、第二扫描电源线GVGL、第一级至第N-K级扫描移位寄存器的第二信号输出线OL2以及第一级至第K级缓冲移位寄存器的第三输出信号线。
在一种示例性实施例中，图14为一种示例性实施例提供的控制移位寄存 器的结构示意图，如图14所示，当第K+1行至第N行像素电路的复位信号线与控制驱动电路电连接时，电路结构层包括：依次叠设在基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层和平坦层；
半导体层包括：多个控制晶体管的有源层；
第一导电层包括：多个控制晶体管的控制极以及多个控制电容的第一极板；
第二导电层包括：多个控制电容的第二极板；
第三导电层包括：多个控制晶体管的第一极和第二极、第一级至第(N-K)/2级控制移位寄存器的第一信号输出线OL1以及第(N-K)/2+1级至第N级控制移位寄存器的第四信号输出线；
第四导电层包括：控制初始信号线SSTV、第一控制时钟信号线SCLK1、第二控制时钟信号线SCLK2、第一控制电源线SVGH、第二控制电源线SVGL、第一级至第(N-K)/2级控制移位寄存器的第二信号输出线OL2以及第一级至第K/2级缓冲移位寄存器的第三输出信号线。
下面以第K+1行至第N行像素电路的复位信号线与扫描驱动电路电连接为例通过显示基板中的包括第一信号输出线和第二信号输出线的扫描移位寄存器的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公 开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。图15至图21是以显示基板包括图11A提供的两级扫描移位寄存器为例进行说明的。
(1)在基底上形成半导体层图案，包括：在基底上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案。如图15所示，图15为形成半导体层图案后的示意图。
在一种示例性实施例中，如图15所示，半导体层图案可以包括：移位寄存器的第一扫描晶体管的有源层T11至第八扫描晶体管的有源层T81。
在一种示例性实施例中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
在一种示例性实施例中，半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、 多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
在一种示例性实施例中，如图15所示，第四扫描晶体管的有源层T41和第五扫描晶体管的有源层T51可以为一体成型结构，第六扫描晶体管的有源层T61与第七扫描晶体管的有源层T71可以为一体成型结构。
在一种示例性实施例中，如图15所示，第一扫描晶体管的有源层T11可以为倒“n”型，第二扫描晶体管的有源层T21沿第二方向延伸，且为可以条状结构，第三扫描晶体管的有源层T31沿第二方向延伸，且为可以条状结构，第四扫描晶体管的有源层T41和第五扫描晶体管的有源层T51的一体成型结构沿第二方向延伸，且为可以条状结构，第六晶体管的有源层T61与第七扫描晶体管的有源层T71的一体成型结构沿第二方向延伸，且为可以条状结构，第八扫描晶体管的有源层T81沿第二方向延伸，且为可以条状结构。
(2)形成第一导电层图案，包括：在形成有前述图案的基底上沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一绝缘薄膜和第一导电薄膜进行图案化，形成第一绝缘层图案以及设置在第一绝缘层图案上的第一导电层图案，如图16A和图16B所示，图16A为第一导电层图案的示意图，图16B为形成第一导电层图案后的示意图。
在一种示例性实施例中，如图16A和图16B所示，第一导电层图案可以包括：第一扫描晶体管的控制极T12至第八扫描晶体管T82、第一扫描电容的第一极板C11和第二扫描电容的第一极板C21。
在一种示例性实施例中，第一导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在一种示例性实施例中，第一绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第一栅绝缘层。
在一种示例性实施例中，如图16A和图16B所示，第一扫描晶体管的控 制极T12和第三扫描晶体管的控制极T32为一体成型结构。第一扫描晶体管的控制极T12和第三扫描晶体管的控制极T32的一体成型结构沿第一方向延伸，且可以为条状。
在一种示例性实施例中，如图16A和图16B所示，第一扫描电容的第一极板C11、第四扫描晶体管的控制极T42和第六扫描晶体管的控制极T62为一体成型结构，且沿第一方向延伸。
在一种示例性实施例中，如图16A和图16B所示，第二扫描电容的第一极板C21和第五扫描晶体管的控制极T52为一体成型结构。且第二扫描电容的第一极板C21和第五扫描晶体管的控制极T52的一体成型结构为梳状结构，第二扫描电容的第一极板C21为梳背，第五扫描晶体管的控制极T52为梳齿。
在一种示例性实施例中，如图16A和图16B所示，第二扫描晶体管的控制极T22和第八扫描晶体管的控制极T82沿第一方向延伸，且可以为条状。
在一种示例性实施例中，如图16A和图16B所示，第一扫描晶体管的控制极T12跨设在第一扫描晶体管的有源层上，第二扫描晶体管的控制极T22跨设在第二扫描晶体管的有源层上，第三扫描晶体管的控制极T32跨设在第三扫描晶体管的有源层上，第四扫描晶体管的控制极T42跨设在第四扫描晶体管的有源层上，第五扫描晶体管的控制极T52跨设在第五扫描晶体管的有源层上，第六扫描晶体管的控制极T62跨设在第六扫描晶体管的有源层上，第七扫描晶体管的控制极T72跨设在第七扫描晶体管的有源层上，第八扫描晶体管的控制极T82跨设在第八扫描晶体管的有源层上，也就是说，至少一个扫描晶体管的控制极的延伸方向与有源层的延伸方向相互垂直。
在一种示例性实施例中，本次工艺还包括导体化处理。导体化处理是在形成第一导电层后，利用多个扫描晶体管的控制极遮挡区域的半导体层(即半导体层与控制极交叠的区域)作为扫描晶体管的沟道区域，未被第一导电层遮挡区域的半导体层被处理成导体化层，形成扫描晶体管的电极连接部。如图16B所示，本公开中的第六扫描晶体管的有源层和第七扫描晶体管的有源层的相互连接的电极连接部被处理成导体化层，形成可以复用为第六扫描晶体管的第二极和第七扫描晶体管的第一极的导体化结构。
(3)形成第二导电层图案，包括：在形成有前述图案的基底上，沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二绝缘薄膜和第二导电薄膜进行图案化，形成第二绝缘层图案和位于第二绝缘层图案上的第二导电层图案，如图17A和图17B所示，图17A为第二导电层图案的示意图，图17B形成第二导电层图案后的示意图。
在一种示例性实施例中，如17A和图17B所示，第二导电层图案可以包括：第一扫描电容的第二极板C12、第二扫描电容的第二极板C22和第一连接线VL1。
在一种示例性实施例中，第二导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在一种示例性实施例中，第二绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第二栅绝缘层。
在一种示例性实施例中，如图17A和图17B所示，第一扫描电容的第二极板C12在基底上的正投影与第一扫描电容的第一极板C11在基底上的正投影至少部分交叠。
在一种示例性实施例中，如图17A和图17B所示，第二扫描电容的第二极板C22在基底上的正投影与第二扫描电容的第一极板C21在基底上的正投影至少部分交叠。
在一种示例性实施例中，如图17A和图17B所示，第一连接线在基底上的正投影位于第二扫描晶体管的控制极在基底上的正投影和第八扫描晶体管的控制极在基底上的正投影之间。
(4)形成第三绝缘层图案，包括：在形成前述图案的基底上沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜和第三绝缘层进行图案化，形成第三绝缘层图案以。如图18所示，图18为形成第三绝缘层图案后的示意图。
在一种示例性实施例中，如图18所示，多个过孔图案可以包括：开设在 第一绝缘层至第三绝缘层上的第一过孔V1至第八过孔V8，开设在第二绝缘层和第三绝缘层上的第九过孔V9至第十四过孔V14,以及开设在第三绝缘层上的第十五过孔V15至第十七过孔V17。其中，第一过孔V1暴露出第一扫描晶体管的有源层，第二过孔V2暴露出第二扫描晶体管的有源层，第三过孔V3暴露出第三扫描晶体管的有源层，第四过孔V4暴露出第四扫描晶体管的有源层T41，第五过孔V5暴露出第五扫描晶体管的有源层T51，第六过孔V6暴露出第六扫描晶体管的有源层T61，第七过孔V7暴露出第七扫描晶体管的有源层T71，第八过孔V8暴露出第八扫描晶体管的有源层T81，第九过孔V9暴露出第一扫描晶体管的控制极和第三扫描晶体管的控制极的一体成型结构，第十过孔V10暴露出第二扫描晶体管的控制极，第十一过孔V11暴露出第五扫描晶体管的控制极，第十二过孔V12暴露出第四扫描晶体管的控制极和第六扫描晶体管的控制极的一体成型结构，第十三过孔V13暴露出第七扫描晶体管的控制极，第十四过孔V14暴露出第八扫描晶体管的控制极，第十五过孔V15暴露出第一连接线，第十六过孔V16暴露出第一扫描电容的第二极板，第十七过孔V17暴露出第二扫描电容的第二极板。
在一种示例性实施例中，第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第二栅绝缘层。
在一种示例性实施例中，如图18所示，第四过孔V4的数量为多个，且多个第四过孔V4阵列排布。
在一种示例性实施例中，如图18所示，第五过孔V5的数量为多个，且多个第五过孔V5阵列排布。
在一种示例性实施例中，如图18所示，第九过孔V9的数量为两个，且沿第二方向延伸的虚拟直线穿过两个第九过孔。
在一种示例性实施例中，如图18所示，第十三过孔V13的数量为两个，其中一个第十三过孔位于第七扫描晶体管的控制极的中部，另外一个第十三过开工位于第七扫描晶体管的控制极靠近第五晶体管的控制极的端部。
在一种示例性实施例中，如图18所示，第十五过孔V15的数量为两个，两个第十五过孔分别位于第一连接线的两端。
在一种示例性实施例中，如图18所示，第十六过孔V16的数量为多个，且多个第十六过孔V16可以沿第一方向排布。
在一种示例性实施例中，如图18所示，第十七过孔V17的数量为多个，且多个第十七过孔V17可以沿第二方向排布。
(5)形成第三导电层图案，包括：在形成前述图案的基底上，沉积第四金属薄膜，通过图案化工艺对第三金属薄膜进行构图，形成第四金属层图案，如图19A和图19B所示，图19A为第三导电层图案的示意图，图19B形成第三导电层图案后的示意图。
在一种示例性实施例中，如图19A和图19B所示，第三导电层图案可以包括：第一扫描晶体管的第一极T13和第二极T14至第五扫描晶体管的第一极T53和第二极T54、第六扫描晶体管的第一极T63、第七扫描晶体管的第二极T74、第八扫描晶体管的第一极T83和第二极T84、第一信号输出线OL1、第二连接线VL2、第三连接线VL3和第四连接线VL4。
在一种示例性实施例中，第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在一种示例性实施例中，如图19A和图19B所示，第一扫描晶体管的第二极T14、第七扫描晶体管的第二极T74和第八扫描晶体管的第一极T83为一体成型结构，第二扫描晶体管的第二极T24和第三扫描晶体管的第二极T34为一体成型结构，第四扫描晶体管的第一极T43和第六扫描晶体管T63的第一极T63为一体成型结构，第四扫描晶体管的第二极T44、第五扫描晶体管的第二极T54和第一信号输出线OL1为一体成型结构。
在一种示例性实施例中，如图19A和图19B所示，第一信号输出线OL1沿第一方向延伸，且在基底上的正投影与第二扫描电容在基底上的正投影部分重叠。
在一种示例性实施例中，如图19A和图19B所示，第二连接线在基底上的正投影与第一扫描晶体管的控制极和第三扫描晶体管的控制极的一体成型 结构在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第三连接线VL3在基底上的正投影与第一连接线和第一扫描电容的第一极板C11、第四扫描晶体管的控制极T42和第六扫描晶体管的控制极T62为一体成型结构在基底上的正投影部分交叠。
在一种示例性实施例中，如图19A和图19B所示，第一扫描晶体管的第一极T13和第二极T14通过第一过孔与第一扫描晶体管的有源层连接，第二扫描晶体管的第一极T23和第二扫描晶体管的第二极T24通过第二过孔与第二扫描晶体管的有源层连接，且第二扫描晶体管的第一极还通过一个第九过孔与第一扫描晶体管的控制极和第三扫描晶体管的控制极的一体成型结构电连接，第三扫描晶体管的第一极T33和第二极T34分别通过第三过孔与第三扫描晶体管的有源层连接，第四扫描晶体管的第一极T43和第二极T44通过第四过孔与暴露出第四扫描晶体管的有源层连接，第五扫描晶体管的第一极T53和第二极T55通过第五过孔与第五扫描晶体管的有源层连接，第六扫描晶体管的第一极T63通过第六过孔与第六扫描晶体管的有源层连接，第七扫描晶体管的第二极T74通过第七过孔与第七扫描晶体管的有源层连接，第八扫描晶体管的第一极T83和第二极T84通过第八过孔与第八扫描晶体管的有源层连接，且第八扫描晶体管的第二极T84通过第十一过孔与第五扫描晶体管的控制极电连接。第二扫描晶体管的第二极T24和第三扫描晶体管的第二极T34的一体成型结构通过第十五过孔与第一连接线电连接，第一晶体管的第二极T14、第七晶体管的第二极T74和第八晶体管的第一极T83的一体成型结构通过第十过孔与第二晶体管的控制极电连接，第四晶体管的第一极T43和第六晶体管T63的第一极T63的一体成型结构通过第十六过孔与第一电容的第二极板电连接，第四晶体管的第二极T44、第五晶体管的第二极T54和第一信号输出线OL1的一体成型结构通过第十七过孔与第二晶体管的第二极板电连接，第五晶体管的第一极T53通过第十三过孔与第七晶体管的控制极电连接，第二连接线VL2通过另一个第九过孔与第一晶体管的控制极和第三晶体管的控制极的一体成型结构电连接，第三连接线VL3通过另一个第十五过孔与第一连接线电连接，且通过第十二过孔与第四晶体管的控制极和 第六晶体管的控制极的一体成型结构电连接，第四连接线VL4通过第十四过孔与第八晶体管的控制极电连接。
在一种示例性实施例中，如图19A和图19B所示，第四晶体管的第二极T44、第五晶体管的第二极T54和第一信号输出线OL1的一体成型结构与下一级扫描移位寄存器的第一晶体管的第一极电连接。
(6)形成第四绝缘层图案，包括：在形成前述图案的基底上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成第四绝缘层图案以。如图20所示，图20为形成第四绝缘层图案后的示意图。
在一种示例性实施例中，如图20所示，多个过孔图案可以包括：开设在第四绝缘层上的第十八过孔V18至第二十三过孔V23。其中，第十八过孔V18暴露出第三晶体管的第一极，第十九过孔V19暴露出第四连接线，第二十过孔V20暴露出第二连接线，第二十一过孔V21暴露出第四晶体管的第一极和第六晶体管的第一极的一体成型结构，第二十二过孔V22暴露出第五晶体管的第一极，第二十三过孔V23暴露出第一信号输出线。
在一种示例性实施例中，第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第二栅绝缘层。
(7)形成第四导电层图案，包括：在形成前述图案的基底上，沉积第四金属薄膜，通过图案化工艺对第四金属薄膜进行构图，形成第四金属层图案，如图21A和图21B所示，图21A为第四导电层图案的示意图，图21B形成第四导电层图案后的示意图。
在一种示例性实施例中，如图21A和图21B所示，第四导电层图案可以包括：扫描初始信号线GSTV、第一扫描时钟信号线GCLK1、第二扫描时钟信号线GCLK2、第一扫描电源线GVGH、第二扫描电源线GVGL和第二信号输出线OL2。
在一种示例性实施例中，第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层 结构，或者多层复合结构，如Ti/Al/Ti等。
在一种示例性实施例中，如图21A和图21B所示，第二扫描电源线GVGL位于第一扫描时钟信号线GCLK1远离显示区域的一侧，第二扫描时钟信号线GCLK2位于第一扫描时钟信号线GCLK1靠近显示区域的一侧，扫描初始信号线GSTV位于第二扫描时钟信号线GCLK2靠近显示区域的一侧，第一扫描电源线GVGH位于扫描初始信号线GSTV靠近显示区域的一侧，第二信号输出线OL2位于第一扫描电源线GVGH靠近显示区域的一侧。
在一种示例性实施例中，如图21A和图21B所示，第三晶体管的第一极和第四连接线在基底上的正投影与第二扫描电源线GVGL在基底上的正投影部分交叠。
在一种示例性实施例中，如图21A和图21B所示，第二连接线在基底上的正投影与扫描移位寄存器的第一时钟信号端所连接的扫描时钟信号线在基底上的正投影部分交叠。
在一种示例性实施例中，如图21A和图21B所示，第五晶体管的第一极在基底上的正投影与扫描移位寄存器的第二时钟信号端所连接的扫描时钟信号线在基底上的正投影部分交叠。
在一种示例性实施例中，如图21A和图21B所示，同一扫描移位寄存器的第二信号输出线在基底上的正投影与第一信号输出线在基底上的正投影部分交叠。
在一种示例性实施例中，如图21A和图21B所示，第二扫描电源线通过第十八过孔与第三晶体管的第一极电连接，且通过第十九过孔与第四连接线连接。第二连接线通过第二十过孔与扫描移位寄存器的第一时钟信号端所连接的扫描时钟信号线电连接。第五晶体管的第一极通过第二十二过孔与扫描移位寄存器的第二时钟信号端所连接的扫描时钟信号线电连接。第一扫描电源线GVGH通过第二十一过孔与第四晶体管的第一极和第六晶体管的第一极的一体成型结构电连接。第二信号输出线OL2通过第二十三过孔与第一信号输出线电连接。图21A和图21B是以上边的扫描移位寄存器的第五晶体管的第一极与第一扫描时钟信号线GCLK1电连接，第二连接线与第二扫描时 钟信号线GCLK2电连接。下边边的扫描移位寄存器的第五晶体管的第一极与第二扫描时钟信号线GCLK2电连接，第二连接线与第一扫描时钟信号线GCLK1电连接为例进行说明的。
(8)形成发光结构层，包括：在形成前述图案的基底上，涂覆平坦薄膜，通过刻蚀对平坦薄膜进行图案化，形成平坦层，在形成有平坦层的基底上沉积透明导电薄膜，通过图案化工艺对透明导电薄膜进行图案化，形成阳极，在形成有阳极的基底上沉积像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层，在形成像素定义层的基底上沉积阴极薄膜，通过图案化工艺对阴极薄膜进行图案化，形成阴极。
在一种示例性实施例中，平坦层可以采用有机材料。
在一种示例性实施例中，阳极薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。
本公开实施例还提供一种显示装置，包括：显示基板。
在一种示例性实施例中，显示装置可以为显示器、电视、手机、平板电脑、导航仪、数码相框、可穿戴显示产品具有任何显示功能的产品或者部件。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利 要求书所界定的范围为准。

Claims (25)

  1. 一种显示基板，包括：基底以及设置在所述基底上的电路结构层，所述电路结构层包括：像素电路、扫描驱动电路、控制驱动电路和缓冲驱动电路；所述像素电路包括：节点复位晶体管、写入晶体管以及复位信号线、扫描信号线和控制信号线，所述复位信号线与所述节点复位晶体管的控制极连接，所述扫描信号线与写入晶体管的控制极连接；
    第一行至第K行像素电路的复位信号线与所述缓冲驱动电路电连接，第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路或者所述控制驱动电路电连接，其中，有效电平信号的开始时间与复位信号线的信号为有效电平信号的结束时间之差大于或等于阈值时间，N为像素电路的总行数。
  2. 根据权利要求1所述的显示基板，其中，所述像素电路还包括：驱动晶体管，所述阈值时间t约等于K*(1/f)/N，或者K*(1/f)/(N+N0)，或者Tstress，其中，f为显示基板的刷新频率，N为像素电路的总行数，N0为显示基板在N行像素电路工作之前和/或之后的所执行的空白行数之和，N0为大于或者等于0的正整数，Tstress为偏置的驱动晶体管的阈值电压的恢复时间。
  3. 根据权利要求1所述的显示基板，其中，第一行至第N行像素电路的扫描信号线与所述扫描驱动电路电连接，第一行至第N行像素电路的控制信号线与所述控制驱动电路电连接；
    当节点复位晶体管与写入晶体管的晶体管类型相同时，第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接；所述像素电路还包括：补偿晶体管和补偿复位晶体管；补偿复位晶体管的晶体管类型与驱动晶体管、节点复位晶体管、写入晶体管和补偿晶体管的晶体管类型相反；扫描信号线还与补偿晶体管的控制极电连接，控制信号线与补偿复位晶体管的控制极电连接；
    当节点复位晶体管与写入晶体管的晶体管类型相反时，第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接，所述像素电路还包括：补偿晶体管；节点复位晶体管和补偿晶体管的晶体管类型与驱动晶体管和写入晶体管的晶体管类型相反；控制信号线与补偿晶体管的控制极电连接。
  4. 根据权利要求1至3任一项所述的显示基板，包括：显示区域和非显示区域，其中，所述非显示区域包括：围设在所述显示区域外围的边框区域和位于所述边框区域远离显示区域一侧的绑定区域；
    所述扫描驱动电路、控制驱动电路和缓冲驱动电路位于所述显示区域和/或非显示区域；
    当所述扫描驱动电路、控制驱动电路和缓冲驱动电路位于所述非显示区域时，所述扫描驱动电路和所述控制驱动电路位于所述显示区域相对设置的第一侧和第二侧，所述缓冲驱动电路位于所述显示区域的第三侧或第四侧，所述第三侧位于显示区域远离所述绑定区域的一侧，所述第四侧位于显示区域靠近所述绑定区域的一侧。
  5. 根据权利要求4所述的显示基板，还包括：发光驱动电路，所述像素电路还包括：发光晶体管和发光信号线；所述发光信号线与发光晶体管的控制极电连接；所述发光驱动电路位于所述控制驱动电路远离显示区域的一侧；
    第一行至第N行像素电路的发光信号线与所述发光驱动电路电连接；
    对于同一行像素电路，像素电路的发光信号线的信号的有效电平信号的开始时间与复位信号线的信号为有效电平信号的结束时间之差大于阈值时间和扫描信号线的信号为有效电平信号的持续时间之和。
  6. 根据权利要求1至5任一项所述的显示基板，还包括：测试电路和多路复用电路；所述像素电路还包括：沿第二方向延伸的数据信号线，第一方向与第二方向相交，所述第一方向为复位信号线、扫描信号线和控制信号线的延伸方向；
    所述数据信号线，分别与写入晶体管的第一极、所述测试电路与所述多路复用电路电连接；
    所述测试电路位于所述显示区域的第一侧和第三侧，所述多路复用电路位于所述显示区域的第一侧和/或第二侧。
  7. 根据权利要求6所述的显示基板，其中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，所述缓冲驱动电路包括：K个级联的缓冲移位寄存器；所述扫描驱动电路包括：N个级联的扫描移位 寄存器；所述控制驱动电路包括：N/2个级联的控制移位寄存器，最后一级缓冲移位寄存器的输出端与第一级扫描移位寄存器的输入端电连接；
    第a级缓冲移位寄存器与第a行像素电路的复位信号线电连接，1≤a≤K；
    第b级扫描移位寄存器与第b行像素电路的扫描信号线电连接，1≤b≤N；
    第c级扫描移位寄存器与第K+c行像素电路的复位信号线电连接，1≤c≤N-K；
    第d级控制移位寄存器分别与第2d-1行像素电路和第2d行像素电路的控制信号线电连接，1≤d≤N/2。
  8. 根据权利要求7所述的显示基板，其中，所述第一级至第N-K扫描移位寄存器包括：相互连接的第一信号输出线和第二信号输出线，所述第二信号输出线位于所述第一信号输出线远离基底的一侧；
    第c级扫描移位寄存器的第一信号输出线与第c行像素电路的扫描信号线电连接，第c级扫描移位寄存器的第二信号输出线与第K+c行像素电路的复位信号线电连接；
    其中，所述第一信号输出线和所述第二信号输出线位于所述扫描驱动电路和所述显示区域之间，且所述第一信号输出线的延伸方向与所述第二信号输出线的延伸方向相交。
  9. 根据权利要求7或8所述的显示基板，其中，第一级至第K级缓冲移位寄存器包括：与所述第二信号输出线同层设置的第三信号输出线，第a级缓冲移位寄存器的第三信号输出线与第a行像素电路的复位信号线电连接；
    所述第N-K+1级至第N级扫描移位寄存器包括：与所述第一信号输出线同层设置的第四信号输出线；第s级扫描移位寄存器的第四信号输出线与第s行像素电路的扫描信号线电连接，N-K+1≤s≤N；
    所述第三信号输出线和所述第四信号输出线位于所述扫描驱动电路和所述显示区域之间。
  10. 根据权利要求6所述的显示基板，其中，当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，所述缓冲驱动电路包括：K/2个级联的缓冲移位寄存器；所述扫描驱动电路包括：N个级联的扫描移 位寄存器；所述控制驱动电路包括：N/2个级联的控制移位寄存器；最后一级缓冲移位寄存器的输出端与第一级控制移位寄存器的输入端电连接；
    第i级缓冲移位寄存器分别与第2i-1行像素电路和第2i行像素电路的复位信号线电连接，1≤i≤K/2；
    第b级扫描移位寄存器与第b行像素电路的扫描信号线电连接，1≤b≤N；
    第m级控制移位寄存器分别与第2m-1行像素电路和第2m行像素电路的控制信号线电连接，1≤m≤N/2；
    第n级控制移位寄存器分别与第K+2n-1行像素电路和第K+2n行像素电路的复位信号线电连接，1≤n≤(N-K)/2。
  11. 根据权利要求10所述的显示基板，其中，所述第一级至第(N-K)/2级控制移位寄存器包括：相互连接的第一信号输出线和第二信号输出线，所述第二信号输出线位于所述第一信号输出线远离基底的一侧；
    第n级控制移位寄存器的第一信号输出线分别与第2n-1行像素电路和第2n行像素电路的控制信号线电连接，第n级控制移位寄存器的第二信号输出线分别与第K+2n-1行像素电路和第K+2n行像素电路的复位信号线电连接；
    其中，所述第一信号输出线和所述第二信号输出线位于所述控制驱动电路和所述显示区域之间，且所述第一信号输出线的延伸方向与所述第二信号输出线的延伸方向相交。
  12. 根据权利要求10所述的显示基板，其中，第一级至第K/2级缓冲移位寄存器包括：与第二信号输出线同层设置的第三信号输出线，第i级缓冲移位寄存器的第三信号输出线分别与第2i-1行像素电路和第2i行像素电路的复位信号线电连接；
    第(N-K)/2+1级至第N级控制移位寄存器包括：与第一信号输出线同层设置的第四信号输出线；第t级控制移位寄存器的第四信号输出线分别与第2t-1行像素电路和第2t行像素电路的控制信号线电连接，(N-K)/2+1≤t≤N；
    所述第三信号输出线和所述第四信号输出线位于所述控制驱动电路和所述显示区域之间。
  13. 根据权利要求5所述的显示基板，其中，所述发光驱动电路包括： N/2级发光移位寄存器；
    第d级发光移位寄存器分别与第2d-1行像素电路和第2d行像素电路的发光信号线电连接，1≤d≤N/2。
  14. 根据权利要求7至13任一项所述的显示基板，其中，所述显示区域的边界的形状包括：圆角矩形，所述圆角矩形包括：四个圆角和四个边框，所述边框区域包括：位于第一圆角外侧的第一圆角区域、位于第二圆角外侧的第二圆角区域、位于第三圆角外侧的第三圆角区域，位于第四圆角外侧的第四圆角区域、位于第一边框外侧的第一边框区域、位于第二边框外侧的第二边框区域、位于第三边框外侧的第三边框区域，位于第四边框外侧的第四边框区域；
    所述第一边框区域、所述第一圆角区域和所述第二圆角区域位于所述显示区域的第一侧，所述第二边框区域、所述第三圆角区域和所述第四圆角区域位于所述显示区域的第二侧，所述第三边框区域位于所述显示区域的第三侧，所述第四边框区域位于所述显示区域的第二侧；
    第一行像素电路靠近第三边框区域，第N行像素电路靠近第四边框区域；
    扫描驱动电路位于所述第一边框区域、所述第一圆角区域和所述第二圆角区域，控制驱动电路和发光驱动电路位于所述所述第二边框区域、所述第三圆角区域和所述第四圆角区域；
    位于所述第一圆角区域的扫描移位寄存器沿第一圆角排布；
    位于所述第二圆角区域的扫描移位寄存器沿第二圆角排布；
    位于所述第三圆角区域的控制移位寄存器沿第三圆角排布；
    位于所述第四圆角区域的控制移位寄存器沿第四圆角排布。
  15. 根据权利要求14所述的显示基板，其中，所述缓冲驱动电路位于所述第三边框区域，且所述缓冲驱动电路中的级联的缓冲移位寄存器沿第一方向排布。
  16. 根据权利要求14或15所述的显示基板，其中，所述测试电路包括：多个测试子电路，部分测试子电路位于所述第三边框区域，且穿插设置在缓冲移位寄存器之间，另一部分测试子电路位于所述第一圆角区域，且穿插设 置在位于第一圆角区域的扫描移位寄存器之间；
    多路复用电路穿插设置在位于第一边框区域的所述扫描移位寄存器和/或位于所述第二边框区域的所述控制移位寄存器之间。
  17. 根据权利要求14至16任一项所述的显示基板，其中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，K大于或者等于14；
    当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，K大于或者等于7。
  18. 根据权利要求7至13任一项所述的显示基板，其中，所述显示区域的边界包括圆形；所述边框区域包括：第一区域至第四区域，所述第一区域和所述第二区域位于所述第三区域和所述第四区域之间，
    所述显示区域的沿第一方向延伸中线穿过所述第三区域和所述第四区域；
    所述第一区域和所述第二区域分别位于所述显示区域的沿第一方向延伸中线的两侧；
    所述第一区域位于所述显示基板的第一侧，所述第二区域位于所述显示区域的第二侧，所述第三区域位于所述显示区域的第三侧，所述第四区域位于所述显示区域的第四侧；
    第一行像素电路靠近第四区域，第N行像素电路靠近第三区域；
    扫描驱动电路位于所述第一区域，控制驱动电路和发光驱动电路位于所述所述第二区域，
    位于所述第一区域的扫描移位寄存器沿圆形边界排布；
    位于所述第二区域的控制移位寄存器沿圆形边界排布；
    位于所述第二区域的发光移位寄存器沿圆形边界排布。
  19. 根据权利要求18所述的显示基板，其中，所述缓冲驱动电路位于所述第四区域，且缓冲驱动电路中的级联的多个缓冲移位寄存器沿第一方向排布。
  20. 根据权利要求18或19所述的显示基板，其中，测试电路位于所述 第一区域和所述第三区域；
    多路复用电路位于所述第一区域和/或第二区域，且穿插设置在所述扫描移位寄存器和/或所述控制移位寄存器之间。
  21. 根据权利要求18至20任一项所述的显示基板，其中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，K大于或者等于10；
    当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，K大于或者等于5。
  22. 根据权利要求1至12任一项所述的显示基板，其中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，所述缓冲移位寄存器和所述扫描移位寄存器的电路结构相同均包括：多个扫描晶体管和多个扫描电容，扫描电容包括：第一极板和第二极板；
    所述显示基板还包括：扫描初始信号线、第一扫描时钟信号线和第二扫描时钟信号线、第一扫描电源线和第二扫描电源线；第一级缓冲移位寄存器与扫描初始信号线电连接，所述缓冲驱动电路和所述扫描驱动电路分别与第一扫描时钟信号线和第二扫描时钟信号线、第一扫描电源线和第二扫描电源线电连接；
    当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，所述缓冲移位寄存器和所述控制移位寄存器的电路结构相同均包括：多个控制晶体管和多个控制电容，控制电容包括：第一极板和第二极板；
    所述显示基板还包括：控制初始信号线、第一控制时钟信号线和第二控制时钟信号线、第一控制电源线和第二控制电源线；第一级缓冲移位寄存器与控制初始信号线电连接，所述缓冲驱动电路和所述控制驱动电路分别与第一控制时钟信号线和第二控制时钟信号线、第一控制电源线和第二控制电源线电连接。
  23. 根据权利要求22所述的显示基板，其中，当第K+1行至第N行像素电路的复位信号线与所述扫描驱动电路电连接时，所述电路结构层包括：依次叠设在所述基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、 第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层和平坦层；
    所述半导体层包括：多个扫描晶体管的有源层；
    所述第一导电层包括：多个扫描晶体管的控制极以及多个扫描电容的第一极板；
    所述第二导电层包括：多个扫描电容的第二极板；
    所述第三导电层包括：多个扫描晶体管的第一极和第二极、第一级至第N-K级扫描移位寄存器的第一信号输出线以及第N-K+1级至第N级扫描移位寄存器的第四信号输出线；
    所述第四导电层包括：扫描初始信号线、第一扫描时钟信号线、第二扫描时钟信号线、第一扫描电源线、第二扫描电源线、第一级至第N-K级扫描移位寄存器的第二信号输出线以及第一级至第K级缓冲移位寄存器的第三输出信号线。
  24. 根据权利要求22所述的显示基板，其中，当第K+1行至第N行像素电路的复位信号线与所述控制驱动电路电连接时，所述电路结构层包括：依次叠设在所述基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层和平坦层；
    所述半导体层包括：多个控制晶体管的有源层；
    所述第一导电层包括：多个控制晶体管的控制极以及多个控制电容的第一极板；
    所述第二导电层包括：多个控制电容的第二极板；
    所述第三导电层包括：多个控制晶体管的第一极和第二极、所述第一级至第(N-K)/2级控制移位寄存器的第一信号输出线以及所述第(N-K)/2+1级至第N级控制移位寄存器的第四信号输出线；
    所述第四导电层包括：控制初始信号线、第一控制时钟信号线、第二控制时钟信号线、第一控制电源线、第二控制电源线、第一级至第(N-K)/2级控制移位寄存器的第二信号输出线以及第一级至第K/2级缓冲移位寄存器的第三输出信号线。
  25. 一种显示装置，包括：如权利要求1至24任一项所述的显示基板。
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