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WO2024178714A1 - 像素驱动电路及其驱动方法、显示基板和显示装置 - Google Patents

像素驱动电路及其驱动方法、显示基板和显示装置 Download PDF

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Publication number
WO2024178714A1
WO2024178714A1 PCT/CN2023/079277 CN2023079277W WO2024178714A1 WO 2024178714 A1 WO2024178714 A1 WO 2024178714A1 CN 2023079277 W CN2023079277 W CN 2023079277W WO 2024178714 A1 WO2024178714 A1 WO 2024178714A1
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WO
WIPO (PCT)
Prior art keywords
signal line
transistor
sub
pixel
substrate
Prior art date
Application number
PCT/CN2023/079277
Other languages
English (en)
French (fr)
Inventor
卢红婷
陈义鹏
闫政龙
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2023/079277 priority Critical patent/WO2024178714A1/zh
Publication of WO2024178714A1 publication Critical patent/WO2024178714A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and specifically to a pixel driving circuit and a driving method thereof, a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a pixel driving circuit configured to drive a light-emitting device, the pixel driving circuit comprising: a node control subcircuit, a light-emitting control subcircuit and a driving subcircuit;
  • the node control subcircuit is electrically connected to the first node, the second node, the third node, the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line, the first initial signal line, the second initial signal line, the third initial signal line, the data signal line and the first power line, respectively, and is configured to drive the signal of the first node through the first initial signal line, the data signal line and the signal of the third node under the control of the signals of the first scan signal line, the second scan signal line, the third scan signal line and the fourth scan signal line, provide the signal of the second initial signal line to the second node, and provide the signal of the third initial signal line to the third node;
  • the light emitting control subcircuit is electrically connected to the first power line, the light emitting signal line and the third node respectively, and is configured to provide the signal of the first power line to the third node under the control of the signal of the light emitting signal line;
  • the driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to output a driving current to the second node under the control of the signals of the first node and the third node;
  • the light emitting device is electrically connected to the second node and the second power line respectively;
  • the node control subcircuit includes: an energy storage subcircuit, the energy storage subcircuit includes: a first capacitor and a second capacitor, the first capacitor and the second capacitor include: a first plate and a second plate;
  • the first plate of the first capacitor is electrically connected to the first power line, and the second plate of the first capacitor is electrically connected to the fourth node;
  • the first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the fourth node.
  • the node control subcircuit further includes: a reset subcircuit, a compensation subcircuit, and a write subcircuit;
  • the reset subcircuit is electrically connected to the first node, the second node, the third node, the first scan signal line, the second scan signal line, the third scan signal line, the first initial signal line, the second initial signal line and the third initial signal line, respectively, and is configured to provide the signal of the first initial signal line to the first node under the control of the signal of the first scan signal line, provide the signal of the second initial signal line to the second node under the control of the signal of the second scan signal line, and provide the signal of the second initial signal line to the second node under the control of the signal of the third scan signal line.
  • the compensation subcircuit is electrically connected to the third node, the fourth node and the first scan signal line respectively, and is configured to provide the signal of the third node to the fourth node under the control of the signal of the first scan signal line, so as to compensate the signal of the fourth node;
  • the writing sub-circuit is electrically connected to the fourth node, the fourth scanning signal line and the data signal line respectively, and is configured to provide the signal of the data signal line to the fourth node under the control of the signal of the fourth scanning signal line.
  • the reset subcircuit includes: a first transistor, a second transistor, and a third transistor;
  • a gate electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to the first node;
  • a gate electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the second initial signal line, and a second electrode of the second transistor is electrically connected to the second node;
  • a gate electrode of the third transistor is electrically connected to the third scan signal line, a first electrode of the third transistor is electrically connected to the third initial signal line, and a second electrode of the second transistor is electrically connected to the third node.
  • the compensation subcircuit includes: a fourth transistor, and the write transistor includes: a fifth transistor;
  • a gate electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the fourth node, and a second electrode of the fourth transistor is electrically connected to the third node;
  • a gate electrode of the fifth transistor is electrically connected to the fourth scan signal line, a first electrode of the fifth transistor is electrically connected to the data signal line, and a second electrode of the fifth transistor is electrically connected to the fourth node.
  • the node control subcircuit further includes: first to fifth transistors, the driving subcircuit includes: a sixth transistor, and the light emission control subcircuit includes: a seventh transistor;
  • a gate electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to the first node;
  • a gate electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the second initial signal line, and a second electrode of the second transistor is electrically connected to the second node;
  • a gate electrode of the third transistor is electrically connected to the third scan signal line, a first electrode of the third transistor is electrically connected to the third initial signal line, and a second electrode of the second transistor is electrically connected to the third node;
  • a gate electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the fourth node, and a second electrode of the fourth transistor is electrically connected to the third node;
  • a gate electrode of the fifth transistor is electrically connected to the fourth scan signal line, a first electrode of the fifth transistor is electrically connected to the data signal line, and a second electrode of the fifth transistor is electrically connected to the fourth node;
  • a gate electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the second node;
  • a gate electrode of the seventh transistor is electrically connected to the light emitting signal line, a first electrode of the seventh transistor is electrically connected to the first power supply line, and a second electrode of the seventh transistor is electrically connected to the third node.
  • the first transistor, the fourth transistor, and the fifth transistor are oxide transistors and are N-type transistors, and the second transistor, the third transistor, the sixth transistor, and the seventh transistor are P-type transistors;
  • the length of the channel region of the active layer of the sixth transistor is greater than the length of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor, and the width of the channel region of the active layer of the sixth transistor is greater than the width of the first to fifth transistors and the seventh transistor.
  • the width of the channel region of the active layer of any one of the transistors from the first transistor to the fifth transistor and the seventh transistor is smaller than the width-to-length ratio of the channel region of the active layer of any one of the transistors from the first transistor to the fifth transistor and the seventh transistor.
  • the signal of the first scanning signal line and the signal of the second scanning signal line are inverted signals to each other;
  • the signals of the first scanning signal line and the second scanning signal line are valid level signals, and the signals of the fourth scanning signal line and the light emitting signal line are invalid level signals;
  • the signals of the first scanning signal line, the second scanning signal line, the third scanning signal line and the light emitting signal line are invalid level signals;
  • the signals of the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line are invalid level signals;
  • a duration in which a signal of any one of the first scan signal line and the second scan signal line is a valid level signal is greater than a duration in which a signal of any one of the third scan signal line and the fourth scan signal line is a valid level signal.
  • the signal of the first initial signal line and the signal of the second initial signal line are the same signal, and a voltage value of the signal of the first initial signal line is smaller than a voltage value of the signal of the third initial signal line;
  • a voltage value of a signal on the second initial signal line is greater than a voltage value of a signal on the second power line.
  • the present disclosure further provides a display substrate, comprising: a substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel comprising: the above-mentioned pixel driving circuit and a light-emitting device driven by the pixel driving circuit.
  • it further comprises: a driving circuit layer and a light emitting structure layer sequentially stacked on the substrate, the driving circuit layer comprising: a plurality of pixel driving circuits, a plurality of light emitting signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of third initial signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of fourth scanning signal lines, a plurality of first power supply lines and a plurality of data signal lines, the light emitting structure layer comprising: a light emitting device;
  • any one of the light-emitting signal line, the first initial signal line, the second initial signal line, the third initial signal line, the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line extends at least partially along the first direction, and any one of the first power line and the data signal line extends at least partially along the second direction, and the first direction and the second direction intersect.
  • the driving circuit layer further includes: a plurality of power connection lines extending at least partially along the first direction;
  • At least one power connection line is respectively connected to the pixel driving circuit and the at least one first power line.
  • the driving circuit layer further includes: a first connection electrode;
  • the first connecting electrodes are respectively connected to the pixel driving circuit, the power connection line and the first power line;
  • the orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projections of the power connection line and the first power line on the substrate.
  • the first initial signal line and the second initial signal line are the same signal line
  • the driving circuit layer further includes: a plurality of initial connection lines extending at least partially along the second direction;
  • At least one initial connection line connected to the pixel driving circuit and at least one first initial signal line respectively;
  • the orthographic projection of the initial connection line on the substrate is located between the orthographic projections of the data signal lines connected to two adjacent columns of sub-pixels connected by the initial connection line on the substrate.
  • the first scan signal line includes: a first sub-signal line and a second sub-signal line electrically connected to each other
  • the fourth scan signal line includes: a third sub-signal line and a fourth sub-signal line electrically connected to each other
  • the orthographic projection of the first sub-signal line on the substrate at least partially overlaps with the orthographic projection of the second sub-signal line on the substrate, and the orthographic projection of the third sub-signal line on the substrate at least partially overlaps with the orthographic projection of the fourth sub-signal line on the substrate.
  • the pixel driving circuit includes: first to seventh transistors and a first capacitor and a second capacitor, the first capacitor and the second capacitor respectively include: a first electrode plate and a second electrode plate, and the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially arranged on a substrate;
  • the first semiconductor layer includes at least: an active layer of a second transistor, an active layer of a third transistor, an active layer of a sixth transistor, and an active layer of a seventh transistor located in at least one sub-pixel;
  • the first conductive layer at least includes: a light emitting signal line, a second scanning signal line, a third scanning signal line, and a first plate of a first capacitor located in at least one sub-pixel, a first plate of a second capacitor, a gate electrode of a second transistor, a gate electrode of a third transistor, a control electrode of a sixth transistor, and a gate electrode of a seventh transistor
  • the second conductive layer at least includes: a first sub-signal line of the first scanning signal line, a third sub-signal line of the fourth scanning signal line, and a second plate of a first capacitor and a second plate of a second capacitor located in at least one sub-pixel;
  • the second semiconductor layer includes at least: an active layer of a first transistor, an active layer of a fourth transistor, and an active layer of a fifth transistor located in at least one sub-pixel.
  • the third conductive layer at least includes: a second sub-signal line of the first scanning signal line, a fourth sub-signal line of the fourth scanning signal line, a power connection line, a first initial signal line, a second initial signal line and a third initial signal line;
  • the fourth conductive layer at least includes: an initial connection line, a first connection electrode located at at least one sub-pixel, and a first electrode and a second electrode of the first transistor to the seventh transistor;
  • the fifth conductive layer at least includes: a first power line and a data signal line.
  • the driving circuit layer further includes: a light shielding layer disposed between the substrate and the first semiconductor layer;
  • the light shielding layer at least includes: a light shielding structure located in at least one sub-pixel, and the light shielding structures of adjacent sub-pixels are connected to each other;
  • the orthographic projection of the light shielding structure on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the sixth transistor on the substrate.
  • the light shielding structure includes: a first light shielding portion, a second light shielding portion, a third light shielding portion, and a fourth light shielding portion;
  • the orthographic projection of the first light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate
  • the orthographic projection of the second light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the seventh transistor on the substrate
  • the orthographic projection of the third light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate
  • the orthographic projection of the fourth light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate.
  • the light shielding structure includes: a light shielding portion, a first light shielding connection portion, a second light shielding connection portion, a third light shielding connection portion, and a fourth light shielding connection portion;
  • the orthographic projection of the light shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate.
  • the orthographic projection of any one of the first light-shielding connection portion, the second light-shielding connection portion, the third light-shielding connection portion and the fourth light-shielding connection portion on the substrate does not overlap with the orthographic projection of any one of the active layer of the second transistor, the active layer of the third transistor and the active layer of the seventh transistor on the substrate.
  • the light emitting signal line connected to the sub-pixel is located on a side where the first plate of the second capacitor of the sub-pixel is away from the first plate of the first capacitor of the sub-pixel
  • the second scanning signal line connected to the sub-pixel is located on a side where the first plate of the first capacitor of the sub-pixel is away from the first plate of the second capacitor of the sub-pixel
  • the third scanning signal line connected to the sub-pixel is located on a side where the second scanning signal line connected to the sub-pixel is away from the first plate of the first capacitor of the sub-pixel.
  • the second electrode plate of the first capacitor and the second electrode plate of the second capacitor are an integrated structure connected to each other, and are provided with a first via hole and a second via hole, the first via hole exposing the first electrode plate of the first capacitor, and the second via hole exposing the second electrode plate of the second capacitor;
  • the third sub-signal line of the fourth scanning signal line is located at a side of the first sub-signal line of the first scanning signal line away from the integrated structure of the second electrode plate of the first capacitor and the second electrode plate of the second capacitor;
  • the orthographic projection of the first sub-signal line of the first scanning signal line connected to the sub-pixel on the substrate is located between the orthographic projection of the light-emitting signal line connected to the sub-pixel on the substrate and the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate, and the orthographic projection of the third sub-signal line of the fourth scanning signal line connected to the sub-pixel on the substrate is located on the side of the orthographic projection of the light-emitting signal line connected to the sub-pixel on the substrate away from the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate.
  • the second sub-signal line of the first scan signal line connected to the sub-pixel is located on one side of the fourth sub-signal line of the fourth scan signal line connected to the sub-pixel
  • the power connection line connected to the sub-pixel is located on one side of the second sub-signal line of the first scan signal line connected to the sub-pixel away from the fourth sub-signal line of the fourth scan signal line connected to the sub-pixel
  • the first initial signal line connected to the sub-pixel is located on one side of the power connection line connected to the sub-pixel away from the second sub-signal line of the first scan signal line connected to the sub-pixel
  • the third initial signal line connected to the sub-pixel is located on one side of the first initial signal line connected to the sub-pixel away from the power connection line connected to the sub-pixel
  • the positive projection of the fourth sub-signal line of the fourth scanning signal line connected to the sub-pixel on the substrate is located on a side where the positive projection of the light emitting signal line connected to the sub-pixel on the substrate is away from the positive projection of the first electrode plate of the second capacitor of the sub-pixel on the substrate;
  • the orthographic projection of the second sub-signal line of the first scanning signal line connected to the sub-pixel on the substrate is located between the orthographic projection of the light emitting signal line connected to the sub-pixel on the substrate and the orthographic projection of the first electrode plate of the second capacitor of the sub-pixel on the substrate;
  • the orthographic projection of the power connection line connected to the sub-pixel on the substrate at least partially overlaps with the orthographic projection of the integrated structure of the second electrode plate of the first capacitor of the sub-pixel and the second electrode plate of the second capacitor on the substrate, and is located between the orthographic projection of the first sub-signal line of the first scanning signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate;
  • the positive projection of the first initial signal line connected to the sub-pixel on the substrate at least partially overlaps with the positive projection of the second scanning signal line connected to the sub-pixel on the substrate, and is located between the positive projection of the first plate of the first capacitor of the sub-pixel on the substrate and the positive projection of the third scanning signal line connected to the sub-pixel on the substrate;
  • the positive projection of the third initial signal line connected to the sub-pixel on the substrate at least partially overlaps with the positive projection of the third scanning signal line connected to the sub-pixel on the substrate, and is located on the side of the positive projection of the second scanning signal line connected to the sub-pixel on the substrate away from the positive projection of the first plate of the first capacitor of the sub-pixel on the substrate.
  • the power connection line includes: a signal main line, a first protrusion, a second protrusion, and a third protrusion
  • the signal main line extends along a first direction
  • the first protrusion is located on a side of the signal main line close to the second sub-signal line of the first scan signal line
  • the second protrusion and the third protrusion are located on a side of the signal main line away from the second sub-signal line of the first scan signal line
  • the second protrusion and the third protrusion are arranged along the first direction
  • the orthographic projections of the second protrusion and the third protrusion on the substrate are aligned with the second electrode plate of the first capacitor and the second electrode plate of the second capacitor.
  • the orthographic projections of the integrated structure of the diode plate on the substrate at least partially overlap;
  • the orthographic projection of the first via hole on the substrate is located between the orthographic projection of the second protrusion on the substrate and the orthographic projection of the third protrusion on the substrate.
  • the orthographic projection of the first connection electrode on the substrate at least partially overlaps with the orthographic projections of the signal main line, the second protrusion and the third protrusion of the power connection line on the substrate, and does not overlap with the orthographic projection of the first protrusion of the power connection line on the substrate.
  • an orthographic projection of the first power line on the substrate at least partially overlaps an orthographic projection of the second plate of the first capacitor and the integrated structure of the second plate of the second capacitor, the first connection electrode, the signal main body portion of the power connection line, and the second protrusion on the substrate;
  • the orthographic projection of the first power supply line connected to the sub-pixel on the substrate is located on a side of the data signal line connected to the sub-pixel away from the initial connection line connected to the sub-pixel.
  • the present disclosure further provides a display device, comprising: the above-mentioned display substrate.
  • the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the above-mentioned pixel driving circuit, and the method includes:
  • the node control subcircuit drives the signal of the first node through the signal of the first initial signal line, the data signal line and the first power line under the control of the signal of the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line, provides the signal of the second initial signal line to the second node, and provides the signal of the third initial signal line to the third node;
  • the light-emitting control subcircuit provides the signal of the first power line to the third node under the control of the signal of the light-emitting signal line, and the driving subcircuit outputs the driving current to the second node under the control of the signals of the first node and the third node.
  • FIG1 is a schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present disclosure
  • FIG2 is a schematic diagram of the structure of a node control subcircuit
  • FIG3 is an equivalent circuit diagram of a node control subcircuit
  • FIG4 is an equivalent circuit diagram of a light emitting control subcircuit and a driving subcircuit
  • FIG5 is an equivalent circuit diagram of a pixel driving circuit
  • FIG6 is a working timing diagram of a pixel driving circuit
  • FIG7 is a first structural schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG8 is a second structural schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG9 is a schematic diagram showing a partial film layer of a substrate
  • FIG10 is a second schematic diagram showing a partial film layer of a display substrate
  • FIG11 is a schematic diagram of a light shielding layer pattern of a display substrate provided in FIG7 ;
  • FIG12 is a schematic diagram of a light shielding layer pattern of the display substrate provided in FIG8 ;
  • FIG13 is a schematic diagram of a first semiconductor layer pattern of a display substrate provided in FIG7 and FIG8 ;
  • FIG14 is a schematic diagram of the display substrate provided in FIG7 after a first semiconductor layer pattern is formed
  • FIG15 is a schematic diagram of the display substrate provided in FIG8 after a first semiconductor layer pattern is formed
  • FIG16 is a schematic diagram of a first conductive layer pattern of a display substrate provided in FIG7 and FIG8 ;
  • FIG17 is a schematic diagram of the display substrate provided in FIG7 after a first conductive layer pattern is formed
  • FIG18 is a schematic diagram of the display substrate provided in FIG8 after a first conductive layer pattern is formed
  • FIG19 is a schematic diagram of a second conductive layer pattern of a display substrate provided in FIG7 and FIG8 ;
  • FIG20 is a schematic diagram of the display substrate provided in FIG7 after a second conductive layer pattern is formed
  • FIG21 is a schematic diagram of the display substrate provided in FIG8 after a second conductive layer pattern is formed
  • FIG22 is a schematic diagram of a second semiconductor layer pattern of the display substrate provided in FIG7 and FIG8;
  • FIG23 is a schematic diagram of the display substrate provided in FIG7 after a second semiconductor layer pattern is formed
  • FIG24 is a schematic diagram of the display substrate provided in FIG8 after a second semiconductor layer pattern is formed
  • FIG25 is a schematic diagram of a third conductive layer pattern of the display substrate provided in FIG7 and FIG8;
  • FIG26 is a schematic diagram of the display substrate provided in FIG7 after a third conductive layer pattern is formed
  • FIG27 is a schematic diagram of the display substrate provided in FIG8 after a third conductive layer pattern is formed
  • FIG28 is a schematic diagram of the display substrate provided in FIG7 after a seventh insulating layer pattern is formed;
  • FIG29 is a schematic diagram of the display substrate provided in FIG8 after a seventh insulating layer pattern is formed;
  • FIG30 is a schematic diagram of a fourth conductive layer pattern of the display substrate provided in FIG7 and FIG8;
  • FIG31 is a schematic diagram of the display substrate provided in FIG7 after a fourth conductive layer pattern is formed
  • FIG32 is a schematic diagram of the display substrate provided in FIG8 after a fourth conductive layer pattern is formed
  • FIG33 is a schematic diagram of the display substrate provided in FIG7 after an eighth insulating layer pattern is formed;
  • FIG34 is a schematic diagram of the display substrate provided in FIG8 after an eighth insulating layer pattern is formed
  • FIG35 is a schematic diagram of a fifth conductive layer pattern of the display substrate provided in FIG7 and FIG8;
  • FIG36 is a schematic diagram of the display substrate provided in FIG7 after a fifth conductive layer pattern is formed
  • FIG. 37 is a schematic diagram of the display substrate provided in FIG. 8 after a fifth conductive layer pattern is formed.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the panel and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the figures.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three elements: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode element, drain region, or drain electrode) and a source electrode (source electrode element, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • the display substrate uses low temperature polysilicon (LTPS) technology, which has the advantages of high resolution, high response speed, high brightness, and high aperture ratio. Although it is popular in the market, LTPS technology also has some defects, such as high production cost and high power consumption.
  • the Low Temperature Polycrystalline Oxide (LTPO) technology solution came into being. Compared with LTPS technology, LTPO technology has a smaller leakage current and faster pixel response.
  • the display substrate has an extra layer of oxide, which reduces the energy consumption required to excite the pixels, thereby reducing the power consumption when the screen is displayed.
  • the manufacturing process is more complicated and the cost is higher. With the emergence of high-mobility oxide materials, oxide-driven OLED devices become possible.
  • oxide technology has a simple process and lower cost, and has a smaller leakage current. It has become a new mainstream trend.
  • the charging time of the pixel driving circuit is short, which cannot meet the requirements of high-resolution display substrates, affecting the display effect of the display product.
  • FIG1 is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present disclosure
  • FIG2 is a schematic diagram of the structure of a node control subcircuit
  • FIG3 is an equivalent circuit diagram of the node control subcircuit.
  • the pixel driving circuit provided in an embodiment of the present disclosure is configured to drive the light-emitting device to emit light
  • the pixel driving circuit includes: a node control subcircuit, a light-emitting control subcircuit, and a driving subcircuit.
  • the node control subcircuit may be electrically connected to the first node N1, the second node N2, the third node N3, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, the fourth scan signal line Gate4, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the data signal line Data and the first power line VDD, respectively, and is configured to drive the signal of the first node N1 through the first initial signal line INIT1, the data signal line Data and the signal of the third node N3 under the control of the signal of the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3 and the fourth scan signal line Gate4, provide the signal of the second initial signal line INIT2 to the second node N2, provide the signal of the third initial signal line INIT3 to the third node N3, and provide the signal of the third node N3 or the data signal line Data to the fourth node N4.
  • the node control subcircuit includes: an energy storage subcircuit, the energy storage subcircuit being electrically connected to the first node N1, the fourth node N4 and the first power line VDD, respectively, and being configured to store a voltage difference between a signal of the first node N1 and the fourth node N4 and a voltage difference between a signal of the fourth node N4 and the first power line VDD, so as to drive a signal of the first node N1 through a signal of the first power line and a signal of the fourth node N4.
  • the energy storage subcircuit may include: a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 and the second capacitor C2 include: a first plate and a second plate.
  • the first plate C11 of the first capacitor C1 is electrically connected to the first power line VDD, and the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4; the first plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected to the fourth node N4.
  • the light emitting control subcircuit may be electrically connected to the first power line VDD, the light emitting signal line EM and the third node N3, respectively, and may be configured to provide the signal of the first power line VDD to the third node N3 under the control of the signal of the light emitting signal line EM.
  • the driving sub-circuit is electrically connected to the first node N1 , the second node N2 , and the third node N3 , respectively, and is configured to output a driving current to the second node N2 under the control of the signals of the first node N1 and the third node N3 .
  • the light emitting device is electrically connected to the second node N2 and the second power line VSS, respectively.
  • the first power line VDD may continuously provide a high voltage power signal
  • the second power line VSS may continuously provide a low voltage power signal
  • the voltage value of the signal of the first power line VDD may be approximately 2.5 volts (V) to 3. Volt (V), illustratively, the voltage value of the signal of the first power line VDD may be approximately 2.8 volts (V).
  • the voltage value of the signal of the second power line VSS may be approximately -3 volts (V) to -3.5 volts (V), and exemplarily, the voltage value of the signal of the second power line VSS may be approximately -3.2 volts (V).
  • the voltage value of the signal of the second power line VSS may be approximately -3 volts (V) to -3.5 volts (V), and exemplarily, the voltage value of the signal of the second power line VSS may be approximately -3.2 volts (V).
  • the light emitting device may be an organic light emitting diode (OLED), including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.
  • OLED organic light emitting diode
  • the anode of the organic light emitting diode is electrically connected to the second node N2
  • the cathode of the organic light emitting diode is electrically connected to the second power line VSS.
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the electron transport layers of all sub-pixels may be a common layer connected together
  • the hole blocking layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the pixel driving circuit configured to drive a light-emitting device, and the pixel driving circuit includes: a node control subcircuit, a light-emitting control subcircuit and a driving subcircuit; the node control subcircuit is electrically connected to the first node, the second node, the third node, the first scanning signal line, the second scanning signal line, the third scanning signal line, the fourth scanning signal line, the first initial signal line, the second initial signal line, the third initial signal line, the data signal line and the first power line, respectively, and is configured to drive the signal of the first node through the first initial signal line, the data signal line and the signal of the third node under the control of the signal of the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line, provide the signal of the second initial signal line to the second node, and provide the signal of the third initial signal line to the third node;
  • the node control subcircuit is electrically connected to the first power line, the light
  • the present disclosure can compensate the pixel driving circuit through the signal of the second initial signal line by setting the cooperation of the node control subcircuit, the light emitting control subcircuit and the driving subcircuit, thereby increasing the compensation time of the pixel driving circuit, extending the charging time of the pixel driving circuit, and improving the reliability of the pixel driving circuit.
  • the node control subcircuit may further include: a reset subcircuit, a compensation subcircuit, and a write subcircuit.
  • the reset subcircuit is electrically connected to the first node N1, the second node N2, the third node N3, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, the first initial signal line INIT1, the second initial signal line INIT2 and the third initial signal line INIT3, respectively, and is configured to provide the signal of the first initial signal line INIT1 to the first node N1 under the control of the signal of the first scan signal line Gate1, provide the signal of the second initial signal line INIT2 to the second node N2 under the control of the signal of the second scan signal line Gate2, and provide the signal of the second initial signal line INIT2 to the second node N3 under the control of the signal of the second scan signal line Gate3.
  • the signal of the third initial signal line INIT3 is provided to the third node N3;
  • the compensation sub-circuit is electrically connected to the third node N3, the fourth node N4 and the first scanning signal line Gate1, respectively, and is configured to provide the signal of the third node N3 to the fourth node N4 under the control of the signal of the first scanning signal line Gate1 to compensate for the signal of the fourth node N4;
  • the write sub-circuit is electrically connected to the fourth node N4, the fourth scanning signal line Gate4 and the data signal line Data, respectively, and is configured to provide the signal of the data signal line Data to the fourth node N4 under the control of the signal of the fourth scanning signal line Gate4.
  • the reset subcircuit may include a first transistor T1 , a second transistor T2 , and a third transistor T3
  • the compensation subcircuit may include a fourth transistor T4
  • the write transistor may include a fifth transistor T5 .
  • the gate electrode of the first transistor T1 is electrically connected to the first scanning signal line Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the gate electrode of the second transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the second initial signal line INIT2, and the second electrode of the second transistor T2 is electrically connected to the second node N2;
  • the gate electrode of the third transistor T3 is electrically connected to the third scanning signal line Gate3, the first electrode of the third transistor T3 is electrically connected to the third initial signal line INIT3, and the second electrode of the second transistor T2 is electrically connected to the third node N3;
  • the gate electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrical
  • FIG4 is an equivalent circuit diagram of the light emitting control subcircuit and the driving subcircuit.
  • the driving subcircuit may include: a sixth transistor T6, and the light emitting control subcircuit may include: a seventh transistor T7.
  • the gate electrode of the sixth transistor T6 is electrically connected to the first node N1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the second node N2;
  • the gate electrode of the seventh transistor T7 is electrically connected to the light emitting signal line EM, the first electrode of the seventh transistor T7 is electrically connected to the first power line VDD, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3.
  • FIG5 is an equivalent circuit diagram of a pixel driving circuit.
  • the node control subcircuit includes: a first transistor T1 to a fifth transistor T5 and a first capacitor C1 and a second capacitor C2, the driving subcircuit includes: a sixth transistor T6, and the light emitting control subcircuit includes: a seventh transistor T7; the first capacitor C1 and the second capacitor C2 include: a first plate and a second plate.
  • the gate electrode of the first transistor T1 is electrically connected to the first scanning signal line Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the gate electrode of the second transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the second initial signal line INIT2, and the second electrode of the second transistor T2 is electrically connected to the second node N2;
  • the gate electrode of the third transistor T3 is electrically connected to the third scanning signal line Gate3, the first electrode of the third transistor T3 is electrically connected to the third initial signal line INIT3, and the second electrode of the second transistor T2 is electrically connected to the third node N3;
  • the gate electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrical
  • the first transistor T1 may be referred to as a first node reset transistor.
  • the signal of the first scan signal line Gate1 is an active level signal
  • the signal of the first initial signal line INIT1 is written into the first node N1.
  • the second transistor T2 may be referred to as a second node reset transistor.
  • the signal of the first scanning signal line Gate2 is an effective level signal
  • the signal of the second initial signal line INIT2 is written into the second node N2 (also the anode of the light emitting device L).
  • the third transistor T3 may be referred to as a third node reset transistor.
  • the signal of the third scan signal line Gate3 is an active level signal
  • the signal of the third initial signal line INIT3 is written into the third node N3.
  • the fourth transistor T4 may be referred to as a compensation transistor.
  • the signal of the first scan signal line Gate1 is an effective level signal
  • the signal of the third node N3 is written into the fourth node N4 to compensate for the signal of the fourth node N4.
  • the fifth transistor T5 may be referred to as a write transistor.
  • the signal of the fourth scan signal line Gate is an active level signal
  • the signal of the data signal line Data is written into the second node N2.
  • the sixth transistor T6 may be referred to as a driving transistor.
  • the sixth transistor T6 determines a driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between its gate electrode and the first electrode.
  • the seventh transistor T7 may be referred to as a light emitting transistor.
  • the seventh transistor T7 enables the light emitting device to emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the length of the channel region of the active layer of the sixth transistor is greater than the length of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor
  • the width of the channel region of the active layer of the sixth transistor is greater than the width of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor
  • the width-to-length ratio of the channel region of the active layer of the sixth transistor is less than the width-to-length ratio of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor.
  • FIG. 5 An exemplary structure of the node control subcircuit, the driving subcircuit and the light emitting control subcircuit is shown in Fig. 5. It is easy for those skilled in the art to understand that the implementation of the node control subcircuit, the driving subcircuit and the light emitting control subcircuit is not limited thereto.
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide thin film transistor. (Low Temperature Polycrystalline Oxide, LTPO for short) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.
  • the first transistor T1 , the fourth transistor T4 , and the fifth transistor T5 may be oxide transistors.
  • the first transistor T1 , the fourth transistor T4 , and the fifth transistor T5 may be N-type transistors
  • the second transistor T2 , the third transistor T3 , the sixth transistor T6 , and the seventh transistor T7 may be P-type transistors.
  • the width-to-length ratio of the channel regions of the active layers of the first to fifth transistors T1 to T5 may be 2.5/3.
  • the width-to-length ratio of the channel region of the active layer of the sixth transistor T6 may be 3.5/20.
  • a width-to-length ratio of a channel region of an active layer of the seventh transistor T7 may be 2.0/2.5.
  • the signal of the first scan signal line Gate1 and the signal of the second scan signal line Gate2 may be inverted signals of each other.
  • the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are effective level signals
  • the signals of the fourth scan signal line Gate4 and the emission signal line EM are ineffective level signals.
  • the signals of the first scan signal line Gate1 , the second scan signal line Gate2 , the third scan signal line Gate3 and the emission signal line EM are invalid level signals.
  • the signals of the first scan signal line Gate1 , the second scan signal line Gate2 , the third scan signal line Gate3 , and the fourth scan signal line Gate4 are ineffective level signals.
  • the duration of the signal of any one of the first scan signal line Gate1 and the second scan signal line Gate2 being the active level signal is greater than the duration of the signal of any one of the third scan signal line Gate3 and the fourth scan signal line Gate4 being the active level signal.
  • the signal of the first initial signal line INIT1 and the signal of the second initial signal line INIT2 may be the same signal, and a voltage value of the signal of the first initial signal line INIT1 is smaller than a voltage value of the signal of the third initial signal line INIT3 .
  • the first initial signal line INIT1 and the second initial signal line INIT2 may be the same signal line, or may be different signal lines transmitting the same signal, which is not limited in the present disclosure.
  • the voltage value of the signal of the first initial signal line INIT1 may be approximately -2.8 volts (V) to -3.2 volts (V), and exemplarily, the voltage value of the signal of the first initial signal line INIT1 may be approximately -3 volts (V).
  • the voltage value of the signal of the third initial signal line INIT3 may be approximately 5 volts (V) to 7 volts (V), and exemplarily, the voltage value of the signal of the third initial signal line INIT3 may be approximately 6 volts (V).
  • the voltage value of the signal of the second initial signal line INIT2 may be greater than the voltage value of the signal of the second power line VSS.
  • the voltage value of the signal of the second initial signal line INIT2 may be slightly greater than the voltage value of the signal of the second power line VSS.
  • the voltage value of the signal of the second initial signal line INIT2 being greater than the voltage value of the signal of the second power line VSS can ensure that when the second node N2 (which is also the anode of the light-emitting device) is reset, the light-emitting device does not emit light, thereby improving the display effect.
  • FIG6 is a working timing diagram of a pixel driving circuit.
  • the pixel driving circuit in FIG5 includes 7 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors (first capacitor C1 and second capacitor C2).
  • the first transistor T1, the fourth transistor T4 and the fifth transistor T5 are N-type transistors, and the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are P-type transistors.
  • the operation process of the pixel driving circuit may include:
  • the first stage P1 is called the initialization stage.
  • the signals of the first scanning signal line Gate1 and the light-emitting signal line EM are high-level signals, and the signals of the second scanning signal line Gate2, the third scanning signal line Gate3 and the fourth scanning signal line Gate4 are low-level signals.
  • the signal of the first scanning signal line Gate1 is a high-level signal, the first transistor T1 and the fourth transistor T4 are turned on, and the first initial signal of the first initial signal line INIT1 is written to the first node N1 through the turned-on first transistor T1, and the first node N1 is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the signal of the second scanning signal line Gate2 is a low-level signal, and the second transistor T2 is turned on.
  • the second initial signal of the second initial signal line INIT2 is written to the second node N2 (also the anode of the light-emitting device L) through the turned-on second transistor T2, and the second node N2 (also the anode of the light-emitting device L) is initialized (reset), and the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the signal of the third scanning signal line Gate3 is a low level signal, the third transistor T3 is turned on, and the third initial signal of the third initial signal line INIT3 is written to the third node N3 and the fourth node N4 through the turned-on third transistor T3 and the fourth transistor T4, and the third node N3 and the fourth node N4 are initialized (reset), and the pre-stored voltage inside them is cleared to complete the initialization.
  • the difference in the voltage value of the signal between the first node N1 and the third node N3 is less than the threshold voltage of the sixth transistor T6, and the sixth transistor T6 is turned on.
  • the signal of the fourth scanning signal line Gate is a low level signal
  • the fifth transistor T5 is turned off
  • the signal of the light-emitting signal line EM is a high level signal
  • the seventh transistor T7 is turned off.
  • the voltage value of the second initial signal of the second initial signal line INIT2 is slightly less than the voltage value of the signal of the second power line VSS, the light-emitting device L does not emit light.
  • the second stage P2 is called the threshold compensation stage.
  • the signals of the first scanning signal line Gate1, the third scanning signal line Gate3 and the light emitting signal line EM are high level signals, and the signals of the second scanning signal line Gate2 and the fourth scanning signal line Gate4 are low level signals.
  • the signal of the first scanning signal line Gate1 is a high level signal, the first transistor T1 and the fourth transistor T4 are continuously turned on, and the first initial signal of the first initial signal line INIT1 is written to the first node N1 through the turned-on first transistor T1, and the first node N1 continues to be initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the signal of the second scanning signal line Gate2 is a low level signal, the second transistor T2 is turned on, the second initial signal of the second initial signal line INIT2 is written to the second node N2 (also the anode of the light emitting device L) through the turned-on second transistor T2, the second node N2 (also the anode of the light emitting device L) is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the signal of the third scanning signal line Gate3 is a high level signal
  • the third transistor T3 is turned off
  • the signal of the fourth scanning signal line Gate is a low level signal
  • the fifth transistor T5 is turned off
  • the signal of the light emitting signal line EM is a high level signal
  • the seventh transistor T7 is turned off.
  • the voltage value of the second initial signal of the second initial signal line INIT2 is slightly lower than the voltage value of the signal of the second power line VSS, the light emitting device L does not emit light.
  • the third stage P3 is called the data writing stage.
  • the signals of the second scanning signal line Gate2, the third scanning signal line Gate3, the fourth scanning signal line Gate4 and the light-emitting signal line EM are high-level signals, and the signal of the first scanning signal line Gate1 is a low-level signal.
  • the data signal line Data outputs a data signal.
  • the signal of the first scanning signal line Gate1 is a low level signal
  • the first transistor T1 and the fourth transistor T4 are turned off
  • the signal of the second scanning signal line Gate2 is a high level signal
  • the second transistor T2 is turned off
  • the signal of the third scanning signal line Gate3 is a high level signal
  • the third transistor T3 is turned off
  • the signal of the light-emitting signal line EM is a high level signal
  • the seventh transistor T7 is turned off.
  • the light-emitting device L does not emit light.
  • the fourth stage P4 is called the light-emitting stage.
  • the signals of the second scanning signal line Gate2 and the third scanning signal line Gate3 are high-level signals, and the signals of the first scanning signal line Gate1, the fourth scanning signal line Gate4 and the light-emitting signal line EM are low-level signals.
  • the signal of the light-emitting signal line EM is a low-level signal, the seventh transistor T7 is turned on, and the power signal output by the first power line VDD provides a driving voltage to the second node N2 (also the first electrode of the light-emitting device L) through the turned-on seventh transistor T7, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting device L to emit light.
  • the signal of the first scanning signal line Gate1 is a low-level signal, the first transistor T1 and the fourth transistor T4 are turned off, the signal of the second scanning signal line Gate2 is a high-level signal, the second transistor T2 is turned off, the signal of the third scanning signal line Gate3 is a high-level signal, the third transistor T3 is turned off, the signal of the fourth scanning signal line Gate4 is a low-level signal, and the fifth transistor T5 is turned off.
  • I is the driving current flowing through the sixth transistor T6, that is, the driving current driving the light emitting device L
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the sixth transistor T6
  • Vth is the threshold voltage of the sixth transistor T6.
  • the driving current of the sixth transistor T6 is no longer affected by the threshold voltage of the sixth transistor T6, thereby eliminating the influence of the threshold voltage of the sixth transistor T6 on the driving current, which can ensure the uniform display brightness of the display product and improve the display effect of the entire display product.
  • the signal of the fourth node N4 is compensated by the signal of the second initial signal line INIT2, which prolongs the compensation time of the pixel driving circuit, increases the charging time of the pixel driving circuit, and improves the reliability of the pixel driving circuit.
  • the embodiment of the present disclosure further provides a display substrate comprising: a substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel comprising: a pixel driving circuit and a light-emitting device driven by the pixel driving circuit.
  • the pixel driving circuit is the pixel driving circuit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be described in detail here.
  • FIG7 is a schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure
  • FIG8 is a schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure
  • FIG9 is a schematic diagram of a part of the membrane layer of the display substrate
  • FIG10 is a schematic diagram of a part of the membrane layer of the display substrate.
  • the display substrate may include: a substrate, and a driving circuit layer and a light-emitting structure layer sequentially arranged on the substrate
  • the driving circuit layer includes: a plurality of pixel driving circuits, a plurality of light-emitting signal lines EM, a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, a plurality of third initial signal lines, a plurality of first scanning signal lines Gate1, a plurality of second scanning signal lines Gate2, a plurality of third scanning signal lines Gate3, a plurality of fourth scanning signal lines Gate4, a plurality of first power lines VDD and a plurality of data signal lines Data
  • the light-emitting structure layer includes: a light-emitting device.
  • any one of the emission signal line EM, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, and the fourth scan signal line Gate4 at least partially extends along the first direction D1.
  • the first power line VDD and the data signal line Data at least partially extend along the second direction D2, and the first direction D1 intersects the second direction D2.
  • the display substrate may further include an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the display substrate may include other film layers, such as a touch control structure layer, etc., which are not limited in the present disclosure.
  • the display substrate may include: a plurality of sub-pixels, at least one sub-pixel may include: a pixel driving circuit and a light-emitting device, the pixel driving circuit being configured to output a corresponding current to the connected light-emitting device so that the light-emitting device emits light of corresponding brightness.
  • the plurality of sub-pixels may include a plurality of pixel rows and a plurality of pixel columns.
  • a plurality of sub-pixels arranged in sequence along the horizontal direction may be referred to as pixel rows
  • a plurality of sub-pixels arranged in sequence along the vertical direction may be referred to as pixel columns
  • the plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.
  • a plurality of sub-pixels constitute one pixel unit, and the pixel unit may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, or a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel.
  • the first sub-pixel when the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel may be a red sub-pixel (R) emitting red light, the second sub-pixel may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light.
  • the shapes of the three sub-pixels may be triangles, rectangles, rhombuses, pentagons, or hexagons, etc., which are not limited in the present disclosure.
  • the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in sequence in an aligned manner, and in the direction of the pixel column, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in sequence in a staggered manner to form a sub-pixel layout.
  • the first sub-pixel in an odd row may be located between the adjacent second and third sub-pixels in an even row, or the first sub-pixel in an even row may be located between the adjacent second and third sub-pixels in an odd row.
  • the second subpixel in an odd-numbered row may be located between the adjacent first and third subpixels in an even-numbered row, or the second subpixel in an even-numbered row may be located between the adjacent first and third subpixels in an odd-numbered row.
  • the third subpixel in an odd-numbered row may be located between the adjacent first and second subpixels in an even-numbered row, or the third subpixel in an even-numbered row may be located between the adjacent first and second subpixels in an odd-numbered row.
  • the first sub-pixel when the pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, the third sub-pixel and the fourth sub-pixel may be green sub-pixels (G) that emit green light, and the shapes of the three sub-pixels may be triangles, rectangles, diamonds, pentagons, or hexagons, etc., which are not limited in the present disclosure.
  • the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, which are not limited in the present disclosure.
  • the four sub-pixels may be arranged in a square manner to form a GGRB pixel arrangement.
  • the four sub-pixels may be arranged in a diamond manner to form an RGGB pixel arrangement.
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the light-emitting structure layer includes: an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer sequentially stacked on the substrate;
  • the anode layer includes: an anode
  • the organic structure layer includes: an organic light-emitting layer
  • the cathode layer includes: a cathode.
  • the driving circuit layer further includes: A plurality of power connection lines VCL extending in the first direction; at least one power connection line VCL is connected to the pixel driving circuit and at least one first power line VDD respectively.
  • the plurality of power connection lines VCL extending in the first direction; and the plurality of first power lines extending in the second direction form a mesh structure, which can ensure that the power signal of each pixel driving circuit is the same, and can improve the display uniformity of the display substrate.
  • the driving circuit layer may further include: a first connecting electrode.
  • the first connecting electrode is connected to the pixel driving circuit, the power connection line VCL and the first power line VDD respectively; the orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the power connection line VCL and the first power line VDD on the substrate.
  • the first initial signal line INIT1 and the second initial signal line INIT2 are the same signal line.
  • the driving circuit layer may further include: a plurality of initial connection lines ICL extending at least partially along the second direction D2; and at least one initial connection line ICL connected to the pixel driving circuit and at least one first initial signal line INIT1, respectively.
  • the plurality of first initial signal lines INIT1 extending along the first direction and the plurality of initial connection lines ICL extending along the second direction form a mesh structure, which can reduce the influence of the difference in initial signals of the first initial signal lines connected to different pixel driving circuits due to the difference in resistance of the first initial signal lines on low grayscale, and can improve the display uniformity of the display substrate.
  • the orthographic projection of the initial connection line ICL on the substrate may be located between the orthographic projections of the data signal lines Data connected to two adjacent columns of sub-pixels connected to the initial connection line ICL on the substrate.
  • the first scan signal line Gate1 includes: a first sub-signal line and a second sub-signal line electrically connected to each other.
  • the first sub-signal line and the second sub-signal line may be arranged in different layers and may be electrically connected at the periphery of the display area, and the orthographic projection of the first sub-signal line on the substrate at least partially overlaps with the orthographic projection of the second sub-signal line on the substrate.
  • the fourth scan signal line Gate4 includes: a third sub-signal line and a fourth sub-signal line that are arranged in different layers and are interconnected.
  • the third sub-signal line and the fourth sub-signal line can be arranged in different layers and can be electrically connected at the periphery of the display area, and the orthographic projection of the third sub-signal line on the substrate at least partially overlaps with the orthographic projection of the fourth sub-signal line on the substrate.
  • the pixel driving circuit includes: first to seventh transistors and a first capacitor and a second capacitor, the first capacitor and the second capacitor respectively include: a first electrode plate and a second electrode plate, and the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially arranged on a substrate;
  • the first semiconductor layer includes at least: an active layer of a second transistor, an active layer of a third transistor, an active layer of a sixth transistor, and an active layer of a seventh transistor located in at least one sub-pixel;
  • the first conductive layer at least includes: a light emitting signal line EM, a second scanning signal line Gate2, a third scanning signal line Gate3, and a first plate of a first capacitor located at at least one sub-pixel, a first plate of a second capacitor, a gate electrode of a second transistor, a gate electrode of a third transistor, a control electrode of a sixth transistor, and a gate electrode of a seventh transistor;
  • the second conductive layer at least includes: a first sub-signal line of the first scanning signal line Gate1, a third sub-signal line of the fourth scanning signal line Gate4, and a second plate of a first capacitor and a second plate of a second capacitor located in at least one sub-pixel;
  • the second semiconductor layer includes at least: an active layer of a first transistor, an active layer of a fourth transistor, and an active layer of a fifth transistor located in at least one sub-pixel.
  • the third conductive layer at least includes: a second sub-signal line of the first scanning signal line Gate1, a fourth sub-signal line of the fourth scanning signal line Gate4, a power connection line VCL, a first initial signal line INIT1, a second initial signal line INIT2 and a Three initial signal lines;
  • the fourth conductive layer at least includes: an initial connection line ICL, a first connection electrode located at at least one sub-pixel, and first electrodes and second electrodes of the first transistor to the seventh transistor;
  • the fifth conductive layer at least includes: a first power line VDD and a data signal line Data.
  • the signal line for power signal transmission in the present disclosure includes a power connection line located on the third conductive layer and a first power line located on the fifth conductive layer
  • the signal line for data signal transmission includes a data signal line on the fifth conductive layer
  • the second plate of the first capacitor and the second plate of the second capacitor are located on the second conductive layer
  • the signal line for power signal transmission includes a power connection line located on the third conductive layer, which can shield the parasitic capacitance between the second plate of the first capacitor located on the second conductive layer and the second plate of the second capacitor and the data signal line on the fifth conductive layer (which is also the parasitic capacitance between the signal of the gate electrode of the sixth transistor and the data signal), thereby avoiding crosstalk between signals and improving the reliability of the display substrate.
  • Fig. 11 is a schematic diagram of a light shielding layer pattern of the display substrate provided in Fig. 7
  • Fig. 12 is a schematic diagram of a light shielding layer pattern of the display substrate provided in Fig. 8.
  • the driving circuit layer may further include: a light shielding layer disposed between the substrate and the first semiconductor layer; the light shielding layer at least includes: a light shielding structure located in at least one sub-pixel, and the light shielding structures of adjacent sub-pixels are connected to each other.
  • the orthographic projection of the shading structure on the substrate may at least partially overlap with the orthographic projection of the gate electrode of the sixth transistor on the substrate.
  • the orthographic projection of the shading structure on the substrate may cover the orthographic projection of the gate electrode of the sixth transistor on the substrate, and the orthographic projection of the shading structure on the substrate covers the orthographic projection of the gate electrode of the sixth transistor (also the driving transistor) on the substrate, which can increase the service life of the driving transistor and improve the reliability of the display substrate.
  • the light-shielding structure may include: a first light-shielding portion 11, a second light-shielding portion 12, a third light-shielding portion 13 and a fourth light-shielding portion 14; wherein the orthographic projection of the first light-shielding portion 11 on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate, the orthographic projection of the second light-shielding portion 12 on the substrate at least partially overlaps with the orthographic projection of the active layer of the seventh transistor on the substrate, the orthographic projection of the third light-shielding portion 13 on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate, and the orthographic projection of the fourth light-shielding portion 14 on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate.
  • the light-shielding structure may include: a light-shielding portion 20, a first light-shielding connection portion 21, a second light-shielding connection portion 22, a third light-shielding connection portion 23 and a fourth light-shielding connection portion 24; wherein the orthographic projection of the light-shielding portion 20 on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate, and the orthographic projection of any one of the first light-shielding connection portion 21, the second light-shielding connection portion 22, the third light-shielding connection portion 23 and the fourth light-shielding connection portion 24 on the substrate does not overlap with the orthographic projection of any one of the active layer of the second transistor, the active layer of the third transistor and the active layer of the seventh transistor on the substrate.
  • the light emitting signal line EM connected to the sub-pixel is located on a side where the first plate of the second capacitor of the sub-pixel is away from the first plate of the first capacitor of the sub-pixel
  • the second scanning signal line Gate2 connected to the sub-pixel is located on a side where the first plate of the first capacitor of the sub-pixel is away from the first plate of the second capacitor of the sub-pixel
  • the third scanning signal line Gate3 connected to the sub-pixel is located on a side where the second scanning signal line Gate2 connected to the sub-pixel is away from the first plate of the first capacitor of the sub-pixel.
  • the second plate C12 of the first capacitor and the second plate C22 of the second capacitor are an integrated structure connected to each other and are provided with a first via hole V1 and a second via hole V2, the first via hole exposing the first plate of the first capacitor and the second via hole exposing the second plate of the second capacitor.
  • the third sub-signal line of the fourth scan signal line Gate4 is located at a side of the first sub-signal line of the first scan signal line Gate1 away from the integrated structure of the second electrode plate C12 of the first capacitor and the second electrode plate C22 of the second capacitor.
  • the positive projection of the first sub-signal line of the first scanning signal line Gate1 connected to the sub-pixel on the substrate is located between the positive projection of the light-emitting signal line EM connected to the sub-pixel on the substrate and the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate, and the positive projection of the third sub-signal line of the fourth scanning signal line Gate4 connected to the sub-pixel on the substrate is located on the side of the positive projection of the light-emitting signal line EM connected to the sub-pixel on the substrate away from the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.
  • the second sub-signal line of the first scanning signal line Gate1 connected to the sub-pixel is located on a side of the fourth sub-signal line of the fourth scanning signal line Gate4 connected to the sub-pixel
  • the power connection line VCL connected to the sub-pixel is located on a side of the second sub-signal line of the first scanning signal line Gate1 connected to the sub-pixel away from the fourth sub-signal line of the fourth scanning signal line Gate4 connected to the sub-pixel
  • the first initial signal line INIT1 connected to the sub-pixel is located on a side of the power connection line VCL connected to the sub-pixel away from the second sub-signal line of the first scanning signal line Gate1 connected to the sub-pixel
  • the third initial signal line connected to the sub-pixel is located on a side of the first initial signal line INIT1 connected to the sub-pixel away from the power connection line VCL connected to the sub-pixel.
  • the positive projection of the fourth sub-signal line of the fourth scanning signal line Gate4 connected to the sub-pixel on the substrate is located on the side of the positive projection of the light-emitting signal line EM connected to the sub-pixel on the substrate away from the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.
  • the orthographic projection of the second sub-signal line of the first scanning signal line Gate1 connected to the sub-pixel on the substrate is located between the orthographic projection of the light-emitting signal line EM connected to the sub-pixel on the substrate and the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate.
  • the orthographic projection of the power connection line VCL connected to the sub-pixel on the substrate at least partially overlaps with the orthographic projection of the integrated structure of the second plate of the first capacitor and the second plate of the second capacitor of the sub-pixel on the substrate, and is located between the orthographic projection of the first sub-signal line of the first scanning signal line Gate1 on the substrate and the orthographic projection of the second scanning signal line Gate2 on the substrate.
  • the positive projection of the first initial signal line INIT1 connected to the sub-pixel on the substrate at least partially overlaps with the positive projection of the second scanning signal line Gate2 connected to the sub-pixel on the substrate, and is located between the positive projection of the first plate of the first capacitor of the sub-pixel on the substrate and the positive projection of the third scanning signal line Gate3 connected to the sub-pixel on the substrate.
  • the positive projection of the third initial signal line INIT3 connected to the sub-pixel on the substrate at least partially overlaps with the positive projection of the third scanning signal line Gate3 connected to the sub-pixel on the substrate, and is located on a side of the positive projection of the second scanning signal line Gate2 connected to the sub-pixel on the substrate away from the positive projection of the first plate of the first capacitor of the sub-pixel on the substrate.
  • the power connection line VCL includes: a signal main line, a first protrusion, a second protrusion, and a third protrusion
  • the signal main line extends along a first direction
  • the first protrusion is located on a side of the signal main line close to the second sub-signal line of the first scanning signal line Gate1
  • the second protrusion and the third protrusion are located on a side of the signal main line away from the second sub-signal line of the first scanning signal line Gate1
  • the second protrusion and the third protrusion are arranged along the first direction.
  • the orthographic projections of the second protrusion and the third protrusion on the substrate at least partially overlap with the orthographic projections of the integrated structure of the second electrode plate of the first capacitor and the second electrode plate of the second capacitor on the substrate.
  • an orthographic projection of the first via hole on the substrate is located between an orthographic projection of the second protrusion on the substrate and an orthographic projection of the third protrusion on the substrate.
  • the orthographic projection of the first connection electrode VL1 on the substrate at least partially overlaps with the orthographic projections of the signal main line, the second protrusion and the third protrusion of the power connection line VCL on the substrate, and does not overlap with the orthographic projection of the first protrusion of the power connection line VCL on the substrate.
  • the orthographic projection of the first power line VDD on the substrate is aligned with the first power line VDD on the substrate.
  • the orthographic projections of the second plate of the first capacitor and the integrated structure of the second plate of the second capacitor, the first connection electrode, the signal main body of the power connection line VCL and the second protrusion on the substrate at least partially overlap.
  • the positive projection of the sub-pixel connected first power line VDD on the substrate is located on a side of the sub-pixel connected data signal line Data away from the sub-pixel connected initial connection line ICL.
  • the following is an exemplary explanation through the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation process of the display substrate provided in FIG7 and FIG8 using a two-row and four-column pixel driving circuit may include:
  • (1) forming a light-shielding layer pattern on a substrate including: depositing a first insulating film and a light-shielding film on the substrate in sequence, patterning the light-shielding film through a patterning process, and forming a first insulating layer covering the substrate and a light-shielding layer pattern located on the first insulating layer, as shown in FIGS. 11 and 12 .
  • the light shielding layer may include at least a light shielding structure located in at least one sub-pixel.
  • all shading structures are interconnected integral structures.
  • the shading structures of adjacent sub-pixels in the same row are symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and the shading structures of all sub-pixels in the same column are the same.
  • the light shielding structure in the display substrate provided in Fig. 7 includes: a first light shielding portion 11, a second light shielding portion 12, a third light shielding portion 13 and a fourth light shielding portion 14.
  • the first light shielding portion 11, the second light shielding portion 12, the third light shielding portion 13 and the fourth light shielding portion 14 are an integrated structure connected to each other.
  • the second light shielding portion 12 and the third light shielding portion 13 are arranged along the second direction D2, and the third light shielding portion 13 and the fourth light shielding portion 14 are arranged along the first direction D1.
  • the second light shielding portion 12 of the sub-pixel may be located on the side of the first light shielding portion 11 close to the previous row of sub-pixels
  • the third light shielding portion 13 and the fourth light shielding portion 14 of the sub-pixel may be located on the side of the first light shielding portion 11 close to the next row of sub-pixels.
  • the fourth light shielding portion 14 of the sub-pixel may be located on the side of the third light shielding portion 13 close to the next column of sub-pixels or on the side of the third light shielding portion 13 close to the previous column of sub-pixels.
  • the first light shielding portion 11 may include a light shielding main body portion 11A and a light shielding connecting portion 11B.
  • the light shielding main body portion 11A and the light shielding connecting portion 11B are an integral structure connected to each other.
  • the light shielding main body portion 11A and the light shielding connecting portion 11B are arranged along the first direction, and the light shielding main body portion 11A of the sub-pixel is located on the side of the light shielding connecting portion 11B close to the next column of sub-pixels or the side of the light shielding connecting portion 11B close to the previous column of sub-pixels.
  • the fourth light shielding portion 14 may be located on the side of the third light shielding portion 13 close to the next column of sub-pixels
  • the light shielding main body portion 11A is located on the side of the light shielding connecting portion 11B close to the next column of sub-pixels.
  • the fourth light shielding portion 14 may be located on a side of the third light shielding portion 13 close to the sub-pixels in the previous column
  • the light shielding main body portion 11A is located on a side of the light shielding connecting portion 11B close to the sub-pixels in the previous column.
  • the light shielding main body portion 11A may be rectangular in shape, and the corners of the rectangle may be chamfered.
  • the light shielding connection portion 11B may be strip-shaped extending along the first direction D1.
  • the second light shielding portion 12 , the third light shielding portion 13 , and the fourth light shielding portion 14 may be in the shape of strips extending along the second direction D2 .
  • the second light shielding portion of the sub-pixel is connected to the third light shielding portion of the sub-pixel located in the same column and the upper row
  • the third light shielding portion of the sub-pixel is connected to the second light shielding portion of the sub-pixel located in the same column and the lower row.
  • the light shielding connection portion of the first light shielding portion of the sub-pixel is connected to the light shielding connection portion of the first light shielding portion of one of the adjacent sub-pixels located in the same row
  • the fourth light shielding portion of the sub-pixel is connected to the fourth light shielding portion of another adjacent sub-pixel located in the same row.
  • the light shielding structure of the display substrate provided in Fig. 8 may include: a light shielding portion 20, a first light shielding connection portion 21, a second light shielding connection portion 22, a third light shielding connection portion 23, and a fourth light shielding connection portion 24.
  • the light shielding portion 20, the first light shielding connection portion 21, the second light shielding connection portion 22, the third light shielding connection portion 23, and the fourth light shielding connection portion 24 are an integrated structure connected to each other.
  • the first light shielding connection portion 21 and the second light shielding connection portion 22 are arranged along the second direction D2.
  • the first light shielding connection portion 21 of the sub-pixel may be located on the side of the light shielding portion 20 close to the previous row of sub-pixels
  • the second light shielding connection portion 22 of the sub-pixel may be located on the side of the light shielding portion 20 close to the next row of sub-pixels.
  • the third light shielding connection portion 23 and the fourth light shielding connection portion 24 of the sub-pixel are on different sides of the light shielding portion 20.
  • the fourth light shielding connection portion 24 of the sub-pixel may be located on the side of the light shielding portion 20 close to the next column of sub-pixels.
  • the fourth light shielding connection portion 24 of the sub-pixel may be located on the side of the light shielding portion 20 close to the previous column of sub-pixels.
  • the shape of the light shielding portion 20 may be a rectangular shape, and the corners of the rectangular shape may be chamfered.
  • the second light shielding connection portion 22 of the first light shielding connection portion 21 may be in the shape of a strip extending along the second direction D2.
  • the third light shielding connection portion 23 and the fourth light shielding connection portion 24 may be in the shape of a strip extending along the first direction D1.
  • the first light-shielding connection portion of the sub-pixel is interconnected with the second light-shielding connection portion of the sub-pixel located in the same column and the upper row
  • the second light-shielding connection portion of the sub-pixel is interconnected with the first light-shielding connection portion of the sub-pixel located in the same column and the lower row.
  • the third light-shielding connection portion of the sub-pixel is interconnected with the third light-shielding connection portion of one of the adjacent sub-pixels located in the same row
  • the fourth light-shielding connection portion of the sub-pixel is interconnected with the fourth light-shielding connection portion of another adjacent sub-pixel located in the same row.
  • forming the first semiconductor layer pattern may include: sequentially depositing a second insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process, and forming a second insulating layer covering the light shielding layer and a first semiconductor layer pattern located on the second insulating layer, as shown in FIGS. 13 to 15 , wherein FIG. 13 is a schematic diagram of the first semiconductor layer pattern of the display substrate provided in FIGS. 7 and 8 , FIG. 14 is a schematic diagram of the display substrate provided in FIG. 7 after the first semiconductor layer pattern is formed, and FIG. 15 is a schematic diagram of the display substrate provided in FIG. 8 after the first semiconductor layer pattern is formed.
  • the first semiconductor layer pattern may include at least an active layer T21 of a second transistor located at at least one sub-pixel, an active layer T31 of a third transistor, an active layer T61 of a sixth transistor, and an active layer T71 of a seventh transistor.
  • the orthographic projection of the first light shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer T61 of the sixth transistor on the substrate.
  • the orthographic projection of the second light shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer T71 of the seventh transistor on the substrate.
  • the orthographic projection of the third light shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer T31 of the third transistor on the substrate.
  • the orthographic projection of the fourth light shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer T21 of the second transistor on the substrate.
  • the orthographic projection of the light shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer T61 of the sixth transistor on the substrate.
  • the orthographic projections of the first light shielding connection portion, the second light shielding connection portion, the third light shielding connection portion, and the fourth light shielding connection portion on the substrate do not overlap with the orthographic projections of any one of the active layer T21 of the second transistor, the active layer T31 of the third transistor, and the active layer T71 of the seventh transistor on the substrate.
  • any one of the active layers T21 of the second transistor, T31 of the third transistor, T61 of the sixth transistor, and T71 of the seventh transistor of adjacent sub-pixels located in the same row is symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and any one of the active layers T21 of the second transistor, T31 of the third transistor, T61 of the sixth transistor, and T71 of the seventh transistor of all sub-pixels located in the same column is the same.
  • the active layer T21 of the second transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor may be an integrated structure connected to each other.
  • the active layer T31 of the third transistor may be provided separately.
  • the active layer T31 of the third transistor of the subpixel is interconnected with the active layer T31 of the third transistor of one of the adjacent subpixels located in the same row
  • the active layer T71 of the seventh transistor of the subpixel is interconnected with the active layer T71 of the seventh transistor of one of the adjacent subpixels located in the same row
  • the active layer T21 of the second transistor of the subpixel is interconnected with the active layer T21 of the second transistor of another adjacent subpixel located in the same row.
  • the active layer T31 of the third transistor and the active layer T71 of the seventh transistor are arranged along the second direction D2.
  • the active layer T21 of the second transistor and the active layer T71 of the seventh transistor may be located on the same side of the active layer T61 of the sixth transistor of the sub-pixel, and the active layer T61 of the sixth transistor may be located on the other side of the active layer T61 of the sixth transistor of the sub-pixel.
  • the active layer T71 of the seventh transistor may be located on a side of the active layer T61 of the sixth transistor of the sub-pixel close to the previous row of sub-pixels, and the active layer T21 of the second transistor and the active layer T31 of the third transistor may be located on a side of the active layer T61 of the sixth transistor of the sub-pixel close to the next row of sub-pixels.
  • the active layers T21, T31 and T71 of the second, third and seventh transistors may be in an "I" shape, and the active layer T61 of the sixth transistor may be in an " ⁇ " shape.
  • the active layer of the transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region T21-2 of the active layer T21 of the second transistor may serve as the second region T61-2 of the active layer T61 of the sixth transistor
  • the first region T61-1 of the active layer T61 of the sixth transistor may serve as the second region T71-2 of the active layer T71 of the seventh transistor.
  • the first region T31-1 and the second region T31-2 of the active layer T31 of the third transistor and the first region T71-1 of the active layer T71 of the seventh transistor may be separately provided.
  • the first region T71-1 of the active layer T71 of the seventh transistor of the sub-pixel is the same region as the first region T71-1 of the active layer T71 of the seventh transistor of one of the adjacent sub-pixels located in the same row, and the first region T21-1 of the active layer T21 of the second transistor of the sub-pixel is the same region as the first region T21-1 of the active layer T21 of the second transistor of another adjacent sub-pixel located in the same row.
  • forming the first conductive layer pattern may include: depositing a third insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, and forming a third insulating layer covering the first semiconductor layer pattern and a first conductive layer pattern located on the third insulating layer, as shown in FIGS. 16 to 18, wherein FIG. 16 is a schematic diagram of the first conductive layer pattern of the display substrate provided in FIGS. 7 and 8, FIG. 17 is a schematic diagram of the display substrate provided in FIG. 7 after the first conductive layer pattern is formed, and FIG. 18 is a schematic diagram of the display substrate provided in FIG. 8 after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (Gate1) layer.
  • the first conductive layer pattern may include at least: a first plate C11 of a first capacitor located in at least one sub-pixel, a first plate C21 of a second capacitor, a gate electrode T22 of a second transistor, a gate electrode T32 of a third transistor, a control electrode T62 of a sixth transistor, and a gate electrode T72 of a seventh transistor, and a light emitting signal line EM, a second scanning signal line Gate2, and a third scanning signal line Gate3 extending at least partially along the first direction D1.
  • any one of the first plates of the first capacitor and the first plates of the second capacitor of adjacent sub-pixels located in the same row is symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and any one of the first plates of the first capacitor and the first plates of the second capacitor of all sub-pixels located in the same column is the same.
  • the first plate C11 of the first capacitor and the first plate C21 of the second capacitor of the sub-pixel are arranged along the second direction D2, and the first plate C21 of the second capacitor of the sub-pixel may be located on a side of the first plate C11 of the first capacitor close to the sub-pixel of the previous row.
  • the shape of the first plate C11 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered, and the orthographic projection of the first plate C11 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate.
  • the shape of the first electrode plate C21 of the second capacitor may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate C21 of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate.
  • the first electrode plate C21 of the second capacitor may also serve as the control electrode T62 of the sixth transistor.
  • the area of the first plate C21 of the second capacitor may be greater than the area of the first plate C11 of the first capacitor.
  • the shape of the second scan signal line Gate2 may be a linear shape extending along the first direction D1
  • the second scan signal line Gate2 connected to the sub-pixel may be located on a side where the first electrode plate C11 of the first capacitor of the sub-pixel is away from the first electrode plate C21 of the second capacitor of the sub-pixel (also the gate electrode T62 of the sixth transistor).
  • the area where the second scan signal line Gate2 overlaps with the active layer of the second transistor serves as the gate electrode T22 of the second transistor.
  • the shape of the third scan signal line Gate3 may be a linear shape extending along the first direction D1, and the third scan signal line Gate3 connected to the subpixel may be located on a side of the second scan signal line Gate2 connected to the subpixel away from the first electrode plate C11 of the first capacitor of the subpixel.
  • the area where the third scan signal line Gate3 overlaps with the active layer of the third transistor serves as the gate electrode T32 of the third transistor.
  • the shape of the light emitting signal line EM may be a linear shape extending along the first direction D1.
  • the light emitting signal line EM connected to the sub-pixel may be located on a side of the first electrode plate C21 of the second capacitor of the sub-pixel (also the gate electrode T62 of the sixth transistor) away from the first electrode plate C11 of the first capacitor of the sub-pixel.
  • the area where the light emitting signal line EM overlaps with the active layer of the seventh transistor serves as the gate electrode T72 of the seventh transistor.
  • the second scan signal line Gate2, the third scan signal line Gate3, and the light emitting signal line EM may be designed with equal width or unequal width, and may be a straight line or a broken line, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between signal lines, which is not limited in the present disclosure.
  • the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer, and the first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the second transistor, the third transistor, the sixth transistor and the seventh transistor T7, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of any one of the active layers of the first transistor, the second transistor, the sixth transistor and the seventh transistor are both conductorized.
  • the gate electrode T22 of the second transistor is arranged across the active layer of the second transistor
  • the gate electrode T32 of the third transistor is arranged across the active layer of the third transistor
  • the gate electrode T62 of the sixth transistor is arranged across the active layer of the sixth transistor
  • the gate electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor, that is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active layer.
  • FIGS. 19 to 21 wherein FIG. 19 is a schematic diagram of the second conductive layer pattern of the display substrate provided in FIGS. 7 and 8, FIG. 20 is a schematic diagram of the display substrate provided in FIG. 7 after the second conductive layer pattern is formed, and FIG. 21 is a schematic diagram of the display substrate provided in FIG. 8 after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer may include at least: a second plate C12 of a first capacitor and a second plate C22 of a second capacitor located at at least one sub-pixel, and a first sub-signal line Gate1A of a first scan signal line extending at least partially along the first direction D1 and a third sub-signal line Gate4A of a fourth scan signal line.
  • any one of the second plates C12 of the first capacitor and the second plates C22 of the second capacitor of adjacent sub-pixels located in the same row is symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and any one of the second plates C12 of the first capacitor and the second plates C22 of the second capacitor of all sub-pixels located in the same column is the same.
  • the second electrode plate C12 of the first capacitor and the second electrode plate C22 of the second capacitor may be an integral structure connected to each other.
  • the outline of the second electrode plate C12 of the first capacitor (also the second electrode plate C22 of the second capacitor) may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the second electrode plate C12 of the first capacitor (also the second electrode plate C22 of the second capacitor) on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor and the first electrode plate of the second capacitor on the substrate.
  • the second plate C12 of the first capacitor (the second plate C22 of the second capacitor) is provided with a first via hole V1 and a second via hole V2, and the shape of the first via hole V1 and the second via hole V2 may be rectangular and located in the middle of the second plate C12 of the first capacitor (the second plate C22 of the second capacitor).
  • the first via hole V1 exposes the fourth insulating layer covering the first plate of the first capacitor
  • the orthographic projection of the first plate of the first capacitor on the substrate includes the orthographic projection of the first via hole on the substrate.
  • the first via hole V1 exposes the first plate of the first capacitor, so that the first connection electrode formed subsequently is connected to the first plate of the first capacitor.
  • the second via hole V2 exposes the fourth insulating layer covering the first plate of the second capacitor, and the orthographic projection of the first plate of the second capacitor on the substrate includes the orthographic projection of the second via hole on the substrate.
  • the second via hole V2 exposes the first plate of the second capacitor, so that the second electrode of the first transistor formed subsequently is connected to the first plate of the second capacitor.
  • the shape of the first sub-signal line Gate1A of the first scan signal line may be a line shape extending at least partially along the first direction D1, and the first scan signal line connected to the sub-pixel
  • the first sub-signal line Gate1A can be located on the side of the second plate C12 of the first capacitor of the sub-pixel (the second plate C22 of the second capacitor) close to the previous sub-pixel, and the area overlapping with the active layer of the first transistor of the subsequently formed sub-pixel serves as the first gate electrode T12A of the first transistor, and the area overlapping with the active layer of the fourth transistor of the subsequently formed sub-pixel serves as the first gate electrode T42A of the fourth transistor.
  • the positive projection of the first sub-signal line Gate1A of the first scanning signal line connected to the sub-pixel on the substrate can be located between the positive projection of the light-emitting signal line connected to the sub-pixel on the substrate and the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.
  • the shape of the third sub-signal line Gate4A of the fourth scan signal line can be a line shape extending at least partially along the first direction D1
  • the third sub-signal line Gate4A of the fourth scan signal line connected to the sub-pixel can be located on the side of the first sub-signal line Gate1A of the first scan signal line connected to the sub-pixel away from the second electrode C12 of the first capacitor of the sub-pixel (the second electrode C22 of the second capacitor), and the area overlapping with the active layer of the fifth transistor of the sub-pixel formed subsequently serves as the first gate electrode T52A of the fifth transistor.
  • the positive projection of the third sub-signal line Gate4A of the fourth scanning signal line connected to the sub-pixel on the substrate can be located on a side of the positive projection of the light-emitting signal line connected to the sub-pixel on the substrate away from the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.
  • the first sub-signal line Gate1A of the first scanning signal line and the third sub-signal line Gate4A of the fourth scanning signal line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • FIGS. 22 to 24 wherein FIG. 22 is a schematic diagram of the second semiconductor layer pattern of the display substrate provided in FIGS. 7 and 8, FIG. 23 is a schematic diagram of the display substrate provided in FIG. 7 after the second semiconductor layer pattern is formed, and FIG. 24 is a schematic diagram of the display substrate provided in FIG. 8 after the second semiconductor layer pattern is formed.
  • the second semiconductor layer may include at least an active layer T11 of a first transistor, an active layer T41 of a fourth transistor, and an active layer T51 of a fifth transistor located in at least one sub-pixel.
  • the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor are an integral structure connected to each other.
  • the active layer T11 of the first transistor is provided separately.
  • any one of the active layers T11 of the first transistor, T41 of the fourth transistor, and T51 of the fifth transistor of adjacent sub-pixels located in the same row is symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and any one of the active layers T11 of the first transistor, T41 of the fourth transistor, and T51 of the fifth transistor of all sub-pixels located in the same column is the same.
  • the active layer T11 of the first transistor of the sub-pixel may be located on a side of the active layer T41 of the fourth transistor close to the previous row of sub-pixels or close to the next row of sub-pixels.
  • the active layer T51 of the fifth transistor of the sub-pixel may be located on a side of the active layer T41 of the fourth transistor of the sub-pixel close to the previous row of sub-pixels.
  • the active layer T11 of the first transistor and the active layer T51 of the fifth transistor may have an "I" shape
  • the active layer T41 of the fourth transistor may have an "L” shape that is horizontally flipped.
  • the positive projection of the active layer T11 of the first transistor of the sub-pixel on the substrate at least partially overlaps with the positive projection of the first sub-signal line Gate1A of the first scanning signal line connected to the sub-pixel, the light-emitting signal line connected to the sub-pixel, and the second plate of the first capacitor of the sub-pixel (also the second plate of the second capacitor) on the substrate.
  • the positive projection of the active layer T11 of the first transistor of the sub-pixel on the substrate at least partially overlaps with the positive projection of the first sub-signal line Gate1A of the first scanning signal line connected to the sub-pixel and the light emitting signal line connected to the sub-pixel on the substrate.
  • an orthographic projection of the active layer T51 of the fifth transistor of the sub-pixel on the substrate overlaps an orthographic projection of the third sub-signal line Gate4A of the fourth scan signal line connected to the sub-pixel on the substrate.
  • the active layer of each transistor located in the second conductive layer may include a first region, a second region, and a channel region located between the first region and the second region.
  • the first region T41-1 of the active layer of the fourth transistor may simultaneously serve as the second region T51-2 of the active layer of the fifth transistor.
  • the first region T11-1 and the second region T11-2 of the active layer T11 of the first transistor, the second region T41-2 of the active layer of the fourth transistor, and the first region T51-1 of the active layer of the fifth transistor may be separately provided.
  • the active layer T11 of the first transistor is disposed across the first gate electrode of the first transistor
  • the active layer T41 of the fourth transistor is disposed across the first gate electrode of the fourth transistor
  • the active layer T51 of the fifth transistor is disposed across the first gate electrode of the fifth transistor.
  • FIGS. 25 to 27 wherein FIG. 25 is a schematic diagram of the third conductive layer pattern of the display substrate provided in FIGS. 7 and 8, FIG. 26 is a schematic diagram of the display substrate provided in FIG. 7 after the third conductive layer pattern is formed, and FIG. 27 is a schematic diagram of the display substrate provided in FIG. 8 after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layer may include at least: a second sub-signal line Gate1B of the first scan signal line extending at least partially along the first direction D1, a fourth sub-signal line Gate4B of the fourth scan signal line, a power connection line VCL, a first initial signal line INIT1, a second initial signal line INIT2 and a third initial signal line INIT3.
  • the second sub-signal line Gate1B of the first scan signal line may be in the shape of a line extending along the first direction D1.
  • the orthographic projection of the second sub-signal line Gate1B of the first scan signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-signal line of the first scan signal line on the substrate, and is electrically connected to the first sub-signal line of the first scan signal line.
  • the area where the second sub-signal line Gate1B of the first scan signal line connected to the subpixel overlaps with the active layer of the second transistor of the subpixel serves as the second gate electrode T22B of the second transistor, and the area where the second sub-signal line Gate1B of the first scan signal line connected to the subpixel overlaps with the active layer of the fourth transistor of the subpixel serves as the second gate electrode T42B of the fourth transistor.
  • the first gate electrode and the second gate electrode of the first transistor constitute the gate electrode of the first transistor.
  • the first gate electrode and the second gate electrode of the fourth transistor constitute the gate electrode of the fourth transistor.
  • the positive projection of the second sub-signal line Gate1B of the first scanning signal line connected to the sub-pixel on the substrate can be located between the positive projection of the light-emitting signal line connected to the sub-pixel on the substrate and the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.
  • the fourth sub-signal line Gate4B of the fourth scan signal line may be in a line shape extending along the first direction D1.
  • the orthographic projection of the fourth sub-signal line Gate4B of the fourth scan signal line on the substrate at least partially overlaps with the orthographic projection of the third sub-signal line of the fourth scan signal line on the substrate, and overlaps with the fourth sub-signal line Gate4B of the fourth scan signal line.
  • the third sub-signal line of the scanning signal line is electrically connected.
  • the area where the fourth sub-signal line Gate4B of the fourth scanning signal line connected to the subpixel overlaps with the active layer of the fifth transistor of the subpixel serves as the second gate electrode T52B of the fifth transistor.
  • the first gate electrode and the second gate electrode of the fifth transistor constitute the gate electrode of the fifth transistor.
  • the positive projection of the fourth sub-signal line Gate4B of the fourth scanning signal line connected to the sub-pixel on the substrate can be located on a side of the positive projection of the light-emitting signal line connected to the sub-pixel on the substrate away from the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.
  • the power connection line VCL may be in the shape of a line whose main portion extends along the first direction D1.
  • the power connection line VCL connected to the subpixel may be located on a side of the second sub-signal line Gate1B of the first scan signal line connected to the subpixel away from the fourth sub-signal line Gate4B of the fourth scan signal line connected to the subpixel.
  • the orthographic projection of the power connection line VCL on the substrate overlaps at least partially with the orthographic projection of the second plate of the first capacitor (also the second plate of the second capacitor) on the substrate.
  • the positive projection of the power connection line VCL connected to the sub-pixel on the substrate can be located between the positive projection of the first sub-signal line of the first scan signal line connected to the sub-pixel on the substrate and the projection of the second scan signal line connected to the sub-pixel on the substrate.
  • the power connection line VCL may include: a signal main line 30, a first protrusion 31, a second protrusion 32, and a third protrusion 33.
  • the signal main line 30, the first protrusion 31, the second protrusion 32, and the third protrusion 33 may be an integral structure connected to each other.
  • the first protrusion 31 may be located on a side of the signal main line 30 close to the second sub-signal line Gate1B of the first scan signal line
  • the second protrusion 32 and the third protrusion 33 may be located on a side of the signal main line 30 away from the second sub-signal line Gate1B of the first scan signal line
  • the second protrusion 32 and the third protrusion 33 are arranged along the first direction D1.
  • the signal main line 30 may be in a line shape extending in the first direction D1.
  • the first convex portion 31, the second convex portion 32, and the third convex portion 33 may be in a rectangular shape.
  • the orthographic projections of the second protrusion 32 and the third protrusion 33 on the substrate at least partially overlap with the orthographic projections of the second plate of the first capacitor (also the second plate of the second capacitor) on the substrate.
  • the first initial signal line INIT1 and the second initial signal line INIT2 are the same signal line, and may be in the shape of a line whose main portion extends along the first direction D1.
  • the first initial signal line INIT1 (also the second initial signal line INIT2) connected to the sub-pixel is located on a side of the power connection line VCL connected to the sub-pixel away from the second sub-signal line Gate1B of the first scanning signal line.
  • the orthographic projection of the first initial signal line INIT1 (also the second initial signal line INIT2) on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line on the substrate.
  • the positive projection of the first initial signal line INIT1 (also the second initial signal line INIT2) connected to the sub-pixel on the substrate is located between the positive projection of the first plate of the first capacitor of the sub-pixel on the substrate and the positive projection of the third scanning signal line connected to the sub-pixel on the substrate.
  • the third initial signal line INIT3 may be in the shape of a line whose main portion extends along the first direction D1.
  • the third initial signal line INIT3 is located on a side of the first initial signal line INIT1 (also the second initial signal line INIT2) away from the power connection line VCL.
  • the positive projection of the third initial signal line INIT3 connected to the subpixel on the substrate at least partially overlaps with the positive projection of the third scanning signal line connected to the subpixel on the substrate.
  • the positive projection of the third initial signal line INIT3 connected to the sub-pixel on the substrate is located on a side of the positive projection of the second scanning signal line connected to the sub-pixel on the substrate away from the positive projection of the first plate of the first capacitor connected to the sub-pixel on the substrate.
  • the fourth sub-signal line Gate4B, the power connection line VCL, the first initial signal line INIT1, the second initial signal line INIT2 and the third initial signal line INIT3 can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the third conductive layer can be used as a shield to perform conductorization on the second semiconductor layer.
  • the second semiconductor layer in the area shielded by the third conductive layer forms the channel region of the active layer of the first transistor, the fourth transistor and the fifth transistor, and the second semiconductor layer in the area not shielded by the third conductive layer is conductorized, that is, the first area and the second area of the active layer of the first transistor, the fourth transistor and the fifth transistor are both conductorized.
  • Forming a seventh insulating layer pattern may include: depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, patterning the seventh insulating film using a patterning process to form a seventh insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the seventh insulating layer, as shown in FIGS. 28 and 29 , where FIG. 28 is a schematic diagram of the display substrate provided in FIG. 7 after the seventh insulating layer pattern is formed, and FIG. 29 is a schematic diagram of the display substrate provided in FIG. 8 after the seventh insulating layer pattern is formed.
  • the plurality of via holes of the seventh insulating layer may include at least third to nineteenth via holes V3 to V19 located in at least one sub-pixel.
  • the third via of the subpixel is the same via as the third via of one of the adjacent subpixels located in the same row
  • the fifth via of the subpixel is the same via as the fifth via of another adjacent subpixel located in the same row
  • the seventh via of the subpixel is the same via as the seventh via of another adjacent subpixel located in the same row.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the second transistor on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the active layer of the second transistor, and the third via hole V3 is configured to connect the first electrode (also the initial connection line ICL) of the subsequently formed second transistor to the first area of the active layer of the second transistor through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the second transistor (also the second area of the active layer of the sixth transistor) on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of the active layer of the second transistor (also the second area of the active layer of the sixth transistor), and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the sixth transistor) to the second area of the active layer of the second transistor (also the second area of the active layer of the sixth transistor) through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the third transistor on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of the active layer of the third transistor, and the fifth via hole V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of the active layer of the third transistor through the via hole.
  • the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the third transistor on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the sixth via V6 are etched away to expose the surface of the second area of the active layer of the third transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed third transistor (which is also the second electrode of the fourth transistor, the first electrode of the sixth transistor and the second electrode of the seventh transistor) to the second area of the active layer of the third transistor through the via.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the seventh transistor on the substrate, and the third insulating layer, The fourth insulating layer, the fifth insulating layer and the sixth insulating layer are etched away to expose the surface of the first area of the active layer of the seventh transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed seventh transistor to the first area of the active layer of the seventh transistor through the via.
  • the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the seventh transistor (also the first area of the sixth transistor) on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the eighth via V8 are etched away to expose the surface of the second area of the active layer of the seventh transistor (also the first area of the sixth transistor), and the eighth via V8 is configured to connect the second electrode of the subsequently formed third transistor (also the second electrode of the fourth transistor, the first electrode of the sixth transistor and the second electrode of the seventh transistor) to the second area of the active layer of the seventh transistor (also the first area of the sixth transistor) through the via.
  • the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the first via on the substrate, the fifth insulating layer and the sixth insulating layer in the ninth via V9 are etched away to expose the surface of the first electrode plate of the first capacitor, and the ninth via V9 is configured to connect a subsequently formed first connecting electrode to the first electrode plate of the first capacitor through the via.
  • the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the second via on the substrate, the fifth insulating layer and the sixth insulating layer in the tenth via V10 are etched away to expose the surface of the first electrode of the second capacitor (also the gate electrode of the sixth transistor), and the tenth via V10 is configured to connect the second electrode of the subsequently formed first transistor to the first electrode of the second capacitor (also the gate electrode of the sixth transistor) through the via.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor (also the second plate of the second capacitor) on the substrate, the fifth insulating layer and the sixth insulating layer in the eleventh via hole V11 are etched away, the eleventh via hole V11 exposes the surface of the second plate of the first capacitor (also the second plate of the second capacitor), and the eleventh via hole V11 is configured to connect the first electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second plate of the first capacitor (also the second plate of the second capacitor) through the via hole.
  • the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the first transistor on the substrate, the sixth insulating layer in the twelfth via V12 is etched away to expose the surface of the first area of the active layer of the first transistor, and the twelfth via V12 is configured to connect the first electrode of the subsequently formed first transistor to the first area of the active layer of the first transistor through the via.
  • the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor on the substrate, the sixth insulating layer in the thirteenth via V13 is etched away to expose the surface of the second region of the active layer of the first transistor, and the thirteenth via V13 is configured to connect the second electrode of the subsequently formed first transistor to the second region of the active layer of the first transistor through the via.
  • the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor) on the substrate, the sixth insulating layer in the fourteenth via V14 is etched away to expose the surface of the first area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor), and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the first area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor) through the via.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the fourth transistor on the substrate, the sixth insulating layer in the fifteenth via hole V15 is etched away, the surface of the second region of the active layer of the fourth transistor is exposed, and the fifteenth via hole V15 is It is configured so that the second electrode of the subsequently formed third transistor (also the second electrode of the fourth transistor, the first electrode of the sixth transistor and the second electrode of the seventh transistor) is connected to the second region of the active layer of the fourth transistor through the via hole.
  • the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fifth transistor on the substrate, the sixth insulating layer in the sixteenth via V16 is etched away, the fifteenth via V15 exposes the surface of the first area of the active layer of the fifth transistor, and the sixteenth via V16 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of the active layer of the fifth transistor through the via.
  • the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the power connection line on the substrate, exposing the surface of the power connection line, and the seventeenth via hole V17 is configured to connect the subsequently formed first connection electrode to the power connection line through the via hole.
  • the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the first initial signal line (also the second initial signal line) on the substrate, exposing the surface of the first initial signal line (also the second initial signal line), and the eighteenth via V18 is configured to connect the first electrode (also the initial connection line ICL) of the subsequently formed second transistor to the first initial signal line (also the second initial signal line) through the via.
  • the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the third initial signal line on the substrate, exposing the surface of the third initial signal line, and the nineteenth via V19 is configured to connect the first electrode of the subsequently formed third transistor to the third initial signal line through the via.
  • a virtual straight line extending in the second direction D2 may pass through the third via hole V3 and the eighteenth via hole V18 .
  • a virtual straight line extending in the second direction D2 may pass through the fifth via hole V5 and the nineteenth via hole V19 .
  • a virtual straight line extending in the second direction D2 may pass through the eighth via hole V8 and the fifteenth via hole V15 .
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer pattern disposed on the seventh insulating layer, as shown in FIGS. 30 to 32, as shown in FIGS. 30 to 32, FIG. 30 is a schematic diagram of the fourth conductive layer pattern of the display substrate provided in FIGS. 7 and 8
  • FIG. 31 is a schematic diagram of the display substrate provided in FIG. 7 after the fourth conductive layer pattern is formed
  • FIG. 32 is a schematic diagram of the display substrate provided in FIG. 8 after the fourth conductive layer pattern is formed.
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the fourth conductive layer pattern may at least include: an initial connection line ICL extending at least partially along the second direction D2, and a first electrode T13 and a second electrode T14 of a first transistor, a first electrode T23 and a second electrode T24 of a second transistor, a first electrode T33 and a second electrode T34 of a third transistor, a first electrode T43 and a second electrode T44 of a fourth transistor, a first electrode T53 and a second electrode T54 of a fifth transistor, a first electrode T63 and a second electrode T64 of a sixth transistor, a first electrode T73 and a second electrode T74 of a seventh transistor, and a first connection electrode VL1.
  • any one of the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the first electrode T33 and the second electrode T34 of the third transistor, the first electrode T43 and the second electrode T44 of the fourth transistor, the first electrode T53 and the second electrode T54 of the fifth transistor, the first electrode T63 and the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, and the first connection electrode VL1 of adjacent sub-pixels located in the same row are symmetrically arranged with respect to a virtual straight line extending along the second direction D2.
  • the initial connection line ICL is located between two adjacent columns of sub-pixels whose active layers of the second transistors are connected to each other, and is electrically connected to the two adjacent columns of sub-pixels respectively.
  • the initial connection line ICL coincides with the symmetry axes of the two adjacent columns of sub-pixels.
  • the shape of the initial connection line ICL may be a line shape extending along the second direction D2.
  • the overlapping region of the initial connection line ICL and the first region of the active layer of the second transistor may also serve as the first electrode T23 of the second transistor.
  • the initial connection line ICL (also the first electrode T23 of the second transistor) is connected to the first region of the active layer of the second transistor through the third via hole, and is connected to the first initial signal line (also the second initial signal line) through the eighteenth via hole.
  • the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the first electrode T33 and the second electrode T34 of the third transistor, the first electrode T43 and the second electrode T44 of the fourth transistor, the first electrode T53 and the second electrode T54 of the fifth transistor, the first electrode T63 and the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, and the first connection electrode VL1 of at least one subpixel may be located on the same side of the initial connection line ICL.
  • the first electrode T13 of the first transistor and the initial connection line ICL are an integral structure connected to each other.
  • the shape of the first electrode T13 of the first transistor may be a line shape extending along the first direction D1.
  • the first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through the twelfth via hole V12.
  • the second electrode T14 of the first transistor is separately provided.
  • the shape of the second electrode T14 of the first transistor can be block-shaped.
  • the second electrode T14 of the first transistor is connected to the second region of the active layer of the first transistor through the thirteenth via hole, and is connected to the first electrode plate of the second capacitor (also the gate electrode of the sixth transistor) through the tenth via hole.
  • the second electrode T24 of the second transistor and the second electrode T64 of the sixth transistor may be an integrated structure connected to each other.
  • the second electrode T24 of the second transistor (also the second electrode T64 of the sixth transistor) may be in the shape of a dumbbell.
  • the second electrode T24 of the second transistor (also the second electrode T64 of the sixth transistor) may be connected to the second region of the active layer of the second transistor (also the second region of the active layer of the sixth transistor) through a fourth via.
  • the first electrode T33 of the third transistor is separately provided.
  • the shape of the first electrode T33 of the third transistor may be a block.
  • the first electrode T33 of the third transistor is connected to the first region of the active layer of the third transistor through the fifth via hole, and is connected to the third initial signal line through the nineteenth via hole.
  • the second pole T34 of the third transistor, the second pole T44 of the fourth transistor, the first pole T63 of the sixth transistor, and the second pole T74 of the seventh transistor may be an integrated structure connected to each other.
  • the shape of the second pole T34 of the third transistor (also the second pole T44 of the fourth transistor, the first pole T63 of the sixth transistor, and the second pole T74 of the seventh transistor) may be a dumbbell extending along the second direction D2.
  • the second pole T34 of the third transistor (also the second pole T44 of the fourth transistor, the first pole T63 of the sixth transistor, and the second pole T74 of the seventh transistor) is connected to the second region of the active layer of the third transistor through the sixth via hole, connected to the second region of the active layer of the seventh transistor (also the first region of the sixth transistor) through the eighth via hole, and connected to the second region of the active layer of the fourth transistor through the fifteenth via hole.
  • the first electrode T43 of the fourth transistor and the second electrode T54 of the fifth transistor are integral structures that can be connected to each other.
  • the first electrode T43 of the fourth transistor (also the second electrode T54 of the fifth transistor) can be shaped like a dumbbell with a main body extending along the second direction D2.
  • the first electrode T43 of the fourth transistor (also the second electrode T54 of the fifth transistor) is connected to the second electrode plate of the first capacitor (also the second electrode plate of the second capacitor) through the eleventh via hole, and to the first region of the active layer of the fourth transistor (also the fifth transistor) through the fourteenth via hole.
  • the second region of the active layer of the tube is connected.
  • the first electrode T53 of the fifth transistor is separately provided.
  • the first electrode T53 of the fifth transistor may be in the shape of a strip extending along the first direction D1.
  • the first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the sixteenth via hole.
  • the first electrode T73 of the seventh transistor is separately provided.
  • the shape of the first electrode T73 of the seventh transistor may be a gourd shape.
  • the first electrode T73 of the seventh transistor is connected to the first region of the active layer of the seventh transistor through the seventh via hole.
  • the first connection electrode VL1 may be rectangular in shape.
  • the first connection electrode VL1 is connected to the power connection line through the seventeenth via hole, and is connected to the first plate of the first capacitor through the ninth via hole.
  • an orthographic projection of the first connection electrode on the substrate at least partially overlaps with an orthographic projection of the second and third protruding portions of the power connection line on the substrate.
  • forming the first flat layer pattern may include: depositing an eighth insulating film on the substrate on which the aforementioned pattern is formed, patterning the eighth insulating film using a patterning process to form an eighth insulating layer covering the fourth conductive layer, coating a first flat film on the eighth insulating layer, patterning the first flat film using a patterning process to form a first flat layer pattern covering the aforementioned pattern, wherein the first flat layer is provided with a plurality of via patterns, as shown in FIGS. 33 and 34 , wherein FIG. 33 is a schematic diagram of the display substrate provided in FIG. 7 after the eighth insulating layer pattern is formed, and FIG. 34 is a schematic diagram of the display substrate provided in FIG. 8 after the eighth insulating layer pattern is formed.
  • the plurality of via holes of the first planar layer may include at least twentieth to twenty-third via holes V20 to V23 .
  • the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second electrode of the second transistor (also the second electrode of the sixth transistor) on the substrate, the eighth insulating layer in the twentieth via V20 is etched away to expose the surface of the second electrode of the second transistor (also the second electrode of the sixth transistor), and the twentieth via V20 is configured to connect a subsequently formed second connecting electrode to the second electrode of the second transistor (also the second electrode of the sixth transistor) through the via.
  • the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the eighth insulating layer in the twenty-first via V21 is etched away to expose the surface of the first electrode of the fifth transistor, and the twenty-first via V21 is configured to connect a subsequently formed data signal line to the first electrode of the fifth transistor through the via.
  • the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the first electrode of the seventh transistor on the substrate, the eighth insulating layer in the twenty-second via V22 is etched away to expose the surface of the first electrode of the seventh transistor, and the twenty-second via V22 is configured to connect a subsequently formed first power line to the first electrode of the seventh transistor through the via.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the first connecting electrode on the substrate, the eighth insulating layer in the twenty-third via hole V23 is etched away to expose the surface of the first connecting electrode, and the twenty-third via hole V23 is configured to connect a subsequently formed first power line to the first connecting electrode through the via hole.
  • a fifth conductive layer pattern comprising: depositing a fifth conductive film on a substrate formed with the aforementioned pattern, and patterning the fifth conductive film through a patterning process to form a fifth conductive layer pattern, as shown in FIGS. 35 to 37 , wherein FIG. 35 is a schematic diagram of the fifth conductive layer pattern of the display substrate provided in FIGS. 7 and 8 , FIG. 36 is a schematic diagram of the display substrate provided in FIG. 7 after the fifth conductive layer pattern is formed, and FIG. 37 is a schematic diagram of the display substrate provided in FIG. 8 after the fifth conductive layer pattern is formed
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fifth conductive layer may include at least a second connection electrode VL2 located at at least one sub-pixel and a data signal line Data and a first power line VDD extending at least partially along the second direction D2.
  • a plurality of data signal lines Data are arranged along the first direction D1, and a plurality of first power lines VDD are arranged along the first direction D1.
  • adjacent sub-pixels are connected to data signal lines Data symmetrically with respect to a virtual straight line extending along the second direction D2.
  • Adjacent sub-pixels are connected to first power lines VDD symmetrically with respect to a virtual straight line extending along the second direction D2.
  • the data signal line Data and the first power line VDD connected to the sub-pixel are located at different sides of the second connection electrode of the sub-pixel.
  • the first power line VDD is connected to one of the adjacent power lines and is spaced apart from another adjacent power line.
  • Two data signal lines Data are disposed between the two spaced apart first power lines.
  • the orthographic projection of the initial connection line ICL on the substrate is located between the orthographic projections of the data signal lines connected to two adjacent columns of sub-pixels connected to the initial connection line ICL on the substrate, and the orthographic projection of the first power line connected to the sub-pixels on the substrate is located on the side of the data signal line connected to the sub-pixels away from the initial connection line ICL connected to the sub-pixels.
  • the data signal line Data may be in the shape of a line whose main body extends along the second direction D2.
  • the subpixel-connected data signal line Data is connected to the first electrode of the fifth transistor of the subpixel through the twenty-first via hole.
  • the shape of the first power line VDD may be a line shape in which the main body portion extends along the second direction D2.
  • the first power line VDD connected to the sub-pixel is connected to the first electrode of the seventh transistor through the 22nd via hole, and is connected to the first connection electrode through the 23rd via hole.
  • the orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projections of the second plate of the first capacitor (also the second plate of the second capacitor) and the signal main body and the second protrusion of the power connection line on the substrate.
  • the shape of the second connection electrode VL2 may be a line shape or a gourd shape at least partially along the second direction D2.
  • the second connection electrode VL2 is connected to the second electrode of the second transistor (also the second electrode of the sixth transistor) through the twenty-third via hole, and is configured to be connected to the anode of the subsequently formed light-emitting device.
  • the shape of the connection electrode connected to the anode of different light-emitting devices may be different.
  • the width of the first power line VDD may be greater than the width of the data signal line Data.
  • (12) forming a second planar layer pattern comprising: coating a second planar film on the substrate having the aforementioned pattern formed thereon, and patterning the second planar film by a patterning process to form a second planar layer pattern covering the aforementioned pattern.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of pixel drive circuits, and the pixel drive circuits are connected to the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line, the light-emitting signal line, the first initial signal line, the second initial signal line, the third initial signal line, the data signal line and the first power line.
  • the drive circuit layer may be arranged on the substrate.
  • the drive circuit layer may include a first insulating layer, a light shielding layer, a second insulating layer, a first semiconductor layer, a third insulating layer, a first conductive layer, a fourth insulating layer, a second conductive layer, a fifth insulating layer, a second semiconductor layer, a sixth insulating layer, a third conductive layer, a seventh insulating layer, a fourth conductive layer, an eighth insulating layer, a first planar layer, a fifth conductive layer and a second planar layer sequentially arranged on the substrate.
  • the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.
  • the second semiconductor layer may be a metal oxide layer.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, a double layer, or a multilayer.
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, the seventh insulating layer and the eighth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • the first planarization layer and the second planarization layer may employ an organic material such as resin or the like.
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode conductive layer pattern arranged on the second flat layer;
  • a pixel definition film is deposited, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern;
  • an organic light-emitting material is coated, and the organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern;
  • a cathode conductive film is deposited, and the cathode conductive film is patterned by a patterning process to form a cathode conductive layer.
  • the light-emitting structure layer is prepared on the substrate.
  • the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the anode conductive layer includes at least a plurality of anode patterns, wherein the plurality of anode patterns may include an anode of a first light emitting device, an anode of a second light emitting device, an anode of a third light emitting device, and an anode of a fourth light emitting device, wherein the anode of the first light emitting device is located at a red sub-pixel emitting red light, the anode of the second light emitting device may be located at a blue sub-pixel emitting blue light, the anode of the third light emitting device may be located at a first green sub-pixel emitting green light, and the anode of the fourth light emitting device may be located at a second green sub-pixel emitting green light.
  • the plurality of anode patterns may include an anode of a first light emitting device, an anode of a second light emitting device, an anode of a third light emitting device, and an anode of a fourth light
  • the anode of the first light emitting device and the anode of the second light emitting device may be alternately disposed along the first direction D1
  • the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately disposed along the first direction D1.
  • the anode of the first light emitting device and the anode of the second light emitting device may be alternately disposed along the second direction D2
  • the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately disposed along the second direction D2.
  • the shapes and areas of anode electrodes of four sub-pixels in one pixel unit may be the same, or may be different.
  • the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the organic structure layer may include at least: an organic light emitting layer of a light emitting device.
  • the cathode conductive layer may include at least: cathodes of a plurality of light emitting devices.
  • the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.
  • the display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.
  • the embodiment of the present disclosure further provides a driving method of a pixel driving circuit.
  • the pixel driving circuit is set to drive.
  • the driving method of the pixel driving circuit provided by the embodiment of the present disclosure may include the following steps:
  • Step 100 the node control subcircuit drives the signal of the first node through the signal of the first initial signal line, the data signal line and the first power line under the control of the signals of the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line, provides the signal of the second initial signal line to the second node, and provides the signal of the third initial signal line to the third node.
  • Step 200 The light-emitting control subcircuit provides the signal of the first power line to the third node under the control of the signal of the light-emitting signal line, and the driving subcircuit outputs the driving current to the second node under the control of the signals of the first node and the third node.
  • the embodiment of the present disclosure further provides a display device, including: a display substrate.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • AMOLED active-matrix organic light emitting diode
  • the thickness and size of the layer or microstructure are exaggerated. It is understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种像素驱动电路及其驱动方法、显示基板、显示装置，其中，像素驱动电路包括：节点控制子电路、发光控制子电路和驱动子电路；节点控制子电路，被配置为在第一扫描信号线(Gate1)、第二扫描信号线(Gate2)、第三扫描信号线(Gate3)和第四扫描信号线(Gate4)的信号的控制下，通过第一初始信号线(INIT1)、数据信号线(Data)和第一电源线(VDD)的信号带动第一节点(N1)的信号，向第二节点(N2)提供第二初始信号线(INIT2)的信号，向第三节点(N3)提供第三初始信号线(INIT3)的信号；发光控制子电路被配置为在发光信号线(EM)的信号的控制下，向第三节点(N3)提供第一电源线(VDD)的信号；驱动子电路被配置为在第一节点(N1)和第三节点(N3)的信号的控制下，向第二节点(N2)输出驱动电流。

Description

像素驱动电路及其驱动方法、显示基板和显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种像素驱动电路及其驱动方法、显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种像素驱动电路，被配置为驱动发光器件，所述像素驱动电路包括：节点控制子电路、发光控制子电路和驱动子电路；
所述节点控制子电路，分别与第一节点、第二节点、第三节点、第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、第一初始信号线、第二初始信号线、第三初始信号线、数据信号线和第一电源线电连接，被配置为在第一扫描信号线、第二扫描信号线、第三扫描信号线和第四扫描信号线的信号的控制下，通过第一初始信号线、数据信号线和第三节点的信号带动第一节点的信号，向第二节点提供第二初始信号线的信号，向第三节点提供第三初始信号线的信号；
所述发光控制子电路，分别与第一电源线、发光信号线和第三节点电连接，被配置为在发光信号线的信号的控制下，向第三节点提供第一电源线的信号；
所述驱动子电路，分别与第一节点、第二节点和第三节点电连接，被配置为在第一节点和第三节点的信号的控制下，向第二节点输出驱动电流；
所述发光器件，分别与第二节点和第二电源线电连接；
所述节点控制子电路包括：储能子电路，所述储能子电路包括：第一电容和第二电容，第一电容和第二电容包括：第一极板和第二极板；
第一电容的第一极板与第一电源线电连接，第一电容的第二极板与第四节点电连接；
第二电容的第一极板与第一节点电连接，第二电容的第二极板与第四节点电连接。
在示例性实施方式中，所述节点控制子电路还包括：复位子电路、补偿子电路和写入子电路；
所述复位子电路，分别与第一节点、第二节点、第三节点、第一扫描信号线、第二扫描信号线、第三扫描信号线、第一初始信号线、第二初始信号线和第三初始信号线电连接，被配置为在第一扫描信号线的信号的控制下，向第一节点提供第一初始信号线的信号，在第二扫描信号线的信号的控制下，向第二节点提供第二初始信号线的信号，在第三扫描信 号线的信号的控制下，向第三节点提供第三初始信号线的信号；
所述补偿子电路，分别与第三节点、第四节点和第一扫描信号线电连接，被配置为在第一扫描信号线的信号的控制下，向第四节点提供第三节点的信号，以对第四节点的信号进行补偿；
所述写入子电路，分别与第四节点、第四扫描信号线和数据信号线电连接，被配置为在第四扫描信号线的信号的控制下，向第四节点提供数据信号线的信号。
在示例性实施方式中，所述复位子电路包括：第一晶体管、第二晶体管和第三晶体管；
第一晶体管的栅电极与第一扫描信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的栅电极与第二扫描信号线电连接，第二晶体管的第一极与第二初始信号线电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的栅电极与第三扫描信号线电连接，第三晶体管的第一极与第三初始信号线电连接，第二晶体管的第二极与第三节点电连接。
在示例性实施方式中，所述补偿子电路包括：第四晶体管，所述写入晶体管包括：第五晶体管；
第四晶体管的栅电极与第一扫描信号线电连接，第四晶体管的第一极与第四节点电连接，第四晶体管的第二极与第三节点电连接；
第五晶体管的栅电极与第四扫描信号线电连接，第五晶体管的第一极与数据信号线电连接，第五晶体管的第二极与第四节点电连接。
在示例性实施方式中，所述节点控制子电路还包括：第一晶体管至第五晶体管，所述驱动子电路包括：第六晶体管，所述发光控制子电路包括：第七晶体管；
第一晶体管的栅电极与第一扫描信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的栅电极与第二扫描信号线电连接，第二晶体管的第一极与第二初始信号线电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的栅电极与第三扫描信号线电连接，第三晶体管的第一极与第三初始信号线电连接，第二晶体管的第二极与第三节点电连接；
第四晶体管的栅电极与第一扫描信号线电连接，第四晶体管的第一极与第四节点电连接，第四晶体管的第二极与第三节点电连接；
第五晶体管的栅电极与第四扫描信号线电连接，第五晶体管的第一极与数据信号线电连接，第五晶体管的第二极与第四节点电连接；
第六晶体管的栅电极与第一节点电连接，第六晶体管的第一极与第三节点电连接，第六晶体管的第二极与第二节点电连接；
第七晶体管的栅电极与发光信号线电连接，第七晶体管的第一极与第一电源线电连接，第七晶体管的第二极与第三节点电连接。
在示例性实施方式中，第一晶体管、第四晶体管和第五晶体管为氧化物晶体管，且为N型晶体管，第二晶体管、第三晶体管、第六晶体管和第七晶体管为P型晶体管；
第六晶体管的有源层的沟道区的长度大于第一晶体管至第五晶体管和第七晶体管中的任一个晶体管的有源层的沟道区的长度，第六晶体管的有源层的沟道区的宽度大于第一 晶体管至第五晶体管和第七晶体管中的任一个晶体管的有源层的沟道区的宽度，且第六晶体管的有源层的沟道区的宽长比小于第一晶体管至第五晶体管和第七晶体管中的任一个晶体管的有源层的沟道区的宽长比。
在示例性实施方式中，所述第一扫描信号线的信号和所述第二扫描信号线的信号互为反相信号；
所述第三扫描信号线的信号为有效电平信号时，所述第一扫描信号线和是第二扫描信号线的信号为有效电平信号，所述第四扫描信号线和所述发光信号线的信号为无效电平信号；
所述第四扫描信号线的信号为有效电平信号时，所述第一扫描信号线、所述第二扫描信号线、所述第三扫描信号线和所述发光信号线的信号为无效电平信号；
所述发光信号线的信号为有效电平信号时，所述第一扫描信号线、所述第二扫描信号线、所述第三扫描信号线和所述第四扫描信号线的信号为无效电平信号；
所述第一扫描信号线和所述第二扫描信号线中的任一条信号线的信号为有效电平信号的持续时间大于所述第三扫描信号线和所述第四扫描信号线中的任一条信号线的信号为有效电平信号的持续时间。
在示例性实施方式中，所述第一初始信号线的信号和所述第二初始信号线的信号为同一信号，且所述第一初始信号线的信号的电压值小于所述第三初始信号线的信号的电压值；
所述第二初始信号线的信号的电压值大于所述第二电源线的信号的电压值。
第二方面，本公开还提供了一种显示基板，包括：基底以及设置在基底上的多个子像素，至少一个子像素包括：上述像素驱动电路以及像素驱动电路所驱动的发光器件。
在示例性实施方式中，还包括：依次叠设在基底上的驱动电路层和发光结构层，所述驱动电路层包括：多个像素驱动电路、多条发光信号线、多条第一初始信号线、多条第二初始信号线、多条第三初始信号线、多条第一扫描信号线、多条第二扫描信号线、多条第三扫描信号线、多条第四扫描信号线、多条第一电源线和多条数据信号线，所述发光结构层包括：发光器件；
发光信号线、第一初始信号线、第二初始信号线、第三初始信号线、第一扫描信号线、第二扫描信号线、第三扫描信号线和第四扫描信号线中任一信号线至少部分沿第一方向延伸，第一电源线和数据信号线中的任一信号线至少部分沿第二方向延伸，所述第一方向和所述第二方向相交。
在示例性实施方式中，所述驱动电路层还包括：至少部分沿第一方向延伸的多条电源连接线；
至少一条电源连接线，分别与像素驱动电路和至少一条第一电源线连接。
在示例性实施方式中，所述驱动电路层还包括：第一连接电极；
所述第一连接电极，分别与像素驱动电路、电源连接线和第一电源线连接；
所述第一连接电极在基底上的正投影与电源连接线和第一电源线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述第一初始信号线和所述第二初始信号线为同一信号线，所述驱动电路层还包括：至少部分沿第二方向延伸的多条初始连接线；
至少一条初始连接线，分别与像素驱动电路和至少一条第一初始信号线连接；
所述初始连接线在基底上的正投影位于初始连接线连接的相邻两列子像素连接的数据信号线在基底上的正投影之间。
在示例性实施方式中，所述第一扫描信号线包括：相互电连接的第一子信号线和第二子信号线，所述第四扫描信号线包括：相互电连接的第三子信号线和第四子信号线；
所述第一子信号线在基底上的正投影与所述第二子信号线在基底上的正投影至少部分交叠，所述第三子信号线在基底上的正投影与所述第四子信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述像素驱动电路包括：第一晶体管至第七晶体管以及第一电容和第二电容，第一电容和第二电容分别包括：第一极板和第二极板，所述驱动电路层包括在基底上依次设置的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层；
第一半导体层至少包括：位于至少一个子像素的第二晶体管的有源层、第三晶体管的有源层、第六晶体管的有源层和第七晶体管的有源层；
第一导电层至少包括：发光信号线、第二扫描信号线、第三扫描信号线以及位于至少一个子像素的第一电容的第一极板、第二电容的第一极板、第二晶体管的栅电极、第三晶体管的栅电极、第六晶体管的控制极和第七晶体管的栅电极
第二导电层至少包括：第一扫描信号线的第一子信号线、第四扫描信号线的第三子信号线以及位于至少一个子像素的第一电容的第二极板和第二电容的第二极板；
第二半导体层至少包括：位于至少一个子像素的第一晶体管的有源层、第四晶体管的有源层和第五晶体管的有源层。
第三导电层至少包括：第一扫描信号线的第二子信号线、第四扫描信号线的第四子信号线、电源连接线、第一初始信号线、第二初始信号线和第三初始信号线；
第四导电层至少包括：初始连接线以及位于至少一个子像素的第一连接电极和第一晶体管至第七晶体管的第一极和第二极；
第五导电层至少包括：第一电源线和数据信号线。
在示例性实施方式中，所述驱动电路层还包括：设置在所述基底和所述第一半导体层之间的遮光层；
遮光层至少包括：位于至少一个子像素的遮光结构，相邻子像素的遮光结构相互连接；
所述遮光结构在基底上的正投影与第六晶体管的栅电极在基底上的正投影至少部分交叠。
在示例性实施方式中，所述遮光结构包括：第一遮光部、第二遮光部、第三遮光部和第四遮光部；
所述第一遮光部在基底上的正投影与第六晶体管的有源层在基底上的正投影至少部分重叠，所述第二遮光部在基底上的正投影与第七晶体管的有源层在基底上的正投影至少部分重叠，所述第三遮光部在基底上的正投影与第三晶体管的有源层在基底上的正投影至少部分重叠，所述第四遮光部在基底上的正投影与第二晶体管的有源层在基底上的正投影至少部分重叠。
在示例性实施方式中，所述遮光结构包括：遮光部、第一遮光连接部、第二遮光连接部、第三遮光连接部和第四遮光连接部；
所述遮光部在基底上的正投影与第六晶体管的有源层在基底上的正投影至少部分重 叠，所述第一遮光连接部、所述第二遮光连接部、所述第三遮光连接部和所述第四遮光连接部中的任一个在基底上的正投影与第二晶体管的有源层、第三晶体管的有源层和第七晶体管的有源层中的任一个在基底上的正投影不交叠。
在示例性实施方式中，子像素连接的发光信号线位于子像素的第二电容的第一极板远离子像素的第一电容的第一极板的一侧，子像素连接的第二扫描信号线位于子像素的第一电容的第一极板远离子像素的第二电容的第一极板的一侧，子像素连接的第三扫描信号线位于子像素连接的第二扫描信号线远离子像素的第一电容的第一极板的一侧。
在示例性实施方式中，第一电容的第二极板和第二电容的第二极板为相互连接的一体结构，且设置有第一过孔和第二过孔，第一过孔暴露出第一电容的第一极板，第二过孔暴露出第二电容的第二极板；
第四扫描信号线的第三子信号线位于第一扫描信号线的第一子信号线远离第一电容的第二极板和第二电容的第二极板的一体结构的一侧；
子像素连接的第一扫描信号线的第一子信号线在基底上的正投影位于子像素连接的发光信号线在基底上的正投影和子像素的第二电容的第一极板在基底上的正投影之间，子像素连接的第四扫描信号线的第三子信号线在基底上的正投影位于子像素连接的发光信号线在基底上的正投影远离子像素的第二电容的第一极板在基底上的正投影的一侧。
在示例性实施方式中，子像素连接的第一扫描信号线的第二子信号线位于子像素连接的第四扫描信号线的第四子信号线的一侧，子像素连接的电源连接线位于子像素连接的第一扫描信号线的第二子信号线远离子像素连接的第四扫描信号线的第四子信号线的一侧，子像素连接的第一初始信号线位于子像素连接的电源连接线远离子像素连接的第一扫描信号线的第二子信号线的一侧，子像素连接的第三初始信号线位于子像素连接的第一初始信号线远离子像素连接的电源连接线的一侧；
子像素连接的第四扫描信号线的第四子信号线在基底上的正投影位于子像素连接的发光信号线在基底上的正投影远离子像素的第二电容的第一极板在基底上的正投影的一侧；
子像素连接的第一扫描信号线的第二子信号线在基底上的正投影位于子像素连接的发光信号线在基底上的正投影和子像素的第二电容的第一极板在基底上的正投影之间；
子像素连接的电源连接线在基底上的正投影与子像素的第一电容的第二极板和第二电容的第二极板的一体结构在基底上的正投影至少部分交叠，且位于第一扫描信号线的第一子信号线在基底上的正投影和第二扫描信号线在基底的正投影之间；
子像素连接的第一初始信号线在基底上的正投影与子像素连接的第二扫描信号线在基底上的正投影至少部分交叠，且位于子像素的第一电容的第一极板在基底上的正投影和子像素连接的第三扫描信号线在基底上的正投影之间；
子像素连接的第三初始信号线在基底上的正投影与子像素连接的第三扫描信号线在基底上的正投影至少部分交叠，且位于子像素连接的第二扫描信号线在基底上的正投影远离子像素的第一电容的第一极板在基底上的正投影的一侧。
在示例性实施方式中，所述电源连接线包括：信号主体线、第一凸起部、第二凸起部和第三凸起部，信号主体线沿第一方向延伸，第一凸起部位于信号主体线靠近第一扫描信号线的第二子信号线的一侧，第二凸起部和第三凸起部位于信号主体线远离第一扫描信号线的第二子信号线的一侧，且第二凸起部和第三凸起部沿第一方向排布；
第二凸起部和第三凸起部在基底上的正投影与第一电容的第二极板和第二电容的第 二极板的一体结构在基底上的正投影至少部分交叠；
第一过孔在基底上的正投影位于第二凸起部在基底上的正投影和第三凸起部在基底上的正投影之间。
在示例性实施方式中，第一连接电极在基底上的正投影与电源连接线的信号主体线、第二凸起部和第三凸起部在基底上的正投影至少部分交叠，且与电源连接线的第一凸起部在基底上的正投影不交叠。
在示例性实施方式中，第一电源线在基底上的正投影与第一电容的第二极板和第二电容的第二极板的一体结构、第一连接电极、电源连接线的信号主体部和第二凸起部在基底上的正投影至少部分交叠；
子像素连接的第一电源线在基底上的正投影位于子像素连接的数据信号线远离子像素连接的初始连接线的一侧。
第三方面，本公开还提供了一种显示装置，包括：上述显示基板。
第四方面，本公开还提供了一种像素驱动电路的驱动方法，被配置为驱动上述像素驱动电路，所述方法包括：
节点控制子电路在第一扫描信号线、第二扫描信号线、第三扫描信号线和第四扫描信号线的信号的控制下，通过第一初始信号线、数据信号线和第一电源线的信号带动第一节点的信号，向第二节点提供第二初始信号线的信号，向第三节点提供第三初始信号线的信号；
发光控制子电路在发光信号线的信号的控制下，向第三节点提供第一电源线的信号，驱动子电路在第一节点和第三节点的信号的控制下，向第二节点输出驱动电流。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的像素驱动电路的结构示意图；
图2为一种节点控制子电路的结构示意图；
图3为节点控制子电路的等效电路图；
图4为发光控制子电路和驱动子电路的等效电路图；
图5为一种像素驱动电路的等效电路图；
图6为一种像素驱动电路的工作时序图；
图7为本公开实施例提供的显示基板的结构示意图一；
图8为本公开实施例提供的显示基板的结构示意图二；
图9为显示基板的部分膜层示意图一；
图10为显示基板的部分膜层示意图二；
图11为图7提供的显示基板的遮光层图案的示意图；
图12为图8提供的显示基板的遮光层图案的示意图；
图13为图7和图8提供的显示基板的第一半导体层图案的示意图；
图14为图7提供的显示基板形成第一半导体层图案后的示意图；
图15为图8提供的显示基板形成第一半导体层图案后的示意图；
图16为图7和图8提供的显示基板的第一导电层图案的示意图；
图17为图7提供的显示基板形成第一导电层图案后的示意图；
图18为图8提供的显示基板形成第一导电层图案后的示意图；
图19为图7和图8提供的显示基板的第二导电层图案的示意图；
图20为图7提供的显示基板形成第二导电层图案后的示意图；
图21为图8提供的显示基板形成第二导电层图案后的示意图；
图22为图7和图8提供的显示基板的第二半导体层图案的示意图；
图23为图7提供的显示基板形成第二半导体层图案后的示意图；
图24为图8提供的显示基板形成第二半导体层图案后的示意图；
图25为图7和图8提供的显示基板的第三导电层图案的示意图；
图26为图7提供的显示基板形成第三导电层图案后的示意图；
图27为图8提供的显示基板形成第三导电层图案后的示意图；
图28为图7提供的显示基板形成第七绝缘层图案后的示意图；
图29为图8提供的显示基板形成第七绝缘层图案后的示意图；
图30为图7和图8提供的显示基板的第四导电层图案的示意图；
图31为图7提供的显示基板形成第四导电层图案后的示意图；
图32为图8提供的显示基板形成第四导电层图案后的示意图；
图33为图7提供的显示基板形成第八绝缘层图案后的示意图；
图34为图8提供的显示基板形成第八绝缘层图案后的示意图；
图35为图7和图8提供的显示基板的第五导电层图案的示意图；
图36为图7提供的显示基板形成第五导电层图案后的示意图；
图37为图8提供的显示基板形成第五导电层图案后的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基 板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个线子的元件。晶体管在漏电极(漏电极线子、漏区域或漏电极)与源电极(源电极线子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
显示基板中所用的是低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)技术，LTPS技术拥有高分辨率、高反应速度、高亮度、高开口率等优势。尽管受到了市场欢迎，但LTPS技术也存在一些缺陷，如生产成本较高，所需功耗较大等，此时，低温多晶氧 化物(Low Temperature Polycrystalline Oxide，简称LTPO)技术方案应运而生。相比于LTPS技术，LTPO技术的漏电流更小，像素点反应更快，显示基板多加了一层氧化物，降低了激发像素点所需的能耗，从而降低屏幕显示时的功耗。但是，相比采用LTP0技术的显示产品的制作工艺较复杂，且成本较高。随着高迁移率氧化物材料的出现，Oxide驱动OLED器件成为可能此时，采用氧化物技术的显示产品成为可能，相比于LTPO技术，氧化物技术的工艺简单且成本较低，漏电流更小，已然成为新的主流趋势。但是氧化物技术的显示产品中，像素驱动电路的充电时间较短，无法满足高分辨率的显示基板的要求，影响了显示产品的显示效果。
图1为本公开实施例提供的像素驱动电路的结构示意图，图2为一种节点控制子电路的结构示意图，图3为节点控制子电路的等效电路图。如图1至图3所示，本公开实施例提供的像素驱动电路，被配置为驱动发光器件发光，像素驱动电路包括：节点控制子电路、发光控制子电路和驱动子电路。
在示例性实施方式中，如图1所示，节点控制子电路，可以分别与第一节点N1、第二节点N2、第三节点N3、第一扫描信号线Gate1、第二扫描信号线Gate2、第三扫描信号线Gate3、第四扫描信号线Gate4、第一初始信号线INIT1、第二初始信号线INIT2、第三初始信号线INIT3、数据信号线Data和第一电源线VDD电连接，被配置为在第一扫描信号线Gate1、第二扫描信号线Gate2、第三扫描信号线Gate3和第四扫描信号线Gate4的信号的控制下，通过第一初始信号线INIT1、数据信号线Data和第三节点N3的信号带动第一节点N1的信号，向第二节点N2提供第二初始信号线INIT2的信号，向第三节点N3提供第三初始信号线INIT3的信号，向第四节点N4提供第三节点N3或者数据信号线Data的信号。
在示例性实施方式中，如图1至图3所示，节点控制子电路包括：储能子电路，储能子电路，分别与第一节点N1、第四节点N4和第一电源线VDD电连接，被配置为存储第一节点N1和第四节点N4的信号之间的电压差以及第四节点N4和第一电源线VDD的信号之间的电压差，以通过第一电源线的信号和第四节点N4的信号，带动第一节点N1的信号。
在示例性实施方式中，如图3所示，储能子电路可以包括：第一电容C1和第二电容C2，第一电容C1和第二电容C2包括：第一极板和第二极板。其中，第一电容C1的第一极板C11与第一电源线VDD电连接，第一电容C1的第二极板C12与第四节点N4电连接；第二电容C2的第一极板C21与第一节点N1电连接，第二电容C2的第二极板C22与第四节点N4电连接。
在示例性实施方式中，如图1所示，发光控制子电路，可以分别与第一电源线VDD、发光信号线EM和第三节点N3电连接，被配置为在发光信号线EM的信号的控制下，向第三节点N3提供第一电源线VDD的信号。
在示例性实施方式中，如图1所示，驱动子电路，分别与第一节点N1、第二节点N2和第三节点N3电连接，被配置为在第一节点N1和第三节点N3的信号的控制下，向第二节点N2输出驱动电流。
在示例性实施方式中，如图1所示，发光器件，分别与第二节点N2和第二电源线VSS电连接。
在示例性实施方式中，第一电源线VDD可以持续提供高压电源信号，第二电源线VSS可以持续提供低压电源信号。
在示例性实施方式中，第一电源线VDD的信号的电压值可以约为2.5伏特(V)至3 伏特(V)，示例性地，第一电源线VDD的信号的电压值可以约为2.8伏特(V)。
在示例性实施方式中，第二电源线VSS的信号的电压值可以约为-3伏特(V)至-3.5伏特(V)，示例性地，第二电源线VSS的信号的电压值可以约为-3.2伏特(V)。
在示例性实施方式中，第二电源线VSS的信号的电压值可以约为-3伏特(V)至-3.5伏特(V)，示例性地，第二电源线VSS的信号的电压值可以约为-3.2伏特(V)。
在示例性实施方式中，发光器件可以为有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。示例性地，有机发光二极管的阳极与第二节点N2电连接，有机发光二极管的阴极与第二电源线VSS电连接。
在示例性实施方式中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(EMectron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(EMectron Transport Layer，简称ETL)和电子注入层(EMectron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
本公开实施例提供的像素驱动电路被配置为驱动发光器件，像素驱动电路包括：节点控制子电路、发光控制子电路和驱动子电路；节点控制子电路，分别与第一节点、第二节点、第三节点、第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、第一初始信号线、第二初始信号线、第三初始信号线、数据信号线和第一电源线电连接，被配置为在第一扫描信号线、第二扫描信号线、第三扫描信号线和第四扫描信号线的信号的控制下，通过第一初始信号线、数据信号线和第三节点的信号带动第一节点的信号，向第二节点提供第二初始信号线的信号，向第三节点提供第三初始信号线的信号；发光控制子电路，分别与第一电源线、发光信号线和第三节点电连接，被配置为在发光信号线的信号的控制下，向第三节点提供第一电源线的信号；驱动子电路，分别与第一节点、第二节点和第三节点电连接，被配置为在第一节点和第三节点的信号的控制下，向第二节点输出驱动电流；发光器件，分别与第二节点和第二电源线电连接，节点控制子电路包括：储能子电路，所述储能子电路包括：第一电容和第二电容，第一电容和第二电容包括：第一极板和第二极板；第一电容的第一极板与第一电源线电连接，第一电容的第二极板与第四节点电连接；第二电容的第一极板与第一节点电连接，第二电容的第二极板与第四节点电连接。本公开通过设置节点控制子电路、发光控制子电路和驱动子电路的配合下，可以通过第二初始信号线的信号对像素驱动电路进行补偿，增加了像素驱动电路的补偿时间，延长像素驱动电路的充电时间，可以提升像素驱动电路的可靠性。
在示例性实施方式中，如图2所示，节点控制子电路还可以包括：复位子电路、补偿子电路和写入子电路。
如图2所示，复位子电路，分别与第一节点N1、第二节点N2、第三节点N3、第一扫描信号线Gate1、第二扫描信号线Gate2、第三扫描信号线Gate3、第一初始信号线INIT1、第二初始信号线INIT2和第三初始信号线INIT3电连接，被配置为在第一扫描信号线Gate1的信号的控制下，向第一节点N1提供第一初始信号线INIT1的信号，在第二扫描信号线Gate2的信号的控制下，向第二节点N2提供第二初始信号线INIT2的信号，在第 三扫描信号线Gate3的信号的控制下，向第三节点N3提供第三初始信号线INIT3的信号；补偿子电路，分别与第三节点N3、第四节点N4和第一扫描信号线Gate1电连接，被配置为在第一扫描信号线Gate1的信号的控制下，向第四节点N4提供第三节点N3的信号，以对第四节点N4的信号进行补偿；写入子电路，分别与第四节点N4、第四扫描信号线Gate4和数据信号线Data电连接，被配置为在第四扫描信号线Gate4的信号的控制下，向第四节点N4提供数据信号线Data的信号。
在示例性实施方式中，如图3所示，复位子电路可以包括：第一晶体管T1、第二晶体管T2和第三晶体管T3，补偿子电路可以包括：第四晶体管T4，写入晶体管可以包括：第五晶体管T5。其中，第一晶体管T1的栅电极与第一扫描信号线Gate1电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的栅电极与第二扫描信号线Gate2电连接，第二晶体管T2的第一极与第二初始信号线INIT2电连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的栅电极与第三扫描信号线Gate3电连接，第三晶体管T3的第一极与第三初始信号线INIT3电连接，第二晶体管T2的第二极与第三节点N3电连接；第四晶体管T4的栅电极与第一扫描信号线Gate1电连接，第四晶体管T4的第一极与第四节点N4电连接，第四晶体管T4的第二极与第三节点N3电连接；第五晶体管T5的栅电极与第四扫描信号线Gate4电连接，第五晶体管T5的第一极与数据信号线Data电连接，第五晶体管T5的第二极与第四节点N4电连接。
图4为发光控制子电路和驱动子电路的等效电路图。如图4所示，驱动子电路可以包括：第六晶体管T6，发光控制子电路可以包括：第七晶体管T7。其中，第六晶体管T6的栅电极与第一节点N1电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第二节点N2电连接；第七晶体管T7的栅电极与发光信号线EM电连接，第七晶体管T7的第一极与第一电源线VDD电连接，第七晶体管T7的第二极与第三节点N3电连接。
图5为一种像素驱动电路的等效电路图。如图5所示，在示例性实施方式中，节点控制子电路包括：第一晶体管T1至第五晶体管T5以及第一电容C1和第二电容C2，驱动子电路包括：第六晶体管T6，发光控制子电路包括：第七晶体管T7；第一电容C1和第二电容C2包括：第一极板和第二极板。其中，第一晶体管T1的栅电极与第一扫描信号线Gate1电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的栅电极与第二扫描信号线Gate2电连接，第二晶体管T2的第一极与第二初始信号线INIT2电连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的栅电极与第三扫描信号线Gate3电连接，第三晶体管T3的第一极与第三初始信号线INIT3电连接，第二晶体管T2的第二极与第三节点N3电连接；第四晶体管T4的栅电极与第一扫描信号线Gate1电连接，第四晶体管T4的第一极与第四节点N4电连接，第四晶体管T4的第二极与第三节点N3电连接；第五晶体管T5的栅电极与第四扫描信号线Gate4电连接，第五晶体管T5的第一极与数据信号线Data电连接，第五晶体管T5的第二极与第四节点N4电连接；第六晶体管T6的栅电极与第一节点N1电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第二节点N2电连接；第七晶体管T7的栅电极与发光信号线EM电连接，第七晶体管T7的第一极与第一电源线VDD电连接，第七晶体管T7的第二极与第三节点N3电连接；第一电容C1的第一极板C11与第一电源线VDD电连接，第一电容C1的第二极板C12与第四节点N4电连接；第二电容C2的第一极板C21与第一节点N1电连接，第二电容C2的第二极板C22与第四节点N4电连接。
在示例性实施方式中，第一晶体管T1可以称为第一节点复位晶体管。第一扫描信号线Gate1的信号为有效电平信号时，第一初始信号线INIT1的信号写入至第一节点N1中。
在示例性实施方式中，第二晶体管T2可以称为第二节点复位晶体管。第扫描信号线Gate2的信号为有效电平信号时，第二初始信号线INIT2的信号写入至第二节点N2(也是发光器件L的阳极)中。
在示例性实施方式中，第三晶体管T3可以称为第三节点复位晶体管。第三扫描信号线Gate3的信号为有效电平信号时，第三初始信号线INIT3的信号写入至第三节点N3中。
在示例性实施方式中，第四晶体管T4可以称为补偿晶体管。第一扫描信号线Gate1的信号为有效电平信号时，第三节点N3的信号写入至第四节点N4中，对第四节点N4的信号进行补偿。
在示例性实施方式中，第五晶体管T5可以称为写入晶体管。第四扫描信号线Gate的信号为有效电平信号时，数据信号线Data的信号写入至第二节点N2中。
在示例性实施方式中，第六晶体管T6可以称为驱动晶体管。第六晶体管T6根据其栅电极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流经的驱动电流。
在示例性实施方式中，第七晶体管T7可以称为发光晶体管。当发光信号线EM的信号为有效电平信号时，第七晶体管T7通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，第六晶体管的有源层的沟道区的长度大于第一晶体管至第五晶体管和第七晶体管中的任一个晶体管的有源层的沟道区的长度，第六晶体管的有源层的沟道区的宽度大于第一晶体管至第五晶体管和第七晶体管中的任一个晶体管的有源层的沟道区的宽度，且第六晶体管的有源层的沟道区的宽长比小于第一晶体管至第五晶体管和第七晶体管中的任一个晶体管的有源层的沟道区的宽长比。
图5中示出了节点控制子电路、驱动子电路和发光控制子电路的一个示例性结构。本领域技术人员容易理解是，节点控制子电路、驱动子电路和发光控制子电路的实现方式不限于此。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物 (Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，第一晶体管T1、第四晶体管T4和第五晶体管T5可以为氧化物晶体管。
在示例性实施方式中，第一晶体管T1、第四晶体管T4和第五晶体管T5可以为N型晶体管，第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7可以为P型晶体管。
在示例性实施方式中，第一晶体管T1至第五晶体管T5的有源层的沟道区域的宽长比可以为2.5/3。
在示例性实施方式中，第六晶体管T6(驱动晶体管)的有源层的沟道区域的宽长比可以为3.5/20。
在示例性实施方式中，第七晶体管T7的有源层的沟道区的宽长比可以为2.0/2.5。
在示例性实施方式中，第一扫描信号线Gate1的信号和第二扫描信号线Gate2的信号可以互为反相信号。
在示例性实施方式中，第三扫描信号线Gate3的信号为有效电平信号时，第一扫描信号线Gate1和是第二扫描信号线Gate2的信号为有效电平信号，第四扫描信号线Gate4和发光信号线EM的信号为无效电平信号。
在示例性实施方式中，第四扫描信号线Gate4的信号为有效电平信号时，第一扫描信号线Gate1、第二扫描信号线Gate2、第三扫描信号线Gate3和发光信号线EM的信号为无效电平信号。
在示例性实施方式中，发光信号线EM的信号为有效电平信号时，第一扫描信号线Gate1、第二扫描信号线Gate2、第三扫描信号线Gate3和第四扫描信号线Gate4的信号为无效电平信号。
在示例性实施方式中，第一扫描信号线Gate1和第二扫描信号线Gate2中的任一条信号线的信号为有效电平信号的持续时间大于第三扫描信号线Gate3和第四扫描信号线Gate4中的任一条信号线的信号为有效电平信号的持续时间。
在示例性实施方式中，第一初始信号线INIT1的信号和第二初始信号线INIT2的信号可以为同一信号，且第一初始信号线INIT1的信号的电压值小于第三初始信号线INIT3的信号的电压值。
在示例性实施方式中，第一初始信号线INIT1和第二初始信号线INIT2可以为同一信号线，或者可以为传输相同的信号的不同信号线，本公开对此不做任何限定。
在示例性实施方式中，第一初始信号线INIT1的信号的电压值可以约为-2.8伏特(V)至-3.2伏特(V)，示例性地，第一初始信号线INIT1的信号的电压值可以约为-3伏特(V)。
在示例性实施方式中，第三初始信号线INIT3的信号的电压值可以约为5伏特(V)至7伏特(V)，示例性地，第三初始信号线INIT3的信号的电压值可以约为6伏特(V)。
在示例性实施方式中，第二初始信号线INIT2的信号的电压值可以大于第二电源线VSS的信号的电压值。示例性地，第二初始信号线INIT2的信号的电压值可以略大于第二电源线VSS的信号的电压值，第二初始信号线INIT2的信号的电压值大于第二电源线VSS的信号的电压值可以保证在对第二节点N2(也是发光器件的阳极)进行复位时，发光器件不发光，可以提升显示效果。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)和2个电容(第一电容C1和第二电容C2)，第一晶体管T1、第四晶体管T4和第五晶体管T5为N型晶体管，第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管为T7为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段P1，称为初始化阶段，第一扫描信号线Gate1和发光信号线EM的信号为高电平信号，第二扫描信号线Gate2、第三扫描信号线Gate3和第四扫描信号线Gate4的信号为低电平信号。第一扫描信号线Gate1的信号为高电平信号，第一晶体管T1和第四晶体管T4导通，第一初始信号线INIT1的第一初始信号通过导通的第一晶体管T1写入至第一节点N1，对第一节点N1进行初始化(复位)，清空其内部的预存电压，完成初始化。第二扫描信号线Gate2的信号为低电平信号，第二晶体管T2导通，第二初始信号线INIT2的第二初始信号通过导通的第二晶体管T2写入至第二节点N2(也是发光器件L的阳极)，对第二节点N2(也是发光器件L的阳极)进行初始化(复位)，清空其内部的预存电压，完成初始化。第三扫描信号线Gate3的信号为低电平信号，第三晶体管T3导通，第三初始信号线INIT3的第三初始信号通过导通的第三晶体管T3和第四晶体管T4写入至第三节点N3和第四节点N4，对第三节点N3和第四节点N4进行初始化(复位)，清空其内部的预存电压，完成初始化。此时，第一节点N1和第三节点N3之间的信号的电压值的差值小于第六晶体管T6的阈值电压，第六晶体管T6导通。第四扫描信号线Gate的信号为低电平信号，第五晶体管T5截止，发光信号线EM的信号为高电平信号，第七晶体管T7截止。本阶段，由于第二初始信号线INIT2的第二初始信号的电压值略小于第二电源线VSS的信号的电压值，发光器件L不发光。
第二阶段P2，称为阈值补偿阶段，第一扫描信号线Gate1、第三扫描信号线Gate3和发光信号线EM的信号为高电平信号，第二扫描信号线Gate2和第四扫描信号线Gate4的信号为低电平信号。第一扫描信号线Gate1的信号为高电平信号，第一晶体管T1和第四晶体管T4持续导通，第一初始信号线INIT1的第一初始信号通过导通的第一晶体管T1写入至第一节点N1，对第一节点N1继续进行初始化(复位)，清空其内部的预存电压，完成初始化。第二扫描信号线Gate2的信号为低电平信号，第二晶体管T2导通，第二初始信号线INIT2的第二初始信号通过导通的第二晶体管T2写入至第二节点N2(也是发光器件L的阳极)，对第二节点N2(也是发光器件L的阳极)进行初始化(复位)，清空其内部的预存电压，完成初始化，第二初始信号线INIT2的第二初始信号通过导通的第二晶体管T2、第二节点N2、第六晶体管T6、第三节点N3和导通第四晶体管T4对第四节点N4进行充电，直至第四节点N4的信号的电压值满足V4＝Vinit1-Vth，Vinit1为第一初始信号的电压值。第三扫描信号线Gate3的信号为高电平信号，第三晶体管T3截止，第四扫描信号线Gate的信号为低电平信号，第五晶体管T5截止，发光信号线EM的信号为高电平信号，第七晶体管T7截止。本阶段，由于第二初始信号线INIT2的第二初始信号的电压值略小于第二电源线VSS的信号的电压值，发光器件L不发光。
第三阶段P3，称为数据写入阶段，第二扫描信号线Gate2、第三扫描信号线Gate3、第四扫描信号线Gate4和发光信号线EM的信号为高电平信号，第一扫描信号线Gate1的信号为低电平信号。数据信号线Data输出数据信号。第四扫描信号线Gate4的信号为高电平信号，第五晶体管T5导通，数据信号线Data的数据信号通过导通的第五晶体管T5写入第四节点N4，此时，第四节点的信号的电压值V4发生跳变，满足V4＝Vdata，Vdata为数据信号的电压值，在第二电容C2的作用下，第一节点N1的信号的电压值V1发生 跳变，满足V1＝Vdata+Vth。第一扫描信号线Gate1的信号为低电平信号，第一晶体管T1和第四晶体管T4截止，第二扫描信号线Gate2的信号为高电平信号，第二晶体管T2截止，第三扫描信号线Gate3的信号为高电平信号，第三晶体管T3截止，发光信号线EM的信号为高电平信号，第七晶体管T7截止。本阶段，发光器件L不发光。
第四阶段P4、称为发光阶段，第二扫描信号线Gate2和第三扫描信号线Gate3的信号为高电平信号，第一扫描信号线Gate1、第四扫描信号线Gate4和发光信号线EM的信号为低电平信号。发光信号线EM的信号为低电平信号，第七晶体管T7导通，第一电源线VDD输出的电源信号通过导通的第七晶体管T7、第三节点N3、导通的第六晶体管T6向第二节点N2(也是发光器件L的第一极)提供驱动电压，驱动发光器件L发光。第一扫描信号线Gate1的信号为低电平信号，第一晶体管T1和第四晶体管T4截止，第二扫描信号线Gate2的信号为高电平信号，第二晶体管T2截止，第三扫描信号线Gate3的信号为高电平信号，第三晶体管T3截止，第四扫描信号线Gate4的信号为低电平信号，第五晶体管T5截止。
在像素驱动电路驱动过程中，流过第六晶体管T6(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata+Vth，第三节点N3的信号的电压值V3＝Vdd，Vdd为第一电源线的信号的电压值，因而第六晶体管T6的驱动电流为：
I＝K*(Vgs-Vth)2＝K*(Vdata+Vth-Vdd-Vth)2＝K*(Vdata-Vdd)2
其中，I为流过第六晶体管T6的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第六晶体管T6的栅电极和第一极之间的电压差，Vth为第六晶体管T6的阈值电压。
由上述电流公式的推导结果可以看出，在发光阶段，第六晶体管T6的驱动电流已经不受第六晶体管T6的阈值电压的影响，从而消除了第六晶体管T6的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
本公开中在第二阶段，即阈值补偿阶段，通过第二初始信号线INIT2的信号对第四节点N4的信号进行补偿，延长了像素驱动电路的补偿时间，增加了像素驱动电路的充电时间，提升了像素驱动电路的可靠性。
本公开实施例还提供一种显示基板包括：基底以及设置在基底上的多个子像素，至少一个子像素包括：像素驱动电路以及像素驱动电路所驱动的发光器件。
像素驱动电路为前述任一个实施例提供的像素驱动电路，实现原理和实现效果类似，在此不再赘述。
图7为本公开实施例提供的显示基板的结构示意图一，图8为本公开实施例提供的显示基板的结构示意图二，图9为显示基板的部分膜层示意图一，图10为显示基板的部分膜层示意图二。如图7至图10所示，显示基板可以包括：基底以及依次设置在基底上的驱动电路层和发光结构层，驱动电路层包括：多个像素驱动电路、多条发光信号线EM、多条第一初始信号线INIT1、多条第二初始信号线INIT2、多条第三初始信号线、多条第一扫描信号线Gate1、多条第二扫描信号线Gate2、多条第三扫描信号线Gate3、多条第四扫描信号线Gate4、多条第一电源线VDD和多条数据信号线Data，发光结构层包括：发光器件。
在示例性实施方式中，如图7至图10所示，发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、第三初始信号线、第一扫描信号线Gate1、第二扫描信号线Gate2、第三扫描信号线Gate3和第四扫描信号线Gate4中任一信号线至少部分沿第一方向D1延 伸，第一电源线VDD和数据信号线Data中的任一信号线至少部分沿第二方向D2延伸，第一方向D1和第二方向D2相交。
在示例性实施方式中，显示基板还可以包括设置在发光结构层远离基底一侧的封装结构层。显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，在平行于显示基板的平面上，显示基板可以包括：多个子像素，至少一个子像素可以包括：像素驱动电路和发光器件，像素驱动电路被配置为向所连接的发光器件输出相应的电流，使该发光器件发出相应亮度的光。
在示例性实施方式中，多个子像素可以包括多个像素行和多个像素列。沿着水平方向依次排布的多个子像素可以称为像素行，沿着竖直方向依次排布的多个子像素可以称为像素列，多个像素行和多个像素列构成阵列排布的像素阵列。
在示例性实施方式中，多个子像素构成一个像素单元，像素单元可以包括第一子像素、第二子像素和第三子像素，或者第一子像素、第二子像素、第三子像素和第四子像素。
在示例性实施方式中，当像素单元包括第一子像素、第二子像素和第三子像素时，第一子像素可以是出射红色光线的红色子像素(R)，第二子像素可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)，三个子像素的形状可以是三角形、矩形状、菱形、五边形或六边形等，本公开在此不做限定。在像素行方向上，第一子像素、第二子像素和第三子像素可以按照对齐方式依次设置，在像素列方向上，第一子像素、第二子像素和第三子像素可以按照错位方式依次设置，形成子像素的品字布局。例如，奇数行中的第一子像素可以位于偶数行中相邻的第二子像素和第三子像素之间，或者，偶数行中的第一子像素可以位于奇数行中相邻的第二子像素和第三子像素之间。又如，奇数行中的第二子像素可以位于偶数行中相邻的第一子像素和第三子像素之间，或者，偶数行中的第二子像素可以位于奇数行中相邻的第一子像素和第三子像素之间。再如，奇数行中的第三子像素可以位于偶数行中相邻的第一子像素和第二子像素之间，或者，偶数行中的第三子像素可以位于奇数行中相邻的第一子像素和第二子像素之间。
在示例性实施方式中，像素单元包括第一子像素、第二子像素、第三子像素和第四子像素时，第一子像素可以是出射红色光线的红色子像素(R)，第二子像素可以是出射蓝色光线的蓝色子像素(B)，第三子像素和第四子像素可以是出射绿色光线的绿色子像素(G)，三个子像素的形状可以是三角形、矩形状、菱形、五边形或六边形等，本公开在此不做限定。在示例性实施方式中，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。四个子像素可以采用正方形(Square)方式排列，形成GGRB像素排布。在另一种示例性实施方式中，四个子像素可以采用钻石形(Diamond)方式排列，形成RGGB像素排布。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、导电箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，发光结构层包括：依次叠设在基底上的阳极层、像素定义层、有机结构层和阴极层；所述阳极层包括：阳极，所述有机结构层包括：有机发光层，所述阴极层包括：阴极。
在示例性实施方式中，如图7至图10所示，驱动电路层还包括：至少部分沿第一方 向延伸的多条电源连接线VCL；至少一条电源连接线VCL，分别与像素驱动电路和至少一条第一电源线VDD连接。本公开中沿第一方向延伸的多条电源连接线VCL；和沿第二方向延伸的多条第一电源线形成网状结构，可以保证每个像素驱动电路的电源信号相同，可以提升显示基板的显示均一性。
在示例性实施方式中，驱动电路层还可以包括：第一连接电极。第一连接电极，分别与像素驱动电路、电源连接线VCL和第一电源线VDD连接；第一连接电极在基底上的正投影与电源连接线VCL和第一电源线VDD在基底上的正投影至少部分交叠。
在示例性实施方式中，如图7和图8所示，第一初始信号线INIT1和第二初始信号线INIT2为同一信号线。
在示例性实施方式中，如图7和图8所示，驱动电路层还可以包括：至少部分沿第二方向D2延伸的多条初始连接线ICL；至少一条初始连接线ICL，分别与像素驱动电路和至少一条第一初始信号线INIT1连接。本公开中沿第一方向延伸的多条第一初始信号线INIT1和沿第二方向延伸的多条初始连接线ICL形成网状结构，可以降低由于第一初始信号线的电阻的差异所导致的不同像素驱动电路的连接的第一初始信号线的初始信号的差异对低灰阶的影响，可以提升显示基板的显示均一性。
在示例性实施方式中，如图7和图8所示，初始连接线ICL在基底上的正投影可以位于初始连接线ICL连接的相邻两列子像素连接的数据信号线Data在基底上的正投影之间。
在示例性实施方式中，第一扫描信号线Gate1包括：相互电连接的第一子信号线和第二子信号线。示例性地，第一子信号线和第二子信号线可以异层设置，且可以在显示区域的外围电连接，第一子信号线在基底上的正投影与第二子信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，第四扫描信号线Gate4包括：异层设置，且相互连接的第三子信号线和第四子信号线，示例性地，第三子信号线和第四子信号线可以异层设置，且可以在显示区域的外围电连接，第三子信号线在基底上的正投影与第四子信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，像素驱动电路包括：第一晶体管至第七晶体管以及第一电容和第二电容，第一电容和第二电容分别包括：第一极板和第二极板，驱动电路层包括在基底上依次设置的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层；
第一半导体层至少包括：位于至少一个子像素的第二晶体管的有源层、第三晶体管的有源层、第六晶体管的有源层和第七晶体管的有源层；
第一导电层至少包括：发光信号线EM、第二扫描信号线Gate2、第三扫描信号线Gate3以及位于至少一个子像素的第一电容的第一极板、第二电容的第一极板、第二晶体管的栅电极、第三晶体管的栅电极、第六晶体管的控制极和第七晶体管的栅电极；
第二导电层至少包括：第一扫描信号线Gate1的第一子信号线、第四扫描信号线Gate4的第三子信号线以及位于至少一个子像素的第一电容的第二极板和第二电容的第二极板；
第二半导体层至少包括：位于至少一个子像素的第一晶体管的有源层、第四晶体管的有源层和第五晶体管的有源层。
第三导电层至少包括：第一扫描信号线Gate1的第二子信号线、第四扫描信号线Gate4的第四子信号线、电源连接线VCL、第一初始信号线INIT1、第二初始信号线INIT2和第 三初始信号线；
第四导电层至少包括：初始连接线ICL以及位于至少一个子像素的第一连接电极和第一晶体管至第七晶体管的第一极和第二极；
第五导电层至少包括：第一电源线VDD和数据信号线Data。
本公开中的电源信号传输的信号线包括位于第三导电层的电源连接线和位于第五导电层的第一电源线，数据信号传输的信号线包括第五导电层的数据信号线，第一电容的第二极板和第二电容的第二极板位于第二导电层，电源信号传输的信号线包括位于第三导电层的电源连接线可以屏蔽位于第二导电层的第一电容的第二极板和第二电容的第二极板与第五导电层的数据信号线之间寄生电容(也是第六晶体管的栅电极的信号和数据信号之间的寄生电容)，可以避免信号之间的串扰，提升显示基板的可靠性。
在示例性实施方式中，图11为图7提供的显示基板的遮光层图案的示意图，图12为图8提供的显示基板的遮光层图案的示意图。如图11和图12所示，驱动电路层还可以包括：设置在基底和第一半导体层之间的遮光层；遮光层至少包括：位于至少一个子像素的遮光结构，相邻子像素的遮光结构相互连接。
在示例性实施方式中，遮光结构在基底上的正投影可以与第六晶体管的栅电极在基底上的正投影至少部分交叠。示例性地，遮光结构在基底上的正投影可以覆盖第六晶体管的栅电极在基底上的正投影，遮光结构在基底上的正投影覆盖第六晶体管的栅电极(也是驱动晶体管)在基底上的正投影可以提升驱动晶体管的使用寿命，提升显示基板的可靠性。
在示例性实施方式中，如图11所示，遮光结构可以包括：第一遮光部11、第二遮光部12、第三遮光部13和第四遮光部14；其中，第一遮光部11在基底上的正投影与第六晶体管的有源层在基底上的正投影至少部分重叠，第二遮光部12在基底上的正投影与第七晶体管的有源层在基底上的正投影至少部分重叠，第三遮光部13在基底上的正投影与第三晶体管的有源层在基底上的正投影至少部分重叠，第四遮光部14在基底上的正投影与第二晶体管的有源层在基底上的正投影至少部分重叠。
在示例性实施方式中，如图12所示，遮光结构可以包括：遮光部20、第一遮光连接部21、第二遮光连接部22、第三遮光连接部23和第四遮光连接部24；其中，遮光部20在基底上的正投影与第六晶体管的有源层在基底上的正投影至少部分重叠，第一遮光连接部21、第二遮光连接部22、第三遮光连接部23和第四遮光连接部24中的任一个在基底上的正投影与第二晶体管的有源层、第三晶体管的有源层和第七晶体管的有源层中的任一个在基底上的正投影不交叠。
在示例性实施方式中，子像素连接的发光信号线EM位于子像素的第二电容的第一极板远离子像素的第一电容的第一极板的一侧，子像素连接的第二扫描信号线Gate2位于子像素的第一电容的第一极板远离子像素的第二电容的第一极板的一侧，子像素连接的第三扫描信号线Gate3位于子像素连接的第二扫描信号线Gate2远离子像素的第一电容的第一极板的一侧。
在示例性实施方式中，如图9所示，第一电容的第二极板C12和第二电容的第二极板C22为相互连接的一体结构，且设置有第一过孔V1和第二过孔V2，第一过孔暴露出第一电容的第一极板，第二过孔暴露出第二电容的第二极板。
在示例性实施方式中，如图9所示，第四扫描信号线Gate4的第三子信号线位于第一扫描信号线Gate1的第一子信号线远离第一电容的第二极板C12和第二电容的第二极板C22的一体结构的一侧。
在示例性实施方式中，如图7和图8所示，子像素连接的第一扫描信号线Gate1的第一子信号线在基底上的正投影位于子像素连接的发光信号线EM在基底上的正投影和子像素的第二电容的第一极板在基底上的正投影之间，子像素连接的第四扫描信号线Gate4的第三子信号线在基底上的正投影位于子像素连接的发光信号线EM在基底上的正投影远离子像素的第二电容的第一极板在基底上的正投影的一侧。
在示例性实施方式中，如图7和图8所示，子像素连接的第一扫描信号线Gate1的第二子信号线位于子像素连接的第四扫描信号线Gate4的第四子信号线的一侧，子像素连接的电源连接线VCL位于子像素连接的第一扫描信号线Gate1的第二子信号线远离子像素连接的第四扫描信号线Gate4的第四子信号线的一侧，子像素连接的第一初始信号线INIT1位于子像素连接的电源连接线VCL远离子像素连接的第一扫描信号线Gate1的第二子信号线的一侧，子像素连接的第三初始信号线位于子像素连接的第一初始信号线INIT1远离子像素连接的电源连接线VCL的一侧。
在示例性实施方式中，如图7和图8所示，子像素连接的第四扫描信号线Gate4的第四子信号线在基底上的正投影位于子像素连接的发光信号线EM在基底上的正投影远离子像素的第二电容的第一极板在基底上的正投影的一侧。
在示例性实施方式中，如图7和图8所示，子像素连接的第一扫描信号线Gate1的第二子信号线在基底上的正投影位于子像素连接的发光信号线EM在基底上的正投影和子像素的第二电容的第一极板在基底上的正投影之间。
在示例性实施方式中，如图7和图8所示，子像素连接的电源连接线VCL在基底上的正投影与子像素的第一电容的第二极板和第二电容的第二极板的一体结构在基底上的正投影至少部分交叠，且位于第一扫描信号线Gate1的第一子信号线在基底上的正投影和第二扫描信号线Gate2在基底的正投影之间。
在示例性实施方式中，如图7和图8所示，子像素连接的第一初始信号线INIT1在基底上的正投影与子像素连接的第二扫描信号线Gate2在基底上的正投影至少部分交叠，且位于子像素的第一电容的第一极板在基底上的正投影和子像素连接的第三扫描信号线Gate3在基底上的正投影之间。
在示例性实施方式中，如图7和图8所示，子像素连接的第三初始信号线INIT3在基底上的正投影与子像素连接的第三扫描信号线Gate3在基底上的正投影至少部分交叠，且位于子像素连接的第二扫描信号线Gate2在基底上的正投影远离子像素的第一电容的第一极板在基底上的正投影的一侧。
在示例性实施方式中，电源连接线VCL包括：信号主体线、第一凸起部、第二凸起部和第三凸起部，信号主体线沿第一方向延伸，第一凸起部位于信号主体线靠近第一扫描信号线Gate1的第二子信号线的一侧，第二凸起部和第三凸起部位于信号主体线远离第一扫描信号线Gate1的第二子信号线的一侧，且第二凸起部和第三凸起部沿第一方向排布。其中，第二凸起部和第三凸起部在基底上的正投影与第一电容的第二极板和第二电容的第二极板的一体结构在基底上的正投影至少部分交叠。
在示例性实施方式中，第一过孔在基底上的正投影位于第二凸起部在基底上的正投影和第三凸起部在基底上的正投影之间。
在示例性实施方式中，如图7、图8和图10所示，第一连接电极VL1在基底上的正投影与电源连接线VCL的信号主体线、第二凸起部和第三凸起部在基底上的正投影至少部分交叠，且与电源连接线VCL的第一凸起部在基底上的正投影不交叠。
在示例性实施方式中，如图7和图8所示，第一电源线VDD在基底上的正投影与第 一电容的第二极板和第二电容的第二极板的一体结构、第一连接电极、电源连接线VCL的信号主体部和第二凸起部在基底上的正投影至少部分交叠。
在示例性实施方式中，如图7和图8所示，子像素连接的第一电源线VDD在基底上的正投影位于子像素连接的数据信号线Data远离子像素连接的初始连接线ICL的一侧。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开在此不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界交叠。
下面以两行四列像素驱动电路说明图7和图8提供的显示基板的制备过程。一种示例性实施例提供的显示基板的制备过程可以包括：
(1)在基底上形成遮光层图案，包括：在基底上依次沉积第一绝缘薄膜和遮光薄膜，通过图案化工艺对遮光薄膜进行图案化，形成覆盖基底的第一绝缘层以及位于第一绝缘层上的遮光层图案，如图11和图12所示。
在示例性实施方式中，如图11和图12所示，遮光层至少可以包括：位于至少一个子像素的遮光结构。
在示例性实施方式中，如图11和图12所示，所有遮光结构为相互连接的一体结构。位于同一行的相邻子像素的遮光结构相对于沿第二方向D2延伸的虚拟直线对称设置，且位于同一列的所有子像素的遮光结构相同。
在示例性实施方式中，如图11所示，图7提供的显示基板中遮光结构包括：第一遮光部11、第二遮光部12、第三遮光部13和第四遮光部14。第一遮光部11、第二遮光部12、第三遮光部13和第四遮光部14为相互连接的一体结构。
在示例性实施方式中，如图11所示，第二遮光部12和第三遮光部13沿第二方向D2排布，第三遮光部13和第四遮光部14沿第一方向D1排布。在第二方向D2上，子像素的第二遮光部12可以位于第一遮光部11靠近上一行子像素的一侧，子像素的第三遮光部13和第四遮光部14可以位于第一遮光部11靠近下一行子像素的一侧。在第一方向D1上，子像素的第四遮光部14可以位于第三遮光部13靠近下一列子像素的一侧或者第三遮光部13靠近上一列子像素的一侧。
在示例性实施方式中，如图11所示，第一遮光部11可以包括：遮光主体部11A和遮光连接部11B。遮光主体部11A和遮光连接部11B为相互连接的一体结构。
在示例性实施方式中，如图11所示，遮光主体部11A和遮光连接部11B沿第一方向排布，子像素的遮光主体部11A位于遮光连接部11B靠近下一列子像素的一侧或者遮光连接部11B靠近上一列子像素的一侧。当第四遮光部14可以位于第三遮光部13靠近下一列子像素的一侧时，遮光主体部11A位于遮光连接部11B靠近下一列子像素的一侧。 当第四遮光部14可以位于第三遮光部13靠近上一列子像素的一侧时，遮光主体部11A位于遮光连接部11B靠近上一列子像素的一侧。
在示例性实施方式中，如图11所示，遮光主体部11A的形状可以为矩形状，且矩形状的角部可以设置倒角。遮光连接部11B的形状可以为沿第一方向D1延伸的条状。
在示例性实施方式中，如图11所示，第二遮光部12、第三遮光部13和第四遮光部14的形状可以为沿第二方向D2延伸的条状。
在示例性实施方式中，如图11所示，子像素的第二遮光部与位于同一列上一行子像素的第三遮光部相互连接，子像素的第三遮光部与位于同一列下一行子像素的第二遮光部相互连接。子像素的第一遮光部的遮光连接部与位于同一行的其中一个相邻子像素的第一遮光部的遮光连接部相互连接，子像素的第四遮光部与位于同一行的另一个相邻子像素的第四遮光部相互连接。
在示例性实施方式中，如图12所示，图8提供的显示基板的遮光结构可以包括：遮光部20、第一遮光连接部21、第二遮光连接部22、第三遮光连接部23和第四遮光连接部24。遮光部20、第一遮光连接部21、第二遮光连接部22、第三遮光连接部23和第四遮光连接部24为相互连接的一体结构。
在示例性实施方式中，如图12所示，第一遮光连接部21和第二遮光连接部22沿第二方向D2排布。在第二方向D2上，子像素的第一遮光连接部21可以位于遮光部20靠近上一行子像素的一侧，子像素的第二遮光连接部22可以位于遮光部20靠近下一行子像素的一侧。在第一方向D1上，子像素的第三遮光连接部23和第四遮光连接部24遮光部20的不同侧。当子像素的第三遮光连接部23可以位于遮光部20靠近上一列子像素的一侧时，子像素的第四遮光连接部24可以位于遮光部20靠近下一列子像素的一侧。当子像素的第三遮光连接部23可以位于遮光部20靠近下一列子像素的一侧时，子像素的第四遮光连接部24可以位于遮光部20靠近上一列子像素的一侧。
在示例性实施方式中，如图12所示，遮光部20的形状可以为矩形状，且矩形状的角部可以设置倒角。
在示例性实施方式中，如图12所示，第一遮光连接部21的第二遮光连接部22的形状可以为沿第二方向D2延伸的条状。第三遮光连接部23和第四遮光连接部24的形状可以为沿第一方向D1延伸的条状。
在示例性实施方式中，如图12所示，子像素的第一遮光连接部与位于同一列上一行子像素的第二遮光连接部相互连接，子像素的第二遮光连接部与位于同一列下一行子像素的第一遮光连接部相互连接。子像素的第三遮光连接部与位于同一行的其中一个相邻子像素的第三遮光连接部相互连接，子像素的第四遮光连接部与位于同一行的另一个相邻子像素的第四遮光连接部相互连接。
(2)形成第一半导体层图案。在示例性实施方式中，形成第一半导体层图案可以包括：在基底上依次沉积第二绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成覆盖遮光层的第二绝缘层以及位于第二绝缘层上的第一半导体层图案，如图13至图15所示，图13为图7和图8提供的显示基板的第一半导体层图案的示意图，图14为图7提供的显示基板形成第一半导体层图案后的示意图，图15为图8提供的显示基板形成第一半导体层图案后的示意图。
在示例性实施方式中，如图13至图15所示，第一半导体层图案至少可以包括：位于至少一个子像素的第二晶体管的有源层T21、第三晶体管的有源层T31、第六晶体管的有源层T61和第七晶体管的有源层T71。
在示例性实施方式中，如图14所示，图7提供的显示基板中，第一遮光部在基底上的正投影与第六晶体管的有源层T61在基底上的正投影至少部分重叠。第二遮光部在基底上的正投影与第七晶体管的有源层T71在基底上的正投影至少部分重叠。第三遮光部在基底上的正投影与第三晶体管的有源层T31在基底上的正投影至少部分重叠。第四遮光部在基底上的正投影与第二晶体管的有源层T21在基底上的正投影至少部分重叠。
在示例性实施方式中，如图15所示，图8提供的显示基板中，遮光部在基底上的正投影与第六晶体管的有源层T61在基底上的正投影至少部分重叠。第一遮光连接部、第二遮光连接部、第三遮光连接部和第四遮光连接部在基底上的正投影与第二晶体管的有源层T21、第三晶体管的有源层T31和第七晶体管的有源层T71中的任一个在基底上的正投影不交叠。
在示例性实施方式中，在示例性实施方式中，如图13至图15所示，位于同一行的相邻子像素的第二晶体管的有源层T21、第三晶体管的有源层T31、第六晶体管的有源层T61和第七晶体管的有源层T71中的任一个相对于沿第二方向D2延伸的虚拟直线对称设置，且位于同一列的所有子像素的第二晶体管的有源层T21、第三晶体管的有源层T31、第六晶体管的有源层T61和第七晶体管的有源层T71中的任一个相同。
在示例性实施方式中，如图13至图15所示，对于同一子像素，第二晶体管的有源层T21、第六晶体管的有源层T61和第七晶体管的有源层T71可以为相互连接的一体结构。第三晶体管的有源层T31可以单独设置。
在示例性实施方式中，如图13至图15所示，子像素的第三晶体管的有源层T31与位于同一行的其中一个相邻子像素的第三晶体管的有源层T31相互连接，子像素的第七晶体管的有源层T71与位于同一行的其中一个相邻子像素的第七晶体管的有源层T71相互连接，子像素的第二晶体管的有源层T21与位于同一行的另一个相邻子像素的第二晶体管的有源层T21相互连接。
在示例性实施方式中，如图13至图15所示，第三晶体管的有源层T31和第七晶体管的有源层T71沿第二方向D2排布。在第一方向D1上，第二晶体管的有源层T21和第七晶体管的有源层T71可以位于子像素的第六晶体管的有源层T61的同一侧，第六晶体管的有源层T61可以位于子像素的第六晶体管的有源层T61的另一侧。在第二方向D2上，第七晶体管的有源层T71可以位于子像素的第六晶体管的有源层T61靠近上一行子像素的一侧，第二晶体管的有源层T21和第三晶体管的有源层T31可以位于子像素的第六晶体管的有源层T61靠近下一行子像素的一侧。
在示例性实施方式中，如图13至图15所示，第二晶体管的有源层T21、第三晶体管的有源层T31和第七晶体管的有源层T71的形状可以为呈“I”字形。第六晶体管的有源层T61的形状可以呈“Ω”字形。
在示例性实施方式中，如图13至图15所示，晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，对于子像素，第二晶体管的有源层T21的第二区T21-2可以作为第六晶体管的有源层T61的第二区T61-2，第六晶体管的有源层T61的第一区T61-1可以作为第七晶体管的有源层T71的第二区T71-2。第三晶体管的有源层T31的第一区T31-1和第二区T31-2和第七晶体管的有源层T71的第一区T71-1可以单独设置。子像素的第七晶体管的有源层T71的第一区T71-1与位于同一行的其中一个相邻子像素的第七晶体管的有源层T71的第一区T71-1为同一区，子像素的第二晶体管的有源层T21的第一区T21-1与位于同一行的另一相邻子像素的第二晶体管的有源层T21的第一区T21-1为同一区。
(3)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖第一半导体层图案的第三绝缘层以及位于第三绝缘层上的第一导电层图案，如图16至图18所示，图16为图7和图8提供的显示基板的第一导电层图案的示意图，图17为图7提供的显示基板形成第一导电层图案后的示意图，图18为图8提供的显示基板形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(Gate1)层。
在示例性实施方式中，如图16至图18所示，第一导电层图案至少可以包括：位于至少一个子像素的第一电容的第一极板C11、第二电容的第一极板C21、第二晶体管的栅电极T22、第三晶体管的栅电极T32、第六晶体管的控制极T62和第七晶体管的栅电极T72以及至少部分沿第一方向D1延伸的发光信号线EM、第二扫描信号线Gate2和第三扫描信号线Gate3。
在示例性实施方式中，如图16至图18所示，位于同一行的相邻子像素的第一电容的第一极板和第二电容的第一极板中的任一个相对于沿第二方向D2延伸的虚拟直线对称设置，且位于同一列的所有子像素的第一电容的第一极板和第二电容的第一极板中的任一个相同。
在示例性实施方式中，如图16至图18所示，子像素的第一电容的第一极板C11和第二电容的第一极板C21沿第二方向D2排布，子像素的第二电容的第一极板C21可以位于第一电容的第一极板C11靠近上一行子像素的一侧。
在示例性实施方式中，如图16至图18所示，第一电容的第一极板C11的形状可以为矩形状，且矩形状的角部可以设置倒角，第一电容的第一极板C11在基底上的正投影与第六晶体管的有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，如图16至图18所示，第二电容的第一极板C21的形状可以为矩形状，且矩形状的角部可以设置倒角，第二电容的第一极板C21在基底上的正投影与第六晶体管的有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第二电容的第一极板C21可以同时作为第六晶体管的控制极T62。
在示例性实施方式中，第二电容的第一极板C21的面积可以大于第一电容的第一极板C11的面积。
在示例性实施方式中，如图16至图18所示，第二扫描信号线Gate2的形状可以为沿着第一方向D1延伸的线性状，子像素连接的第二扫描信号线Gate2可以位于子像素的第一电容的第一极板C11远离子像素的第二电容的第一极板C21(也是第六晶体管的栅电极T62)的一侧。第二扫描信号线Gate2与第二晶体管的有源层相交叠的区域作为第二晶体管的栅电极T22。
在示例性实施方式中，如图16至图18所示，第三扫描信号线Gate3的形状可以为沿着第一方向D1延伸的线性状，子像素连接的第三扫描信号线Gate3可以位于子像素连接的第二扫描信号线Gate2远离子像素的第一电容的第一极板C11的一侧。第三扫描信号线Gate3与第三晶体管的有源层相交叠的区域作为第三晶体管的栅电极T32。
在示例性实施方式中，如图16至图18所示，发光信号线EM的形状可以为沿着第一方向D1延伸的线性状。子像素连接的发光信号线EM可以位于子像素的第二电容的第一极板C21(也是第六晶体管的栅电极T62)远离子像素的第一电容的第一极板C11的一侧。发光信号线EM与第七晶体管的有源层相交叠的区域作为第七晶体管的栅电极T72。
在示例性实施方式中，第二扫描信号线Gate2、第三扫描信号线Gate3和发光信号线 EM可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对第一半导体层进行导体化处理，被第一导电层遮挡区域的第一半导体层形成第二晶体管、第三晶体管、第六晶体管和第七晶体管T7的沟道区，未被第一导电层遮挡区域的第一半导体层被导体化，即第一晶体管的有源层、第二晶体管的有源层、第六晶体管的有源层和第七晶体管的有源层中的任一个有源层的第一区和第二区均被导体化。
在示例性实施方式中，第二晶体管的栅电极T22跨设在第二晶体管的有源层上，第三晶体管的栅电极T32跨设在第三晶体管的有源层上，第六晶体管的栅电极T62跨设在第六晶体管的有源层上，第七晶体管的栅电极T72跨设在第七晶体管的有源层上，也就是说，至少一个晶体管的栅电极的延伸方向与有源层的延伸方向相互垂直。
(4)形成第二导电层图案，包括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第二导电薄膜，通过图案化工艺对第四绝缘薄膜和第二导电薄膜进行图案化，形成第四绝缘层以及位于第四绝缘层上的第二导电层图案，如图19至图21所示，图19为图7和图8提供的显示基板的第二导电层图案的示意图，图20为图7提供的显示基板形成第二导电层图案后的示意图，图21为图8提供的显示基板形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图19至图21所示，第二导电层至少可以包括：位于至少一个子像素的第一电容的第二极板C12和第二电容的第二极板C22以及至少部分沿第一方向D1延伸的第一扫描信号线的第一子信号线Gate1A和第四扫描信号线的第三子信号线Gate4A。
在示例性实施方式中，位于同一行的相邻子像素的第一电容的第二极板C12和第二电容的第二极板C22中的任一个相对于沿第二方向D2延伸的虚拟直线对称设置，且位于同一列的所有子像素的第一电容的第二极板C12和第二电容的第二极板C22中的任一个相同。
在示例性实施方式中，如图19至图21所示，第一电容的第二极板C12和第二电容的第二极板C22可以为相互连接的一体结构。第一电容的第二极板C12(也是第二电容的第二极板C22)的轮廓可以为矩形状，矩形状的角部可以设置倒角，第一电容的第二极板C12(也是第二电容的第二极板C22)在基底上的正投影与第一电容的第一极板和第二电容的第一极板在基底上的正投影至少部分交叠。
在示例性实施方式中，如图19至图21所示，第一电容的第二极板C12(第二电容的第二极板C22)设置有第一过孔V1和第二过孔V2，第一过孔V1和第二过孔V2的形状可以为可以为矩形状，且位于第一电容的第二极板C12(第二电容的第二极板C22)的中部。其中，第一过孔V1暴露出覆盖第一电容的第一极板的第四绝缘层，且第一电容的第一极板在基底上的正投影包含第一过孔在基底上的正投影。在示例性实施方式中，第一过孔V1暴露出第一电容的第一极板，使后续形成的第一连接电极与第一电容的第一极板连接。第二过孔V2暴露出覆盖第二电容的第一极板的第四绝缘层，且第二电容的第一极板在基底上的正投影包含第二过孔在基底上的正投影。在示例性实施方式中，第二过孔V2暴露出第二电容的第一极板，使后续形成的第一晶体管的第二极与第二电容的第一极板连接。
在示例性实施方式中，如图19至图21所示，第一扫描信号线的第一子信号线Gate1A的形状可以为至少部分沿着第一方向D1延伸的线形状，子像素连接的第一扫描信号线的 第一子信号线Gate1A可以位于子像素的第一电容的第二极板C12(第二电容的第二极板C22)靠近上一个子像素的一侧，且与后续形成的子像素的第一晶体管的有源层相重叠的区域作为第一晶体管的第一栅电极T12A，与后续形成的子像素的第四晶体管的有源层相重叠的区域作为第四晶体管的第一栅电极T42A。
在示例性实施方式中，如图19至图21所示，子像素连接的第一扫描信号线的第一子信号线Gate1A在基底上的正投影可以位于子像素连接的发光信号线在基底上的正投影和子像素的第二电容的第一极板在基底上的正投影之间。
在示例性实施方式中，如图19至图21所示，第四扫描信号线的第三子信号线Gate4A的形状可以为至少部分沿着第一方向D1延伸的线形状，子像素连接的第四扫描信号线的第三子信号线Gate4A可以位于子像素连接的第一扫描信号线的第一子信号线Gate1A远离子像素的第一电容的第二极板C12(第二电容的第二极板C22)的一侧，且与后续形成的子像素的第五晶体管的有源层相重叠的区域作为第五晶体管的第一栅电极T52A。
在示例性实施方式中，如图19至图21所示，子像素连接的第四扫描信号线的第三子信号线Gate4A在基底上的正投影可以位于子像素连接的发光信号线在基底上的正投影远离子像素的第二电容的第一极板在基底上的正投影的一侧。
在示例性实施方式中，第一扫描信号线的第一子信号线Gate1A和第四扫描信号线的第三子信号线Gate4A可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
(5)形成第二半导体层图案，包括：在形成前述图案的基底上，包括：在基底上依次沉积第五绝缘薄膜和第二半导体薄膜，通过图案化工艺对第五绝缘薄膜和第二半导体薄膜进行图案化，形成第五绝缘层以及位于第五绝缘层上的第二半导体层图案，如图22至图24所示，图22为图7和图8提供的显示基板的第二半导体层图案的示意图，图23为图7提供的显示基板形成第二半导体层图案后的示意图，图24为图8提供的显示基板形成第二半导体层图案后的示意图。
在示例性实施方式中，如图22至图24所示，第二半导体层至少可以包括：位于至少一个子像素的第一晶体管的有源层T11、第四晶体管的有源层T41和第五晶体管的有源层T51。
在示例性实施方式中，第四晶体管的有源层T41和第五晶体管的有源层T51为相互连接的一体结构。第一晶体管的有源层T11单独设置。
在示例性实施方式中，如图22至图24所示，位于同一行的相邻子像素的第一晶体管的有源层T11、第四晶体管的有源层T41和第五晶体管的有源层T51中的任一个相对于沿第二方向D2延伸的虚拟直线对称设置，且位于同一列的所有子像素的第一晶体管的有源层T11、第四晶体管的有源层T41和第五晶体管的有源层T51中的任一个相同。
在示例性实施方式中，如图22至图24所示，在第一方向D1上，子像素的第一晶体管的有源层T11可以位于第四晶体管的有源层T41靠近上一行子像素或者靠近下一行子像素的一侧。在第二方向D2上，子像素的第五晶体管的有源层T51可以位于子像素的第四晶体管的有源层T41靠近上一行子像素的一侧。
在示例性实施方式中，如图22至图24所示，第一晶体管的有源层T11和第五晶体管的有源层T51的形状可以呈“I”字形。第四晶体管的有源层T41的形状可以呈水平翻转的“L”字形。
在示例性实施方式中，如图22至图24所示，子像素的第一晶体管的有源层T11在基底上的正投影与子像素连接的第一扫描信号线的第一子信号线Gate1A、子像素连接的发光信号线和子像素的第一电容的第二极板(也是第二电容的第二极板)在基底上的正投影至少部分交叠。
在示例性实施方式中，如图22至图24所示，子像素的第一晶体管的有源层T11在基底上的正投影与子像素连接的第一扫描信号线的第一子信号线Gate1A和子像素连接的发光信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，子像素的第五晶体管的有源层T51在基底上的正投影与子像素连接的第四扫描信号线的第三子信号线Gate4A在基底上的正投影交叠。
在示例性实施方式中，位于第二导电层的每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第四晶体管的有源层的第一区T41-1可以同时作为第五晶体管的有源层的第二区T51-2。第一晶体管的有源层T11的第一区T11-1和第二区T11-2、第四晶体管的有源层的第二区T41-2和第五晶体管的有源层的第一区T51-1可以单独设置。
在示例性实施方式中，第一晶体管的有源层T11跨设在第一晶体管的第一栅电极上，第四晶体管的有源层T41跨设在第四晶体管的第一栅电极上，第五晶体管的有源层T51跨设在第五晶体管的第一栅电极上。
(6)形成第三导电层，包括：在形成前述图案的基底上，依次沉积第六绝缘薄膜和第三导电薄膜，通过图案化工艺对第六绝缘薄膜和第三导电薄膜进行图案化，形成第六绝缘层图案以及位于第六绝缘层上的第三导电层图案，如图25至图27所示，图25为图7和图8提供的显示基板的第三导电层图案的示意图，图26为图7提供的显示基板形成第三导电层图案后的示意图，图27为图8提供的显示基板形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第三栅金属(GATE3)层。
在示例性实施方式中，如图25至图27所示，第三导电层至少可以包括：至少部分沿第一方向D1延伸的第一扫描信号线的第二子信号线Gate1B、第四扫描信号线的第四子信号线Gate4B、电源连接线VCL、第一初始信号线INIT1、第二初始信号线INIT2和第三初始信号线INIT3。
在示例性实施方式中，如图25至图27所示，第一扫描信号线的第二子信号线Gate1B可以为沿着第一方向D1延伸的线形状。第一扫描信号线的第二子信号线Gate1B在基底上的正投影与第一扫描信号线的第一子信号线在基底上的正投影至少部分交叠，且与第一扫描信号线的第一子信号线电连接。子像素连接的第一扫描信号线的第二子信号线Gate1B与子像素的第二晶体管的有源层相重叠的区域作为第二晶体管的第二栅电极T22B，子像素连接的第一扫描信号线的第二子信号线Gate1B与子像素的第四晶体管的有源层相重叠的区域作为第四晶体管的第二栅电极T42B。第一晶体管的第一栅电极和第二栅电极组成第一晶体管的栅电极。第四晶体管的第一栅电极和第二栅电极组成第四晶体管的栅电极。
在示例性实施方式中，如图25至图27所示，子像素连接的第一扫描信号线的第二子信号线Gate1B在基底上的正投影可以位于子像素连接的发光信号线在基底上的正投影和子像素的第二电容的第一极板在基底上的正投影之间。
在示例性实施方式中，如图25至图27所示，第四扫描信号线的第四子信号线Gate4B可以为沿着第一方向D1延伸的线形状。第四扫描信号线的第四子信号线Gate4B在基底上的正投影与第四扫描信号线的第三子信号线在基底上的正投影至少部分交叠，且与第四 扫描信号线的第三子信号线电连接。子像素连接的第四扫描信号线的第四子信号线Gate4B与子像素的第五晶体管的有源层相重叠的区域作为第五晶体管的第二栅电极T52B。第五晶体管的第一栅电极和第二栅电极组成第五晶体管的栅电极。
在示例性实施方式中，如图25至图27所示，子像素连接的第四扫描信号线的第四子信号线Gate4B在基底上的正投影可以位于子像素连接的发光信号线在基底上的正投影远离子像素的第二电容的第一极板在基底上的正投影的一侧。
在示例性实施方式中，如图25至图27所示，电源连接线VCL可以为主体部分沿着第一方向D1延伸的线形状。子像素连接的电源连接线VCL可以位于子像素连接的第一扫描信号线的第二子信号线Gate1B远离子像素连接的第四扫描信号线的第四子信号线Gate4B的一侧。电源连接线VCL在基底上的正投影与第一电容的第二极板(也是第二电容的第二极板)在基底上的正投影之至少部分交叠。
在示例性实施方式中，如图25至图27所示，子像素连接的电源连接线VCL在基底上的正投影可以位于子像素连接的第一扫描信号线的第一子信号线在基底上的正投影和子像素连接的第二扫描信号线在基底上的投影之间。
在示例性实施方式中，如图25至图27所示，电源连接线VCL可以包括：信号主体线30、第一凸起部31、第二凸起部32和第三凸起部33。信号主体线30、第一凸起部31、第二凸起部32和第三凸起部33可以为相互连接的一体结构。其中，第一凸起部31可以位于信号主体线30靠近第一扫描信号线的第二子信号线Gate1B的一侧，第二凸起部32和第三凸起部33可以位于信号主体线30远离第一扫描信号线的第二子信号线Gate1B的一侧，且第二凸起部32和第三凸起部33沿第一方向D1排布。
在示例性实施方式中，如图25至图27所示，信号主体线30可以为沿第一方向D1延伸的线形状。第一凸起部31、第二凸起部32和第三凸起部33的形状可以为矩形状。
在示例性实施方式中，如图25至图27所示，第二凸起部32和第三凸起部33在基底上的正投影与第一电容的第二极板(也是第二电容的第二极板)在基底上的正投影至少部分交叠。
示例性实施方式中，如图25至图27所示，第一初始信号线INIT1和第二初始信号线INIT2为同一信号线，且可以为主体部分沿第一方向D1延伸的线形状。子像素连接的第一初始信号线INIT1(也是第二初始信号线INIT2)位于子像素连接的电源连接线VCL远离第一扫描信号线的第二子信号线Gate1B的一侧。第一初始信号线INIT1(也是第二初始信号线INIT2)在基底上的正投影与第二扫描信号线在基底上的正投影至少部分交叠。
示例性实施方式中，如图25至图27所示，子像素连接的第一初始信号线INIT1(也是第二初始信号线INIT2)在基底上的正投影位于子像素的第一电容的第一极板在基底上的正投影和子像素连接的第三扫描信号线在基底上的正投影之间。
示例性实施方式中，如图25至图27所示，第三初始信号线INIT3可以为主体部分沿第一方向D1延伸的线形状。第三初始信号线INIT3位于第一初始信号线INIT1(也是第二初始信号线INIT2)远离电源连接线VCL的一侧。子像素连接的第三初始信号线INIT3在基底上的正投影与子像素连接的第三扫描信号线在基底上的正投影至少部分交叠。
示例性实施方式中，如图25至图27所示，子像素连接的第三初始信号线INIT3在基底上的正投影位于子像素连接的第二扫描信号线在基底上的正投影远离子像素连接的第一电容的第一极板在基底上的正投影的一侧。
在示例性实施方式中，第一扫描信号线的第二子信号线Gate1B、第四扫描信号线的 第四子信号线Gate4B、电源连接线VCL、第一初始信号线INIT1、第二初始信号线INIT2和第三初始信号线INIT3可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，形成第三导电层图案后，可以利用第三导电层作为遮挡，对第二半导体层进行导体化处理，被第三导电层遮挡区域的第二半导体层形成第一晶体管、第四晶体管和第五晶体管的有源层的沟道区，未被第三导电层遮挡区域的第二半导体层被导体化，即第一晶体管、第四晶体管和第五晶体管的有源层的第一区和第二区均被导体化。
(7)形成第七绝缘层图案。在示例性实施方式中，形成第七绝缘层图案可以包括：在形成前述图案的基底上，沉积第七绝缘薄膜，采用图案化工艺对第七绝缘薄膜进行图案化，形成覆盖第三导电层的第七绝缘层，第七绝缘层上设置有多个过孔，如图28和图29所示，图28为图7提供的显示基板形成第七绝缘层图案后的示意图，图29为图8提供的显示基板形成第七绝缘层图案后的示意图。
在示例性实施方式中，如图28和图29所示，第七绝缘层的多个过孔至少可以包括：位于至少一个子像素的第三过孔V3至第十九过孔V19。
在示例性实施方式中，子像素的第三过孔与位于同一行的其中一个相邻子像素的第三过孔为同一过孔，子像素的第五过孔与位于同一行的另一个相邻子像素的第五过孔为同一过孔，子像素的第七过孔与位于同一行的另一个相邻子像素的第七过孔为同一过孔。
在示例性实施方式中，如图28和图29所示，第三过孔V3在基底上的正投影位于第二晶体管的有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层被刻蚀掉，暴露出第二晶体管的有源层的第一区的表面，第三过孔V3被配置为使后续形成的第二晶体管的第一极(也是初始连接线ICL)通过该过孔与第二晶体管的有源层的第一区连接。
在示例性实施方式中，如图28和图29所示，第四过孔V4在基底上的正投影位于第二晶体管的有源层的第二区(也是第六晶体管的有源层的第二区)在基底上的正投影的范围之内，第四过孔V4内的第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层被刻蚀掉，暴露出第二晶体管的有源层的第二区(也是第六晶体管的有源层的第二区)的表面，第四过孔V4被配置为使后续形成的第二晶体管的第二极(也是第六晶体管的第二极)通过该过孔与第二晶体管的有源层的第二区(也是第六晶体管的有源层的第二区)连接。
在示例性实施方式中，如图28和图29所示，第五过孔V5在基底上的正投影位于第三晶体管的有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层被刻蚀掉，暴露出第三晶体管的有源层的第一区的表面，第五过孔V5被配置为使后续形成的第三晶体管的第一极通过该过孔与第三晶体管的有源层的第一区连接。
在示例性实施方式中，如图28和图29所示，第六过孔V6在基底上的正投影位于第三晶体管的有源层的第二区在基底上的正投影的范围之内，第六过孔V6内的第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层被刻蚀掉，暴露出第三晶体管的有源层的第二区的表面，第六过孔V6被配置为使后续形成的第三晶体管的第二极(也是第四晶体管的第二极、第六晶体管的第一极和第七晶体管的第二极)通过该过孔与第三晶体管的有源层的第二区连接。
在示例性实施方式中，如图28和图29所示，第七过孔V7在基底上的正投影位于第七晶体管的有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第三绝缘层、 第四绝缘层、第五绝缘层和第六绝缘层被刻蚀掉，暴露出第七晶体管的有源层的第一区的表面，第七过孔V7被配置为使后续形成的第七晶体管的第一极通过该过孔与第七晶体管的有源层的第一区连接。
在示例性实施方式中，如图28和图29所示，第八过孔V8在基底上的正投影位于第七晶体管的有源层的第二区(也是第六晶体管的第一区)在基底上的正投影的范围之内，第八过孔V8内的第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层被刻蚀掉，暴露出第七晶体管的有源层的第二区(也是第六晶体管的第一区)的表面，第八过孔V8被配置为使后续形成的第三晶体管的第二极(也是第四晶体管的第二极、第六晶体管的第一极和第七晶体管的第二极)通过该过孔与第七晶体管的有源层的第二区(也是第六晶体管的第一区)连接。
在示例性实施方式中，如图28和图29所示，第九过孔V9在基底上的正投影位于第一过孔在基底上的正投影的范围之内，第九过孔V9内的第五绝缘层和第六绝缘层被刻蚀掉，暴露出第一电容的第一极板的表面，第九过孔V9被配置为使后续形成的第一连接电极通过该过孔与第一电容的第一极板连接。
在示例性实施方式中，如图28和图29所示，第十过孔V10在基底上的正投影位于第二过孔在基底上的正投影的范围之内，第十过孔V10内的第五绝缘层和第六绝缘层被刻蚀掉，暴露出第二电容的第一极板(也是第六晶体管的栅电极)的表面，第十过孔V10被配置为使后续形成的第一晶体管的第二极通过该过孔与第二电容的第一极板(也是第六晶体管的栅电极)连接。
在示例性实施方式中，如图28和图29所示，第十一过孔V11在基底上的正投影位于第一电容的第二极板(也是第二电容的第二极板)在基底上的正投影的范围之内，第十一过孔V11内的第五绝缘层和第六绝缘层被刻蚀掉，第十一过孔V11暴露出第一电容的第二极板(也是第二电容的第二极板)的表面，第十一过孔V11被配置为使后续形成的第四晶体管的第一极(也是第五晶体管的第二极)通过该过孔与第一电容的第二极板(也是第二电容的第二极板)连接。
在示例性实施方式中，如图28和图29所示，第十二过孔V12在基底上的正投影位于第一晶体管的有源层的第一区在基底上的正投影的范围之内，第十二过孔V12内的第六绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第一区的表面，第十二过孔V12被配置为使后续形成的第一晶体管的第一极通过该过孔与第一晶体管的有源层的第一区连接。
在示例性实施方式中，如图28和图29所示，第十三过孔V13在基底上的正投影位于第一晶体管的有源层的第二区在基底上的正投影的范围之内，第十三过孔V13内的第六绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第二区的表面，第十三过孔V13被配置为使后续形成的第一晶体管的第二极通过该过孔与第一晶体管的有源层的第二区连接。
在示例性实施方式中，如图28和图29所示，第十四过孔V14在基底上的正投影位于第四晶体管的有源层的第一区(也是第五晶体管的有源层的第二区)在基底上的正投影的范围之内，第十四过孔V14内的第六绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区(也是第五晶体管的有源层的第二区)的表面，第十四过孔V14被配置为使后续形成的第四晶体管的第一极(也是第五晶体管的第二极)通过该过孔与第四晶体管的有源层的第一区(也是第五晶体管的有源层的第二区)连接。
在示例性实施方式中，如图28和图29所示，第十五过孔V15在基底上的正投影位于第四晶体管的有源层的第二区在基底上的正投影的范围之内，第十五过孔V15内的第六绝缘层被刻蚀掉，第暴露出第四晶体管的有源层的第二区的表面，第十五过孔V15被 配置为使后续形成的第三晶体管的第二极(也是第四晶体管的第二极、第六晶体管的第一极和第七晶体管的第二极)通过该过孔与第四晶体管的有源层的第二区连接。
在示例性实施方式中，如图28和图29所示，第十六过孔V16在基底上的正投影位于第五晶体管的有源层的第一区在基底上的正投影的范围之内，第十六过孔V16内的第六绝缘层被刻蚀掉，第十五过孔V15暴露出第五晶体管的有源层的第一区的表面，第十六过孔V16被配置为使后续形成的第五晶体管的第一极通过该过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，如图28和图29所示，第十七过孔V17在基底上的正投影位于电源连接线在基底上的正投影的范围之内，暴露出电源连接线的表面，第十七过孔V17被配置为使后续形成的第一连接电极通过该过孔与电源连接线连接。
在示例性实施方式中，如图28和图29所示，第十八过孔V18在基底上的正投影位于第一初始信号线(也是第二初始信号线)在基底上的正投影的范围之内，暴露出第一初始信号线(也是第二初始信号线)的表面，第十八过孔V18被配置为使后续形成的第二晶体管的第一极(也是初始连接线ICL)通过该过孔与第一初始信号线(也是第二初始信号线)连接。
在示例性实施方式中，如图28和图29所示，第十九过孔V19在基底上的正投影位于第三初始信号线在基底上的正投影的范围之内，暴露出第三初始信号线的表面，第十九过孔V19被配置为使后续形成的第三晶体管的第一极通过该过孔与第三初始信号线连接。
在示例性实施方式中，沿第二方向D2延伸的虚拟直线可以经过第三过孔V3和第十八过孔V18。
在示例性实施方式中，沿第二方向D2延伸的虚拟直线可以经过第五过孔V5和第十九过孔V19。
在示例性实施方式中，沿第二方向D2延伸的虚拟直线可以经过第八过孔V8和第十五过孔V15。
(9)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第七绝缘层上的第四导电层图案，图30至图32所示，如图30至图32所示，图30为图7和图8提供的显示基板的第四导电层图案的示意图，图31为图7提供的显示基板形成第四导电层图案后的示意图，图32为图8提供的显示基板形成第四导电层图案后的示意图。在示例性实施方式中，第四导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图30至图32所示，第四导电层图案至少可以包括：至少部分沿第二方向D2延伸的初始连接线ICL以及位于至少一个子像素的第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23和第二极T24、第三晶体管的第一极T33和第二极T34、第四晶体管的第一极T43和第二极T44、第五晶体管的第一极T53和第二极T54、第六晶体管的第一极T63和第二极T64、第七晶体管的第一极T73和第二极T74以及第一连接电极VL1。
在示例性实施方式中，如图30至图32所示，位于同一行的相邻子像素的第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23和第二极T24、第三晶体管的第一极T33和第二极T34、第四晶体管的第一极T43和第二极T44、第五晶体管的第一极T53和第二极T54、第六晶体管的第一极T63和第二极T64、第七晶体管的第一极T73和第二极T74以及第一连接电极VL1中的任一个相对于沿第二方向D2延伸的虚拟直线对称设置。
在示例性实施方式中，如图30至图32所示，初始连接线ICL位于第二晶体管的有源层相互连接的相邻两列子像素之间，且分别与相邻的两列子像素电连接。初始连接线ICL与相邻的两列子像素的对称轴相重合。
在示例性实施方式中，如图30至图32所示，初始连接线ICL的形状可以为沿第二方向D2延伸的线形状。初始连接线ICL与第二晶体管的有源层的第一区的交叠区域同时可以作为第二晶体管的第一极T23。初始连接线ICL(也是第二晶体管的第一极T23)通过第三过孔与第二晶体管的有源层的第一区连接，且通过第十八过孔与第一初始信号线(也是第二初始信号线)连接。
在示例性实施方式中，如图30至图32所示，在第一方向D1上，位于至少一个子像素的第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23和第二极T24、第三晶体管的第一极T33和第二极T34、第四晶体管的第一极T43和第二极T44、第五晶体管的第一极T53和第二极T54、第六晶体管的第一极T63和第二极T64、第七晶体管的第一极T73和第二极T74以及第一连接电极VL1可以位于初始连接线ICL的同一侧。
在示例性实施方式中，如图30至图32所示，第一晶体管的第一极T13与初始连接线ICL为相互连接的一体结构。第一晶体管的第一极T13的形状可以为沿第一方向D1延伸的线形状。第一晶体管的第一极T13通过第十二过孔V12与第一晶体管的有源层的第一区连接。
在示例性实施方式中，如图30至图32所示，第一晶体管的第二极T14单独设置。第一晶体管的第二极T14的形状可以为块状。第一晶体管的第二极T14通过第十三过孔与第一晶体管的有源层的第二区连接，且通过第十过孔与第二电容的第一极板(也是第六晶体管的栅电极)连接。
在示例性实施方式中，如图30至图32所示，第二晶体管的第二极T24和第六晶体管的第二极T64可以为相互连接的一体结构。第二晶体管的第二极T24(也是第六晶体管的第二极T64)的形状可以为哑铃状。第二晶体管的第二极T24(也是第六晶体管的第二极T64)可以通过第四过孔与第二晶体管的有源层的第二区(也是第六晶体管的有源层的第二区)连接。
在示例性实施方式中，如图30至图32所示，第三晶体管的第一极T33单独设置。第三晶体管的第一极T33的形状可以为块状。第三晶体管的第一极T33通过第五过孔与第三晶体管的有源层的第一区连接，且通过第十九过孔与第三初始信号线连接。
在示例性实施方式中，如图30至图32所示，第三晶体管的第二极T34、第四晶体管的第二极T44、第六晶体管的第一极T63和第七晶体管的第二极T74可以为相互连接的一体结构。第三晶体管的第二极T34(也是第四晶体管的第二极T44、第六晶体管的第一极T63和第七晶体管的第二极T74)的形状可以为沿第二方向D2延伸的哑铃状。第三晶体管的第二极T34(也是第四晶体管的第二极T44、第六晶体管的第一极T63和第七晶体管的第二极T74)通过第六过孔与第三晶体管的有源层的第二区连接，通过第八过孔与第七晶体管的有源层的第二区(也是第六晶体管的第一区)连接，且通过第十五过孔与第四晶体管的有源层的第二区连接。
在示例性实施方式中，如图30至图32所示，第四晶体管的第一极T43和第五晶体管的第二极T54为可以为相互连接的一体结构。第四晶体管的第一极T43(也是第五晶体管的第二极T54)的形状可以为主体部分沿第二方向D2延伸的哑铃状。第四晶体管的第一极T43(也是第五晶体管的第二极T54)通过第十一过孔与第一电容的第二极板(也是第二电容的第二极板)，通过第十四过孔与第四晶体管的有源层的第一区(也是第五晶体 管的有源层的第二区)连接。
在示例性实施方式中，如图30至图32所示，第五晶体管的第一极T53单独设置。第五晶体管的第一极T53的形状可以为沿第一方向D1延伸的条状。第五晶体管的第一极T53通过第十六过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，如图30至图32所示，第七晶体管的第一极T73单独设置。第七晶体管的第一极T73的形状可以为葫芦状。第七晶体管的第一极T73通过第七过孔与第七晶体管的有源层的第一区连接。
在示例性实施方式中，如图30至图32所示，第一连接电极VL1可以为矩形状。第一连接电极VL1通过第十七过孔与电源连接线连接，且通过第九过孔与第一电容的第一极板连接。
在示例性实施方式中，如图30至图32所示，第一连接电极在基底上的正投影与电源连接线的第二凸起部和第三凸起部在基底上的正投影至少部分交叠。
(10)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，沉积第八绝缘薄膜，采用图案化工艺对第八绝缘薄膜进行图案化，形成覆盖第四导电层的第八绝缘层，在第八绝缘层上涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成覆盖前述图案的第一平坦层图案，第一平坦层开设有多个过孔图案，如图33和图34所示，图33为图7提供的显示基板形成第八绝缘层图案后的示意图，图34为图8提供的显示基板形成第八绝缘层图案后的示意图。
在示例性实施方式中，如图33和图34所示，第一平坦层的多个过孔至少可以包括：第二十过孔V20至第二十三过孔V23。
在示例性实施方式中，如图33和图34所示，第二十过孔V20在基底上的正投影位于第二晶体管的第二极(也是第六晶体管的第二极)在基底上的正投影的范围之内，第二十过孔V20内的第八绝缘层被刻蚀掉，暴露出第二晶体管的第二极(也是第六晶体管的第二极)的表面，第二十过孔V20被配置为使后续形成的第二连接电极通过该过孔与第二晶体管的第二极(也是第六晶体管的第二极)连接。
在示例性实施方式中，如图33和图34所示，第二十一过孔V21在基底上的正投影位于第五晶体管的第一极在基底上的正投影的范围之内，第二十一过孔V21内的第八绝缘层被刻蚀掉，暴露出第五晶体管的第一极的表面，第二十一过孔V21被配置为使后续形成的数据信号线通过该过孔与第五晶体管的第一极连接。
在示例性实施方式中，如图33和图34所示，第二十二过孔V22在基底上的正投影位于第七晶体管的第一极在基底上的正投影的范围之内，第二十二过孔V22内的第八绝缘层被刻蚀掉，暴露出第七晶体管的第一极的表面，第二十二过孔V22被配置为使后续形成的第一电源线通过该过孔与第七晶体管的第一极连接。
在示例性实施方式中，如图33和图34所示，第二十三过孔V23在基底上的正投影位于第一连接电极在基底上的正投影的范围之内，第二十三过孔V23内的第八绝缘层被刻蚀掉，暴露出第一连接电极的表面，第二十三过孔V23被配置为使后续形成的第一电源线通过该过孔与第一连接电极连接。
(11)形成第五导电层图案，包括：在形成前述图案的基底上，沉积第五导电薄膜，通过图案化工艺对第五导电薄膜进行图案化，形成第五导电层图案，如图35至图37所示，图35为图7和图8提供的显示基板的第五导电层图案的示意图，图36为图7提供的显示基板形成第五导电层图案后的示意图，图37为图8提供的显示基板形成第五导电层图案 后的示意图。在示例性实施方式中，第五导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图35至图37所示，第五导电层至少可以包括：位于至少一个子像素的第二连接电极VL2以及至少部分沿第二方向D2延伸的数据信号线Data和第一电源线VDD。多条数据信号线Data沿第一方向D1排布，多条第一电源线VDD沿第一方向D1排布。
在示例性实施方式中，如图35至图37所示，相邻子像素连接的数据信号线Data相对于沿第二方向D2延伸的虚拟直线轴对称。相邻子像素连接的第一电源线VDD相对于沿第二方向D2延伸的虚拟直线轴对称。
在示例性实施方式中，如图35至图37所示，子像素连接的数据信号线Data和第一电源线VDD位于子像素的第二连接电极的不同侧。
在示例性实施方式中，如图35至图37所示，第一电源线VDD与其中一条相邻电源线连接，且与另一条相邻电源线之间间隔设置。间隔设置的两条第一电源线之间设置有两条数据信号线Data。
在示例性实施方式中，如图35至图37所示，初始连接线ICL在基底上的正投影位于初始连接线ICL所连接的相邻两列子像素连接的数据信号线在基底上的正投影之间，子像素连接的第一电源线在基底上的正投影位于子像素连接的数据信号线远离子像素连接的初始连接线ICL的一侧。
在示例性实施方式中，如图35至图37所示，数据信号线Data的形状可以为主体部分沿第二方向D2延伸的线形状。子像素连接的数据信号线Data通过第二十一过孔与子像素的第五晶体管的第一极连接。
在示例性实施方式中，如图35至图37所示，第一电源线VDD的形状可以为主体部分沿第二方向D2延伸的线形状。子像素连接的第一电源线VDD通过第二十二过孔与第七晶体管的第一极连接，且通过第二十三过孔与第一连接电极连接。
在示例性实施方式中，如图35至图37所示，第一电源线VDD在基底上的正投影与第一电容的第二极板(也是第二电容的第二极板)以及电源连接线的信号主体部和第二凸起部在基底上的正投影至少部分交叠。
在示例性实施方式中，如图35至图37所示，第二连接电极VL2的形状可以为至少部分沿第二方向D2的线形状或者葫芦状。第二连接电极VL2通过第二十三过孔与第二晶体管的第二极(也是第六晶体管的第二极)连接，且被配置为与后续形成的发光器件的阳极连接。不同发光器件的阳极连接的连接电极的形状可以不同。
在示例性实施方式中，第一电源线VDD的宽度可以大于数据信号线Data的宽度。
(12)形成第二平坦层图案，包括：在形成有前述图案的基底上，涂覆第二平坦薄膜，通过图案化工艺对第二平坦薄膜进行图案化，形成覆盖前述图案的第二平坦层图案。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个像素驱动电路，像素驱动电路与第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、发光信号线、第一初始信号线、第二初始信号线、第三初始信号线、数据信号线和第一电源线连接。驱动电路层可以设置在基底上。驱动电路层可以包括在基底上依次设置的第一绝缘层、遮光层、第二绝缘层、第一半导体层、第三绝缘层、第一导电层、第四绝缘层、第二导电层、第五绝缘层、第二半导体层、第六绝缘层、第三导电层、第七绝缘层、第四导电层、第八绝缘层、第一平坦层、第五导电层和第二平坦层。
在示例性实施方式中，第一半导体层可以为非晶硅层或者多晶硅层。
在一种示例示例性实施例中，第二半导体层可以为金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层、第六绝缘层、第七绝缘层和第八绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
在示例性实施方式中，第一平坦层和第二平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第二平坦层上的阳极导电层图案，在形成前述图案的基底上，沉积像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成暴露出阳极导电层图案的像素定义层图案，在形成有像素定义层图案的基底上，涂覆有机发光材料，通过图案化工艺对有机发光材料进行图案化，形成有机结构层图案，在形成有机材料层图案的基底上，沉积阴极导电薄膜，通过图案化工艺对阴极导电薄膜进行图案化，形成阴极导电层。
至此，在基底上制备完成发光结构层。
在示例性实施方式中，后续制备流程可以包括：在阴极导电层上形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，阳极导电层至少包括多个阳极图案。其中，多个阳极图案可以包括第一发光器件的阳极、第二发光器件的阳极、第三发光器件的阳极和第四发光器件的阳极，第一发光器件的阳极位于出射红色光线的红色子像素，第二发光器件的阳极可以位于出射蓝色光线的蓝色子像素，第三发光器件的阳极可以位于出射绿色光线的第一绿色子像素，第四发光器件的阳极可以位于出射绿色光线的第二绿色子像素。
在示例性实施方式中，第一发光器件的阳极和第二发光器件的阳极可以沿着第一方向D1交替设置，第三发光器件的阳极和第四发光器件的阳极可以沿着第一方向D1交替设置。或者，第一发光器件的阳极和第二发光器件的阳极可以沿着第二方向D2交替设置，第三发光器件的阳极和第四发光器件的阳极可以沿着第二方向D2交替设置。
在示例性实施方式中，一个像素单元中四个子像素的阳极形状和面积可以相同，或者可以不同。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，有机结构层至少可以包括：发光器件的有机发光层。
在示例性实施方式中，阴极导电层至少可以包括：多个发光器件的阴极。
在示例性实施方式中，阴极层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述导电的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。示例性地，第四导电层可以为钛、铝和钛形成的三层堆叠结构。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。
本公开实施例还提供了一种像素驱动电路的驱动方法，设置驱动像素驱动电路，本公开实施例提供的像素驱动电路的驱动方法可以包括以下步骤：
步骤100、节点控制子电路在第一扫描信号线、第二扫描信号线、第三扫描信号线和第四扫描信号线的信号的控制下，通过第一初始信号线、数据信号线和第一电源线的信号带动第一节点的信号，向第二节点提供第二初始信号线的信号，向第三节点提供第三初始信号线的信号。
步骤200、发光控制子电路在发光信号线的信号的控制下，向第三节点提供第一电源线的信号，驱动子电路在第一节点和第三节点的信号的控制下，向第二节点输出驱动电流。
本公开实施例还提供了一种显示装置，包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (26)

  1. 一种像素驱动电路，被配置为驱动发光器件，所述像素驱动电路包括：节点控制子电路、发光控制子电路和驱动子电路；
    所述节点控制子电路，分别与第一节点、第二节点、第三节点、第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、第一初始信号线、第二初始信号线、第三初始信号线、数据信号线和第一电源线电连接，被配置为在第一扫描信号线、第二扫描信号线、第三扫描信号线和第四扫描信号线的信号的控制下，通过第一初始信号线、数据信号线和第一电源线的信号带动第一节点的信号，向第二节点提供第二初始信号线的信号，向第三节点提供第三初始信号线的信号；
    所述发光控制子电路，分别与第一电源线、发光信号线和第三节点电连接，被配置为在发光信号线的信号的控制下，向第三节点提供第一电源线的信号；
    所述驱动子电路，分别与第一节点、第二节点和第三节点电连接，被配置为在第一节点和第三节点的信号的控制下，向第二节点输出驱动电流；
    所述发光器件，分别与第二节点和第二电源线电连接；
    所述节点控制子电路包括：储能子电路，所述储能子电路包括：第一电容和第二电容，第一电容和第二电容包括：第一极板和第二极板；
    第一电容的第一极板与第一电源线电连接，第一电容的第二极板与第四节点电连接；
    第二电容的第一极板与第一节点电连接，第二电容的第二极板与第四节点电连接。
  2. 根据权利要求1所述的像素驱动电路，其中，所述节点控制子电路还包括：复位子电路、补偿子电路和写入子电路；
    所述复位子电路，分别与第一节点、第二节点、第三节点、第一扫描信号线、第二扫描信号线、第三扫描信号线、第一初始信号线、第二初始信号线和第三初始信号线电连接，被配置为在第一扫描信号线的信号的控制下，向第一节点提供第一初始信号线的信号，在第二扫描信号线的信号的控制下，向第二节点提供第二初始信号线的信号，在第三扫描信号线的信号的控制下，向第三节点提供第三初始信号线的信号；
    所述补偿子电路，分别与第三节点、第四节点和第一扫描信号线电连接，被配置为在第一扫描信号线的信号的控制下，向第四节点提供第三节点的信号，以对第四节点的信号进行补偿；
    所述写入子电路，分别与第四节点、第四扫描信号线和数据信号线电连接，被配置为在第四扫描信号线的信号的控制下，向第四节点提供数据信号线的信号。
  3. 根据权利要求2所述的像素驱动电路，其中，所述复位子电路包括：第一晶体管、第二晶体管和第三晶体管；
    第一晶体管的栅电极与第一扫描信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的栅电极与第二扫描信号线电连接，第二晶体管的第一极与第二初始信号线电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的栅电极与第三扫描信号线电连接，第三晶体管的第一极与第三初始信号线电连接，第二晶体管的第二极与第三节点电连接。
  4. 根据权利要求2所述的像素驱动电路，其中，所述补偿子电路包括：第四晶体管， 所述写入晶体管包括：第五晶体管；
    第四晶体管的栅电极与第一扫描信号线电连接，第四晶体管的第一极与第四节点电连接，第四晶体管的第二极与第三节点电连接；
    第五晶体管的栅电极与第四扫描信号线电连接，第五晶体管的第一极与数据信号线电连接，第五晶体管的第二极与第四节点电连接。
  5. 根据权利要求1所述的像素驱动电路，其中，所述节点控制子电路还包括：第一晶体管至第五晶体管，所述驱动子电路包括：第六晶体管，所述发光控制子电路包括：第七晶体管；
    第一晶体管的栅电极与第一扫描信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的栅电极与第二扫描信号线电连接，第二晶体管的第一极与第二初始信号线电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的栅电极与第三扫描信号线电连接，第三晶体管的第一极与第三初始信号线电连接，第二晶体管的第二极与第三节点电连接；
    第四晶体管的栅电极与第一扫描信号线电连接，第四晶体管的第一极与第四节点电连接，第四晶体管的第二极与第三节点电连接；
    第五晶体管的栅电极与第四扫描信号线电连接，第五晶体管的第一极与数据信号线电连接，第五晶体管的第二极与第四节点电连接；
    第六晶体管的栅电极与第一节点电连接，第六晶体管的第一极与第三节点电连接，第六晶体管的第二极与第二节点电连接；
    第七晶体管的栅电极与发光信号线电连接，第七晶体管的第一极与第一电源线电连接，第七晶体管的第二极与第三节点电连接。
  6. 根据权利要求5所述的像素驱动电路，其中，第一晶体管、第四晶体管和第五晶体管为氧化物晶体管，且为N型晶体管，第二晶体管、第三晶体管、第六晶体管和第七晶体管为P型晶体管；
    第六晶体管的有源层的沟道区的长度大于第一晶体管至第五晶体管和第七晶体管中的任一个晶体管的有源层的沟道区的长度，第六晶体管的有源层的沟道区的宽度大于第一晶体管至第五晶体管和第七晶体管中的任一个晶体管的有源层的沟道区的宽度，且第六晶体管的有源层的沟道区的宽长比小于第一晶体管至第五晶体管和第七晶体管中的任一个晶体管的有源层的沟道区的宽长比。
  7. 根据权利要求1或6所述的像素驱动电路，其中，所述第一扫描信号线的信号和所述第二扫描信号线的信号互为反相信号；
    所述第三扫描信号线的信号为有效电平信号时，所述第一扫描信号线和是第二扫描信号线的信号为有效电平信号，所述第四扫描信号线和所述发光信号线的信号为无效电平信号；
    所述第四扫描信号线的信号为有效电平信号时，所述第一扫描信号线、所述第二扫描信号线、所述第三扫描信号线和所述发光信号线的信号为无效电平信号；
    所述发光信号线的信号为有效电平信号时，所述第一扫描信号线、所述第二扫描信号线、所述第三扫描信号线和所述第四扫描信号线的信号为无效电平信号；
    所述第一扫描信号线和所述第二扫描信号线中的任一条信号线的信号为有效电平信 号的持续时间大于所述第三扫描信号线和所述第四扫描信号线中的任一条信号线的信号为有效电平信号的持续时间。
  8. 根据权利要求7所述的像素驱动电路，其中，所述第一初始信号线的信号和所述第二初始信号线的信号为同一信号，且所述第一初始信号线的信号的电压值小于所述第三初始信号线的信号的电压值；
    所述第二初始信号线的信号的电压值大于所述第二电源线的信号的电压值。
  9. 一种显示基板，包括：基底以及设置在基底上的多个子像素，至少一个子像素包括：如权利要求1至8任一项所述的像素驱动电路以及像素驱动电路所驱动的发光器件。
  10. 根据权利要求9所述的显示基板，还包括：依次叠设在基底上的驱动电路层和发光结构层，所述驱动电路层包括：多个像素驱动电路、多条发光信号线、多条第一初始信号线、多条第二初始信号线、多条第三初始信号线、多条第一扫描信号线、多条第二扫描信号线、多条第三扫描信号线、多条第四扫描信号线、多条第一电源线和多条数据信号线，所述发光结构层包括：发光器件；
    发光信号线、第一初始信号线、第二初始信号线、第三初始信号线、第一扫描信号线、第二扫描信号线、第三扫描信号线和第四扫描信号线中任一信号线至少部分沿第一方向延伸，第一电源线和数据信号线中的任一信号线至少部分沿第二方向延伸，所述第一方向和所述第二方向相交。
  11. 根据权利要求10所述的显示基板，其中，所述驱动电路层还包括：至少部分沿第一方向延伸的多条电源连接线；
    至少一条电源连接线，分别与像素驱动电路和至少一条第一电源线连接。
  12. 根据权利要求11所述的显示基板，其中，所述驱动电路层还包括：第一连接电极；
    所述第一连接电极，分别与像素驱动电路、电源连接线和第一电源线连接；
    所述第一连接电极在基底上的正投影与电源连接线和第一电源线在基底上的正投影至少部分交叠。
  13. 根据权利要求12所述的显示基板，其中，所述第一初始信号线和所述第二初始信号线为同一信号线，所述驱动电路层还包括：至少部分沿第二方向延伸的多条初始连接线；
    至少一条初始连接线，分别与像素驱动电路和至少一条第一初始信号线连接；
    所述初始连接线在基底上的正投影位于初始连接线连接的相邻两列子像素连接的数据信号线在基底上的正投影之间。
  14. 根据权利要求13所述的显示基板，其中，所述第一扫描信号线包括：相互电连接的第一子信号线和第二子信号线，所述第四扫描信号线包括：相互电连接的第三子信号线和第四子信号线；
    所述第一子信号线在基底上的正投影与所述第二子信号线在基底上的正投影至少部分交叠，所述第三子信号线在基底上的正投影与所述第四子信号线在基底上的正投影至少部分交叠。
  15. 根据权利要求14所述的显示基板，其中，所述像素驱动电路包括：第一晶体管至第七晶体管以及第一电容和第二电容，第一电容和第二电容分别包括：第一极板和第二极板，所述驱动电路层包括在基底上依次设置的第一半导体层、第一导电层、第二导电层、 第二半导体层、第三导电层、第四导电层和第五导电层；
    第一半导体层至少包括：位于至少一个子像素的第二晶体管的有源层、第三晶体管的有源层、第六晶体管的有源层和第七晶体管的有源层；
    第一导电层至少包括：发光信号线、第二扫描信号线、第三扫描信号线以及位于至少一个子像素的第一电容的第一极板、第二电容的第一极板、第二晶体管的栅电极、第三晶体管的栅电极、第六晶体管的控制极和第七晶体管的栅电极
    第二导电层至少包括：第一扫描信号线的第一子信号线、第四扫描信号线的第三子信号线以及位于至少一个子像素的第一电容的第二极板和第二电容的第二极板；
    第二半导体层至少包括：位于至少一个子像素的第一晶体管的有源层、第四晶体管的有源层和第五晶体管的有源层；
    第三导电层至少包括：第一扫描信号线的第二子信号线、第四扫描信号线的第四子信号线、电源连接线、第一初始信号线、第二初始信号线和第三初始信号线；
    第四导电层至少包括：初始连接线以及位于至少一个子像素的第一连接电极和第一晶体管至第七晶体管的第一极和第二极；
    第五导电层至少包括：第一电源线和数据信号线。
  16. 根据权利要求15所述的显示基板，其中，所述驱动电路层还包括：设置在所述基底和所述第一半导体层之间的遮光层；
    遮光层至少包括：位于至少一个子像素的遮光结构，相邻子像素的遮光结构相互连接；
    所述遮光结构在基底上的正投影与第六晶体管的栅电极在基底上的正投影至少部分交叠。
  17. 根据权利要求16所述的显示基板，其中，所述遮光结构包括：第一遮光部、第二遮光部、第三遮光部和第四遮光部；
    所述第一遮光部在基底上的正投影与第六晶体管的有源层在基底上的正投影至少部分重叠，所述第二遮光部在基底上的正投影与第七晶体管的有源层在基底上的正投影至少部分重叠，所述第三遮光部在基底上的正投影与第三晶体管的有源层在基底上的正投影至少部分重叠，所述第四遮光部在基底上的正投影与第二晶体管的有源层在基底上的正投影至少部分重叠。
  18. 根据权利要求16所述的显示基板，其中，所述遮光结构包括：遮光部、第一遮光连接部、第二遮光连接部、第三遮光连接部和第四遮光连接部；
    所述遮光部在基底上的正投影与第六晶体管的有源层在基底上的正投影至少部分重叠，所述第一遮光连接部、所述第二遮光连接部、所述第三遮光连接部和所述第四遮光连接部中的任一个在基底上的正投影与第二晶体管的有源层、第三晶体管的有源层和第七晶体管的有源层中的任一个在基底上的正投影不交叠。
  19. 根据权利要求17或18所述的显示基板，其中，子像素连接的发光信号线位于子像素的第二电容的第一极板远离子像素的第一电容的第一极板的一侧，子像素连接的第二扫描信号线位于子像素的第一电容的第一极板远离子像素的第二电容的第一极板的一侧，子像素连接的第三扫描信号线位于子像素连接的第二扫描信号线远离子像素的第一电容的第一极板的一侧。
  20. 根据权利要求19所述的显示基板，其中，第一电容的第二极板和第二电容的第二极板为相互连接的一体结构，且设置有第一过孔和第二过孔，第一过孔暴露出第一电容 的第一极板，第二过孔暴露出第二电容的第二极板；
    第四扫描信号线的第三子信号线位于第一扫描信号线的第一子信号线远离第一电容的第二极板和第二电容的第二极板的一体结构的一侧；
    子像素连接的第一扫描信号线的第一子信号线在基底上的正投影位于子像素连接的发光信号线在基底上的正投影和子像素的第二电容的第一极板在基底上的正投影之间，子像素连接的第四扫描信号线的第三子信号线在基底上的正投影位于子像素连接的发光信号线在基底上的正投影远离子像素的第二电容的第一极板在基底上的正投影的一侧。
  21. 根据权利要求20所述的显示基板，其中，子像素连接的第一扫描信号线的第二子信号线位于子像素连接的第四扫描信号线的第四子信号线的一侧，子像素连接的电源连接线位于子像素连接的第一扫描信号线的第二子信号线远离子像素连接的第四扫描信号线的第四子信号线的一侧，子像素连接的第一初始信号线位于子像素连接的电源连接线远离子像素连接的第一扫描信号线的第二子信号线的一侧，子像素连接的第三初始信号线位于子像素连接的第一初始信号线远离子像素连接的电源连接线的一侧；
    子像素连接的第四扫描信号线的第四子信号线在基底上的正投影位于子像素连接的发光信号线在基底上的正投影远离子像素的第二电容的第一极板在基底上的正投影的一侧；
    子像素连接的第一扫描信号线的第二子信号线在基底上的正投影位于子像素连接的发光信号线在基底上的正投影和子像素的第二电容的第一极板在基底上的正投影之间；
    子像素连接的电源连接线在基底上的正投影与子像素的第一电容的第二极板和第二电容的第二极板的一体结构在基底上的正投影至少部分交叠，且位于第一扫描信号线的第一子信号线在基底上的正投影和第二扫描信号线在基底的正投影之间；
    子像素连接的第一初始信号线在基底上的正投影与子像素连接的第二扫描信号线在基底上的正投影至少部分交叠，且位于子像素的第一电容的第一极板在基底上的正投影和子像素连接的第三扫描信号线在基底上的正投影之间；
    子像素连接的第三初始信号线在基底上的正投影与子像素连接的第三扫描信号线在基底上的正投影至少部分交叠，且位于子像素连接的第二扫描信号线在基底上的正投影远离子像素的第一电容的第一极板在基底上的正投影的一侧。
  22. 根据权利要求21所述的显示基板，其中，所述电源连接线包括：信号主体线、第一凸起部、第二凸起部和第三凸起部，信号主体线沿第一方向延伸，第一凸起部位于信号主体线靠近第一扫描信号线的第二子信号线的一侧，第二凸起部和第三凸起部位于信号主体线远离第一扫描信号线的第二子信号线的一侧，且第二凸起部和第三凸起部沿第一方向排布；
    第二凸起部和第三凸起部在基底上的正投影与第一电容的第二极板和第二电容的第二极板的一体结构在基底上的正投影至少部分交叠；
    第一过孔在基底上的正投影位于第二凸起部在基底上的正投影和第三凸起部在基底上的正投影之间。
  23. 根据权利要求22所述的显示基板，其中，第一连接电极在基底上的正投影与电源连接线的信号主体线、第二凸起部和第三凸起部在基底上的正投影至少部分交叠，且与电源连接线的第一凸起部在基底上的正投影不交叠。
  24. 根据权利要求22或23所述的显示基板，其中，第一电源线在基底上的正投影与第一电容的第二极板和第二电容的第二极板的一体结构、第一连接电极、电源连接线的信 号主体部和第二凸起部在基底上的正投影至少部分交叠；
    子像素连接的第一电源线在基底上的正投影位于子像素连接的数据信号线远离子像素连接的初始连接线的一侧。
  25. 一种显示装置，包括：如权利要求9至24任一项所述的显示基板。
  26. 一种像素驱动电路的驱动方法，被配置为驱动如权利要求1至8任一项所述的像素驱动电路，所述方法包括：
    节点控制子电路在第一扫描信号线、第二扫描信号线、第三扫描信号线和第四扫描信号线的信号的控制下，通过第一初始信号线、数据信号线和第一电源线的信号带动第一节点的信号，向第二节点提供第二初始信号线的信号，向第三节点提供第三初始信号线的信号；
    发光控制子电路在发光信号线的信号的控制下，向第三节点提供第一电源线的信号，驱动子电路在第一节点和第三节点的信号的控制下，向第二节点输出驱动电流。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180102733A (ko) * 2017-03-07 2018-09-18 아이프라임 리미티드 유기발광 표시 장치
CN109215582A (zh) * 2018-09-28 2019-01-15 昆山国显光电有限公司 显示面板、像素电路的驱动方法及显示装置
CN112071269A (zh) * 2020-09-24 2020-12-11 京东方科技集团股份有限公司 像素单元驱动电路、驱动方法、显示面板及显示装置
CN113066428A (zh) * 2019-12-27 2021-07-02 乐金显示有限公司 电致发光显示装置
CN113223458A (zh) * 2021-01-25 2021-08-06 重庆京东方显示技术有限公司 一种像素电路及其驱动方法、显示基板和显示装置
CN113963668A (zh) * 2020-07-21 2022-01-21 京东方科技集团股份有限公司 一种显示装置及其驱动方法
CN115620672A (zh) * 2021-07-12 2023-01-17 三星显示有限公司 像素和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180102733A (ko) * 2017-03-07 2018-09-18 아이프라임 리미티드 유기발광 표시 장치
CN109215582A (zh) * 2018-09-28 2019-01-15 昆山国显光电有限公司 显示面板、像素电路的驱动方法及显示装置
CN113066428A (zh) * 2019-12-27 2021-07-02 乐金显示有限公司 电致发光显示装置
CN113963668A (zh) * 2020-07-21 2022-01-21 京东方科技集团股份有限公司 一种显示装置及其驱动方法
CN112071269A (zh) * 2020-09-24 2020-12-11 京东方科技集团股份有限公司 像素单元驱动电路、驱动方法、显示面板及显示装置
CN113223458A (zh) * 2021-01-25 2021-08-06 重庆京东方显示技术有限公司 一种像素电路及其驱动方法、显示基板和显示装置
CN115620672A (zh) * 2021-07-12 2023-01-17 三星显示有限公司 像素和显示装置

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