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WO2024113224A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2024113224A1
WO2024113224A1 PCT/CN2022/135410 CN2022135410W WO2024113224A1 WO 2024113224 A1 WO2024113224 A1 WO 2024113224A1 CN 2022135410 W CN2022135410 W CN 2022135410W WO 2024113224 A1 WO2024113224 A1 WO 2024113224A1
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WO
WIPO (PCT)
Prior art keywords
line
signal
scan
signal line
substrate
Prior art date
Application number
PCT/CN2022/135410
Other languages
English (en)
French (fr)
Other versions
WO2024113224A9 (zh
Inventor
张星
徐攀
韩影
罗程远
赵冬辉
吕广爽
许程
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/277,228 priority Critical patent/US20250008790A1/en
Priority to PCT/CN2022/135410 priority patent/WO2024113224A1/zh
Priority to CN202280004760.2A priority patent/CN118414707A/zh
Publication of WO2024113224A1 publication Critical patent/WO2024113224A1/zh
Publication of WO2024113224A9 publication Critical patent/WO2024113224A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display panel, comprising: a substrate and a driving circuit layer disposed on the substrate, the substrate comprising a display area and a non-display area, the driving circuit layer comprising: a plurality of pixel driving circuits disposed in the display area and a plurality of first scanning signal lines disposed in the display area and the non-display area, the first scanning signal lines at least partially extending along a first direction, the pixel driving circuits being electrically connected to the first scanning signal lines, and the first scanning signal lines connected to the pixel driving circuits in adjacent rows being electrically isolated;
  • the driving circuit layer further includes: a first signal line located in the non-display area and a second signal line corresponding to the first signal line, the first signal line being electrically connected to the first scanning signal line and configured to provide a signal to the first scanning signal line, an orthographic projection of the first signal line on the substrate at least partially overlapping an orthographic projection of the corresponding second signal line on the substrate;
  • the resistance of the first signal lines electrically connected to adjacent first scanning signal lines is substantially equal and/or the capacitance between the first signal lines electrically connected to adjacent first scanning signal lines and the corresponding second signal lines is substantially equal.
  • the driving circuit layer further includes: a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of light emitting signal lines, and a plurality of reference signal lines disposed in the display area and the non-display area, the pixel driving circuit being electrically connected to the second scanning signal lines, the third scanning signal lines, the light emitting signal lines, and the reference signal lines, respectively, and the second scanning signal lines, the third scanning signal lines, the light emitting signal lines, and the reference signal lines at least partially extending along the first direction;
  • the i-th row of pixel driving circuits is electrically connected to the i-th first scanning signal line, the i-th second scanning signal line, the i-th third scanning signal line, the i-th light emitting signal line and the i-th reference signal line, 1 ⁇ i ⁇ M, M is the total number of rows of pixel driving circuits;
  • the i-th third scanning signal line, the i-th reference signal line, the i-th second scanning signal line, the i-th first scanning signal line and the i-th light emitting signal line are arranged in sequence along the second direction, the i-th third scanning signal line is located on the side of the i-th reference signal line close to the i-1-th light emitting signal line, the i-th light emitting signal line is located on the side of the i-th first scanning signal line close to the i+1-th third scanning signal line, and the second direction intersects the first direction;
  • the second signal line is electrically connected to at least one of a second scanning signal line, a third scanning signal line, and a light emitting signal line.
  • the driving circuit layer further includes: M first scan output lines, M/2 second scan output lines, M/2 third scan output lines, M reference output lines, and M/2 light emitting output lines located in the non-display area, wherein the first scan output lines, the second scan output lines, the third scan output lines, the reference output lines, and the light emitting output lines at least partially extend along the first direction;
  • the i-th first scan output line is electrically connected to the i-th first scan signal line
  • the i-th reference output line is electrically connected to the i-th reference signal line
  • the j-th second scan output line is electrically connected to the 2j-1-th second scan signal line and the 2j-th second scan signal line, respectively
  • the j-th third scan output line is electrically connected to the 2j-1-th third scan signal line and the 2j-th third scan signal line, respectively
  • the j-th light emitting output line is electrically connected to the 2j-1-th light emitting signal line and the 2j-th light emitting signal line, respectively, 1 ⁇ j ⁇ M/2;
  • the 2j-1th reference output line, the 2j-1th first scan output line, the jth second scan output line, the jth third scan output line, the 2jth reference output line, the jth light emitting output line and the 2jth first scan output line are arranged in sequence along the second direction.
  • the driving circuit layer further includes: a reference power supply line located in the non-display area, and a data signal line and a first power supply line located at least partially in the display area, wherein the reference power supply line, the data signal line and the first power supply line extend at least partially along the second direction;
  • the pixel driving circuit is electrically connected to the data signal line and the first power line respectively, and the orthographic projection of the reference power supply line on the substrate at least partially overlaps with the orthographic projection of the reference output line on the substrate and is electrically connected to the reference output line.
  • the driving circuit layer includes: a first conductive layer and a second conductive layer sequentially stacked on a substrate;
  • the first conductive layer at least includes: a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emitting signal line and a reference power supply line;
  • the second conductive layer at least includes: a first scan output line, a second scan output line, a third scan output line, a reference output line, a light emitting output line, a data signal line and a first power supply line.
  • the sheet resistances of the first conductive layer and the second conductive layer are substantially equal.
  • the first conductive layer and the second conductive layer are made of the same material and have the same thickness.
  • the distances between first signal lines electrically connected to adjacent first scan signal lines and the display area are substantially equal, and the average lengths of first signal lines electrically connected to adjacent first scan signal lines along the second direction are substantially equal.
  • the areas of overlapping regions between first signal lines electrically connected to adjacent first scan signal lines and corresponding second signal lines are substantially equal.
  • the driving circuit layer further includes: a first signal connection line located in the first conductive layer, the first signal connection line extending along the second direction and electrically connected to the 2j-1 third scanning signal line and the 2j third scanning signal line, respectively;
  • the orthographic projection of the first signal connection line on the substrate at least partially overlaps with the orthographic projection of the 2j-1th first scan output line on the substrate;
  • the orthographic projection of the jth third scan output line on the substrate at least partially overlaps with the orthographic projection of the 2jth third scan signal line on the substrate, and is electrically connected to the 2jth third scan signal line.
  • the driving circuit layer further includes: a second signal connection line located in the second conductive layer, the second signal connection line extending along the first direction;
  • the 2jth second scan signal line comprises: a first scan connection portion and a second scan connection portion connected to each other, the first scan connection portion extends along a first direction, the second scan connection portion extends along a second direction, and the first signal connection line is located at a side of the second scan connection portion close to the display area;
  • the orthographic projection of the second scan connection portion on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line, the jth second scan output line, the jth third scan output line and the second signal connection line on the substrate, and is electrically connected to the jth second scan output line and the second signal connection line respectively;
  • the orthographic projection of the second signal connection line on the substrate at least partially overlaps with the orthographic projections of the 2j-1th second scanning signal line and the first signal connection line on the substrate, and is electrically connected to the 2j-1th second scanning signal line.
  • the driving circuit layer further includes: a third signal connection line located in the second conductive layer, the third signal connection line extending along the first direction;
  • the 2jth light-emitting signal line comprises: a first light-emitting connection portion and a second light-emitting connection portion connected to each other, the first light-emitting connection portion extends along a first direction, the second light-emitting connection portion extends along a second direction, and the second light-emitting connection portion is located between the reference power supply line and the second scanning connection portion;
  • the orthographic projection of the second light-emitting connection portion on the substrate at least partially overlaps with the orthographic projections of the j-th light-emitting output line, the j-th third scan output line, the 2j-th first scan output line and the third signal connection line on the substrate, and is electrically connected to the j-th light-emitting output line and the third signal connection line respectively;
  • the orthographic projection of the third signal connection line on the substrate at least partially overlaps with the orthographic projections of the 2j-1 th luminous signal line, the first signal connection line and the second scanning connection portion on the substrate, and is electrically connected to the 2j-1 th luminous signal line;
  • a length of an overlapping area between the second light emitting connection portion and the 2jth first scan output line along the first direction is greater than a length of the first light emitting connection portion along the second direction.
  • the first signal line to which the ith first scan signal line is electrically connected includes: an ith first scan output line;
  • the second signal line corresponding to the first signal line electrically connected to the 2j-1st first scanning signal line includes the first signal connection line and the 2jth second scanning signal line
  • the second signal line corresponding to the first signal line electrically connected to the 2jth first scanning signal line includes the 2jth light-emitting signal line
  • the orthographic projection of the 2j-1th reference output line on the substrate at least partially overlaps with the orthographic projections of the first signal connection line and the 2j-1th reference signal line on the substrate, and is electrically connected to the 2j-1th reference signal line;
  • the orthographic projection of the 2jth reference output line on the substrate at least partially overlaps with the orthographic projections of the second scanning connection portion, the second light-emitting connection portion, and the 2jth reference signal line on the substrate, and is electrically connected to the 2jth reference output line.
  • the driving circuit layer further includes: a first signal connection line located in the first conductive layer, the first signal connection line extending along the second direction and electrically connected to the 2j-1 third scanning signal line and the 2j third scanning signal line, respectively;
  • the orthographic projection of the first signal connection line on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line and the 2jth first scan output line on the substrate;
  • the orthographic projection of the jth third scan output line on the substrate at least partially overlaps with the orthographic projection of the 2jth third scan signal line on the substrate, and is electrically connected to the 2jth third scan signal line.
  • the driving circuit layer further includes: a second signal connection line located in the first conductive layer, and a third signal connection line and a fourth signal connection line located in the second conductive layer, the second signal connection line extending along the second direction, the third signal connection line and the fourth signal connection line at least partially extending along the first direction, and the second signal connection line being located on a side of the first signal connection line away from the display area;
  • the orthographic projection of the second signal connection line on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line, the 2jth first scan output line, the jth second scan output line, the jth third scan output line, the third signal connection line and the fourth signal connection line on the substrate, and is electrically connected to the jth second scan output line, the third signal connection line and the fourth signal connection line respectively;
  • the orthographic projection of the third signal connection line on the substrate at least partially overlaps with the orthographic projections of the first signal connection line and the 2j-1th second scanning signal line on the substrate, and is electrically connected to the 2j-1th second scanning signal line;
  • the orthographic projection of the fourth signal connection line on the substrate at least partially overlaps with the orthographic projections of the first signal connection line and the 2jth second scanning signal line on the substrate, and is electrically connected to the 2jth second scanning signal line.
  • the driving circuit layer further includes: a fifth signal connection line located in the first conductive layer, and a sixth signal connection line and a seventh signal connection line located in the second conductive layer, the fifth signal connection line extending along the second direction, the sixth signal connection line and the seventh signal connection line at least partially extending along the first direction, and the fifth signal connection line being located on a side of the second signal connection line away from the display area;
  • the orthographic projection of the fifth signal connection line on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line, the 2jth first scan output line, the jth second scan output line, the jth third scan output line, the jth light emitting output line, the sixth signal connection line and the seventh signal connection line on the substrate, and is electrically connected to the jth light emitting output line, the sixth signal connection line and the seventh signal connection line respectively;
  • the orthographic projection of the sixth signal connection line on the substrate at least partially overlaps with the orthographic projections of the fifth signal connection line, the second signal connection line and the 2j-1 luminous signal line on the substrate, and is electrically connected to the 2j-1 luminous signal line;
  • the orthographic projection of the seventh signal connection line on the substrate at least partially overlaps with the orthographic projections of the first signal connection line, the second signal connection line and the 2jth luminescence signal line on the substrate, and is electrically connected to the 2jth luminescence signal line.
  • the first signal line to which the ith first scan signal line is electrically connected includes: an ith first scan output line;
  • the second signal line corresponding to the first signal line electrically connected to the 2j-1st first scanning signal line includes the first signal connection line, the second signal connection line and the fifth signal connection line
  • the second signal line corresponding to the first signal line electrically connected to the 2jth first scanning signal line includes the first signal connection line, the second signal connection line and the fifth signal connection line.
  • the orthographic projection of the 2j-1th reference output line on the substrate at least partially overlaps with the orthographic projections of the first signal connection line, the second signal connection line, the fifth signal connection line, and the 2j-1th reference signal line on the substrate, and is electrically connected to the 2j-1th reference signal line;
  • the orthographic projection of the 2jth reference output line on the substrate at least partially overlaps with the orthographic projections of the first signal connection line, the second signal connection line, the fifth signal connection line, and the 2jth reference signal line on the substrate, and is electrically connected to the 2jth reference output line.
  • the third connection signal line, the fourth connection signal line, the sixth connection signal line, the seventh connection signal line and the 2j-1th first scan output line are approximately equidistant from the boundary of the display area and the display area.
  • the driving circuit layer further includes: a first signal connection line located in the first conductive layer, the first signal connection line extending along the second direction and electrically connected to the 2j-1 third scanning signal line and the 2j third scanning signal line, respectively;
  • the orthographic projection of the first signal connection line on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line, the jth second scan output line and the jth third scan output line on the substrate, and is electrically connected to the jth third scan output line.
  • the 2j-1 second scan signal line includes: a first scan connection portion and a second scan connection portion connected to each other, the first scan connection portion extending along the first direction, and the second scan connection portion extending along the second direction
  • the j-th second scan output line includes: a first scan output connection portion and a second scan output connection portion connected to each other, the first scan output connection portion extending along the first direction, the second scan output connection portion extending along the second direction, a virtual straight line extending along the second direction passes through the second scan connection portion and the second scan output connection portion, and the second scan connection portion is located on a side of the first signal connection line close to the display area;
  • the orthographic projection of the second scan connection portion on the substrate at least partially overlaps with the orthographic projection of the 2j-1th first scan output line and the first scan output connection portion on the substrate, and is electrically connected to the first scan output connection portion;
  • the orthographic projection of the first scan output connection portion on the substrate at least partially overlaps with the orthographic projection of the first signal connection line on the substrate;
  • the orthographic projection of the second scan output connection portion on the substrate at least partially overlaps with the orthographic projections of the 2jth third scan signal line and the 2jth second scan signal line on the substrate, and is electrically connected to the 2jth second scan signal line.
  • the driving circuit layer further includes: a second signal connection line located in the first conductive layer, the second signal connection line extending along the first direction;
  • the orthographic projection of the second signal connecting line on the substrate at least partially overlaps with the orthographic projection of the 2j-th first scan output line on the substrate, and is electrically connected to the 2j-th first scan output line and the 2j-th first scan signal line respectively, and the length of the second signal connecting line along the second direction is greater than the length of the first scan signal line along the second direction.
  • the j-th light emitting output line includes: a first light emitting output connection portion and a second light emitting output connection portion connected to each other, the first light emitting output connection portion extending along a first direction, and the second light emitting output connection portion extending along a second direction; the second light emitting output connection portion is located on a side of the second scanning output connection portion close to the display area;
  • the orthographic projection of the second light-emitting output connection portion on the substrate at least partially overlaps with the orthographic projections of the second signal connection line, the 2j-1th light-emitting signal line, the 2jth light-emitting signal line, the 2jth third scanning signal line and the 2jth second scanning signal line on the substrate, and is electrically connected to the 2j-1th light-emitting signal line and the 2jth light-emitting signal line, respectively.
  • the first signal line electrically connected to the 2j-1st first scan signal line includes the 2j-1st first scan output line
  • the first signal line electrically connected to the 2jth first scan signal line includes the 2jth first scan output line and the second signal connection line
  • the second signal line corresponding to the first signal line electrically connected to the 2j-1th first scanning signal line includes the first signal connection line and the 2j-1th second scanning signal line, and the second signal line corresponding to the first signal line electrically connected to the 2jth first scanning signal line includes the jth light-emitting output line.
  • the orthographic projection of the 2j-1th reference output line on the substrate at least partially overlaps with the orthographic projection of the 2j-1th reference signal line on the substrate, and is electrically connected to the 2j-1th reference signal line; the orthographic projection of the 2jth reference output line on the substrate at least partially overlaps with the orthographic projection of the 2jth reference signal line on the substrate, and is electrically connected to the 2jth reference output line.
  • the driving circuit layer further includes: a shielding layer, the shielding layer being located on a side of the first conductive layer close to the substrate;
  • the shielding layer at least includes: a reference signal line.
  • the present disclosure further provides a display device, comprising: the above-mentioned display panel.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic diagram of a planar structure of a display panel
  • FIG3 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG4 is a working timing diagram of a pixel driving circuit
  • FIG5 is a first structural diagram of a display panel provided in an embodiment of the present disclosure.
  • FIG6 is a second structural schematic diagram of a display panel provided in an embodiment of the present disclosure.
  • FIG7 is a third structural schematic diagram of a display panel provided in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of the display panel provided in FIGS. 5 to 7 after a shielding layer pattern is formed;
  • FIG9 is a schematic diagram of a semiconductor layer pattern of the display panel provided in FIGS. 5 to 7 ;
  • FIG10 is a schematic diagram of the display panel provided in FIGS. 5 to 7 after a semiconductor layer pattern is formed;
  • FIG11 is a schematic diagram of a first conductive layer pattern of the display panel provided in FIG5 ;
  • FIG12 is a schematic diagram of the display panel provided in FIG5 after a first conductive layer pattern is formed
  • FIG13 is a schematic diagram of a first conductive layer pattern of the display panel provided in FIG6 ;
  • FIG14 is a schematic diagram of the display panel provided in FIG6 after a first conductive layer pattern is formed
  • FIG15 is a schematic diagram of a first conductive layer pattern of the display panel provided in FIG7 ;
  • FIG16 is a schematic diagram of the display panel provided in FIG7 after a first conductive layer pattern is formed
  • FIG17 is a schematic diagram of the display panel provided in FIG5 after a third insulating layer pattern is formed;
  • FIG18 is a schematic diagram of the display panel provided in FIG6 after a third insulating layer pattern is formed
  • FIG19 is a schematic diagram of the display panel provided in FIG7 after a third insulating layer pattern is formed
  • FIG20 is a schematic diagram of a second conductive layer pattern of the display panel provided in FIG5 ;
  • FIG21 is a schematic diagram of the display panel provided in FIG5 after a second conductive layer pattern is formed
  • FIG22 is a schematic diagram of a second conductive layer pattern of the display panel provided in FIG6 ;
  • FIG23 is a schematic diagram of forming a second conductive layer pattern of the display panel provided in FIG6 ;
  • FIG24 is a schematic diagram of a second conductive layer pattern of the display panel provided in FIG7 ;
  • FIG. 25 is a schematic diagram of the display panel provided in FIG. 7 after a second conductive layer pattern is formed.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is respectively connected to the data driver, the scan driver, and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines Data, the scan driver is respectively connected to a plurality of first scan signal lines G1, a plurality of second scan signal lines G2, and a plurality of third scan signal lines G3, and the light emitting driver is respectively connected to a plurality of light emitting signal lines EM.
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the first scan signal line, the second scan signal line, the third scan signal line, the light emitting signal line, and the data signal line.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc.
  • the scan driver can provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver.
  • the data driver can generate a data voltage to be provided to the data signal line Data using the grayscale value and the control signal received from the timing controller. For example, the data driver can sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal line in units of pixel rows.
  • the scan driver can generate a scan signal to be provided to the first scan signal line, the second scan signal line, and the third scan signal line by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan driver can sequentially provide a scan signal with a conduction level pulse to the first scan signal line, the second scan signal line, and the third scan signal line.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit to generate a scan signal under the control of the clock signal.
  • the light-emitting driver can generate an emission signal to be provided to the light-emitting signal line by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light-emitting driver can sequentially provide an emission signal with a cut-off level pulse to the light-emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in such a manner that an emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to a next stage circuit under the control of a clock signal.
  • FIG2 is a schematic diagram of a planar structure of a display panel.
  • the display panel may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the first scanning signal line, the second scanning signal line, the third scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the first scanning signal line, the second scanning signal line, the third scanning signal line, and the light-emitting signal line, and output a corresponding current to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in horizontal parallel, vertical parallel or in a herringbone manner, which is not limited in the present disclosure.
  • the pixel unit may include four sub-pixels, and the four sub-pixels may be respectively arranged with the first sub-pixel to the fourth sub-pixel.
  • the four sub-pixels may be arranged in horizontal parallel, vertical parallel or square manner, etc., which is not limited in the present disclosure.
  • the first subpixel may be a red subpixel that emits red (R) light
  • the second subpixel may be a blue subpixel that emits blue (B) light
  • the third subpixel may be a green subpixel that emits green (G) light
  • the fourth subpixel may be a white subpixel that emits white (W) light.
  • the shape of the sub-pixel in the pixel unit may be a rectangle, a diamond, a pentagon, or a hexagon, which is not limited in the present disclosure.
  • FIG3 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 5 transistors (a first transistor T1 to a fifth transistor T5), 1 storage capacitor Cst, and the pixel driving circuit may be electrically connected to 8 signal lines (a data signal line Data, a first scanning signal line G1, a second scanning signal line G2, a third scanning signal line G3, a light emitting signal line EM, a reference signal line REF, an initial signal line INIT and a first power line VDD).
  • a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1
  • a first electrode of the first transistor T1 is electrically connected to the data signal line Data
  • a second electrode of the first transistor T1 is connected to the first node N1.
  • the first transistor T1 may be referred to as a write transistor, and when the signal of the first scan signal line G1 is an effective level signal, the first transistor T1 transmits the data voltage of the data signal line to the first node N1.
  • the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2
  • the first electrode of the second transistor T2 is electrically connected to the reference signal line REF
  • the second electrode of the second transistor T2 is electrically connected to the first node N1.
  • the second transistor T2 can be called a compensation transistor, and when the signal of the second scan signal line G2 is an effective level signal, the second transistor T2 transmits the signal of the reference signal line REF to the first node N1 to compensate the first node N1.
  • a control electrode of the third transistor T3 is electrically connected to the third scan signal line G3, a first electrode of the third transistor T3 is electrically connected to the initial signal line INIT, and a second electrode of the third transistor T3 is electrically connected to the third node N3.
  • the third transistor T3 may be referred to as a reset transistor, and when the signal of the third scan signal line G3 is an effective level signal, the third transistor T3 transmits an initial signal of the initial signal line INIT to the third node N3, so that the charge accumulated in the first electrode of the light emitting device L is initialized or the charge accumulated in the first electrode of the light emitting device is released.
  • a control electrode of the fourth transistor T4 is electrically connected to the light emitting signal line EM, a first electrode of the fourth transistor T4 is electrically connected to the first power line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2.
  • the fourth transistor T4 may be referred to as a light emitting transistor.
  • the fourth transistor T4 forms a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.
  • the control electrode of the fifth transistor T5 is electrically connected to the first node N1
  • the first electrode of the fifth transistor T5 is electrically connected to the second node N2
  • the second electrode of the fifth transistor T5 is electrically connected to the third node N3.
  • the fifth transistor T5 can be called a driving transistor, and the fifth transistor T5 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between the control electrode and the first electrode.
  • a first end of the storage capacitor Cst is connected to the first node N1, and a second end of the storage capacitor Cst is connected to the third node N3, that is, the first end of the storage capacitor Cst is connected to the control electrode of the fifth transistor T5.
  • the storage capacitor Cst is configured to store the voltage value of the signal of the control electrode of the fifth transistor.
  • a first electrode of the light emitting device L is electrically connected to the third node N3 , and a second electrode of the light emitting device L is connected to the second power line VSS.
  • the first power line VDD continuously provides a high level signal
  • the second power line VSS continuously provides a low level signal
  • the reference signal line REF and the initial signal line INIT provide constant voltage signals
  • the voltage value of the initial signal line INIT is lower than the voltage value of the second power line VSS.
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first transistor T1 to the fifth transistor T5 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the fifth transistor T5 may include a P-type transistor and an N-type transistor.
  • the storage capacitor Cst may be a capacitor device made by a process, for example, a capacitor device is realized by making a special capacitor electrode, and a plurality of capacitor electrodes of the capacitor may be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc.
  • the storage capacitor Cst may be a parasitic capacitor between a plurality of devices, which may be realized by the transistor itself and other devices and lines.
  • the connection mode of the storage capacitor Cst includes but is not limited to the mode described above, and may be other applicable connection modes, and the level of the corresponding node may be stored.
  • the exemplary embodiments of the present disclosure are not limited to this.
  • the first transistor T1 to the fifth transistor T5 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display panel to form a low-temperature polycrystalline oxide (LTPO) display panel, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the first scan signal line G1, the second scan signal line G2, the emission signal line EM, the reference signal line REF, and the initial signal line INIT may extend in a horizontal direction
  • the first power line VDD and the data signal line Data may extend in a vertical direction.
  • the light-emitting device L may include: any one of an organic light-emitting diode OLED, a quantum dot light-emitting diode, and an inorganic light-emitting diode.
  • the light-emitting device L may be a micron-level light-emitting device, such as a micro light-emitting diode (Micro Light-Emitting Diode, Micro LED), a sub-millimeter light-emitting diode (Mini Light-Emitting Diode, Mini LED) or a micro organic light-emitting diode (Micro OLED), etc., and the embodiments of the present disclosure are not limited to this.
  • the light-emitting device L as an organic light-emitting diode (OLED) as an example, the light-emitting device may include: a stacked first electrode (for example, as an anode), an organic light-emitting layer, and a second electrode (for example, as a cathode).
  • a stacked first electrode for example, as an anode
  • an organic light-emitting layer for example, an organic light-emitting layer
  • a second electrode for example, as a cathode
  • the display panel of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • the organic light emitting layer may include a light emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • FIG4 is a working timing diagram of a pixel driving circuit. The following is an explanation of an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit shown in FIG3.
  • the pixel driving circuit in FIG3 includes five transistors (first transistor T1 to fifth transistor T5) and one storage capacitor Cst, and all five transistors are N-type transistors.
  • the operation process of the pixel driving circuit may include:
  • the first stage S1 is called the reset stage.
  • the signals of the second scanning signal line G2 and the third scanning signal line G3 are high-level signals, and the signals of the first scanning signal line G1 and the light-emitting signal line EM are low-level signals.
  • the signal of the second scanning signal line G2 is a high-level signal, the second transistor T2 is turned on, the reference signal of the reference signal line REF is written to the first node N1, the storage capacitor Cst is initialized (reset), and the original charge in the storage capacitor Cst is cleared.
  • the signal of the third scanning signal line G3 is a high-level signal
  • the third transistor T3 is turned on, and the initial signal of the initial signal line INIT is written to the third node N3, the first electrode of the light-emitting device L is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the signals of the first scanning signal line G1 and the light-emitting signal line EM are low-level signals, the first transistor T1 and the fourth transistor T4 are turned off, and at this stage, the light-emitting device L does not emit light.
  • the second stage S2 is called the threshold compensation stage.
  • the signals of the second scanning signal line G2 and the light emitting signal line EM are high level signals, and the signals of the first scanning signal line G1 and the third scanning signal line G3 are low level signals.
  • the signal of the second scanning signal line G2 is a high level signal, the second transistor T2 is continuously turned on, the reference signal of the reference signal line REF is written to the first node N1, the storage capacitor Cst is initialized (reset), and the original charge in the storage capacitor Cst is cleared.
  • the signals of the first scanning signal line G1 and the third scanning signal line G3 are low level signals, the first transistor T1 and the third transistor T3 are turned off, and at this stage, the light emitting device L does not emit light.
  • the third stage S3 is called the data writing stage.
  • the signal of the first scanning signal line G1 is a high-level signal
  • the signals of the second scanning signal line G2, the third scanning signal line G3 and the light-emitting signal line EM are low-level signals.
  • the data signal line Data outputs a data voltage.
  • the fifth transistor T5 is turned on
  • the signal of the first scanning signal line G1 is a high-level signal
  • the first transistor T1 is turned on
  • the data voltage output by the data signal line D is written to the first node N1.
  • Vata is the voltage value of the data voltage
  • the third node N3 jumps under the action of the storage capacitor Cst
  • a is a constant value.
  • the signals of the second scanning signal line G2, the third scanning signal line G3 and the light-emitting signal line EM are low-level signals, and the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned off. In this stage, the light-emitting device L does not emit light.
  • the fourth stage S4 is called the light-emitting stage, the signal of the light-emitting signal line EM is a pulse signal, and the signals of the first scanning signal line G1, the second scanning signal line G2 and the third scanning signal line G3 are low-level signals.
  • the fourth transistor T4 is turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the second node N2, the turned-on fifth transistor T5 and the third node N3, driving the light-emitting device L to emit light.
  • the driving current flowing through the fifth transistor T5 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the fifth transistor T5, that is, the driving current driving the light emitting device L
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the fifth transistor T5.
  • the driving current of the fifth transistor T5 is no longer affected by the threshold voltage of the fifth transistor T5, thereby eliminating the influence of the threshold voltage of the fifth transistor T5 on the driving current, which can ensure the uniform display brightness of the display product and improve the display effect of the entire display product.
  • the compensation time of the pixel driving circuit does not occupy the data writing time, so the compensation effect is not affected by the resolution and refresh frequency of the display panel.
  • FIG5 is a schematic diagram of the structure of the display panel provided in the embodiment of the present disclosure
  • FIG6 is a schematic diagram of the structure of the display panel provided in the embodiment of the present disclosure
  • FIG7 is a schematic diagram of the structure of the display panel provided in the embodiment of the present disclosure.
  • the display panel provided in the embodiment of the present disclosure may include: a substrate and a driving circuit layer arranged on the substrate, the substrate includes a display area AA and a non-display area AA', the driving circuit layer includes: a plurality of pixel driving circuits PE arranged in the display area AA and a plurality of first scanning signal lines arranged in the display area AA and the non-display area AA', the first scanning signal lines at least partially extending along the first direction D1, the pixel driving circuit PE is electrically connected to the first scanning signal lines, and the first scanning signal lines connected to the adjacent row pixel driving circuits are electrically isolated.
  • G1(2j-1) in FIG5 to FIG7 refers to the first scanning signal line electrically connected to the 2j-1th row pixel driving circuit
  • G1(2j) refers to the first scanning signal line electrically connected to the 2jth row pixel driving circuit
  • FIG5 to FIG7 are illustrated by taking the two rows and two columns of pixel driving circuits in the display area as an example.
  • the driving circuit layer may further include: a first signal line located in the non-display area AA' and a second signal line corresponding to the first signal line, the first signal line being electrically connected to the first scan signal line and configured to provide a signal to the first scan signal line, and an orthographic projection of the first signal line on the substrate at least partially overlaps with an orthographic projection of the corresponding second signal line on the substrate.
  • R1 is an overlapping region of the first signal line electrically connected to the 2j-1st first scan signal line and the corresponding second signal line
  • R2 is an overlapping region of the first signal line electrically connected to the 2jth first scan signal line and the corresponding second signal line.
  • the resistance R of the first signal lines electrically connected to the adjacent first scan signal lines is substantially equal and/or the capacitance C between the first signal lines electrically connected to the adjacent first scan signal lines and the corresponding second signal lines is substantially equal.
  • a and B being substantially equal means that A and B may be equal, or there may be a difference between A and B, but the difference is less than a threshold difference.
  • a and B may represent the resistance of the first signal lines electrically connected to the adjacent first scan signal lines or may represent the capacitance between the first signal lines electrically connected to the adjacent first scan signal lines and the corresponding second signal lines.
  • the threshold difference refers to a difference that can make the difference in the display effect of the display panel unrecognizable by the human eye, and may be determined according to the configuration of the display panel, and the present disclosure does not make any limitation on this.
  • the resistance of the first signal lines electrically connected by adjacent first scanning signal lines is approximately equal and/or the capacitance value between the first signal lines electrically connected by adjacent first scanning signal lines and the corresponding second signal lines is approximately equal, thereby reducing the RC difference of the first signal lines electrically connected by adjacent first scanning signal lines, eliminating display abnormalities, and improving the display effect of the display panel.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked.
  • the first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc.
  • the first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers, and the semiconductor layer may be made of amorphous silicon (a-Si).
  • its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.
  • PI1 first flexible
  • a-si amorphous silicon
  • the display panel may further include: a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the display panel may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the second electrode of the driving transistor through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer.
  • the organic light-emitting layer emits light of corresponding colors when driven by the anode and the cathode.
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer.
  • the first touch metal layer may include a plurality of bridging electrodes
  • the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes
  • the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.
  • the driving circuit layer further includes: a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of light-emitting signal lines, and a plurality of reference signal lines disposed in the display area AA and the non-display area AA', the pixel driving circuit PE is electrically connected to the second scanning signal lines, the third scanning signal lines, the light-emitting signal lines, and the reference signal lines, respectively, and the second scanning signal lines, the third scanning signal lines, the light-emitting signal lines, and the reference signal lines at least partially extend along the first direction D1.
  • 5 to 7 refers to the i-th second scanning signal line
  • G3(i) refers to the i-th third scanning signal line
  • EM(i) refers to the i-th light-emitting signal line
  • REF(i) refers to the i-th reference signal line.
  • the i-th row of pixel driving circuits are electrically connected to the i-th first scanning signal line, the i-th second scanning signal line, the i-th third scanning signal line, the i-th light emitting signal line and the i-th reference signal line, respectively, 1 ⁇ i ⁇ M, and M is the total number of rows of pixel driving circuits.
  • the pixel driving circuit in the 2j-1th row is electrically connected to the 2j-1th first scanning signal line G1(2j-1), the 2j-1th second scanning signal line G2(2j-1), the 2j-1th third scanning signal line G3(2j-1), the 2j-1th luminous signal line EM(2j-1) and the 2j-1th reference signal line REF(2j-1), respectively;
  • the pixel driving circuit in the 2jth row is electrically connected to the 2jth first scanning signal line G1(2j), the 2jth second scanning signal line G2(2j-1), the 2jth third scanning signal line G3(2j), the 2jth luminous signal line EM(2j) and the 2jth reference signal line REF(2j), respectively.
  • the i-th third scan signal line, the i-th reference signal line, the i-th second scan signal line, the i-th first scan signal line and the i-th light-emitting signal line are arranged in sequence along the second direction D2, the i-th third scan signal line is located on the side of the i-th reference signal line close to the i-1-th light-emitting signal line, the i-th light-emitting signal line is located on the side of the i-th first scan signal line close to the i+1-th third scan signal line, and the second direction D2 intersects with the first direction D1.
  • the 2j-1th third scanning signal line G3(2j-1), the 2j-1th reference signal line REF(2j-1), the 2j-1th second scanning signal line G2(2j-1), the 2j-1th first scanning signal line G1(2j-1) and the 2j-1th light-emitting signal line EM(2j-1) are arranged along the second direction D2, the 2j-1th third scanning signal line G3(2j-1) is located on the side of the 2j-1th reference signal line REF(2j-1) close to the 2j-2th light-emitting signal line EM(2j-2), and the 2j-1th light-emitting signal line EM(2j-1) is located on the side of the 2j-1th first scanning signal line G1(2j-1) close to the 2j-3 third scanning signal line G3(2j).
  • the second signal line may be electrically connected to at least one of the second scan signal line, the third scan signal line, and the light emitting signal line.
  • the driving circuit layer may further include: M initial signal lines at least partially located in the display area AA, the initial signal lines extending along the first direction.
  • the i-th row of pixel driving circuits is electrically connected to the i-th initial signal line.
  • the 2j-1-th row of pixel driving circuits is electrically connected to the 2j-1-th initial signal line INIT(2j-1), and the 2j-th row of pixel driving circuits is electrically connected to the 2j-th initial signal line INIT(2j).
  • the i-th initial signal line is located at a side of the i-th third scan signal line away from the i-th reference signal line.
  • the driving circuit layer may further include: M first scan output lines, M/2 second scan output lines, M/2 third scan output lines, M reference output lines, and M/2 light emitting output lines located in the non-display area AA'.
  • the first scan output lines, the second scan output lines, the third scan output lines, the reference output lines, and the light emitting output lines extend at least partially along the first direction D1.
  • REFOUTL(i) refers to the i-th reference output line
  • GOUTL2(j) refers to the j-th second scan output line
  • GOUTL3(j) refers to the j-th third scan output line
  • EMOUTL(j) refers to the j-th light emitting output line.
  • the i-th first scan output line GOUTL1(i) is electrically connected to the i-th first scan signal line G1(i)
  • the i-th reference output line REFOUTL1(i) is electrically connected to the i-th reference signal line REF(i)
  • the j-th second scan output line GOUTL2(j) is electrically connected to the 2j-1-th second scan signal line G2(2j-1) and the 2j-th second scan signal line G2(2j), respectively
  • the j-th third scan output line GOUTL3(j) is electrically connected to the 2j-1-th third scan signal line G3(2j-1) and the 2j-th third scan signal line G3(2j), respectively
  • the j-th light-emitting output line EMOUTL(j) is electrically connected to the 2j-1-th light-emitting signal line EM(2j-1) and the 2j-th light-emitting signal line EM
  • the first first scan output line is electrically connected to the first first scan signal line
  • the second first scan output line is electrically connected to the second first scan signal line
  • the first reference output line is electrically connected to the first reference signal line
  • the second reference output line is electrically connected to the second reference signal line, and so on.
  • the first second scan output line is electrically connected to the first second scan signal line and the second second scan signal line, respectively
  • the second second scan output line is electrically connected to the third second scan signal line and the fourth second scan signal line, respectively, and so on.
  • the first third scan output line is electrically connected to the first third scan signal line and the second third scan signal line, respectively, the second third scan output line is electrically connected to the third third scan signal line and the fourth third scan signal line, and so on.
  • the first light-emitting output line is electrically connected to the first light-emitting signal line and the second light-emitting signal line, respectively, the second light-emitting output line is electrically connected to the third light-emitting signal line and the fourth light-emitting signal line, and so on.
  • one light output line connects two light signal lines
  • one second scan output line connects two second scan signal lines
  • one third scan output line connects two third scan signal lines, which can reduce the number of signal lines of the display panel and achieve a narrow frame of the display panel.
  • the 2j-1th reference output line REFOUTL1(2j-1), the 2j-1th first scan output line GOUTL1(2j-1), the jth second scan output line GOUTL2(j), the jth third scan output line GOUTL3(j), the 2jth reference output line REFOUTL(2j), the jth light emitting output line EMOUTL(j) and the 2jth first scan output line GOUTL1(2j) are arranged sequentially along the second direction D2.
  • the driving circuit layer may further include: a reference power supply line REFL located in the non-display area AA' and a data signal line Data and a first power supply line VDD located at least partially in the display area, and the reference power supply line REFL, the data signal line Data and the first power supply line VDD extend at least partially along the second direction D2.
  • the pixel driving circuit is electrically connected to the data signal line Data and the first power line VDD, respectively.
  • an orthographic projection of the reference power supply line REFL on the substrate at least partially overlaps with an orthographic projection of the reference output line on the substrate, and is electrically connected to the reference output line.
  • the driving circuit layer may include: a first conductive layer and a second conductive layer sequentially stacked on a substrate, wherein:
  • the first conductive layer may include at least: a first scan signal line, a second scan signal line, a third scan signal line, a light emitting signal line and a reference power supply line REFL;
  • the second conductive layer may include at least a first scan output line, a second scan output line, a third scan output line, a reference output line, a light emitting output line, a data signal line Data, and a first power line VDD.
  • the sheet resistance of the first conductive layer and the second conductive layer are substantially equal.
  • the first conductive layer and the second conductive layer are made of the same material and have the same thickness.
  • average lengths of the first scan output line, the second scan output line, the third scan output line, the reference output line, and the light emitting output line along the second direction may be substantially equal.
  • average lengths of the data signal line Data and the first power line VDD along the first direction are substantially equal.
  • the distances between the first signal lines electrically connected to adjacent first scan signal lines and the border B of the display area are substantially equal, and the average lengths of the first signal lines electrically connected to adjacent first scan signal lines along the second direction are substantially equal.
  • the distances between the first signal lines electrically connected to adjacent first scan signal lines and the border B of the display area are substantially equal, and when the sheet resistances of the first conductive layer and the second conductive layer are the same, the resistances of the first signal lines electrically connected to adjacent first scan signal lines can be made equal.
  • the areas of overlapping regions between first signal lines electrically connected to adjacent first scan signal lines and corresponding second signal lines are substantially equal.
  • the areas of overlapping regions between first signal lines electrically connected to adjacent first scan signal lines and corresponding second signal lines are substantially equal, and when the sheet resistances of the first conductive layer and the second conductive layer are the same, the resistances of the first signal lines electrically connected to adjacent first scan signal lines can be made equal.
  • the driving circuit layer may further include: a first signal connection line 11 located in the first conductive layer.
  • the first signal connection line 11 may extend along the second direction D2 and be electrically connected to the 2j-1 third scanning signal line G3 (2j-1) and the 2j third scanning signal line G3 (2j), respectively.
  • the first signal connection line 11 may be an integral structure with the 2j-1th third scan signal line G3 (2j-1) and the 2jth third scan signal line G3 (2j).
  • an orthographic projection of the first signal connection line 11 on the substrate at least partially overlaps an orthographic projection of the 2j-1 th first scan output line GOUTL1 ( 2j-1 ) on the substrate.
  • the length of the first signal connection line 11 along the first direction may be substantially equal to the length of the third scan signal line along the second direction.
  • the orthographic projection of the jth third scan output line GOUTL3(j) on the substrate at least partially overlaps the orthographic projection of the 2jth third scan signal line G3(2j) on the substrate, and is electrically connected to the 2jth third scan signal line G3(2j).
  • the jth third scan output line GOUTL3(j) is electrically connected to the 2j-1th third scan signal line G3(2j-1) through the 2jth third scan signal line G3(2j) and the first signal connection line 11.
  • the driving circuit layer may further include: a second signal connection line 12 located in the second conductive layer, and the second signal connection line 12 may extend along the first direction D1 .
  • the 2j-th second scan signal line G2(2j) may include: a first scan connection portion G2A and a second scan connection portion G2B connected to each other, wherein the first scan connection portion G2A extends along the first direction D1, the second scan connection portion G2B extends along the second direction D2, and the first signal connection line 11 may be located on a side of the second scan connection portion G2B close to the display area AA.
  • the orthographic projection of the second scan connection portion G2B on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line GOUTL1(2j-1), the jth second scan output line GOUTL2(j), the jth third scan output line GOUTL3(j) and the second signal connection line 12 on the substrate, and is electrically connected to the jth second scan output line GOUTL2(j) and the second signal connection line 12, respectively.
  • the orthographic projection of the second signal connection line 12 on the substrate at least partially overlaps with the orthographic projection of the 2j-1th second scanning signal line G2 (2j-1) and the first signal connection line 11 on the substrate, and is electrically connected to the 2j-1th second scanning signal line G2 (2j-1).
  • the driving circuit layer may further include: a third signal connection line 13 located in the second conductive layer, and the third signal connection line 13 extends along the first direction D1 .
  • the distances between the second signal connection line 12 and the third signal connection line 13 near the boundary of the display area and the boundary of the display area can be approximately equal, and the distance between the 2j-1th second scanning signal line G2 (2j-1) near the boundary B of the display area and the boundary of the display area can be approximately equal.
  • the distances between the second signal connection line 12 and the third signal connection line 13 away from the boundary of the display area and the boundary of the display area may be substantially equal.
  • an average length of the second signal connection line 12 along the second direction may be substantially equal to an average length of the third signal connection line 13 along the second direction.
  • the 2jth light-emitting signal line EM (2j) may include: a first light-emitting connection portion EMA and a second light-emitting connection portion EMB connected to each other, the first light-emitting connection portion EMA extending along a first direction D1, the second light-emitting connection portion extending along a second direction D2, and the second light-emitting connection portion EMB being located between the reference power supply line REFL and the second scan connection portion G2B.
  • the orthographic projection of the second light-emitting connection portion EMB on the substrate at least partially overlaps with the orthographic projections of the j-th light-emitting output line EMOUTL(j), the j-th third scan output line GOUTL3(j), the 2j-th first scan output line GOUTL1(2j) and the third signal connection line 13 on the substrate, and is electrically connected to the j-th light-emitting output line EMOUTL(j) and the third signal connection line 13, respectively.
  • the orthographic projection of the third signal connection line 13 on the substrate at least partially overlaps with the orthographic projection of the 2j-1 th light emitting signal line EM(2j-1), the first signal connection line 11, and the second scanning connection portion G2B on the substrate, and is electrically connected to the 2j-1 th light emitting signal line EM(2j-1).
  • the j th light emitting output line EMOUTL(j) is electrically connected to the 2j-1 th light emitting signal line EM(2j-1) through the second light emitting connection portion EMB and the third signal connection line 13.
  • a length of an overlapping region of the second light emitting connection portion and the 2j-th first scan output line along the first direction is greater than a length of the first light emitting connection portion along the second direction.
  • the first signal line electrically connected to the i-th first scan signal line includes: the i-th first scan output line, that is, the first signal line electrically connected to the 2j-1-th first scan signal line G1 (2j-1) may include: the 2j-1-th first scan output line GOUTL1 (2j-1), and the first signal line electrically connected to the 2j-th first scan signal line G1 (2j) may include: the 2j-th first scan output line GOUTL1 (2j).
  • the second signal line corresponding to the first signal line electrically connected to the 2j-1th first scan signal line G1 (2j-1) may include a first signal connection line 11 and a 2jth second scan signal line G2 (2j).
  • the second signal line corresponding to the first signal line electrically connected to the 2j-th first scanning signal line G1 ( 2 j ) may include the 2j-th emission signal line EM ( 2 j ).
  • the orthographic projection of the 2j-1th reference output line REFOUTL (2j-1) on the substrate at least partially overlaps with the orthographic projection of the first signal connection line 11 and the 2j-1th reference signal line REF (2j-1) on the substrate, and is electrically connected to the 2j-1th reference signal line REF (2j-1).
  • the orthographic projection of the 2j-th reference output line REFOUTL (2j) on the substrate at least partially overlaps with the orthographic projection of the second scanning connection portion G2B, the second light emitting connection portion EMB and the 2j-th reference signal line REF (2j) on the substrate, and is electrically connected to the 2j-th reference output line REFOUTL (2j).
  • the driving circuit layer may further include: a first signal connection line 21 located in the first conductive layer.
  • the first signal connection line 21 may extend along the second direction D2 and be electrically connected to the 2j-1th third scanning signal line G3 (2j-1) and the 2jth third scanning signal line G3 (2j), respectively.
  • the orthographic projection of the first signal connection line 21 on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line GOUTL1 (2j-1) and the 2jth first scan output line GOUTL1 (2j) on the substrate.
  • the orthographic projection of the j-th third scan output line GOUTL3(j) on the substrate at least partially overlaps the orthographic projection of the 2j-th third scan signal line G3(2j) on the substrate, and is electrically connected to the 2j-th third scan signal line G3(2j).
  • the j-th third scan output line GOUTL3(j) is electrically connected to the 2j-1-th third scan signal line G3(2j-1) through the 2j-th third scan signal line G3(2j) and the first signal connection line.
  • the driving circuit layer may further include: a second signal connection line 22 located in the first conductive layer, and a third signal connection line 23 and a fourth signal connection line 24 located in the second conductive layer.
  • the second signal connection line 22 extends along the second direction D2
  • the third signal connection line 23 and the fourth signal connection line 24 at least partially extend along the first direction D1
  • the second signal connection line 22 is located on a side of the first signal connection line 21 away from the display area.
  • the orthographic projection of the second signal connection line 22 on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line GOUTL1(2j-1), the 2jth first scan output line GOUTL1(2j), the jth second scan output line GOUTL2(j), the jth third scan output line GOUTL3(j), the third signal connection line 23 and the fourth signal connection line 24 on the substrate, and is electrically connected to the jth second scan output line GOUTL2(j), the third signal connection line 23 and the fourth signal connection line 24, respectively.
  • the orthographic projection of the third signal connection line 23 on the substrate at least partially overlaps with the orthographic projection of the first signal connection line 21 and the 2j-1 second scanning signal line G2 (2j-1) on the substrate, and is electrically connected to the 2j-1 second scanning signal line G2 (2j-1).
  • the j-th second scanning output line GOUTL2 (j) is electrically connected to the 2j-1 second scanning signal line G2 (2j-1) through the second signal connection line 22 and the third signal connection line 23.
  • the orthographic projection of the fourth signal connection line 24 on the substrate at least partially overlaps the orthographic projection of the first signal connection line 21 and the 2j-th second scanning signal line G2 (2j) on the substrate, and is electrically connected to the 2j-th second scanning signal line G2 (2j).
  • the j-th second scanning output line GOUTL2 (j) is electrically connected to the 2j-1-th second scanning signal line G2 (2j) through the second signal connection line 22 and the fourth signal connection line 24.
  • the driving circuit layer may further include: a fifth signal connection line 25 located in the first conductive layer, and a sixth signal connection line 26 and a seventh signal connection line 27 located in the second conductive layer.
  • the fifth signal connection line 25 may extend along the second direction D2
  • the sixth signal connection line 26 and the seventh signal connection line 27 may at least partially extend along the first direction D1
  • the fifth signal connection line 25 may be located on a side of the second signal connection line 22 away from the display area.
  • the orthographic projection of the fifth signal connection line 25 on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line GOUTL1(2j-1), the 2jth first scan output line GOUTL1(2j), the jth second scan output line GOUTL2(j), the jth third scan output line GOUTL3(j), the jth light emitting output line EMOUTL(j), the sixth signal connection line 26 and the seventh signal connection line 27 on the substrate, and is electrically connected to the jth light emitting output line EMOUTL(j), the sixth signal connection line 26 and the seventh signal connection line 27, respectively.
  • the orthographic projection of the sixth signal connection line 26 on the substrate at least partially overlaps with the orthographic projections of the first signal connection line 21, the second signal connection line 22 and the 2j-1th light-emitting signal line EM (2j-1) on the substrate, and is electrically connected to the 2j-1th light-emitting signal line EM (2j-1).
  • the orthographic projection of the seventh signal connection line 27 on the substrate at least partially overlaps with the orthographic projections of the first signal connection line 21, the second signal connection line 22 and the 2j-th luminous signal line EM (2j) on the substrate, and is electrically connected to the 2j-th luminous signal line EM (2j).
  • the first signal line electrically connected to the i-th first scan signal line includes: the i-th first scan output line, i.e., the first signal line electrically connected to the 2j-1th first scan signal line G1(2j-1) includes the 2j-1th first scan output line GOUTL1(2j-1), and the first signal line electrically connected to the 2j-th first scan signal line G1(2j) includes the 2j-th first scan output line GOUTL1(2j).
  • the second signal line corresponding to the first signal line electrically connected to the 2j-1th first scan signal line may include a first signal connection line 21 , a second signal connection line 22 , and a fifth signal connection line 25 .
  • the second signal line corresponding to the first signal line electrically connected to the 2j-th first scan signal line G1 ( 2 j ) may include a first signal connection line 21 , a second signal connection line 22 , and a fifth signal connection line 25 .
  • the length of the first signal connection line 21 along the first direction D1, the length of the second signal connection line 22 along the first direction D1, and the length of the fifth signal connection line 25 along the first direction D1 may be substantially equal or may be unequal, which is not limited in the present disclosure.
  • the distance between the third signal connection line 23 near the boundary of the display area and the display area may be substantially equal to the distance between the 2j-1th first scan output line GOUTL1 (2j-1) near the boundary B of the display area and the display area.
  • the distance between the fourth signal connection line 24 near the boundary of the display area and the display area may be substantially equal to the distance between the 2j-1th first scan output line GOUTL1 (2j-1) near the boundary B of the display area and the display area.
  • the length of the third signal connection line 23 along the first direction D1 may be substantially equal to the length of the fourth signal connection line 24 along the first direction D1.
  • the distance between the sixth signal connection line 26 near the boundary of the display area and the display area may be substantially equal to the distance between the 2j-1th first scan output line GOUTL1 (2j-1) near the boundary B of the display area and the display area.
  • the distance between the seventh signal connection line 27 near the boundary of the display area and the display area may be substantially equal to the distance between the 2j-1th first scan output line GOUTL1 (2j-1) near the boundary B of the display area and the display area.
  • the length of the sixth signal connection line 26 along the first direction D1 may be substantially equal to the length of the seventh signal connection line 27 along the first direction D1 and greater than the length of the third signal connection line 23 along the first direction D1.
  • the orthographic projection of the 2j-1th reference output line REFOUTL (2j-1) on the substrate at least partially overlaps with the orthographic projections of the first signal connection line 21, the second signal connection line 22, the fifth signal connection line 25 and the 2j-1th reference signal line REF (2j-1) on the substrate, and is electrically connected to the 2j-1th reference signal line REF (2j-1).
  • the orthographic projection of the 2j-th reference output line REFOUTL (2j) on the substrate at least partially overlaps with the orthographic projections of the first signal connection line 21, the second signal connection line 22, the fifth signal connection line 25 and the 2j-th reference signal line REF (2j) on the substrate, and is electrically connected to the 2j-th reference output line REFOUTL (2j).
  • the driving circuit layer may further include: a first signal connection line 31 located in the first conductive layer.
  • the first signal connection line 31 may extend along the second direction D2 and be electrically connected to the 2j-1th third scanning signal line G3 (2j-1) and the 2jth third scanning signal line G3 (2j), respectively.
  • the orthographic projection of the first signal connection line 31 on the substrate at least partially overlaps with the orthographic projections of the 2j-1st first scan output line GOUTL1(2j-1), the jth second scan output line GOUTL2(j), and the jth third scan output line GOUTL3(j) on the substrate, and is electrically connected to the jth third scan output line GOUTL3(j).
  • the jth third scan output line GOUTL3(j) is electrically connected to the 2j-1st third scan signal line G3(2j-1) and the 2jth third scan signal line G3(2j) through the first signal connection line 31, respectively.
  • the length of the first signal connection line 31 along the first direction may be substantially equal to the length of the third scan signal line along the second direction.
  • the 2j-1th second scan signal line G2 (2j-1) includes: a first scan connection portion G2C and a second scan connection portion G2D connected to each other, the first scan connection portion G2C extends along the first direction D1, and the second scan connection portion G2D extends along the second direction D2.
  • the j-th second scan output line GOUTL2(j) includes a first scan output connection portion GOLA and a second scan output connection portion GOLB connected to each other, the first scan output connection portion GOLA extending along a first direction D1, and the second scan output connection portion GOLB extending along a second direction D2.
  • a virtual straight line extending along the second direction D2 passes through the second scan connection portion G2D and the second scan output connection portion GOLB, and the second scan connection portion G2D is located on a side of the first signal connection line 31 close to the display area AA.
  • the orthographic projection of the second scan connection portion G2D on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line GOUTL1(2j-1) and the first scan output connection portion GOLA on the substrate, and is electrically connected to the first scan output connection portion GOLA.
  • an orthographic projection of the first scan output connection portion GOLA on the substrate at least partially overlaps an orthographic projection of the first signal connection line 31 on the substrate.
  • the orthographic projection of the second scan output connection portion GOLB on the substrate at least partially overlaps with the orthographic projections of the 2j-th third scan signal line G3 (2j) and the 2j-th second scan signal line G2 (2j) on the substrate, and is electrically connected to the 2j-th second scan signal line G2 (2j).
  • the driving circuit layer further includes: a second signal connection line 32 located in the first conductive layer, and the second signal connection line 32 extends along the first direction D1 .
  • the orthographic projection of the second signal connection line 32 on the substrate at least partially overlaps with the orthographic projection of the 2j-th first scan output line GOUTL1(2j) on the substrate, and is electrically connected to the 2j-th first scan output line GOUTL1(2j) and the 2j-th first scan signal line G1(2j), respectively.
  • the length of the second signal connection line 32 along the second direction D2 is greater than the length of the first scan signal line along the second direction D2 .
  • the j-th light emitting output line EMOUTL(j) includes: a first light emitting output connection portion EOLA and a second light emitting output connection portion EOLB connected to each other, the first light emitting output connection portion EOLA extending along a first direction D1, and the second light emitting output connection portion EOLB extending along a second direction D2; the second light emitting output connection portion EOLB is located on a side of the second scanning output connection portion GOLB close to the display area AA.
  • the orthographic projection of the second light-emitting output connection portion EOLB on the substrate at least partially overlaps with the orthographic projections of the second signal connection line 32, the 2j-1th light-emitting signal line EM(2j-1), the 2jth light-emitting signal line EM(2j), the 2jth third scanning signal line G3(2j) and the 2jth second scanning signal line G2(2j) on the substrate, and is electrically connected to the 2j-1th light-emitting signal line EM(2j-1) and the 2jth light-emitting signal line EM(2j), respectively.
  • the first signal line electrically connected to the 2j-1th first scan signal line G1 ( 2j-1) may include a 2j-1th first scan output line GOUTL1 ( 2j-1).
  • the first signal line electrically connected to the 2j-th first scan signal line G1 ( 2 j ) may include the 2j-th first scan output line GOUTL1 ( 2 j ) and the second signal connection line 32 .
  • the second signal line corresponding to the first signal line electrically connected to the 2j-1th first scan signal line may include a first signal connection line 31 and a 2j-1th second scan signal line G2 (2j-1).
  • the second signal line corresponding to the first signal line electrically connected to the 2j-th first scan signal line G1 ( 2 j ) may include the j-th emission output line EMOUTL(j).
  • the orthographic projection of the 2j-1th reference output line REFOUTL(2j-1) on the substrate at least partially overlaps with the orthographic projection of the 2j-1th reference signal line REF(2j-1) on the substrate, and is electrically connected to the 2j-1th reference signal line REF(2j-1).
  • the orthographic projection of the 2j-th reference output line REFOUTL(2j) on the substrate at least partially overlaps with the orthographic projection of the 2j-th reference signal line REF(2j) on the substrate, and is electrically connected to the 2j-th reference output line REFOUTL(2j).
  • the distance between the reference power supply line REFL away from the boundary of the display area and the boundary of the 2j-1th first scan output line GOUTL1 (2j-1) close to the display area can be approximately equal to the distance between the reference power supply line REFL away from the boundary of the display area and the boundary of the second signal connection line close to the display area, and is a.
  • the length of the 2j-1th first scan output line GOUTL1 (2j-1) along the second direction is substantially equal to the length of the second signal connection line 32 along the second direction, and is b.
  • the actual value of the first scan output line may be 2 micrometers smaller than the theoretical value.
  • the square resistance difference between the first signal line electrically connected to the 2j-1 first scan signal line and the first signal line electrically connected to the 2j first scan signal line is relatively large, different manufacturing materials may be used or the directions of the signal lines may be changed so that the resistance of the first signal line electrically connected to the 2j-1 first scan signal line and the first signal line electrically connected to the 2j first scan signal line in the same area and the capacitance between the overlapping areas with the corresponding second signal lines are equal.
  • the driving circuit layer may further include: a shielding layer, the shielding layer is located on a side of the first conductive layer close to the substrate.
  • the shielding layer at least includes: a reference signal line and an initial signal line.
  • the driving circuit layer may further include: a semiconductor layer, the semiconductor layer is located between the shielding layer and the first conductive layer, and the semiconductor layer may include at least: an active layer of a plurality of transistors.
  • the storage capacitor in the pixel driving circuit may include: a first plate, a second plate and a third plate, wherein the first plate and the third plate are electrically connected.
  • the first plate may be located in the shielding layer
  • the second plate may be located in the semiconductor layer
  • the third plate may be located in the second conductive layer.
  • the storage capacitor includes three plates, which can improve the storage capacity of the storage capacitor, ensure the stability of the signal of the first node in the pixel driving circuit, and improve the reliability of the display panel.
  • the display panel may further include: a first insulating layer located between the blocking layer and the semiconductor layer, a second insulating layer located between the semiconductor layer and the first conductive layer, a third insulating layer located between the first conductive layer and the second conductive layer, and a fourth insulating layer and a planarizing layer located on a side of the second conductive layer away from the substrate.
  • the following is an exemplary description of the preparation process of the display panel.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating, and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made of a certain material on a substrate by deposition, coating, or other processes. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display panel.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • a process of preparing a display panel may include the following operations.
  • forming the shielding layer pattern may include: sequentially depositing a shielding film on a substrate, patterning the shielding film through a patterning process, and forming a shielding layer pattern covering the substrate.
  • FIG8 is a schematic diagram of the display panel provided in FIG5 to FIG7 after the shielding layer pattern is formed. FIG8 is illustrated by taking the pixel circuits of the first column of the 2j-1th row, the second column of the 2j-1th row, the first column of the 2jth row, and the second column of the 2jth row in the display area AA as an example.
  • the shielding layer pattern may include at least a first electrode C1 and a first connection line VL1 of a storage capacitor of a sub-pixel located in the display area, and an initial signal line and a reference signal line at least partially located in the display area.
  • FIG8 is illustrated by taking the initial signal line located in the display area and the reference signal line located in the display area AA and the non-display area AA' as an example, and FIG8 only shows the 2j-1st initial signal line INIT (2j-1), the 2jth initial signal line INIT (2j), the reference signal line REF (2j-1), and the 2jth reference signal line REF (2j).
  • the initial signal line, the reference signal line and the first connection line VL1 extend along the first direction D1, and the initial signal line electrically connected to the same pixel driving circuit is located on a side of the reference signal line electrically connected away from the first plate of the storage capacitor of the pixel driving circuit.
  • the 2j-1st initial signal line INIT (2j-1) electrically connected to the pixel driving circuit of the 2j-1st row is located on a side of the 2j-1st reference signal line REF (2j-1) electrically connected to the pixel driving circuit of the 2j-1st row away from the first plate C1 of the storage capacitor of the pixel driving circuit of the 2j-1st row
  • the 2jth initial signal line INIT (2j) electrically connected to the pixel driving circuit of the 2jth row is located on a side of the 2jth reference signal line REF (2j) electrically connected to the pixel driving circuit of the 2jth row away from the first plate C1 of the storage capacitor of the pixel driving circuit of the 2j-1st row.
  • the first plate C1 of the storage capacitor is a strip-shaped structure and is located between the reference signal line electrically connected to the pixel driving circuit and the first connection line of the pixel driving circuit.
  • the first plate C1 of the storage capacitor of the 2j-1st row of pixel driving circuits is located between the 2j-1st reference signal line REF(2j-1) electrically connected to the 2j-1st row of pixel driving circuits and the first connection line VL1 of the 2j-1st row of pixel driving circuits.
  • the first plate C1 of the storage capacitor of the 2j-th row of pixel driving circuits is located between the 2j-th reference signal line REF(2j) electrically connected to the 2j-th row of pixel driving circuits and the first connection line VL1 of the 2j-th row of pixel driving circuits.
  • the initial signal line and the scanning signal line can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 9 and 10 , where FIG. 9 is a schematic diagram of a semiconductor layer pattern of a display panel provided in FIGS. 5 to 7 , and FIG. 10 is a schematic diagram of a display panel provided in FIGS. 5 to 7 after a semiconductor layer pattern is formed.
  • the semiconductor layer pattern may include at least active layers T11 of the first transistor T1 to T51 of the fifth transistor T5 located in each sub-pixel of the display area.
  • the active layer T11 of the first transistor and the active layer T21 of the second transistor are connected to each other as an integral structure.
  • the active layer T31 of the third transistor, the active layer T41 of the fourth transistor, and the active layer T51 of the fifth transistor are separately provided.
  • the active layer T31 of the third transistor, the active layer T41 of the fourth transistor, and the active layer T51 of the fifth transistor may be located on the same side of the integrated structure of the active layer T11 of the first transistor and the active layer T21 of the second transistor in the present sub-pixel.
  • the active layer T31 of the third transistor in the present row of sub-pixels may be located on a side of the integrated structure of the active layer T11 of the first transistor and the active layer T21 of the second transistor close to the previous row of sub-pixels
  • the active layer T41 of the fourth transistor in the present row of sub-pixels may be located on a side of the integrated structure of the active layer T11 of the first transistor and the active layer T21 of the second transistor close to the next row of sub-pixels
  • the active layer T51 of the fifth transistor in the present column of sub-pixels may be located on a side of the integrated structure of the active layer T11 of the first transistor and the active layer T21 of the second transistor close to the previous column of sub-pixels.
  • the active layer T31 of the third transistor, the active layer T41 of the fourth transistor, and the active layer T51 of the fifth transistor may be shaped like a strip structure, the active layer T11 of the first transistor may be shaped like a "7", and the active layer T21 of the second transistor may be shaped like a horizontally flipped "7".
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region T11_2 of the active layer T11 of the first transistor may serve as the second region T21_2 of the active layer T21 of the second transistor, and the first region and the second region of the active layer of the remaining transistors except the second region T11_2 of the active layer T11 of the first transistor and the second region of the active layer T21 of the second transistor may be separately provided.
  • the orthographic projection of the first electrode plate of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of the active layer T51 of the fifth transistor and the integral structure of the active layer T11 of the first transistor and the active layer T21 of the second transistor on the substrate.
  • the first electrode plate of the storage capacitor can shield the active layer T51 of the fifth transistor to prevent the influence of light on the active layer of the driving transistor, and can improve the reliability of the pixel driving circuit.
  • forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 11 to 16, wherein FIG. 11 is a schematic diagram of the first conductive layer pattern of the display panel provided in FIG. 5, FIG. 12 is a schematic diagram of the display panel provided in FIG. 5 after the first conductive layer pattern is formed, FIG. 13 is a schematic diagram of the first conductive layer pattern of the display panel provided in FIG.
  • FIG. 14 is a schematic diagram of the display panel provided in FIG. 6 after the first conductive layer pattern is formed
  • FIG. 15 is a schematic diagram of the first conductive layer pattern of the display panel provided in FIG. 7
  • FIG. 16 is a schematic diagram of the display panel provided in FIG. 7 after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a gate metal (GATE) layer.
  • Figures 11 to 16 only show the 2j-1th first scanning signal line G1(2j-1), the 2jth first scanning signal line G1(2j), the 2j-1th second scanning signal line G2(2j-1), the 2jth second scanning signal line G2(2j), the 2j-1th third scanning signal line G3(2j-1), the 2jth second scanning signal line G3(2j), the 2j-1th luminous signal line EM(2j-1) and the 2jth luminous signal line EM(2j).
  • the first conductive layer pattern may include at least: control electrodes T12 of the first transistor to T52 of the fifth transistor of the sub-pixel located in the display area, a first scan signal line, a second scan signal line, a third scan signal line and a light-emitting signal line at least partially located in the display area, and a reference power supply line REFL located in the non-display area.
  • At least portions of the first, second, third and light emitting signal lines extend in the first direction D1
  • the reference power supply line REFL extends in the second direction D2 .
  • the first scanning signal line, the second scanning signal line, the third scanning signal line and the light-emitting signal line can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the overlapping area of the third scan signal line electrically connected to the sub-pixel and the active layer of the third transistor serves as the control electrode T32 of the third transistor of the sub-pixel
  • the overlapping area of the second scan signal line electrically connected to the sub-pixel and the active layer of the second transistor serves as the control electrode T22 of the second transistor of the sub-pixel
  • the overlapping area of the first scan signal line electrically connected to the sub-pixel and the active layer of the first transistor serves as the control electrode T12 of the first transistor of the sub-pixel
  • the overlapping area of the light-emitting signal line electrically connected to the sub-pixel and the active layer of the fourth transistor serves as the control electrode T42 of the fourth transistor of the sub-pixel
  • the control electrode T52 of the fifth transistor of each sub-pixel is located between the second scan signal line and the first scan signal line electrically connected to the sub-pixel.
  • control electrode T52 of the fifth transistor extends along the first direction D1.
  • the i-th third scan signal line, the i-th reference signal line, the i-th second scan signal line, the i-th first scan signal line and the i-th light-emitting signal line are arranged in sequence along the second direction D2, the i-th third scan signal line is located on the side of the i-th reference signal line close to the i-1-th light-emitting signal line, and the i-th light-emitting signal line is located on the side of the i-th first scan signal line close to the i+1-th third scan signal line.
  • the 2j-1th third scanning signal line G3(2j-1), the 2j-1th reference signal line REF(2j-1), the 2j-1th second scanning signal line G2(2j-1), the 2j-1th first scanning signal line G1(2j-1) and the 2j-1th light-emitting signal line EM(2j-1) are arranged along the second direction D2, the 2j-1th third scanning signal line G3(2j-1) is located on the side of the 2j-1th reference signal line REF(2j-1) close to the 2j-2th light-emitting signal line EM(2j-2), and the 2j-1th light-emitting signal line EM(2j-1) is located on the side of the 2j-1th first scanning signal line G1(2j-1) close to the 2j-3 third scanning signal line G3(2j).
  • the orthographic projection of the i-th third scanning signal line on the substrate is located between the orthographic projection of the i-th initial signal line on the substrate and the orthographic projection of the i-th reference signal line on the substrate.
  • the orthographic projection of the 2j-th third scanning signal line G3(2j) on the substrate is located between the orthographic projection of the 2j-th initial signal line INIT(2j) on the substrate and the orthographic projection of the 2j-th reference signal line REF(2j) on the substrate.
  • the first conductive layer pattern of the display panel provided in Figure 5 may also include: a first signal connection line 11 electrically connected to the 2j-1th third scanning signal line G3 (2j-1) and the 2jth second scanning signal line G3 (2j).
  • the first signal connection line 11 may extend along the second direction D2 , and the first signal connection line 11 may be located at a side of the reference power supply line REFL close to the display area.
  • the first signal connection line 11 is an integral structure with the 2j-1th third scanning signal line G3 ( 2j-1) and the 2jth second scanning signal line G3 ( 2j ).
  • the 2j-1th first scan signal line G1(2j-1), the 2j-th first scan signal line G1(2j), the 2j-1th second scan signal line G2(2j-1), the 2j-1th third scan signal line G3(2j-1), the 2j-3rd scan signal line G3(2j), and the 2j-1th light emitting signal line EM(2j-1) extend along the first direction D1.
  • the 2j-th second scan signal line G2 (2j) includes: a first scan connection portion G2A and a second scan connection portion G2B connected to each other, wherein the first scan connection portion G2A extends along the first direction D1, the second scan connection portion G2B extends along the second direction D2, and the first signal connection line 11 is located on a side of the second scan connection portion G2B close to the display area AA.
  • the 2j-th light-emitting signal line EM (2j) may include: a first light-emitting connection portion EMA and a second light-emitting connection portion EMB connected to each other, the first light-emitting connection portion EMA extending along the first direction D1, the second light-emitting connection portion EMB extending along the second direction D2, and the second light-emitting connection portion EMB being located between the reference power supply line REFL and the second scan connection portion G2B.
  • the first conductive layer pattern of the display panel provided in FIG. 6 further includes: a first signal connection line 21 , a second signal connection line 22 and a fifth signal connection line 25 .
  • the first signal connection line 21 is electrically connected to the 2j-1 third scanning signal line G3 (2j-1) and the 2j second scanning signal line G3 (2j), and is an integrated structure with the 2j-1 third scanning signal line G3 (2j-1) and the 2j second scanning signal line G3 (2j).
  • the first signal connection line 21, the second signal connection line 22, and the fifth signal connection line 25 may extend along the second direction D2.
  • the first signal connection line 21, the second signal connection line 22, and the fifth signal connection line 25 may be located on a side of the reference power supply line REF close to the display area
  • the first signal connection line 21 and the second signal connection line 22 may be located on a side of the fifth signal connection line 25 close to the display area
  • the first signal connection line 21 may be located on a side of the second signal connection line 22 close to the display area.
  • the first signal connection line, the second signal connection line and the fifth signal connection line can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the 2j-1th first scan signal line G1(2j-1), the 2j-th first scan signal line G1(2j), the 2j-1th second scan signal line G2(2j-1), the 2j-th second scan signal line G2(2j), the 2j-1th third scan signal line G3(2j-1), the 2j-th third scan signal line G3(2j), the 2j-1th light-emitting signal line EM(2j-1), and the 2j-th light-emitting signal line EM(2j) all extend along the first direction D1.
  • the first conductive layer pattern of the display panel provided in Figure 7 also includes: a first signal connection line 31 electrically connected to the 2j-1th third scanning signal line G3(2j-1) and the 2jth second scanning signal line G3(2j), and a second signal connection line 32 electrically connected to the 2jth first scanning signal line G1(2j).
  • the first signal connection line 31 may extend along the second direction D2 , and the first signal connection line 31 may be located at a side of the reference power supply line REF close to the display area.
  • the second signal connection line 32 may extend along the first direction D1 , and the length of the second signal connection line 32 along the second direction is greater than the width of the 2j-th first scan signal line G1 ( 2j ) along the second direction D2 .
  • the 2j-1th first scan signal line G1(2j-1), the 2j-th first scan signal line G1(2j), the 2j-th second scan signal line G2(2j), the 2j-1th third scan signal line G3(2j-1), the 2j-th third scan signal line G3(2j), the 2j-1th light emitting signal line EM(2j-1), and the 2j-th light emitting signal line EM(2j) all extend along the first direction D1.
  • the 2j-1th second scan signal line G2 (2j-1) includes: a first scan connection portion G2C and a second scan connection portion G2D connected to each other, the first scan connection portion G2C extends along the first direction D1, and the second scan connection portion G2D extends along the second direction D2.
  • the first conductive layer can be used as a shield to perform conductor processing on the semiconductor layer, and the semiconductor layer in the area shielded by the first conductive layer forms the channel area of the first transistor T1 to the fifth transistor T5, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the active layer of the first transistor to the active layer of the fifth transistor are both conductorized.
  • the second area of the active layer of the second transistor (also the second area of the active layer of the first transistor) is reused as the second electrode plate C2 of the storage capacitor and the second electrode T24 of the second transistor.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the first conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIGS. 17 to 19 , wherein FIG. 17 is a schematic diagram of the display panel provided in FIG. 5 after the third insulating layer pattern is formed, FIG. 18 is a schematic diagram of the display panel provided in FIG. 6 after the third insulating layer pattern is formed, and FIG. 19 is a schematic diagram of the display panel provided in FIG. 7 after the third insulating layer pattern is formed.
  • the plurality of via holes in the display panel provided in FIG. 5 may include at least first to ninth via holes V1 to V9 of each sub-pixel located in the display area AA and tenth to nineteenth via holes V10 to V19 located in the non-display area AA′.
  • the number of any of the tenth via hole V10 to the twenty-first via hole V21 may be plural, and may be arranged in an array, and the present disclosure does not make any limitation to this.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the third insulating layer and the second insulating layer in the first via hole V1 are removed to expose the surface of the first region of the active layer of the first transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor to the first region of the active layer of the first transistor through the via hole.
  • the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the control electrode of the fifth transistor and the second area of the active layer of the first transistor (also the second area and the second electrode plate of the active layer of the second transistor) on the substrate, the third insulating layer and the second insulating layer in the second via V2 are removed to expose the surface of the second area of the active layer of the first transistor, the third insulating layer in the second via V2 is removed to expose the control electrode of the fifth transistor, and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor to the control electrode of the fifth transistor and the second area of the active layer of the first transistor (also the second area and the second electrode plate of the active layer of the second transistor) through the via.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the second transistor and the reference signal line electrically connected to the sub-pixel on the substrate, the third insulating layer and the second insulating layer in the third via hole V3 are removed to expose the surface of the first area of the active layer of the second transistor, the first insulating layer to the third insulating layer in the third via hole V3 are removed to expose the surface of the reference signal line electrically connected to the sub-pixel, and the third via hole V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of the active layer of the second transistor and the reference signal line electrically connected to the sub-pixel through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the third transistor on the substrate, the third insulating layer and the second insulating layer in the fourth via hole V4 are removed to expose the surface of the second region of the active layer of the third transistor, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed third transistor to the second region of the active layer of the third transistor through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the third transistor and the initial signal line electrically connected to the sub-pixel on the substrate, the third insulating layer and the second insulating layer in the fifth via hole V5 are removed to expose the surface of the first area of the active layer of the third transistor, the first insulating layer to the third insulating layer in the fifth via hole V5 are removed to expose the surface of the initial signal line electrically connected to the sub-pixel, and the fifth via hole V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of the active layer of the third transistor and the initial signal line electrically connected to the sub-pixel through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the fourth transistor on the substrate, the third insulating layer and the second insulating layer in the sixth via hole V6 are removed to expose the surface of the second region of the active layer of the fourth transistor, and the sixth via hole V6 is configured to connect the second electrode of the subsequently formed fourth transistor to the second region of the active layer of the fourth transistor through the via hole.
  • the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth transistor and the first connecting line on the substrate, the third insulating layer and the second insulating layer in the seventh via V7 are removed to expose the surface of the first area of the active layer of the fourth transistor, the first insulating layer to the third insulating layer in the seventh via V7 are removed to expose the surface of the first connecting line, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of the active layer and the first connecting line of the fourth transistor through the via.
  • the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fifth transistor on the substrate, the third insulating layer and the second insulating layer in the eighth via V8 are removed to expose the surface of the first area of the active layer of the fifth transistor, and the eighth via V8 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of the active layer of the fifth transistor through the via.
  • the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projections of the second region of the active layer and the first electrode plate of the fifth transistor on the substrate, the third insulating layer and the second insulating layer in the ninth via V9 are removed to expose the surface of the second region of the active layer of the fifth transistor, the first insulating layer to the third insulating layer in the ninth via V9 are removed to expose the surface of the first electrode plate, and the ninth via V9 is configured to connect the second electrode of the subsequently formed fifth transistor to the second region of the active layer and the first electrode plate of the fifth transistor through the via.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the 2j-1th reference signal line REF(2j-1) on the substrate, the first to third insulating layers in the tenth via hole V10 are removed to expose the surface of the 2j-1th reference signal line REF(2j-1), and the tenth via hole V10 is configured to connect the subsequently formed 2j-1th reference output line REFOUTL(2j-1) to the 2j-1th reference signal line REF(2j-1) through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the 2j-th reference signal line REF(2j) on the substrate, the first insulating layer to the third insulating layer in the tenth via hole V10 are removed to expose the surface of the 2j-th reference signal line REF(2j), and the eleventh via hole V11 is configured to connect the subsequently formed 2j-th reference output line REFOUTL(2j) to the 2j-1-th reference signal line REF(2j) through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the 2j-1th first scan signal line G1 (2j-1) on the substrate, the third insulating layer in the twelfth via hole V12 is removed to expose the surface of the 2j-1th first scan signal line G1 (2j-1), and the twelfth via hole V12 is configured to connect the subsequently formed 2j-1th first scan output line GOUTL1 (2j-1) to the 2j-1th first scan signal line G1 (2j-1) through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the 2j-th first scan signal line G1 (2j) on the substrate, the third insulating layer in the thirteenth via hole V13 is removed to expose the surface of the 2j-th first scan signal line G1 (2j), and the thirteenth via hole V13 is configured to connect the subsequently formed 2j-th first scan output line GOUTL1 (2j) to the 2j-th first scan signal line G1 (2j) through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the 2j-1th second scanning signal line G2 (2j-1) on the substrate, the third insulating layer in the fourteenth via hole V14 is removed to expose the surface of the 2j-1th second scanning signal line G2 (2j-1), and the fourteenth via hole V14 is configured to connect a subsequently formed second signal connecting line to the 2j-1th second scanning signal line G2 (2j-1) through the via hole.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second scanning connection portion of the 2j-th second scanning signal line G2(2j) on the substrate, the third insulating layer in the fifteenth via hole V15 is removed to expose the surface of the second scanning connection portion of the 2j-th second scanning signal line G2(2j), and the fifteenth via hole V15 is configured to connect the subsequently formed j-th second scanning output line GOUTL2(j) and the second signal connection line to the 2j-th second scanning signal line G2(2j) through the via hole.
  • the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the 2j-th third scan signal line G3(2j) on the substrate, the third insulating layer in the sixteenth via hole V16 is removed to expose the surface of the 2j-th third scan signal line G3(2j), and the sixteenth via hole V16 is configured to connect the subsequently formed j-th third scan output line GOUTL3(j) to the 2j-th third scan signal line G3(2j) through the via hole.
  • the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the 2j-1th light-emitting signal line EM (2j-1) on the substrate, the third insulating layer in the seventeenth via hole V17 is removed to expose the surface of the 2j-1th light-emitting signal line EM (2j-1), and the seventeenth via hole V17 is configured to connect a subsequently formed third signal connecting line to the 2j-1th light-emitting signal line EM (2j-1) through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second light-emitting connection portion of the 2j-th light-emitting signal line EM (2j) on the substrate, the third insulating layer in the eighteenth via hole V18 is removed to expose the surface of the second light-emitting connection portion of the 2j-th light-emitting signal line EM (2j), and the eighteenth via hole V18 is configured to connect the subsequently formed j-th light-emitting output line and the third signal connection line to the 2j-th light-emitting signal line EM (2j) through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the reference power supply line on the substrate, the third insulating layer in the nineteenth via hole V19 is removed to expose the surface of the reference power supply line, and the nineteenth via hole V19 is configured to connect a subsequently formed reference output line to the reference power supply line through the via hole.
  • the plurality of via holes in the display panel provided in FIG. 6 may include at least first to ninth via holes V1 to V9 of each sub-pixel located in the display area AA and tenth to twenty-first via holes V10 to V21 located in the non-display area AA′.
  • the number of any of the tenth via hole V10 to the twenty-first via hole V21 may be plural, and may be arranged in an array, and the present disclosure does not make any limitation to this.
  • the first to thirteenth via holes V13 and the sixteenth via hole V16 in FIG. 18 are the same as the first to thirteenth via holes V13 and the sixteenth via hole V16 in FIG. 17 in terms of their locations and connection structures.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the 2j-1th second scanning signal line G2 (2j-1) on the substrate, the third insulating layer in the fourteenth via hole V14 is removed to expose the surface of the 2j-1th second scanning signal line G2 (2j-1), and the fourteenth via hole V14 is configured to connect a subsequently formed third signal connecting line to the 2j-1th second scanning signal line G2 (2j-1) through the via hole.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second scanning connection portion of the 2j-th second scanning signal line G2 (2j) on the substrate, the third insulating layer in the fifteenth via hole V15 is removed to expose the surface of the second scanning connection portion of the 2j-th second scanning signal line G2 (2j), and the fifteenth via hole V15 is configured to connect a subsequently formed fourth signal connection line to the 2j-th second scanning signal line G2 (2j) through the via hole.
  • the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the 2j-1th light-emitting signal line EM (2j-1) on the substrate, the third insulating layer in the seventeenth via hole V17 is removed to expose the surface of the 2j-1th light-emitting signal line EM (2j-1), and the seventeenth via hole V17 is configured to connect the subsequently formed sixth signal connection line to the 2j-1th light-emitting signal line EM (2j-1) through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second light-emitting connection portion of the 2j-th light-emitting signal line EM (2j) on the substrate, the third insulating layer in the eighteenth via hole V18 is removed to expose the surface of the 2j-th light-emitting signal line EM (2j), and the eighteenth via hole V18 is configured to connect the subsequently formed seventh signal connection line to the 2j-th light-emitting signal line EM (2j) through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the second signal connection line on the substrate, the third insulating layer in the nineteenth via hole V19 is removed to expose the surface of the second signal connection line, and the nineteenth via hole V19 is configured to connect the subsequently formed j-th second scan output line, the third connection signal line and the fourth connection signal line to the second signal connection line through the via hole.
  • the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the fifth signal connection line on the substrate, the third insulating layer in the twentieth via hole V20 is removed to expose the surface of the fifth signal connection line, and the twentieth via hole V20 is configured to connect the subsequently formed j-th light-emitting output line, the sixth connection signal line, and the seventh connection signal line to the fifth signal connection line through the via hole.
  • the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the reference power supply line on the substrate, the third insulating layer in the twenty-first via V21 is removed to expose the surface of the reference power supply line, and the twenty-first via V21 is configured to connect a subsequently formed reference output line to the reference power supply line through the via.
  • the plurality of via holes in the display panel provided in FIG. 7 may include at least first to ninth via holes V1 to V9 of each sub-pixel located in the display area AA and tenth to nineteenth via holes V10 to V19 located in the non-display area AA′.
  • the number of any of the tenth via hole V10 to the nineteenth via hole V19 may be plural, and may be arranged in an array, and the present disclosure does not impose any limitation on this.
  • the first to twelfth vias V1 to V12, the seventeenth vias V17 and the nineteenth vias V19 in FIG. 19 are respectively the same in position and connection structure as the first to twelfth vias V12, the seventeenth vias V17 and the nineteenth vias V19 in FIG. 17 .
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second signal connection line on the substrate, the third insulating layer in the thirteenth via hole V13 is removed to expose the surface of the second signal connection line, and the thirteenth via hole V13 is configured to connect the subsequently formed 2jth first scan output line to the second signal connection line through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second scan connection portion of the 2j-1th second scan signal line G2 (2j-1) on the substrate, the third insulating layer in the fourteenth via hole V14 is removed to expose the surface of the 2j-1th second scan signal line G2 (2j-1), and the fourteenth via hole V14 is configured to connect the subsequently formed jth second scan output line to the 2j-1th second scan signal line G2 (2j-1) through the via hole.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the 2j-th second scanning signal line G2 (2j) on the substrate, the third insulating layer in the fifteenth via hole V15 is removed to expose the surface of the 2j-th second scanning signal line G2 (2j), and the fifteenth via hole V15 is configured to connect the subsequently formed j-th second scanning output line and the second signal connecting line to the 2j-th second scanning signal line G2 (2j) through the via hole.
  • the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the first signal connection line on the substrate, the third insulating layer in the sixteenth via hole V16 is removed to expose the surface of the first signal connection line, and the sixteenth via hole V16 is configured to connect the subsequently formed j-th third scan output line to the first signal connection line through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the 2j-th light-emitting signal line EM (2j) on the substrate, the third insulating layer in the eighteenth via hole V18 is removed to expose the surface of the 2j-th light-emitting signal line EM (2j), and the eighteenth via hole V18 is configured to connect the subsequently formed j-th light-emitting output line to the 2j-th light-emitting signal line EM (2j) through the via hole.
  • forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the third insulating layer, as shown in FIGS. 20 to 25, wherein FIG. 20 is a schematic diagram of the second conductive layer pattern of the display panel provided in FIG. 5, FIG. 21 is a schematic diagram of the display panel provided in FIG. 5 after the second conductive layer pattern is formed, FIG. 22 is a schematic diagram of the display panel provided in FIG. 6 after the second conductive layer pattern is formed, FIG. 23 is a schematic diagram of the display panel provided in FIG.
  • FIG. 24 is a schematic diagram of the second conductive layer pattern of the display panel provided in FIG. 7
  • FIG. 25 is a schematic diagram of the display panel provided in FIG. 7 after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a source-drain metal (SD) layer.
  • SD source-drain metal
  • the second conductive layer pattern may include at least: the first electrode T13 and the second electrode T14 of the first transistor to the first electrode T53 and the second electrode T54 of the fifth transistor of each sub-pixel located in the display area, the third electrode C3 of the storage capacitor, the first power line VDD, the data signal line Data, and the second connection line VL2 located at least partially in the display area, and the first scan output line, the second scan output line, the third scan output line, the light emitting output line, and the reference output line located in the non-display area.
  • the data signal line Data and the first power line VDD at least partially extend in the second direction VDD.
  • the data signal line Data and the first electrode T13 of the first transistor are an integral structure, and the first electrode T13 of the first transistor is electrically connected to the first region of the active layer of the first transistor through a first via hole.
  • the first power line VDD and the first electrode T43 of the fourth transistor of the pixel driving circuit close to the first power line VDD are integrated into a structure, and the first electrode T43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor and the first connection line through the seventh via hole.
  • the first electrode T43 of the fourth transistor of the pixel driving circuit far away from the first power line VDD is separately provided, and the first electrode T43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor and the first connection line through the seventh via hole.
  • the first electrode T43 of the fourth transistor of the pixel driving circuit far away from the first power line VDD is electrically connected to the first power line VDD through the first connection line and the first electrode T43 of the fourth transistor of the pixel driving circuit close to the first power line VDD.
  • the first electrode of the second transistor may be provided separately, or may be integrally formed with the second connection line VL2.
  • the second connection line VL2 may form a mesh structure with the reference signal line, which may improve the uniformity of the reference signal.
  • the second electrode T34 of the third transistor, the second electrode T54 of the fifth transistor and the third electrode plate C3 are an integrated structure
  • the second electrode T44 of the fourth transistor and the first electrode T53 of the fifth transistor are an integrated structure
  • the second electrode T14 of the first transistor, the first electrode T23 of the second transistor and the first electrode T33 of the third transistor can be set separately.
  • the second electrode T44 of the fourth transistor and the first electrode T53 of the fifth transistor are integrally extended along the second direction D2.
  • the second electrode T14 of the first transistor and the first electrode T23 of the second transistor extend along the second direction D2.
  • the first electrode T33 of the third transistor extends along the first direction D1.
  • the second electrode T14 of the first transistor is electrically connected to the second area of the active layer of the first transistor and the control electrode of the fifth transistor through the second via hole
  • the first electrode T23 of the second transistor is electrically connected to the first area of the active layer of the second transistor and the reference signal line electrically connected to the sub-pixel through the third via hole
  • the first electrode T33 of the third transistor is electrically connected to the first area of the active layer of the third transistor and the initial signal line electrically connected to the sub-pixel through the fifth via hole
  • the second electrode T34 of the third transistor (also the second electrode T54 of the fifth transistor and the third electrode plate C3) is electrically connected to the second area of the active layer of the third transistor through the fourth via hole, and is electrically connected to the second area of the active layer of the fifth transistor and the first electrode plate through the ninth via hole
  • the second electrode T44 of the fourth transistor (also the first electrode T53 of the fifth transistor) is electrically connected to the first area of the active layer of the fifth transistor through the eighth via hole
  • the first scan output line, the second scan output line, the third scan output line, the light emitting output line, and the reference output line at least partially extend along the first direction D1.
  • the second conductive layer pattern may further include at least a second signal connection line 12 and a third signal connection line 13 .
  • the second signal connection line 12 and the third signal connection line 13 extend in the first direction D1.
  • a distance between the reference output line near a boundary of the display area and the display area is smaller than a distance between the first scan output line near a boundary of the display area and the display area.
  • the distance between the second scan output line and the light emitting output line near the border of the display area and the display area is greater than the distance between the first scan output line near the border of the display area and the display area.
  • the distance between the third scan output line, the second signal connection line 13 and the third signal connection line 13 near the boundary of the display area and the display area is equal to the distance between the first scan output line near the boundary of the display area and the display area.
  • the orthographic projection of the 2j-1th first scan output line GOUTL1 (2j-1) on the substrate at least partially overlaps with the first signal connection line 11, the second scan connection portion of the 2j-1th second scan signal line G2 (2j), and the orthographic projection of the 2j-1th first scan signal line G1 (2j-1) on the substrate, and is electrically connected to the 2j-1th first scan signal line G1 (2j-1) through a twelfth via hole.
  • the orthographic projection of the 2j-th first scan output line GOUTL1 (2j) on the substrate at least partially overlaps with the second light-emitting connection portion of the 2j-th light-emitting signal line EM (2j) and the orthographic projection of the 2j-th first scan signal line G1 (2j) on the substrate, respectively, and is electrically connected to the 2j-th first scan signal line G1 (2j) through a thirteenth via hole.
  • the orthographic projection of the jth third scan output line GOUTL3(j) on the substrate at least partially overlaps the orthographic projection of the 2jth third scan signal line G3(2j) on the substrate, and is electrically connected to the 2jth third scan signal line G3(2j) through the sixteenth via hole.
  • the jth third scan output line GOUTL3(j) is electrically connected to the 2j-1th third scan signal line G3(2j-1) through the 2jth third scan signal line G3(2j) and the first signal connection line 11.
  • the orthographic projection of the second scan connection portion on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line GOUTL1(2j-1), the jth second scan output line GOUTL2(j), the jth third scan output line GOUTL3(j) and the second signal connection line 12 on the substrate, and is electrically connected to the jth second scan output line GOUTL2(j) and the second signal connection line 12 respectively through the fifteenth via.
  • the orthographic projection of the second signal connection line 12 on the substrate at least partially overlaps with the orthographic projection of the 2j-1th second scanning signal line G2 (2j-1) and the first signal connection line 11 on the substrate, and is electrically connected to the 2j-1th second scanning signal line G2 (2j-1) through the fourteenth via hole.
  • the orthographic projection of the second light-emitting connection portion EMB on the substrate at least partially overlaps with the orthographic projections of the j-th light-emitting output line EMOUTL(j), the j-th third scan output line GOUTL3(j), the 2j-th first scan output line GOUTL1(2j) and the third signal connection line 13 on the substrate, and is electrically connected to the j-th light-emitting output line EMOUTL(j) and the third signal connection line 13 respectively through the eighteenth via hole.
  • the orthographic projection of the third signal connection line 13 on the substrate at least partially overlaps with the orthographic projections of the 2j-1 th light emitting signal line EM(2j-1), the first signal connection line 11, and the second scanning connection portion G2B on the substrate, and is electrically connected to the 2j-1 th light emitting signal line EM(2j-1) through the seventeenth via hole.
  • the j th light emitting output line EMOUTL(j) is electrically connected to the 2j-1 th light emitting signal line EM(2j-1) through the second light emitting connection portion EMB and the third signal connection line 13.
  • a length of the second light emitting connection portion along the first direction D1 is greater than a length of the first light emitting connection portion along the second direction D2.
  • the orthographic projection of the 2j-1th reference output line REFOUTL (2j-1) on the substrate at least partially overlaps with the orthographic projection of the first signal connection line 11 and the 2j-1th reference signal line REF (2j-1) on the substrate, and is electrically connected to the 2j-1th reference signal line REF (2j-1) through the tenth via, and is electrically connected to the reference power supply line through the nineteenth via.
  • the orthographic projection of the 2j-th reference output line REFOUTL (2j) on the substrate at least partially overlaps with the orthographic projection of the second scanning connection portion G2B, the second light-emitting connection portion and the 2j-th reference signal line REF (2j) on the substrate, and is electrically connected to the 2j-th reference output line REFOUTL (2j) through the eleventh via hole, and is electrically connected to the reference power supply line through the nineteenth via hole.
  • the second conductive layer pattern may further include at least a third signal connection line 23 , a fourth signal connection line 24 , a sixth signal connection line 26 , and a seventh signal connection line 27 .
  • the third signal connection line 23 , the fourth signal connection line 24 , the sixth signal connection line 26 , and the seventh signal connection line 27 may extend in the first direction D1 .
  • a distance between the reference output line near a boundary of the display area and the display area is smaller than a distance between the first scan output line near a boundary of the display area and the display area.
  • the distance between the second scan output line, the third scan output line, and the light-emitting output line near the boundary of the display area and the display area is greater than the distance between the first scan output line near the boundary of the display area and the display area, and the distance between the third scan output line near the boundary of the display area and the display area is less than the distance between the second scan output line and the light-emitting output line near the boundary of the display area and the display area.
  • the distance between the third signal connection line 23, the fourth signal connection line 24, the sixth signal connection line 26 and the seventh signal connection line 27 near the boundary of the display area and the display area is equal to the distance between the first scan output line near the boundary of the display area and the display area.
  • the orthographic projections of the 2j-1th first scan output line GOUTL1 (2j-1) on the substrate at least partially overlap with the orthographic projections of the first signal connection line 21, the second signal connection line 22, the fifth signal connection line 25 and the 2j-1th first scan signal line G1 (2j-1) on the substrate, respectively, and are electrically connected to the 2j-1th first scan signal line G1 (2j-1) through the twelfth via hole.
  • the orthographic projections of the 2j-th first scan output line GOUTL1 (2j) on the substrate at least partially overlap with the orthographic projections of the first signal connection line 21, the second signal connection line 22, the fifth signal connection line 25 and the 2j-th first scan signal line G1 (2j) on the substrate, respectively, and are electrically connected to the 2j-th first scan signal line G1 (2j) through the thirteenth via hole.
  • the orthographic projection of the jth third scan output line GOUTL3(j) on the substrate at least partially overlaps the orthographic projection of the 2jth third scan signal line G3(2j) on the substrate, and is electrically connected to the 2jth third scan signal line G3(2j) through the sixteenth via hole.
  • the jth third scan output line GOUTL3(j) is electrically connected to the 2j-1th third scan signal line G3(2j-1) through the 2jth third scan signal line G3(2j) and the first signal connection line.
  • the orthographic projection of the second signal connection line 22 on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line GOUTL1(2j-1), the 2jth first scan output line GOUTL1(2j), the jth second scan output line GOUTL2(j), the jth third scan output line GOUTL3(j), the third signal connection line 23 and the fourth signal connection line 24 on the substrate, and is electrically connected to the jth second scan output line GOUTL2(j), the third signal connection line 23 and the fourth signal connection line 24 respectively through the nineteenth via.
  • the orthographic projection of the third signal connection line 23 on the substrate is electrically connected to the first signal connection line 21 and the 2j-1 second scanning signal line G2 (2j-1), and is electrically connected to the 2j-1 second scanning signal line G2 (2j-1) through the fourteenth via hole.
  • the j-th second scanning output line GOUTL2 (j) is electrically connected to the 2j-1 second scanning signal line G2 (2j-1) through the second signal connection line 22 and the third signal connection line 23.
  • the orthographic projection of the fourth signal connection line 24 on the substrate is electrically connected to the first signal connection line 21 and the 2j-th second scanning signal line G2 (2j), and is electrically connected to the 2j-th second scanning signal line G2 (2j) through the fifteenth via hole.
  • the j-th second scanning output line GOUTL2 (j) is electrically connected to the 2j-1-th second scanning signal line G2 (2j) through the second signal connection line 22 and the fourth signal connection line 24.
  • the orthographic projection of the fifth signal connection line 25 on the substrate at least partially overlaps with the orthographic projections of the 2j-1th first scan output line GOUTL1(2j-1), the 2jth first scan output line GOUTL1(2j), the jth second scan output line GOUTL2(j), the jth third scan output line GOUTL3(j), the jth light emitting output line EMOUTL(j), the sixth signal connection line 26 and the seventh signal connection line 27 on the substrate, and is electrically connected to the jth light emitting output line EMOUTL(j), the sixth signal connection line 26 and the seventh signal connection line 27 respectively through the twentieth via hole.
  • the orthographic projection of the sixth signal connection line 26 on the substrate at least partially overlaps with the orthographic projections of the first signal connection line 21, the second signal connection line 22 and the 2j-1th luminous signal line EM (2j-1) on the substrate, and is electrically connected to the 2j-1th luminous signal line EM (2j-1) through the seventeenth via hole.
  • the orthographic projection of the seventh signal connection line 27 on the substrate is electrically connected to the first signal connection line 21, the second signal connection line 22 and the 2j-th light-emitting signal line EM (2j), and is electrically connected to the 2j-th light-emitting signal line EM (2j) through the eighteenth via hole.
  • the orthographic projection of the 2j-1th reference output line REFOUTL (2j-1) on the substrate at least partially overlaps with the orthographic projections of the first signal connection line 21, the second signal connection line 22, the fifth signal connection line 25 and the 2j-1th reference signal line REF (2j-1) on the substrate, and is electrically connected to the 2j-1th reference signal line REF (2j-1) through the tenth via, and is electrically connected to the reference power supply line through the twenty-first via.
  • the orthographic projection of the 2j-th reference output line REFOUTL (2j) on the substrate at least partially overlaps with the orthographic projections of the first signal connection line 21, the second signal connection line 22, the fifth signal connection line 25 and the 2j-th reference signal line REF (2j) on the substrate, and is electrically connected to the 2j-th reference output line REFOUTL (2j) through the eighteenth via, and is electrically connected to the reference power supply line through the twenty-first via.
  • the j-th second scan output line GOUTL2(j) includes: a first scan output connection portion GOLA and a second scan output connection portion GOLB connected to each other, the first scan output connection portion GOLA extends along the first direction D1, the second scan output connection portion GOLB extends along the second direction D2, a virtual straight line extending along the second direction D2 passes through the second scan connection portion G2D and the second scan output connection portion GOLB, and the second scan connection portion is located on a side of the first signal connection line close to the display area AA.
  • the j-th light emitting output line EMOUTL(j) includes: a first light emitting output connection portion EOLA and a second light emitting output connection portion EOLB connected to each other, the first light emitting output connection portion EOLA extends along a first direction D1, and the second light emitting output connection portion EOLB extends along a second direction D2; the second light emitting output connection portion EOLB is located on a side of the second scanning output connection portion GOLB close to the display area AA.
  • a distance between the reference output line near a boundary of the display area and the display area is greater than a distance between the first scan output line near a boundary of the display area and the display area.
  • the distance between the 2j-1th first scan output line GOUTL1(2j-1) near the boundary of the display area and the display area is smaller than the distance between the jth light-emitting output line EMOUTL(j) near the boundary of the display area and the display area
  • the distance between the jth light-emitting output line EMOUTL(j) near the boundary of the display area and the display area is smaller than the distance between the 2jth first scan output line GOUTL1(2j) and the jth second scan output line GOUTL2(j) near the boundary of the display area and the display area
  • the distance between the jth second scan output line GOUTL2(j) near the boundary of the display area and the display area is smaller than the distance between the jth third scan output line GOUTL3(j) near the boundary of the display area and the display area
  • the orthographic projection of the 2j-1th first scan output line GOUTL1 (2j-1) on the substrate at least partially overlaps with the first signal connection line 21, the second scan connection portion of the 2j-1th second scan signal line G2 (2j-1) and the orthographic projection of the 2j-1th first scan signal line G1 (2j-1) on the substrate, respectively, and is electrically connected to the 2j-1th first scan signal line G1 (2j-1) through the twelfth via hole.
  • the orthographic projection of the 2j-th first scan output line GOUTL1 (2j) on the substrate at least partially overlaps with the orthographic projection of the second signal connection line 32 on the substrate, and is electrically connected to the second signal connection line 32 through the thirteenth via hole.
  • the orthographic projection of the first signal connection line 31 on the substrate at least partially overlaps with the orthographic projections of the 2j-1st first scan output line GOUTL1(2j-1), the jth second scan output line GOUTL2(j), and the jth third scan output line GOUTL3(j) on the substrate, and is electrically connected to the jth third scan output line GOUTL3(j) through the sixteenth via hole.
  • the jth third scan output line GOUTL3(j) is electrically connected to the 2j-1st third scan signal line G3(2j-1) and the 2jth third scan signal line G3(2j) through the first signal connection line 31, respectively.
  • the orthographic projection of the second scan connection portion on the substrate at least partially overlaps with the orthographic projection of the 2j-1th first scan output line GOUTL1 (2j-1) and the first scan output connection portion GOLA on the substrate, and is electrically connected to the first scan output connection portion GOLA through the fourteenth via.
  • the orthographic projection of the second scan output connection portion GOLB on the substrate at least partially overlaps with the orthographic projections of the 2j-th third scan signal line G3 (2j) and the 2j-th second scan signal line G2 (2j) on the substrate, and is electrically connected to the 2j-th second scan signal line G2 (2j) through the fifteenth via hole.
  • the orthographic projection of the second signal connection line 32 on the substrate at least partially overlaps with the orthographic projection of the 2j-th first scan output line GOUTL1 (2j) on the substrate, and is electrically connected to the 2j-th first scan output line GOUTL1 (2j) and the 2j-th first scan signal line G1 (2j), respectively.
  • the length of the second signal connection line 32 along the second direction D2 is greater than the length of the first scan signal line along the second direction D2.
  • the orthographic projection of the second light emitting output connection portion EOLB on the substrate at least partially overlaps with the orthographic projections of the second signal connection line 32, the 2j-1th light emitting signal line EM(2j-1), the 2jth light emitting signal line EM(2j), the 2jth third scanning signal line G3(2j), and the 2jth second scanning signal line G2(2j) on the substrate, and is electrically connected to the 2j-1th light emitting signal line EM(2j-1) through the seventeenth via hole and to the 2jth light emitting signal line EM(2j) through the eighteenth via hole.
  • the orthographic projection of the 2j-1th reference output line REFOUTL (2j-1) on the substrate at least partially overlaps with the orthographic projection of the 2j-1th reference signal line REF (2j-1) on the substrate, and is electrically connected to the 2j-1th reference signal line REF (2j-1) through the tenth via, and is electrically connected to the reference power supply line through the nineteenth via.
  • the orthographic projection of the 2j-th reference output line REFOUTL(2j) on the substrate at least partially overlaps with the orthographic projection of the 2j-th reference signal line REF(2j) on the substrate, and is electrically connected to the 2j-th reference output line REFOUTL(2j) through the tenth via, and is electrically connected to the reference power supply line through the nineteenth via.
  • forming the planar layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, coating a planar film on the fourth insulating layer, and patterning the planar film using a patterning process to form a planar layer pattern covering the fourth insulating layer.
  • the fourth insulating layer and the planarizing layer are provided with a via exposing the second electrode of the fifth transistor (also the second electrode and the third electrode plate of the third transistor), and the via is configured to connect a subsequently formed anode to the second electrode of the fifth transistor (also the second electrode and the third electrode plate of the third transistor).
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and the pixel drive circuit is connected to the first scan signal line, the second scan signal line, the third scan signal line, the light emitting signal line, the initial signal line, the reference signal line, the data signal line and the first power supply line.
  • the drive circuit layer may be arranged on the substrate.
  • the driving circuit layer may include a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer and a flat layer arranged in sequence on the substrate.
  • the shielding layer may at least include: a reference signal line, an initial signal line and a first plate of a storage capacitor, the semiconductor layer may at least include an active layer of the first transistor to the fifth transistor and a second plate of the storage capacitor, the first conductive layer may at least include gate electrodes of the first transistor to the seventh transistor, a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line and a reference power supply line, the second conductive layer may at least include a data signal line, a first power supply line, a first electrode and a second electrode of a plurality of transistors, a third plate of a storage capacitor, a first scanning output line, a second scanning output line, a third scanning output line, a light-emitting output line and a reference output line.
  • the first conductive layer and the second conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer may be called a buffer layer
  • the second insulating layer may be called a gate insulating (GI) layer
  • the third insulating layer may be called an interlayer insulating (ILD) layer
  • the fourth insulating layer may be a passivation (PVX) layer
  • the planar layer may be made of an organic material such as a resin.
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • Forming an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns.
  • the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the plurality of anode patterns may include a first anode of a red light emitting device, a second anode of a blue light emitting device, a third anode of a first green light emitting device, and a fourth anode of a second green light emitting device, the first anode may be located at a red sub-pixel emitting red light, the second anode may be located at a blue sub-pixel emitting blue light, the third anode may be located at a first green sub-pixel emitting green light, and the fourth anode may be located at a second green sub-pixel emitting green light.
  • the first anode and the second anode may be sequentially arranged along the first direction
  • the third anode and the fourth anode may be sequentially arranged along the first direction
  • the third anode and the fourth anode may be arranged on one side of the first anode and the second anode in the second direction.
  • the first anode and the second anode may be sequentially arranged along the second direction
  • the third anode and the fourth anode may be sequentially arranged along the second direction Y
  • the third anode and the fourth anode may be arranged on one side of the first anode and the second anode in the first direction X.
  • the first anode, the second anode, the third anode and the fourth anode may be connected to the second electrode of the driving transistor of the sub-pixel through the anode via, respectively, and the anode shapes and areas of the four sub-pixels in one pixel unit may be the same or different.
  • At least one of the first anode, the second anode, the third anode, and the fourth anode may include an anode body part and an anode connection part that are connected to each other.
  • the first anode may include a first anode main body and a first anode connection part connected to each other, the shape of the first anode main body may be rectangular, and the corner of the rectangular shape may be provided with an arc-shaped chamfer.
  • the second anode may include a second anode main body and a second anode connection part connected to each other, the shape of the second anode main body may be rectangular, the corner of the rectangular shape may be provided with an arc-shaped chamfer, and the shape of the second anode connection part may be a strip.
  • the third anode may include a third anode main body and a third anode connection part connected to each other, the shape of the third anode main body may be rectangular, the corner of the rectangular shape may be provided with an arc-shaped chamfer, and the shape of the third anode connection part may be a strip.
  • the fourth anode may include a fourth anode main body and a fourth anode connection part connected to each other, the shape of the fourth anode main body may be rectangular, the corner of the rectangular shape may be provided with an arc-shaped chamfer, and the shape of the fourth anode connection part may be a strip.
  • Forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer, wherein a pixel opening is provided on the pixel definition layer of each sub-pixel, and the pixel definition film in the pixel opening is removed to expose the anode of the sub-pixel.
  • an orthographic projection of the pixel opening on the substrate does not overlap with an orthographic projection of the anode via on the substrate.
  • the second distance between the edge of the pixel opening on the side close to the anode via and the edge of the anode via on the side close to the pixel opening may be greater than or equal to 3.0 ⁇ m, and the second distance may be the minimum distance between the pixel opening and the anode via.
  • the second distance between the pixel opening and the anode via may be about 7.88 ⁇ m. Since the anode via is a via that penetrates the flat layer, the present disclosure can ensure the flatness of the anode in the pixel opening by setting the pixel opening outside the set distance of the anode via, thereby improving the flatness of the pixel and the display quality.
  • the subsequent preparation process may include: first forming an organic light-emitting layer by evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the structure and preparation process shown in the above disclosure are only an exemplary description.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • some overlapping vias can be set in sub-pixels away from the first center line to increase the spacing between adjacent overlapping vias, reduce mutual interference, and ensure that the display screen does not have crosstalk.
  • the disclosure does not limit this.
  • the display panel of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.
  • the present disclosure also provides a display device, which includes the aforementioned display panel.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.
  • the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种显示面板和显示装置，其中，显示面板包括：基底以及驱动电路层，驱动电路层包括：像素驱动电路(PE)以及第一扫描信号线(G1)，像素驱动电路与第一扫描信号线(G1)电连接，且相邻行像素驱动电路连接的第一扫描信号线(G1)电气隔离；驱动电路层还包括：位于非显示区域(AA')的第一信号线和与第一信号线对应的第二信号线，第一信号线，被配置为向第一扫描信号线(G1)提供信号，第一信号线在基底上的正投影与对应的第二信号线在基底上的正投影至少部分交叠；相邻第一扫描信号线(G1)电连接的第一信号线的电阻大致相等和/或相邻第一扫描信号线(G1)电连接的第一信号线与对应的第二信号线之间的电容值大致相等。

Description

显示面板和显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示面板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示面板，包括：基底以及设置在基底上的驱动电路层，所述基底包括显示区域和非显示区域，所述驱动电路层包括：设置在所述显示区域的多个像素驱动电路以及设置在显示区域和非显示区域的多条第一扫描信号线，所述第一扫描信号线至少部分沿第一方向延伸，所述像素驱动电路与所述第一扫描信号线电连接，且相邻行像素驱动电路连接的第一扫描信号线电气隔离；
所述驱动电路层还包括：位于非显示区域的第一信号线和与所述第一信号线对应的第二信号线，所述第一信号线，与第一扫描信号线电连接，被配置为向第一扫描信号线提供信号，所述第一信号线在基底上的正投影与对应的第二信号线在基底上的正投影至少部分交叠；
相邻第一扫描信号线电连接的第一信号线的电阻大致相等和/或相邻第一扫描信号线电连接的第一信号线与对应的第二信号线之间的电容值大致相 等。
在示例性实施方式中，所述驱动电路层还包括：设置在显示区域和非显示区域的多条第二扫描信号线、多条第三扫描信号线、多条发光信号线和多条参考信号线，所述像素驱动电路分别与第二扫描信号线、第三扫描信号线、发光信号线和参考信号线电连接，所述第二扫描信号线、所述第三扫描信号线、所述发光信号线和所述参考信号线至少部分沿第一方向延伸；
第i行像素驱动电路，分别与第i条第一扫描信号线、第i条第二扫描信号线、第i条第三扫描信号线、第i条发光信号线和第i条参考信号线电连接，1≤i≤M，M为像素驱动电路的总行数；
第i条第三扫描信号线、第i条参考信号线、第i条第二扫描信号线、第i条第一扫描信号线和第i条发光信号线沿第二方向依次排布，第i条第三扫描信号线位于第i条参考信号线靠近第i-1条发光信号线的一侧，第i条发光信号线位于第i条第一扫描信号线靠近第i+1条第三扫描信号线的一侧，所述第二方向与所述第一方向相交；
所述第二信号线与第二扫描信号线、第三扫描信号线和发光信号线中的至少一种信号线电连接。
在示例性实施方式中，所述驱动电路层还包括：位于非显示区域的M条第一扫描输出线、M/2条第二扫描输出线、M/2条第三扫描输出线、M条参考输出线和M/2条发光输出线，所述第一扫描输出线、所述第二扫描输出线、所述第三扫描输出线、所述参考输出线和所述发光输出线至少部分沿第一方向延伸；
第i条第一扫描输出线与第i条第一扫描信号线电连接，第i条参考输出线与第i条参考信号线电连接，第j条第二扫描输出线分别与第2j-1条第二扫描信号线和第2j条第二扫描信号线电连接，第j条第三扫描输出线分别与第2j-1条第三扫描信号线和第2j条第三扫描信号线电连接，第j条发光输出线分别与第2j-1条发光信号线和第2j条发光信号线电连接，1≤j≤M/2；
第2j-1条参考输出线、第2j-1条第一扫描输出线、第j条第二扫描输出线、第j条第三扫描输出线、第2j条参考输出线、第j条发光输出线和第2j条第一扫描输出线沿第二方向依次排布。
在示例性实施方式中，所述驱动电路层还包括：位于非显示区域的参考供电线以及位于至少部分位于显示区域的数据信号线和第一电源线，所述参考供电线、所述数据信号线和所述第一电源线至少部分沿第二方向延伸；
所述像素驱动电路分别与数据信号线和第一电源线电连接，所述参考供电线在基底上的正投影与所述参考输出线在基底上的正投影至少部分重叠，且与参考输出线电连接。
在示例性实施方式中，所述驱动电路层包括：依次叠设在基底上的第一导电层和第二导电层；
所述第一导电层至少包括：第一扫描信号线、第二扫描信号线、第三扫描信号线、发光信号线和参考供电线；
所述第二导电层至少包括：第一扫描输出线、第二扫描输出线、第三扫描输出线、参考输出线、发光输出线、数据信号线和第一电源线。
在示例性实施方式中，所述第一导电层和所述第二导电层的方阻大致相等。
在示例性实施方式中，所述第一导电层和所述第二导电层的制作材料和厚度相同。
在示例性实施方式中，相邻第一扫描信号线电连接的第一信号线靠近显示区域的边界与显示区域之间的距离大致相等，相邻第一扫描信号线电连接的第一信号线沿第二方向的平均长度大致相等。
在示例性实施方式中，相邻第一扫描信号线电连接的第一信号线与对应的第二信号线之间的交叠区域的面积大致相等。
在示例性实施方式中，所述驱动电路层还包括：位于第一导电层的第一信号连接线，所述第一信号连接线沿第二方向延伸，且分别与第2j-1条第三扫描信号线和第2j条第三扫描信号线电连接；
所述第一信号连接线在基底上的正投影与第2j-1条第一扫描输出线在基底上的正投影至少部分交叠；
第j条第三扫描输出线在基底上的正投影与第2j条第三扫描信号线在基底上的正投影至少部分交叠，且与第2j条第三扫描信号线电连接。
在示例性实施方式中，所述驱动电路层还包括：位于第二导电层的第二信号连接线，所述第二信号连接线沿第一方向延伸；
第2j条第二扫描信号线包括：相互连接的第一扫描连接部和第二扫描连接部，所述第一扫描连接部沿第一方向延伸，所述第二扫描连接部沿第二方向延伸，所述第一信号连接线位于所述第二扫描连接部靠近显示区域的一侧；
所述第二扫描连接部在基底上的正投影与第2j-1条第一扫描输出线、第j条第二扫描输出线、第j条第三扫描输出线和第二信号连接线在基底上的正投影至少部分交叠，且分别与第j条第二扫描输出线和第二信号连接线电连接；
所述第二信号连接线在基底上的正投影与第2j-1条第二扫描信号线和第一信号连接线在基底上的正投影至少部分交叠，且与第2j-1条第二扫描信号线电连接。
在示例性实施方式中，所述驱动电路层还包括：位于第二导电层的第三信号连接线，所述第三信号连接线沿第一方向延伸；
第2j条发光信号线包括：相互连接的第一发光连接部和第二发光连接部，所述第一发光连接部沿第一方向延伸，所述第二发光连接部沿第二方向延伸，所述第二发光连接部位于所述参考供电线和所述第二扫描连接部之间；
所述第二发光连接部在基底上的正投影与第j条发光输出线、第j条第三扫描输出线、第2j条第一扫描输出线和第三信号连接线在基底上的正投影至少部分交叠，且分别与第j条发光输出线和第三信号连接线电连接；
所述第三信号连接线在基底上的正投影与第2j-1条发光信号线、第一信号连接线和第二扫描连接部在基底上的正投影至少部分交叠，且与第2j-1条发光信号线电连接；
所述第二发光连接部与第2j条第一扫描输出线交叠区域沿第一方向的长度大于所述第一发光连接部沿第二方向的长度。
在示例性实施方式中，第i条第一扫描信号线电连接的第一信号线包括：第i条第一扫描输出线；
第2j-1条第一扫描信号线电连接的第一信号线对应的第二信号线包括第 一信号连接线和第2j条第二扫描信号线，第2j条第一扫描信号线电连接的第一信号线对应的第二信号线包括第2j条发光信号线。
在示例性实施方式中，第2j-1条参考输出线在基底上的正投影与第一信号连接线和第2j-1条参考信号线在基底的正投影至少部分交叠，且与第2j-1条参考信号线电连接；第2j条参考输出线在基底上的正投影与第二扫描连接部、第二发光连接部和第2j条参考信号线在基底的正投影至少部分交叠，且与第2j条参考输出线电连接。
在示例性实施方式中，所述驱动电路层还包括：位于第一导电层的第一信号连接线，所述第一信号连接线沿第二方向延伸，且分别与第2j-1条第三扫描信号线和第2j条第三扫描信号线电连接；
所述第一信号连接线在基底上的正投影与第2j-1条第一扫描输出线和第2j条第一扫描输出线在基底上的正投影至少部分交叠；
第j条第三扫描输出线在基底上的正投影与第2j条第三扫描信号线在基底上的正投影至少部分交叠，且与第2j条第三扫描信号线电连接。
在示例性实施方式中，所述驱动电路层还包括：位于第一导电层的第二信号连接线以及位于第二导电层的第三信号连接线和第四信号连接线，所述第二信号连接线沿第二方向延伸，所述第三信号连接线和所述第四信号连接线至少部分沿第一方向延伸，所述第二信号连接线位于第一信号连接线远离显示区域的一侧；
所述第二信号连接线在基底上的正投影与第2j-1条第一扫描输出线、第2j条第一扫描输出线、第j条第二扫描输出线、第j条第三扫描输出线、第三信号连接线和第四信号连接线在基底上的正投影至少部分交叠，且分别与第j条第二扫描输出线、第三信号连接线和第四信号连接线电连接；
所述第三信号连接线在基底上的正投影与第一信号连接线和第2j-1条第二扫描信号线在基底上的正投影至少部分交叠，且与第2j-1条第二扫描信号线电连接；
所述第四信号连接线在基底上的正投影与第一信号连接线和第2j条第二扫描信号线在基底上的正投影至少部分交叠，且与第2j条第二扫描信号线 电连接。
在示例性实施方式中，所述驱动电路层还包括：位于第一导电层的第五信号连接线以及位于第二导电层的第六信号连接线和第七信号连接线，所述第五信号连接线沿第二方向延伸，所述第六信号连接线和所述第七信号连接线至少部分沿第一方向延伸，所述第五信号连接线位于第二信号连接线远离显示区域的一侧；
所述第五信号连接线在基底上的正投影与第2j-1条第一扫描输出线、第2j条第一扫描输出线、第j条第二扫描输出线、第j条第三扫描输出线、第j条发光输出线、第六信号连接线和第七信号连接线在基底上的正投影至少部分交叠，且分别与第j条发光输出线、第六信号连接线和第七信号连接线电连接；
所述第六信号连接线在基底上的正投影与第五信号连接线、第二信号连接线和第2j-1条发光信号线在基底上的正投影至少部分交叠，且与第2j-1条发光信号线电连接；
所述第七信号连接线在基底上的正投影与第一信号连接线、第二信号连接线和第2j条发光信号线在基底上的正投影至少部分交叠，且与第2j条发光信号线电连接。
在示例性实施方式中，第i条第一扫描信号线电连接的第一信号线包括：第i条第一扫描输出线；
第2j-1条第一扫描信号线电连接的第一信号线对应的第二信号线包括第一信号连接线、第二信号连接线和第五信号连接线，第2j条第一扫描信号线电连接的第一信号线对应的第二信号线包括第一信号连接线、第二信号连接线和第五信号连接线。
在示例性实施方式中，第2j-1条参考输出线在基底上的正投影与第一信号连接线、第二信号连接线、第五信号连接线和第2j-1条参考信号线在基底的正投影至少部分交叠，且与第2j-1条参考信号线电连接；第2j条参考输出线在基底上的正投影与第一信号连接线、第二信号连接线、第五信号连接线和第2j条参考信号线在基底的正投影至少部分交叠，且与第2j条参考输出线电连接。
在示例性实施方式中，所述第三连接信号线、所述第四连接信号线、所述第六连接信号线、所述第七连接信号线和所述第2j-1条第一扫描输出线靠近显示区域的边界与显示区域之间的距离大致相等。
在示例性实施方式中，所述驱动电路层还包括：位于第一导电层的第一信号连接线，所述第一信号连接线沿第二方向延伸，且分别与第2j-1条第三扫描信号线和第2j条第三扫描信号线电连接；
所述第一信号连接线在基底上的正投影与第2j-1条第一扫描输出线、第j条第二扫描输出线和第j条第三扫描输出线在基底上的正投影至少部分交叠，且与第j条第三扫描输出线电连接。
在示例性实施方式中，第2j-1条第二扫描信号线包括：相互连接的第一扫描连接部和第二扫描连接部，所述第一扫描连接部沿第一方向延伸，所述第二扫描连接部沿第二方向延伸，第j条第二扫描输出线包括：相互连接的第一扫描输出连接部和第二扫描输出连接部，所述第一扫描输出连接部沿第一方向延伸，所述第二扫描输出连接部沿第二方向延伸，沿第二方向延伸的虚拟直线穿过所述第二扫描连接部和所述第二扫描输出连接部，第二扫描连接部位于第一信号连接线靠近显示区域的一侧；
所述第二扫描连接部在基底上的正投影与第2j-1条第一扫描输出线和第一扫描输出连接部在基底上的正投影至少部分交叠，且与第一扫描输出连接部电连接；
所述第一扫描输出连接部在基底上的正投影与第一信号连接线在基底上的正投影至少部分交叠；
所述第二扫描输出连接部在基底上的正投影与第2j条第三扫描信号线和第2j条第二扫描信号线在基底上的正投影至少部分交叠，且与第2j条第二扫描信号线电连接。
在示例性实施方式中，所述驱动电路层还包括：位于第一导电层的第二信号连接线，所述第二信号连接线沿第一方向延伸；
所述第二信号连接线在基底上的正投影与第2j条第一扫描输出线在基底上的正投影至少部分交叠，且分别与第2j条第一扫描输出线和第2j条第 一扫描信号线电连接，所述第二信号连接线沿第二方向的长度大于所述第一扫描信号线沿第二方向的长度。
在示例性实施方式中，第j条发光输出线包括：相互连接的第一发光输出连接部和第二发光输出连接部，所述第一发光输出连接部沿第一方向延伸，所述第二发光输出连接部沿第二方向延伸；所述第二发光输出连接部位于所述第二扫描输出连接部靠近显示区域的一侧；
所述第二发光输出连接部在基底上的正投影与第二信号连接线、第2j-1条发光信号线、第2j条发光信号线，第2j条第三扫描信号线和第2j条第二扫描信号线在基底上的正投影至少部分交叠，且分别与第2j-1条发光信号线和第2j条发光信号线电连接。
在示例性实施方式中，第2j-1条第一扫描信号线电连接的第一信号线包括第2j-1条第一扫描输出线、第2j条第一扫描信号线电连接的第一信号线包括第2j条第一扫描输出线和第二信号连接线；
第2j-1条第一扫描信号线电连接的第一信号线对应的第二信号线包括第一信号连接线和第2j-1条第二扫描信号线，第2j条第一扫描信号线电连接的第一信号线对应的第二信号线包括第j条发光输出线。
在示例性实施方式中，第2j-1条参考输出线在基底上的正投影与第2j-1条参考信号线在基底的正投影至少部分交叠，且与第2j-1条参考信号线电连接；第2j条参考输出线在基底上的正投影与第2j条参考信号线在基底的正投影至少部分交叠，且与第2j条参考输出线电连接。
在示例性实施方式中，所述驱动电路层还包括：遮挡层，所述遮挡层位于第一导电层靠近基底的一侧；
所述遮挡层至少包括：参考信号线。
第二方面，本公开还提供了一种显示装置，包括：上述显示面板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与 本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示面板的平面结构示意图；
图3为一种像素驱动电路的等效电路示意图；
图4为一种像素驱动电路的工作时序图；
图5为本公开实施例提供的显示面板的结构示意图一；
图6为本公开实施例提供的显示面板的结构示意图二；
图7为本公开实施例提供的显示面板的结构示意图三；
图8为图5至图7提供的显示面板形成遮挡层图案后的示意图；
图9为图5至图7提供的显示面板的半导体层图案的示意图；
图10为图5至图7提供的显示面板的形成半导体层图案后的示意图；
图11为图5提供的显示面板的第一导电层图案的示意图；
图12为图5提供的显示面板的形成第一导电层图案后的示意图；
图13为图6提供的显示面板的第一导电层图案的示意图；
图14为图6提供的显示面板的形成第一导电层图案后的示意图；
图15为图7提供的显示面板的第一导电层图案的示意图；
图16为图7提供的显示面板的形成第一导电层图案后的示意图；
图17为图5提供的显示面板的形成第三绝缘层图案后的示意图；
图18为图6提供的显示面板的形成第三绝缘层图案后的示意图；
图19为图7提供的显示面板的形成第三绝缘层图案后的示意图；
图20为图5提供的显示面板的第二导电层图案的示意图；
图21为图5提供的显示面板的形成第二导电层图案后的示意图；
图22为图6提供的显示面板的第二导电层图案后的示意图；
图23为图6提供的显示面板的形成第二导电层图案的示意图；
图24为图7提供的显示面板的第二导电层图案的示意图；
图25为图7提供的显示面板的形成第二导电层图案后的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示面板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连 接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多条数据信号线Data连接，扫描驱动器分别与多条第一扫描信号线G1、多条第二扫描信号线G2和多条第三扫描信号线G3连接，发光驱动器分别与多条发光信号线EM连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路可以分别与第一扫描信号线、第二扫描信号线、第三扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线Data的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到第一扫描信号线、第二扫描信号线和第三扫描信号线的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到第一扫描信号线、第二扫描信号线和第三扫描信号线。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1 至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号。
图2为一种显示面板的平面结构示意图。如图2所示，显示面板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与第一扫描信号线、第二扫描信号线、第三扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在第一扫描信号线、第二扫描信号线、第三扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以分别与第一子像素至第四子像素，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在示例性实施方式中，第一子像素可以是出射红色(R)光线的红色子像素、第二子像素可以是出射蓝色(B)光线的蓝色子像素，第三子像素可以是出射绿色(G)光线的绿色子像素，第四子像素可以是出射白色(W)光线的白色子像素。
在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形，本公开在此不做限定。
图3为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图3所示，像素驱动电路可以包括5个晶体管(第一晶体管T1到第五晶体管T5)、1个存储电容Cst，像素驱动电路可以与8个信号线(数据信号线Data、第一扫描信号线G1、第二扫描信号线G2、第三扫描信号线G3、发光信号线EM、参考信号线REF、初始信号线INIT和第一电源线VDD)电连接。
在示例性实施方式中，如图3所示，第一晶体管T1的控制极与第一扫描信号线G1电连接，第一晶体管T1的第一极与数据信号线Data电连接，第一晶体管T1的第二极与第一节点N1连接。第一晶体管T1可以称为写入晶体管，当第一扫描信号线G1的信号为有效电平信号时，第一晶体管T1将数据信号线的数据电压传输到第一节点N1。
在示例性实施方式中，如图3所示，第二晶体管T2的控制极与第二扫描信号线G2电连接，第二晶体管T2的第一极与参考信号线REF电连接，第二晶体管T2的第二极与第一节点N1电连接。第二晶体管T2可以称为补偿晶体管，当第二扫描信号线G2的信号为有效电平信号时，第二晶体管T2将参考信号线REF的信号传输到第一节点N1，以对第一节点N1进行补偿。
在示例性实施方式中，如图3所示，第三晶体管T3的控制极与第三扫描信号线G3电连接，第三晶体管T3的第一极与初始信号线INIT电连接，第三晶体管T3的第二极与第三节点N3电连接。第三晶体管T3可以称为复位晶体管，当第三扫描信号线G3的信号为有效电平信号时，第三晶体管T3将初始信号线INIT的初始信号传输到第三节点N3，以使发光器件L的第一电极中累积的电荷量初始化或释放发光器件的第一电极中累积的电荷量。
在示例性实施方式中，如图3所示，第四晶体管T4的控制极与发光信号线EM电连接，第四晶体管T4的第一极与第一电源线VDD电连接，第四晶体管T4的第二极与第二节点N2电连接。第四晶体管T4可以称为发光晶体管。当发光信号线EM的信号为有效电平信号时，第四晶体管T4通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，如图3所示，第五晶体管T5的控制极与第一节点N1电连接，第五晶体管T5的第一极与第二节点N2电连接，第五晶体管T5的第二极与第三节点N3电连接。第五晶体管T5可以称为驱动晶体管，第五晶体管T5根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的大小。
在示例性实施方式中，存储电容Cst的第一端与第一节点N1连接，存储电容Cst的第二端与第三节点N3连接，即存储电容Cst的第一端与第五晶体管T5的控制极连接。存储电容Cst被配置为存储第五晶体管的控制极的信号的电压值。
在示例性实施方式中，如图3所示，发光器件L的第一电极与第三节点N3电连接，发光器件L的第二电极与第二电源线VSS连接。
在示例性实施方式中，第一电源线VDD持续提供高电平信号，第二电源线VSS持续提供低电平信号，参考信号线REF和初始信号线INIT提供恒压信号，初始信号线INIT的电压值小于第二电源线VSS的电压值。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管T1到第五晶体管T5可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第五晶体管T5可以包括P型晶体管和N型晶体管。
在一种示例性实施例中，存储电容Cst可以是通过工艺制程制作的电容器件，例如，通过制作专门的电容电极来实现电容器件，电容的多个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。或者，存储电容Cst可以是多个器件之间的寄生电容，可以通过晶体管本身与其他器件、线 路来实现。存储电容Cst的连接方式包括但不局限于上面描述的方式，可以为其它适用的连接方式，可以存储相应节点的电平即可。这里，本公开示例性实施例对此不做限定。
在示例性实施方式中，第一晶体管T1到第五晶体管T5可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示面板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，第一扫描信号线G1、第二扫描信号线G2、发光信号线EM、参考信号线REF和初始信号线INIT可以沿水平方向延伸，第一电源线VDD和数据信号线Data可以沿竖直方向延伸。
在一种示例性实施例中，发光器件L可以包括：有机发光二极管OLED、量子点发光二极管和无机发光二极管中的任意一种。例如，发光器件L可以采用微米级发光器件，例如微型发光二极管(Micro Light-Emitting Diode，Micro LED)、次毫米发光发光二极管(Mini Light-Emitting Diode，Mini LED)或者微型有机发光二极管(Micro OLED)等，本公开实施例对此不做限定。例如，以发光器件L为有机电致发光二极管(OLED)为例，发光器件可以包括：叠设的第一极(例如，作为阳极)、有机发光层和第二极(例如，作为阴极)。
在示例性实施方式中，本公开显示面板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、 空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的。
图4为一种像素驱动电路的工作时序图。下面通过图3示例的像素驱动电路的工作过程说明本公开示例性实施例，图3中的像素驱动电路包括5个晶体管(第一晶体管T1到第五晶体管T5)和1个存储电容Cst，5个晶体管均为N型晶体管。
在示例性实施方式中，如图3和图4所示，像素驱动电路的工作过程可以包括：
第一阶段S1，称为复位阶段，第二扫描信号线G2和第三扫描信号线G3的信号为高电平信号，第一扫描信号线G1和发光信号线EM的信号为低电平信号。第二扫描信号线G2的信号为高电平信号，第二晶体管T2导通，参考信号线REF的参考信号写入至第一节点N1，对存储电容Cst进行初始化(复位)，清除存储电容Cst中原有电荷，此时，第一节点N1的电压值V N1满足V N1＝Vref，Vref为参考信号的电压值，第三扫描信号线G3的信号为高电平信号，第三晶体管T3导通，初始信号线INIT的初始信号写入至第三节点N3，对发光器件L的第一电极进行初始化(复位)，清空其内部的预存电压，完成初始化，此时，第三节点N3的电压值满足V N3＝Vinit。第一扫描信号线G1和发光信号线EM的信号为低电平信号，第一晶体管T1和第四晶体管T4断开，此阶段，发光器件L不发光。
第二阶段S2、称为阈值补偿阶段，第二扫描信号线G2和发光信号线EM的信号为高电平信号，第一扫描信号线G1和第三扫描信号线G3的信号为低电平信号。第二扫描信号线G2的信号为高电平信号，第二晶体管T2持续导通，参考信号线REF的参考信号写入至第一节点N1，对存储电容Cst进行初始化(复位)，清除存储电容Cst中原有电荷，此时，第一节点N1的电压值V N1满足V N1＝Vref，Vref为参考信号的电压值，发光信号线EM的信号为高电平信号，第四晶体管T4导通，第一电源线VDD的信号经过导通第四晶体管T4、第二节点N2、导通的第五晶体管T5对第三节点N3进行充电， 直至第三节点N3的电压值满足V N3＝Vref-Vth，Vth为第五晶体管T5的阈值电压，此时存储电容存储电压值为Vth。第一扫描信号线G1和第三扫描信号线G3的信号为低电平信号，第一晶体管T1和第三晶体管T3断开，此阶段，发光器件L不发光。
第三阶段S3、称为数据写入阶段，第一扫描信号线G1的信号为高电平信号，第二扫描信号线G2、第三扫描信号线G3和发光信号线EM的信号为低电平信号。数据信号线Data输出数据电压。此阶段由于存储电容Cst的第一端为低电平，因此第五晶体管T5导通，第一扫描信号线G1的信号为高电平信号，第一晶体管T1导通，数据信号线D输出的数据电压写入至第一节点N1，此时，第一节点N1的电压值V N1满足V N1＝Vdata，Vata为数据电压，的电压值，此时，第三节点N3在存储电容Cst的作用下发生跳变，第三节点N3的电压值满足V N3＝Vref-Vth+a(Vdata-Vref)，a为定值。第二扫描信号线G2、第三扫描信号线G3和发光信号线EM的信号为低电平信号的信号为低电平信号，第二晶体管T2、第三晶体管T3和第四晶体管T4断开，此阶段，发光器件L不发光。
第四阶段S4、称为发光阶段，发光信号线EM的信号为脉冲信号，第一扫描信号线G1、第二扫描信号线G2和第三扫描信号线G3的信号为低电平信号。发光信号线EM的信号为有效电平信号时，第四晶体管T4导通，第一电源线VDD输出的电源电压通过导通的第四晶体管T4、第二节点N2、导通的第五晶体管T5和第三节点N3向发光器件L的第一电极提供驱动电压，驱动发光器件L发光。
在像素驱动电路驱动过程中，流过第五晶体管T5(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第五晶体管T5的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[Vdata–Vref+Vth-a(Vdata-Vref))-Vth] 2＝K*[(1-a)*(Vdata-Vref)] 2
其中，I为流过第五晶体管T5的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第五晶体管T5的栅电极和第一极之间的电压差。
由上述电流公式的推导结果可以看出，在发光阶段，第五晶体管T5的驱动电流已经不受第五晶体管T5的阈值电压的影响，从而消除了第五晶体管T5的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
在示例性实施方式中，像素驱动电路的补偿时间不占用数据写入时间，因此补偿效果不受显示面板的分辨率和刷新频率影响。
图5为本公开实施例提供的显示面板的结构示意图一，图6为本公开实施例提供的显示面板的结构示意图二，图7为本公开实施例提供的显示面板的结构示意图三。如图5至图7所示，本公开实施例提供的显示面板可以包括：基底以及设置在基底上的驱动电路层，基底包括显示区域AA和非显示区域AA’，驱动电路层包括：设置在显示区域AA的多个像素驱动电路PE以及设置在显示区域AA和非显示区域AA’的多条第一扫描信号线，第一扫描信号线至少部分沿第一方向D1延伸，像素驱动电路PE与第一扫描信号线电连接，且相邻行像素驱动电路连接的第一扫描信号线电气隔离。图5至图7中的G1(2j-1)指的是与第2j-1行像素驱动电路电连接的第一扫描信号线，G1(2j)指的是与第2j行像素驱动电路电连接的第一扫描信号线，图5至图7是以显示区域中的两行两列像素驱动电路为例进行说明。
在示例性实施方式中，驱动电路层还可以包括：位于非显示区域AA’的第一信号线和与第一信号线对应的第二信号线，第一信号线，与第一扫描信号线电连接，被配置为向第一扫描信号线提供信号，第一信号线在基底上的正投影与对应的第二信号线在基底上的正投影至少部分交叠。如图5至图7所示，R1为与第2j-1条第一扫描信号线电连接的第一信号线与对应的第二信号线的交叠区域，R2为与第2j条第一扫描信号线电连接的第一信号线与对应的第二信号线的交叠区域。
在示例性实施方式中，相邻第一扫描信号线电连接的第一信号线的电阻R大致相等和/或相邻第一扫描信号线电连接的第一信号线与对应的第二信号线之间的电容值C大致相等。其中，A和B大致相等指的是A和B可以相等，或者A和B之间可以存在差值，但是差值小于阈值差值。A和B可以表示相邻第一扫描信号线电连接的第一信号线的电阻或者可以表示相邻第 一扫描信号线电连接的第一信号线与对应的第二信号线之间的电容值，阈值差值指的是可以使得显示面板的显示效果的差异无法被人眼识别的差值，可以根据显示面板的配置确定，本公开对此不做任何限定。
本公开中的通过相邻第一扫描信号线电连接的第一信号线的电阻大致相等和/或相邻第一扫描信号线电连接的第一信号线与对应的第二信号线之间的电容值大致相等，减小了相邻第一扫描信号线电连接的第一信号线的RC差异，消除了显示异常，可以提升显示面板的显示效果。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
在示例性实施方式中，显示面板还可以包括：设置在驱动电路层远离基底的一侧的发光结构层以及设置在发光结构层远离基底的一侧的封装结构层。在示例性实施方式中，显示面板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，发光结构层可以包括阳极、像素定义层、有机发光层和阴极，阳极通过过孔与驱动晶体管的第二极连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，触控结构层可以包括设置在封装结构层上的第一触控绝缘层、设置在第一触控绝缘层上的第一触控金属层、覆盖第一触控金属层的第二触控绝缘层、设置在第二触控绝缘层上的第二触控金属层和覆盖第二触控金属层的触控保护层，第一触控金属层可以包括多个桥接电极，第二触控金属层可以包括多个第一触控电极和第二触控电极，第一触控电极或第二触控电极可以通过过孔与桥接电极连接。
在示例性实施方式中，如图5至图7所示，驱动电路层还包括：设置在显示区域AA和非显示区域AA’的多条第二扫描信号线、多条第三扫描信号线、多条发光信号线和多条参考信号线，像素驱动电路PE分别与第二扫描信号线、第三扫描信号线、发光信号线和参考信号线电连接，第二扫描信号线、第三扫描信号线、发光信号线和参考信号线至少部分沿第一方向D1延伸。图5至图7中的G2(i)指的是第i条第二扫描信号线，G3(i)指的第i条第三扫描信号线，EM(i)指的是第i条发光信号线，REF(i)指的是第i条参考信号线。
在示例性实施方式中，如图5至图7，第i行像素驱动电路，分别与第i条第一扫描信号线、第i条第二扫描信号线、第i条第三扫描信号线、第i条发光信号线和第i条参考信号线电连接，1≤i≤M，M为像素驱动电路的总行数。示例性地，第2j-1行像素驱动电路，分别与第2j-1条第一扫描信号线G1(2j-1)、第2j-1条第二扫描信号线G2(2j-1)、第2j-1条第三扫描信号线G3(2j-1)、第2j-1条发光信号线EM(2j-1)和第2j-1条参考信号线REF(2j-1)电连接，第2j行像素驱动电路，分别与第2j条第一扫描信号线G1(2j)、第2j 条第二扫描信号线G2(2j-1)、第2j条第三扫描信号线G3(2j)、第2j条发光信号线EM(2j)和第2j条参考信号线REF(2j)电连接，
在示例性实施方式中，如图5至图7，第i条第三扫描信号线、第i条参考信号线、第i条第二扫描信号线、第i条第一扫描信号线和第i条发光信号线沿第二方向D2依次排布，第i条第三扫描信号线位于第i条参考信号线靠近第i-1条发光信号线的一侧，第i条发光信号线位于第i条第一扫描信号线靠近第i+1条第三扫描信号线的一侧，第二方向D2与第一方向D1相交。示例性地，第2j-1条第三扫描信号线G3(2j-1)、第2j-1条参考信号线REF(2j-1)、第2j-1条第二扫描信号线G2(2j-1)、第2j-1条第一扫描信号线G1(2j-1)和第2j-1条发光信号线EM(2j-1)沿第二方向D2排布，第2j-1条第三扫描信号线G3(2j-1)位于第2j-1条参考信号线REF(2j-1)靠近第2j-2条发光信号线EM(2j-2)的一侧，第2j-1条发光信号线EM(2j-1)位于第2j-1条第一扫描信号线G1(2j-1)靠近第2j条第三扫描信号线G3(2j)的一侧。
在示例性实施方式中，第二信号线可以与第二扫描信号线、第三扫描信号线和发光信号线中的至少一种信号线电连接。
在示例性实施方式中，如图5至图7所示，驱动电路层还可以包括：至少部分位于显示区域AA的M条初始信号线，初始信号线沿第一方向延伸。第i行像素驱动电路，与第i条初始信号线电连接。示例性地，第2j-1行像素驱动电路，与第2j-1条初始信号线INIT(2j-1)电连接，第2j行像素驱动电路，与第2j条初始信号线INIT(2j)电连接。
在示例性实施方式中，如图5至图7所示，第i条初始信号线位于第i条第三扫描信号线远离第i条参考信号线的一侧。
在示例性实施方式中，如图5至图7所示，驱动电路层还可以包括：位于非显示区域AA’的M条第一扫描输出线、M/2条第二扫描输出线、M/2条第三扫描输出线、M条参考输出线和M/2条发光输出线。其中，第一扫描输出线、第二扫描输出线、第三扫描输出线、参考输出线和发光输出线至少部分沿第一方向D1延伸。图5至图7中的GOUTL1(i)指的是第i条第一扫描输出线，REFOUTL(i)指的是第i条参考输出线，GOUTL2(j)指的是第j条第二扫描输出线，GOUTL3(j)指的是第j条第三扫描输出线，EMOUTL(j) 指的是第j条发光输出线。
在示例性实施方式中，如图5至图7所示，第i条第一扫描输出线GOUTL1(i)与第i条第一扫描信号线G1(i)电连接，第i条参考输出线REFOUTL1(i)与第i条参考信号线REF(i)电连接，第j条第二扫描输出线GOUTL2(j)分别与第2j-1条第二扫描信号线G2(2j-1)和第2j条第二扫描信号线G2(2j)电连接，第j条第三扫描输出线GOUTL3(j)分别与第2j-1条第三扫描信号线G3(2j-1)和第2j条第三扫描信号线G3(2j)电连接，第j条发光输出线EMOUTL(j)分别与第2j-1条发光信号线EM(2j-1)和第2j条发光信号线EM(2j)电连接，1≤j≤M/2。示例性地，第一条第一扫描输出线与第一条第一扫描信号线电连接，第二条第一扫描输出线与第二条第一扫描信号线电连接，依次类推。第一条参考输出线与第一条参考信号线电连接，第二条参考输出线与第二条参考信号线电连接，依次类推。第一条第二扫描输出线分别与第一条第二扫描信号线和第二条第二扫描信号线电连接，第二条第二扫描输出线分别与第三条第二扫描信号线和第四条第二扫描信号线电连接，依次类推。第一条第三扫描输出线分别与第一条第三扫描信号线和第二条第三扫描信号线电连接，第二条第三扫描输出线分别与第三条第三扫描信号线和第四条第三扫描信号线电连接，以此类推。第一条发光输出线分别与第一条发光信号线和第二条发光信号线电连接，第二条发光输出线分别与第三条发光信号线和第四条发光信号线电连接，依次类推。
在示例性实施方式中，一条发光输出线连接两条发光信号线，一条第二扫描输出线连接两条第二扫描信号线，一条第三扫描输出线连接两条第三扫描信号线可以减少显示面板的信号线的数量，实现显示面板的窄边框。
在示例性实施方式中，如图5至图7所示，第2j-1条参考输出线REFOUTL1(2j-1)、第2j-1条第一扫描输出线GOUTL1(2j-1)、第j条第二扫描输出线GOUTL2(j)、第j条第三扫描输出线GOUTL3(j)、第2j条参考输出线REFOUTL(2j)、第j条发光输出线EMOUTL(j)和第2j条第一扫描输出线GOUTL1(2j)沿第二方向D2依次排布。
在示例性实施方式中，如图5至图7所示，驱动电路层还可以包括：位于非显示区域AA’的参考供电线REFL以及位于至少部分位于显示区域的 数据信号线Data和第一电源线VDD，参考供电线REFL、数据信号线Data和第一电源线VDD至少部分沿第二方向D2延伸。
在示例性实施方式中，像素驱动电路分别与数据信号线Data和第一电源线VDD电连接。
在示例性实施方式中，参考供电线REFL在基底上的正投影与参考输出线在基底上的正投影至少部分重叠，且与参考输出线电连接。
在示例性实施方式中，驱动电路层可以包括：依次叠设在基底上的第一导电层和第二导电层，其中，
第一导电层可以至少包括：第一扫描信号线、第二扫描信号线、第三扫描信号线、发光信号线和参考供电线REFL；
第二导电层可以至少包括：第一扫描输出线、第二扫描输出线、第三扫描输出线、参考输出线、发光输出线、数据信号线Data和第一电源线VDD。
在示例性实施方式中，第一导电层和第二导电层的方阻大致相等。
在示例性实施方式中，第一导电层和第二导电层的制作材料和厚度相同。
在示例性实施方式中，第一扫描输出线、第二扫描输出线、第三扫描输出线、参考输出线和发光输出线沿第二方向的平均长度可以大致相等。
在示例性实施方式中，数据信号线Data和第一电源线VDD沿第一方向的平均长度大致相等。
在示例性实施方式中，相邻第一扫描信号线电连接的第一信号线靠近显示区域的边界B与显示区域之间的距离大致相等，相邻第一扫描信号线电连接的第一信号线沿第二方向的平均长度大致相等。相邻第一扫描信号线电连接的第一信号线靠近显示区域的边界与显示区域之间的距离大致相等，在第一导电层和第二导电层的方阻相同的情况下，可以使得相邻第一扫描信号线电连接的第一信号线的电阻相等。
在示例性实施方式中，相邻第一扫描信号线电连接的第一信号线与对应的第二信号线之间的交叠区域的面积大致相等。相邻第一扫描信号线电连接的第一信号线与对应的第二信号线之间的交叠区域的面积大致相等，在第一导电层和第二导电层的方阻相同的情况下，可以使得相邻第一扫描信号线电 连接的第一信号线的电阻相等。
在示例性实施方式中，如图5所示，驱动电路层还可以包括：位于第一导电层的第一信号连接线11。其中，第一信号连接线11可以沿第二方向D2延伸，且分别与第2j-1条第三扫描信号线G3(2j-1)和第2j条第三扫描信号线G3(2j)电连接。
在示例性实施方式中，第一信号连接线11可以与第2j-1条第三扫描信号线G3(2j-1)和第2j条第三扫描信号线G3(2j)为一体结构。
在示例性实施方式中，如图5所示，第一信号连接线11在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)在基底上的正投影至少部分交叠。
在示例性实施方式中，第一信号连接线11沿第一方向的长度可以与第三扫描信号沿第二方向的长度大致相等。
在示例性实施方式中，如图5所示，第j条第三扫描输出线GOUTL3(j)在基底上的正投影与第2j条第三扫描信号线G3(2j)在基底上的正投影至少部分交叠，且与第2j条第三扫描信号线G3(2j)电连接。在示例性实施方式中，第j条第三扫描输出线GOUTL3(j)通过第2j条第三扫描信号线G3(2j)和第一信号连接线11与第2j-1条第三扫描信号线G3(2j-1)电连接。
在示例性实施方式中，如图5所示，驱动电路层还可以包括：位于第二导电层的第二信号连接线12，第二信号连接线12可以沿第一方向D1延伸。
在示例性实施方式中，如图5所示，第2j条第二扫描信号线G2(2j)可以包括：相互连接的第一扫描连接部G2A和第二扫描连接部G2B。其中，第一扫描连接部G2A沿第一方向D1延伸，第二扫描连接部G2B沿第二方向D2延伸，第一信号连接线11可以位于第二扫描连接部G2B靠近显示区域AA的一侧。
在示例性实施方式中，如图5所示，第二扫描连接部G2B在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)、第j条第二扫描输出线GOUTL2(j)、第j条第三扫描输出线GOUTL3(j)和第二信号连接线12在基底上的正投影至少部分交叠，且分别与第j条第二扫描输出线GOUTL2(j)和第 二信号连接线12电连接。
在示例性实施方式中，如图5所示，第二信号连接线12在基底上的正投影与第2j-1条第二扫描信号线G2(2j-1)和第一信号连接线11在基底上的正投影至少部分交叠，且与第2j-1条第二扫描信号线G2(2j-1)电连接。
在示例性实施方式中，如图5所示，驱动电路层还可以包括：位于第二导电层的第三信号连接线13，第三信号连接线13沿第一方向D1延伸。
在示例性实施方式中，如图5所示，第二信号连接线12和第三信号连接线13靠近显示区域的边界与显示区域的边界之间的距离可以大致相等，且可以与第2j-1条第二扫描信号线G2(2j-1)靠近显示区域的边界B与显示区域的边界之间的距离可以大致相等。
在示例性实施方式中，如图5所示，第二信号连接线12和第三信号连接线13远离显示区域的边界与显示区域的边界之间的距离可以大致相等。
在示例性实施方式中，如图5所示，第二信号连接线12沿第二方向的平均长度可以与第三信号连接线13沿第二方向的平均长度可以大致相等。
在示例性实施方式中，如图5所示，第2j条发光信号线EM(2j)可以包括：相互连接的第一发光连接部EMA和第二发光连接部EMB，第一发光连接部EMA沿第一方向D1延伸，第二发光连接部沿第二方向D2延伸，第二发光连接部EMB位于参考供电线REFL和第二扫描连接部G2B之间。
在示例性实施方式中，如图5所示，第二发光连接部EMB在基底上的正投影与第j条发光输出线EMOUTL(j)、第j条第三扫描输出线GOUTL3(j)、第2j条第一扫描输出线GOUTL1(2j)和第三信号连接线13在基底上的正投影至少部分交叠，且分别与第j条发光输出线EMOUTL(j)和第三信号连接线13电连接。
在示例性实施方式中，如图5所示，第三信号连接线13在基底上的正投影与第2j-1条发光信号线EM(2j-1)、第一信号连接线11和第二扫描连接部G2B在基底上的正投影至少部分交叠，且与第2j-1条发光信号线EM(2j-1)电连接。第j条发光输出线EMOUTL(j)通过第二发光连接部EMB和第三信号连接线13与第2j-1条发光信号线EM(2j-1)电连接。
在示例性实施方式中，第二发光连接部与第2j条第一扫描输出线交叠区域的沿第一方向的长度大于所述第一发光连接部沿第二方向的长度。
在示例性实施方式中，如图5所示，第i条第一扫描信号线电连接的第一信号线包括：第i条第一扫描输出线，即第2j-1条第一扫描信号线G1(2j-1)电连接的第一信号线可以包括：第2j-1条第一扫描输出线GOUTL1(2j-1)，第2j条第一扫描信号线G1(2j)电连接的第一信号线可以包括：第2j条第一扫描输出线GOUTL1(2j)。
在示例性实施方式中，如图5所示，第2j-1条第一扫描信号线G1(2j-1)电连接的第一信号线对应的第二信号线可以包括第一信号连接线11和第2j条第二扫描信号线G2(2j)。
在示例性实施方式中，如图5所示，第2j条第一扫描信号线G1(2j)电连接的第一信号线对应的第二信号线可以包括第2j条发光信号线EM(2j)。
在示例性实施方式中，如图5所示，第2j-1条参考输出线REFOUTL(2j-1)在基底上的正投影与第一信号连接线11和第2j-1条参考信号线REF(2j-1)在基底的正投影至少部分交叠，且与第2j-1条参考信号线REF(2j-1)电连接。
在示例性实施方式中，如图5所示，第2j条参考输出线REFOUTL(2j)在基底上的正投影与第二扫描连接部G2B、第二发光连接部EMB和第2j条参考信号线REF(2j)在基底的正投影至少部分交叠，且与第2j条参考输出线REFOUTL(2j)电连接。
在示例性实施方式中，如图6所示，驱动电路层还可以包括：位于第一导电层的第一信号连接线21。其中，第一信号连接线21可以沿第二方向D2延伸，且分别与第2j-1条第三扫描信号线G3(2j-1)和第2j条第三扫描信号线G3(2j)电连接。
在示例性实施方式中，如图6所示，第一信号连接线21在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)和第2j条第一扫描输出线GOUTL1(2j)在基底上的正投影至少部分交叠。
在示例性实施方式中，如图6所示，第j条第三扫描输出线GOUTL3(j)在基底上的正投影与第2j条第三扫描信号线G3(2j)在基底上的正投影至少部 分交叠，且与第2j条第三扫描信号线G3(2j)电连接。第j条第三扫描输出线GOUTL3(j)通过第2j条第三扫描信号线G3(2j)和第一信号连接线与第2j-1条第三扫描信号线G3(2j-1)电连接。
在示例性实施方式中，如图6所示，驱动电路层还可以包括：位于第一导电层的第二信号连接线22以及位于第二导电层的第三信号连接线23和第四信号连接线24。其中，第二信号连接线22沿第二方向D2延伸，第三信号连接线23和第四信号连接线24至少部分沿第一方向D1延伸，第二信号连接线22位于第一信号连接线21远离显示区域的一侧。
在示例性实施方式中，如图6所示，第二信号连接线22在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)、第2j条第一扫描输出线GOUTL1(2j)、第j条第二扫描输出线GOUTL2(j)、第j条第三扫描输出线GOUTL3(j)、第三信号连接线23和第四信号连接线24在基底上的正投影至少部分交叠，且分别与第j条第二扫描输出线GOUTL2(j)、第三信号连接线23和第四信号连接线24电连接。
在示例性实施方式中，如图6所示，第三信号连接线23在基底上的正投影与第一信号连接线21和第2j-1条第二扫描信号线G2(2j-1)在基底上的正投影至少部分交叠，且与第2j-1条第二扫描信号线G2(2j-1)电连接。第j条第二扫描输出线GOUTL2(j)通过第二信号连接线22和第三信号连接线23与第2j-1条第二扫描信号线G2(2j-1)电连接。
在示例性实施方式中，如图6所示，第四信号连接线24在基底上的正投影与第一信号连接线21和第2j条第二扫描信号线G2(2j)在基底上的正投影至少部分交叠，且与第2j条第二扫描信号线G2(2j)电连接。第j条第二扫描输出线GOUTL2(j)通过第二信号连接线22和第四信号连接线24与第2j-1条第二扫描信号线G2(2j)电连接。
在示例性实施方式中，如图6所示，驱动电路层还可以包括：位于第一导电层的第五信号连接线25以及位于第二导电层的第六信号连接线26和第七信号连接线27。其中，第五信号连接线25可以沿第二方向D2延伸，第六信号连接线26和第七信号连接线27至少部分沿第一方向D1延伸，第五信号连接线25可以位于第二信号连接线22远离显示区域的一侧。
在示例性实施方式中，如图6所示，第五信号连接线25在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)、第2j条第一扫描输出线GOUTL1(2j)、第j条第二扫描输出线GOUTL2(j)、第j条第三扫描输出线GOUTL3(j)、第j条发光输出线EMOUTL(j)、第六信号连接线26和第七信号连接线27在基底上的正投影至少部分交叠，且分别与第j条发光输出线EMOUTL(j)、第六信号连接线26和第七信号连接线27电连接。
在示例性实施方式中，如图6所示，第六信号连接线26在基底上的正投影与第一信号连接线21、第二信号连接线22和第2j-1条发光信号线EM(2j-1)在基底上的正投影至少部分交叠，且与第2j-1条发光信号线EM(2j-1)电连接。
在示例性实施方式中，如图6所示，第七信号连接线27在基底上的正投影与第一信号连接线21、第二信号连接线22和第2j条发光信号线EM(2j)在基底上的正投影至少部分交叠，且与第2j条发光信号线EM(2j)电连接。
在示例性实施方式中，如图6所示，第i条第一扫描信号线电连接的第一信号线包括：第i条第一扫描输出线，即第2j-1条第一扫描信号线G1(2j-1)电连接的第一信号线包括第2j-1条第一扫描输出线GOUTL1(2j-1)，第2j条第一扫描信号线G1(2j)电连接的第一信号线包括第2j条第一扫描输出线GOUTL1(2j)。
在示例性实施方式中，如图6所示，第2j-1条第一扫描信号线电连接的第一信号线对应的第二信号线可以包括第一信号连接线21、第二信号连接线22和第五信号连接线25。
在示例性实施方式中，如图6所示，第2j条第一扫描信号线G1(2j)电连接的第一信号线对应的第二信号线可以包括第一信号连接线21、第二信号连接线22和第五信号连接线25。
在示例性实施方式中，第一信号连接线21沿第一方向D1的长度、第二信号连接线22沿第一方向D1的长度以及第五信号连接线25沿第一方向D1的长度可以大致相等，或者可以不相等，本公开对此不做任何限定。
在示例性实施方式中，第三信号连接线23靠近显示区域的边界与显示区域之间的距离可以与第2j-1条第一扫描输出线GOUTL1(2j-1)靠近显示区域的边界B与显示区域之间的距离大致相等。
在示例性实施方式中，第四信号连接线24靠近显示区域的边界与显示区域之间的距离可以与第2j-1条第一扫描输出线GOUTL1(2j-1)靠近显示区域的边界B与显示区域之间的距离大致相等。
在示例性实施方式中，第三信号连接线23沿第一方向D1的长度可以与第四信号连接线24沿第一方向D1的长度大致相等。
在示例性实施方式中，第六信号连接线26靠近显示区域的边界与显示区域之间的距离可以与第2j-1条第一扫描输出线GOUTL1(2j-1)靠近显示区域的边界B与显示区域之间的距离大致相等。
在示例性实施方式中，第七信号连接线27靠近显示区域的边界与显示区域之间的距离可以与第2j-1条第一扫描输出线GOUTL1(2j-1)靠近显示区域的边界B与显示区域之间的距离大致相等。
在示例性实施方式中，第六信号连接线26沿第一方向D1的长度可以与第七信号连接线27沿第一方向D1的长度大致相等，且大于第三信号连接线23沿第一方向D1的长度。
在示例性实施方式中，如图6所示，第2j-1条参考输出线REFOUTL(2j-1)在基底上的正投影与第一信号连接线21、第二信号连接线22、第五信号连接线25和第2j-1条参考信号线REF(2j-1)在基底的正投影至少部分交叠，且与第2j-1条参考信号线REF(2j-1)电连接。
在示例性实施方式中，如图6所示，第2j条参考输出线REFOUTL(2j)在基底上的正投影与第一信号连接线21、第二信号连接线22、第五信号连接线25和第2j条参考信号线REF(2j)在基底的正投影至少部分交叠，且与第2j条参考输出线REFOUTL(2j)电连接。
在示例性实施方式中，如图7所示，驱动电路层还可以包括：位于第一导电层的第一信号连接线31。其中，第一信号连接线31可以沿第二方向D2延伸，且分别与第2j-1条第三扫描信号线G3(2j-1)和第2j条第三扫描信号线G3(2j)电连接。
在示例性实施方式中，如图7所示，第一信号连接线31在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)、第j条第二扫描输出线 GOUTL2(j)和第j条第三扫描输出线GOUTL3(j)在基底上的正投影至少部分交叠，且与第j条第三扫描输出线GOUTL3(j)电连接。第j条第三扫描输出线GOUTL3(j)通过第一信号连接线31分别与第2j-1条第三扫描信号线G3(2j-1)和第2j条第三扫描信号线G3(2j)电连接。
在示例性实施方式中，如图7所示，第一信号连接线31沿第一方向的长度可以与第三扫描信号线沿第二方向的长度大致相等。
在示例性实施方式中，如图7所示，第2j-1条第二扫描信号线G2(2j-1)包括：相互连接的第一扫描连接部G2C和第二扫描连接部G2D，第一扫描连接部G2C沿第一方向D1延伸，第二扫描连接部G2D沿第二方向D2延伸。
在示例性实施方式中，如图7所示，第j条第二扫描输出线GOUTL2(j)包括：相互连接的第一扫描输出连接部GOLA和第二扫描输出连接部GOLB，第一扫描输出连接部GOLA沿第一方向D1延伸，第二扫描输出连接部GOLB沿第二方向D2延伸。
在示例性实施方式中，如图7所示，沿第二方向D2延伸的虚拟直线穿过第二扫描连接部G2D和第二扫描输出连接部GOLB，第二扫描连接部G2D位于第一信号连接线31靠近显示区域AA的一侧。
在示例性实施方式中，如图7所示，第二扫描连接部G2D在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)和第一扫描输出连接部GOLA在基底上的正投影至少部分交叠，且与第一扫描输出连接部GOLA电连接。
在示例性实施方式中，如图7所示，第一扫描输出连接部GOLA在基底上的正投影与第一信号连接线31在基底上的正投影至少部分交叠。
在示例性实施方式中，如图7所示，第二扫描输出连接部GOLB在基底上的正投影与第2j条第三扫描信号线G3(2j)和第2j条第二扫描信号线G2(2j)在基底上的正投影至少部分交叠，且与第2j条第二扫描信号线G2(2j)电连接。
在示例性实施方式中，如图7所示，驱动电路层还包括：位于第一导电层的第二信号连接线32，第二信号连接线32沿第一方向D1延伸。
在示例性实施方式中，如图7所示，第二信号连接线32在基底上的正投 影与第2j条第一扫描输出线GOUTL1(2j)在基底上的正投影至少部分交叠，且分别与第2j条第一扫描输出线GOUTL1(2j)和第2j条第一扫描信号线G1(2j)电连接。
在示例性实施方式中，如图7所示，第二信号连接线32沿第二方向D2的长度大于第一扫描信号线沿第二方向D2的长度。
在示例性实施方式中，如图7所示，第j条发光输出线EMOUTL(j)包括：相互连接的第一发光输出连接部EOLA和第二发光输出连接部EOLB，第一发光输出连接部EOLA沿第一方向D1延伸，第二发光输出连接部EOLB沿第二方向D2延伸；第二发光输出连接部EOLB位于第二扫描输出连接部GOLB靠近显示区域AA的一侧。
在示例性实施方式中，如图7所示，第二发光输出连接部EOLB在基底上的正投影与第二信号连接线32、第2j-1条发光信号线EM(2j-1)、第2j条发光信号线EM(2j)、第2j条第三扫描信号线G3(2j)和第2j条第二扫描信号线G2(2j)在基底上的正投影至少部分交叠，且分别与第2j-1条发光信号线EM(2j-1)和第2j条发光信号线EM(2j)电连接。
在示例性实施方式中，如图7所示，第2j-1条第一扫描信号线G1(2j-1)电连接的第一信号线可以包括第2j-1条第一扫描输出线GOUTL1(2j-1)。
在示例性实施方式中，如图7所示，第2j条第一扫描信号线G1(2j)电连接的第一信号线可以包括第2j条第一扫描输出线GOUTL1(2j)和第二信号连接线32。
在示例性实施方式中，如图7所示，第2j-1条第一扫描信号线电连接的第一信号线对应的第二信号线可以包括第一信号连接线31和第2j-1条第二扫描信号线G2(2j-1)。
在示例性实施方式中，如图7所示，第2j条第一扫描信号线G1(2j)电连接的第一信号线对应的第二信号线可以包括第j条发光输出线EMOUTL(j)。
在示例性实施方式中，如图7所示，第2j-1条参考输出线REFOUTL(2j-1)在基底上的正投影与第2j-1条参考信号线REF(2j-1)在基底的正投影至少部分交叠，且与第2j-1条参考信号线REF(2j-1)电连接。
在示例性实施方式中，如图7所示，第2j条参考输出线REFOUTL(2j)在基底上的正投影与第2j条参考信号线REF(2j)在基底的正投影至少部分交叠，且与第2j条参考输出线REFOUTL(2j)电连接。
在示例性实施方式中，如图7所示，参考供电线REFL远离显示区域的边界与第2j-1条第一扫描输出线GOUTL1(2j-1)靠近显示区域的边界之间的距离可以与参考供电线REFL远离显示区域的边界与第二信号连接线靠近显示区域的边界之间的距离大致相等，且为a。
在示例性实施方式中，如图7所示，第2j-1条第一扫描输出线GOUTL1(2j-1)沿第二方向的长度与第二信号连接线32沿第二方向的长度大致相等，且为b。
在示例性实施方式中，如图7所示，当第一信号连接线31与第2j-1条第一扫描输出线GOUTL1(2j-1)的交叠区域的沿第一方向的长度为c，第二扫描连接部与第2j-1条第一扫描输出线GOUTL1(2j-1)的交叠区域的沿第一方向的长度也为c时，为了保证相邻第一扫描信号线电连接的第一信号线的RC相同，第二发光输出部EOLB沿第一方向的长度d可以为2c微米。例如，当c＝6时，d＝12。
在示例性实施方式中，如图7所示，第一扫描输出线的实际值与理论值会存在误差，示例性地，第一扫描输出线的实际值可以比理论值小2微米。
在示例性实施方式中，当a＝475微米，b＝10微米，c＝6微米，d＝12微米时，位于参考供电线REFL远离显示区域的边界与第2j-1条第一扫描输出线GOUTL1(2j-1)靠近显示区域的边界之间的第2j-1条第一扫描输出线GOUTL1(2j-1)的电阻R满足R＝Rs*a/b＝0.03*475/10＝1.425Ω，其中，Rs为第一导电层的方阻。其中，a和b为实际值，位于区域R1的电容值C 1满足C 1＝K*S/D，其中，K为介电常数，S为交叠区域的面积，D为第二导电层的厚度，S＝2*10微米*6微米＝120平方微米。位于参考供电线REFL远离显示区域的边界与第二信号连接线靠近显示区域的边界之间的第2j-1条第一扫描输出线GOUTL1(2j-1)和第一信号连接线的电阻R 2满足R 2＝Rs*a/b＝0.03*475/10＝1.425Ω，与位于参考供电线REFL远离显示区域的边界与第2j-1条第一扫描输出线GOUTL1(2j-1)靠近显示区域的边界之间的第2j-1 条第一扫描输出线GOUTL1(2j-1)的电阻R 1相同。另外，位于区域R2的电容值C 2满足C 2＝10微米*12微米＝120平方微米，与位于区域R1的电容值C 1相等，也就是说，本公开中与第2j-1条第一扫描信号线电连接的第一信号线和与第2j条第一扫描信号线电连接的第一信号线在相同区域的电阻以及与对应的第二信号线之间的交叠区域之间的电容值均相等。
在示例性实施方式中，当第2j-1条第一扫描信号线电连接的第一信号线和与第2j条第一扫描信号线电连接的第一信号线的方阻差距较大，可以通过采用不同的制作材料或者改变信号线的走向以使得与第2j-1条第一扫描信号线电连接的第一信号线和与第2j条第一扫描信号线电连接的第一信号线在相同区域的电阻以及与对应的第二信号线之间的交叠区域之间的电容值均相等。
在示例性实施方式中，驱动电路层还可以包括：遮挡层，遮挡层位于第一导电层靠近基底的一侧。遮挡层至少包括：参考信号线和初始信号线。
在示例性实施方式中，驱动电路层还可以包括：半导体层，半导体层位于遮挡层和第一导电层之间，半导体层至少可以包括：多个晶体管的有源层。
在示例性实施例中，像素驱动电路中的存储电容可以包括：第一极板、第二极板和第三极板，其中，第一极板和第三极板电连接。示例性地，第一极板可以位于遮挡层，第二极板可以位于半导体层，第三极板可以位于第二导电层。在示例性实施方式中，存储电容包括三个极板可以提升存储电容的存储能力，保证像素驱动电路中的第一节点的信号的稳定性，可以提升显示面板的可靠性。
在示例性实施方式中，显示面板还可以包括：位于遮挡层和半导体层之间的第一绝缘层、位于半导体层和第一导电层之间的第二绝缘层、位于第一导电层和第二导电层之间的第三绝缘层以及位于第二导电层远离基底的一侧的第四绝缘层和平坦层。
下面通过显示面板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种 或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开在此不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示面板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，显示面板的制备过程可以包括如下操作。
(1)形成遮挡层图案，在示例性实施方式中，形成遮挡层图案可以包括：在基底上依次沉积遮挡薄膜，通过图案化工艺对遮挡薄膜进行图案化，形成覆盖基底的遮挡层图案，图8为图5至图7提供的显示面板形成遮挡层图案后的示意图。图8是以显示区域AA中第2j-1行第一列、第2j-1行第二列、第2j行第一列和第2j行第二列的像素电路为例进行说明的。
在示例性实施方式中，如图8所示，遮挡层图案可以至少包括位于显示区域的子像素的存储电容的第一极板C1和第一连接线VL1以及至少部分位于显示区域的初始信号线和参考信号线。图8是以初始信号线位于显示区域，参考信号线位于显示区域AA和非显示区域AA’为例进行说明的，且图8中仅示出了第2j-1条初始信号线INIT(2j-1)、第2j条初始信号线INIT(2j)、参考信号线REF(2j-1)和第2j条参考信号线REF(2j)。
在示例性实施方式中，如图8所示，初始信号线、参考信号线和第一连接线VL1沿第一方向D1延伸，且同一像素驱动电路电连接的初始信号线位于电连接的参考信号线远离像素驱动电路的存储电容的第一极板的一侧。示例性地，第2j-1行像素驱动电路电连接的第2j-1条初始信号线INIT(2j-1)位于第2j-1行像素驱动电路电连接的第2j-1条参考信号线REF(2j-1)远离第2j-1行像素驱动电路的存储电容的第一极板C1的一侧，第2j行像素驱动电路电 连接的第2j条初始信号线INIT(2j)位于第2j行像素驱动电路电连接的第2j条参考信号线REF(2j)远离第2j行像素驱动电路的存储电容的第一极板C1的一侧。
在示例性实施方式中，如图8所示，存储电容的第一极板C1为条状结构，且位于所在的像素驱动电路电连接的参考信号线和所在的像素驱动电路的第一连接线之间，示例性地，第2j-1行像素驱动电路的存储电容的第一极板C1位于第2j-1行像素驱动电路电连接的第2j-1条参考信号线REF(2j-1)和第2j-1行像素驱动电路的第一连接线VL1之间。第2j行像素驱动电路的存储电容的第一极板C1位于第2j行像素驱动电路电连接的第2j条参考信号线REF(2j)和第2j行像素驱动电路的第一连接线VL1之间。
在示例性实施方式中，初始信号线和扫描信号线可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
(2)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图9和图10所示，图9为图5至图7提供的显示面板的半导体层图案的示意图，图10为图5至图7提供的显示面板的形成半导体层图案后的示意图。
在示例性实施方式中，如图9和图10所示，半导体层图案可以至少包括位于显示区域的每个子像素的第一晶体管T1的有源层T11至第五晶体管T5的T51。
在示例性实施方式中，第一晶体管的有源层T11和第二晶体管的有源层T21为相互连接的一体结构。第三晶体管的有源层T31、第四晶体管的有源层T41和第五晶体管的有源层T51单独设置。
在示例性实施方式中，在第一方向D1上，第三晶体管的有源层T31、第四晶体管的有源层T41和第五晶体管的有源层T51可以位于本子像素中第一晶体管的有源层T11和第二晶体管的有源层T21的一体结构的同一侧。在 第二方向D2上，本行子像素中的第三晶体管的有源层T31可以位于第一晶体管的有源层T11和第二晶体管的有源层T21的一体结构靠近上一行子像素的一侧，本行子像素中的第四晶体管的有源层T41可以位于第一晶体管的有源层T11和第二晶体管的有源层T21的一体结构靠近下一行子像素的一侧，本列子像素中的第五晶体管的有源层T51可以位于第一晶体管的有源层T11和第二晶体管的有源层T21的一体结构靠近上一列子像素的一侧。
在示例性实施方式中，第三晶体管的有源层T31、第四晶体管的有源层T41和第五晶体管的有源层T51的形状可以呈条状结构，第一晶体管的有源层T11的形状可以呈“7”字形，第二晶体管的有源层T21可以呈水平翻转的“7”字形。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一晶体管的有源层T11的第二区T11_2可以作为第二晶体管的有源层T21的第二区T21_2，除了第一晶体管的有源层T11的第二区T11_2和第二晶体管的有源层T21的第二区的其余的晶体管的有源层的第一区和第二区可以单独设置。
在示例性实施方式中，存储电容的第一极板在基底上的正投影与第五晶体管的有源层T51以及第一晶体管的有源层T11和第二晶体管的有源层T21的一体结构在基底上的正投影至少部分交叠。存储电容的第一极板可以对第五晶体管的有源层T51进行遮挡，避免光线对驱动晶体管的有源层的影响，可以提升像素驱动电路的可靠性。
(3)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图11至图16所示，图11为图5提供的显示面板的第一导电层图案的示意图，图12为图5提供的显示面板的形成第一导电层图案后的示意图，图13为图6提供的显示面板的第一导电层图案的示意图，图14为图6提供的显示面板的形成第一导电层图案后的示意图，图15为图7提供的显示面板的第一导电层图案的示意图，图16为图7提供的显示面板的形成第一导电层图案后的示意图。在示 例性实施方式中，第一导电层可以称为栅金属(GATE)层。图11至图16中仅示出了第2j-1条第一扫描信号线G1(2j-1)、第2j条第一扫描信号线G1(2j)、第2j-1条第二扫描信号线G2(2j-1)、第2j条第二扫描信号线G2(2j)、第2j-1条第三扫描信号线G3(2j-1)、第2j条第二扫描信号线G3(2j)、第2j-1条发光信号线EM(2j-1)和第2j条发光信号线EM(2j)。
在示例性实施方式中，如图11至图16所示，第一导电层图案可以至少包括：位于显示区域的子像素的第一晶体管的控制极T12至第五晶体管的控制极T52、至少部分位于显示区域的第一扫描信号线、第二扫描信号线、第三扫描信号线和发光信号线以及位于非显示区域的参考供电线REFL。
在示例性实施方式中，如图11至图16所示，第一扫描信号线、第二扫描信号线、第三扫描信号线和发光信号线的至少部分沿第一方向D1延伸，参考供电线REFL沿第二方向D2延伸。
在示例性实施方式中，第一扫描信号线、第二扫描信号线、第三扫描信号线和发光信号线可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，如图11至图16所示，对于每个子像素，子像素电连接的第三扫描信号线与第三晶体管的有源层的交叠区域作为本子像素的第三晶体管的控制极T32，子像素电连接的第二扫描信号线与第二晶体管的有源层的交叠区域作为本子像素的第二晶体管的控制极T22，子像素电连接的第一扫描信号线与第一晶体管的有源层的交叠区域作为本子像素的第一晶体管的控制极T12，子像素电连接的发光信号线与第四晶体管的有源层的交叠区域作为本子像素的第四晶体管的控制极T42，每个子像素的第五晶体管的控制极T52位于本子像素电连接的第二扫描信号线和第一扫描信号线之间。
在示例性实施方式中，第五晶体管的控制极T52沿第一方向D1延伸。
在示例性实施方式中，如图11至图16所示，第i条第三扫描信号线、第i条参考信号线、第i条第二扫描信号线、第i条第一扫描信号线和第i条发光信号线沿第二方向D2依次排布，第i条第三扫描信号线位于第i条参考信号线靠近第i-1条发光信号线的一侧，第i条发光信号线位于第i条第一扫 描信号线靠近第i+1条第三扫描信号线的一侧。示例性地，第2j-1条第三扫描信号线G3(2j-1)、第2j-1条参考信号线REF(2j-1)、第2j-1条第二扫描信号线G2(2j-1)、第2j-1条第一扫描信号线G1(2j-1)和第2j-1条发光信号线EM(2j-1)沿第二方向D2排布，第2j-1条第三扫描信号线G3(2j-1)位于第2j-1条参考信号线REF(2j-1)靠近第2j-2条发光信号线EM(2j-2)的一侧，第2j-1条发光信号线EM(2j-1)位于第2j-1条第一扫描信号线G1(2j-1)靠近第2j条第三扫描信号线G3(2j)的一侧。
在示例性实施方式中，第i条第三扫描信号线在基底上的正投影位于第i条初始信号线在基底上的正投影和第i条参考信号线在基底的正投影之间。示例性地，对于第2j条第三扫描信号线G3(2j)在基底上的正投影位于第2j条初始信号线INIT(2j)在基底上的正投影和第2j条参考信号线REF(2j)在基底的正投影之间。
在示例性实施方式中，如图11和图12所示，图5提供的显示面板的第一导电层图案还可以包括：与第2j-1条第三扫描信号线G3(2j-1)和第2j条第二扫描信号线G3(2j)电连接的第一信号连接线11。
在示例性实施方式中，如图11和图12所示，第一信号连接线11可以沿第二方向D2延伸，第一信号连接线11可以位于参考供电线REFL靠近显示区域的一侧。
在示例性实施方式中，如图11和图12所示，第一信号连接线11与第2j-1条第三扫描信号线G3(2j-1)和第2j条第二扫描信号线G3(2j)为一体结构。
在示例性实施方式中，如图11和图12所示，第2j-1条第一扫描信号线G1(2j-1)、第2j条第一扫描信号线G1(2j)、第2j-1条第二扫描信号线G2(2j-1)、第2j-1条第三扫描信号线G3(2j-1)、第2j条第三扫描信号线G3(2j)和第2j-1条发光信号线EM(2j-1)沿第一方向D1延伸。
在示例性实施方式中，如图11和图12所示，第2j条第二扫描信号线G2(2j)包括：相互连接的第一扫描连接部G2A和第二扫描连接部G2B。其中，第一扫描连接部G2A沿第一方向D1延伸，第二扫描连接部G2B沿第二方向D2延伸，第一信号连接线11位于第二扫描连接部G2B靠近显示区域AA的一侧。
在示例性实施方式中，如图11和图12所示，第2j条发光信号线EM(2j)可以包括：相互连接的第一发光连接部EMA和第二发光连接部EMB，第一发光连接部EMA沿第一方向D1延伸，第二发光连接部EMB沿第二方向D2延伸，第二发光连接部EMB位于参考供电线REFL和第二扫描连接部G2B之间。
在示例性实施方式中，如图13和图14所示，图6提供的显示面板的第一导电层图案还包括：第一信号连接线21、第二信号连接线22和第五信号连接线25。
在示例性实施方式中，如图13和图14所示，第一信号连接线21与第2j-1条第三扫描信号线G3(2j-1)和第2j条第二扫描信号线G3(2j)电连接，且与第2j-1条第三扫描信号线G3(2j-1)和第2j条第二扫描信号线G3(2j)为一体结构。
在示例性实施方式中，如图13和图14所示，第一信号连接线21、第二信号连接线22和第五信号连接线25可以沿第二方向D2延伸。其中，第一信号连接线21、第二信号连接线22和第五信号连接线25可以位于参考供电线REF靠近显示区域的一侧，第一信号连接线21和第二信号连接线22可以位于第五信号连接线25靠近显示区域的一侧，第一信号连接线21可以位于第二信号连接线22靠近显示区域的一侧。
在示例性实施方式中，第一信号连接线、第二信号连接线和第五信号连接线可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，如图13和图14所示，第2j-1条第一扫描信号线G1(2j-1)、第2j条第一扫描信号线G1(2j)、第2j-1条第二扫描信号线G2(2j-1)、第2j条第二扫描信号线G2(2j)、第2j-1条第三扫描信号线G3(2j-1)、第2j条第三扫描信号线G3(2j)、第2j-1条发光信号线EM(2j-1)和第2j条发光信号线EM(2j)均沿第一方向D1延伸。
在示例性实施方式中，如图15和图16所示，图7提供的显示面板的第一导电层图案还包括：与第2j-1条第三扫描信号线G3(2j-1)和第2j条第二扫 描信号线G3(2j)电连接的第一信号连接线31以及与第2j条第一扫描信号线G1(2j)电连接的第二信号连接线32。
在示例性实施方式中，如图15和图16所示，第一信号连接线31可以沿第二方向D2延伸，第一信号连接线31可以位于参考供电线REF靠近显示区域的一侧。
在示例性实施方式中，如图15和图16所示，第二信号连接线32可以沿第一方向D1延伸，且第二信号连接线32沿第二方向的长度大于第2j条第一扫描信号线G1(2j)沿第二方向D2的宽度。
在示例性实施方式中，如图15和图16所示，第2j-1条第一扫描信号线G1(2j-1)、第2j条第一扫描信号线G1(2j)、第2j条第二扫描信号线G2(2j)、第2j-1条第三扫描信号线G3(2j-1)、第2j条第三扫描信号线G3(2j)、第2j-1条发光信号线EM(2j-1)和第2j条发光信号线EM(2j)均沿第一方向D1延伸。
在示例性实施方式中，如图15和图16所示，第2j-1条第二扫描信号线G2(2j-1)包括：相互连接的第一扫描连接部G2C和第二扫描连接部G2D，第一扫描连接部G2C沿第一方向D1延伸，第二扫描连接部G2D沿第二方向D2延伸。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第五晶体管T5的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管的有源层至第五晶体管的有源层的第一区和第二区均被导体化。如图12、图14和图16所示，第二晶体管的有源层的第二区(也是第一晶体管的有源层的第二区)被复用为存储电容的第二极板C2和第二晶体管的第二极T24。
(4)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图17至图19所示，图17为图5提供的显示面板的形成第三绝缘层图案后的示意图，图18为图6提供的显示面板的形成第三绝缘层图案后的示意图，图19为图7提供的显示面板的形成第三绝缘层图案后 的示意图。
在示例性实施方式中，如图17所示，图5提供的显示面板中的多个过孔可以至少包括：位于显示区域AA的每个子像素的第一过孔V1至第九过孔V9以及位于非显示区域AA’的第十过孔V10至第十九过孔V19。
在示例性方式中，第十过孔V10至第二十一过孔V21中的任一过孔的数量可以为多个，且可以阵列排布，本公开对此不做任何限定。
在示例性实施方式中，如图17所示，第一过孔V1在基底上的正投影位于第一晶体管的有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第三绝缘层和第二绝缘层被去掉，暴露出第一晶体管的有源层的第一区的表面，第一过孔V1被配置为使后续形成的第一晶体管的第一极通过该过孔与第一晶体管的有源层的第一区连接。
在示例性实施方式中，如图17所示，第二过孔V2在基底上的正投影位于第五晶体管的控制极和第一晶体管的有源层的第二区(也是第二晶体管的有源层的第二区和第二极板)在基底上的正投影的范围之内，第二过孔V2内的第三绝缘层和第二绝缘层被去掉，暴露出第一晶体管的有源层的第二区的表面，第二过孔V2内的第三绝缘层被去掉暴露出第五晶体管的控制极，第二过孔V2被配置为使后续形成的第一晶体管的第二极通过该过孔与第五晶体管的控制极和第一晶体管的有源层的第二区(也是第二晶体管的有源层的第二区和第二极板)连接。
在示例性实施方式中，如图17所示，第三过孔V3在基底上的正投影位于第二晶体管的有源层的第一区和子像素电连接的参考信号线在基底上的正投影的范围之内，第三过孔V3内的第三绝缘层和第二绝缘层被去掉，暴露出第二晶体管的有源层的第一区的表面，第三过孔V3内的第一绝缘层至第三绝缘层被去掉，暴露出子像素电连接的参考信号线的表面，第三过孔V3被配置为使后续形成的第二晶体管的第一极通过该过孔与第二晶体管的有源层的第一区和子像素电连接的参考信号线连接。
在示例性实施方式中，如图17所示，第四过孔V4在基底上的正投影位于第三晶体管的有源层的第二区在基底上的正投影的范围之内，第四过孔V4内的第三绝缘层和第二绝缘层被去掉，暴露出第三晶体管的有源层的第二区 的表面，第四过孔V4被配置为使后续形成的第三晶体管的第二极通过该过孔与第三晶体管的有源层的第二区连接。
在示例性实施方式中，如图17所示，第五过孔V5在基底上的正投影位于第三晶体管的有源层的第一区和子像素电连接的初始信号线在基底上的正投影的范围之内，第五过孔V5内的第三绝缘层和第二绝缘层被去掉，暴露出第三晶体管的有源层的第一区的表面，第五过孔V5内的第一绝缘层至第三绝缘层被去掉，暴露出子像素电连接的初始信号线的表面，第五过孔V5被配置为使后续形成的第三晶体管的第一极通过该过孔与第三晶体管的有源层的第一区和子像素电连接的初始信号线连接。
在示例性实施方式中，如图17所示，第六过孔V6在基底上的正投影位于第四晶体管的有源层的第二区在基底上的正投影的范围之内，第六过孔V6内的第三绝缘层和第二绝缘层被去掉，暴露出第四晶体管的有源层的第二区的表面，第六过孔V6被配置为使后续形成的第四晶体管的第二极通过该过孔与第四晶体管的有源层的第二区连接。
在示例性实施方式中，如图17所示，第七过孔V7在基底上的正投影位于第四晶体管的有源层的第一区和第一连接线在基底上的正投影的范围之内，第七过孔V7内的第三绝缘层和第二绝缘层被去掉，暴露出第四晶体管的有源层的第一区的表面，第七过孔V7内的第一绝缘层至第三绝缘层被去掉，暴露出第一连接线的表面，第七过孔V7被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管的有源层的第一区和第一连接线连接。
在示例性实施方式中，如图17所示，第八过孔V8在基底上的正投影位于第五晶体管的有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第三绝缘层和第二绝缘层被去掉，暴露出第五晶体管的有源层的第一区的表面，第八过孔V8被配置为使后续形成的第五晶体管的第一极通过该过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，如图17所示，第九过孔V9在基底上的正投影位于第五晶体管的有源层的第二区和第一极板在基底上的正投影的范围之内，第九过孔V9内的第三绝缘层和第二绝缘层被去掉，暴露出第五晶体管的有源层的第二区的表面，第九过孔V9内的第一绝缘层至第三绝缘层被去掉， 暴露出第一极板的表面，第九过孔V9被配置为使后续形成的第五晶体管的第二极通过该过孔与第五晶体管的有源层的第二区和第一极板连接。
在示例性实施方式中，如图17所示，第十过孔V10在基底上的正投影位于第2j-1条参考信号线REF(2j-1)在基底上的正投影的范围之内，第十过孔V10内的第一绝缘层至第三绝缘层被去掉，暴露出第2j-1条参考信号线REF(2j-1)的表面，第十过孔V10被配置为使后续形成的第2j-1条参考输出线REFOUTL(2j-1)通过该过孔与第2j-1条参考信号线REF(2j-1)连接。
在示例性实施方式中，如图17所示，第十一过孔V11在基底上的正投影位于第2j条参考信号线REF(2j)在基底上的正投影的范围之内，第十过孔V10内的第一绝缘层至第三绝缘层被去掉，暴露出第2j条参考信号线REF(2j)的表面，第十一过孔V11被配置为使后续形成的第2j条参考输出线REFOUTL(2j)通过该过孔与第2j-1条参考信号线REF(2j)连接。
在示例性实施方式中，如图17所示，第十二过孔V12在基底上的正投影位于第2j-1条第一扫描信号线G1(2j-1)在基底上的正投影的范围之内，第十二过孔V12内的第三绝缘层被去掉，暴露出第2j-1条第一扫描信号线G1(2j-1)的表面，第十二过孔V12被配置为使后续形成的第2j-1条第一扫描输出线GOUTL1(2j-1)通过该过孔与第2j-1条第一扫描信号线G1(2j-1)连接。
在示例性实施方式中，如图17所示，第十三过孔V13在基底上的正投影位于第2j条第一扫描信号线G1(2j)在基底上的正投影的范围之内，第十三过孔V13内的第三绝缘层被去掉，暴露出第2j条第一扫描信号线G1(2j)的表面，第十三过孔V13被配置为使后续形成的第2j条第一扫描输出线GOUTL1(2j)通过该过孔与第2j条第一扫描信号线G1(2j)连接。
在示例性实施方式中，如图17所示，第十四过孔V14在基底上的正投影位于第2j-1条第二扫描信号线G2(2j-1)在基底上的正投影的范围之内，第十四过孔V14内的第三绝缘层被去掉，暴露出第2j-1条第二扫描信号线G2(2j-1)的表面，第十四过孔V14被配置为使后续形成的第二信号连接线通过该过孔与第2j-1条第二扫描信号线G2(2j-1)连接。
在示例性实施方式中，如图17所示，第十五过孔V15在基底上的正投影位于第2j条第二扫描信号线G2(2j)的第二扫描连接部在基底上的正投影的 范围之内，第十五过孔V15内的第三绝缘层被去掉，暴露出第2j条第二扫描信号线G2(2j)的第二扫描连接部的表面，第十五过孔V15被配置为使后续形成的第j条第二扫描输出线GOUTL2(j)和第二信号连接线通过该过孔与第2j条第二扫描信号线G2(2j)连接。
在示例性实施方式中，如图17所示，第十六过孔V16在基底上的正投影位于第2j条第三扫描信号线G3(2j)在基底上的正投影的范围之内，第十六过孔V16内的第三绝缘层被去掉，暴露出第2j条第三扫描信号线G3(2j)的表面，第十六过孔V16被配置为使后续形成的第j条第三扫描输出线GOUTL3(j)通过该过孔与第2j条第三扫描信号线G3(2j)连接。
在示例性实施方式中，如图17所示，第十七过孔V17在基底上的正投影位于第2j-1条发光信号线EM(2j-1)在基底上的正投影的范围之内，第十七过孔V17内的第三绝缘层被去掉，暴露出第2j-1条发光信号线EM(2j-1)的表面，第十七过孔V17被配置为使后续形成的第三信号连接线通过该过孔与第2j-1条发光信号线EM(2j-1)连接。
在示例性实施方式中，如图17所示，第十八过孔V18在基底上的正投影位于第2j条发光信号线EM(2j)的第二发光连接部在基底上的正投影的范围之内，第十八过孔V18内的第三绝缘层被去掉，暴露出第2j条发光信号线EM(2j)的第二发光连接部的表面，第十八过孔V18被配置为使后续形成的第j条发光输出线和第三信号连接线通过该过孔与第2j条发光信号线EM(2j)连接。
在示例性实施方式中，如图17所示，第十九过孔V19在基底上的正投影位于参考供电线在基底上的正投影的范围之内，第十九过孔V19内的第三绝缘层被去掉，暴露出参考供电线的表面，第十九过孔V19被配置为使后续形成的参考输出线通过该过孔与参考供电线连接。
在示例性实施方式中，如图18所示，图6提供的显示面板中的多个过孔可以至少包括：位于显示区域AA的每个子像素的第一过孔V1至第九过孔V9以及位于非显示区域AA’的第十过孔V10至第二十一过孔V21。
在示例性方式中，第十过孔V10至第二十一过孔V21中的任一过孔的数量可以为多个，且可以阵列排布，本公开对此不做任何限定。
在示例性实施方式中，如图18所示，图18中的第一过孔V1至第十三过孔V13以及第十六过孔V16与图17中的第一过孔V1至第十三过孔V13以及第十六过孔V16开设的位置以及连接的结构均相同。
在示例性实施方式中，如图18所示，第十四过孔V14在基底上的正投影位于第2j-1条第二扫描信号线G2(2j-1)在基底上的正投影的范围之内，第十四过孔V14内的第三绝缘层被去掉，暴露出第2j-1条第二扫描信号线G2(2j-1)的表面，第十四过孔V14被配置为使后续形成的第三信号连接线通过该过孔与第2j-1条第二扫描信号线G2(2j-1)连接。
在示例性实施方式中，如图18所示，第十五过孔V15在基底上的正投影位于第2j条第二扫描信号线G2(2j)的第二扫描连接部在基底上的正投影的范围之内，第十五过孔V15内的第三绝缘层被去掉，暴露出第2j条第二扫描信号线G2(2j)的第二扫描连接部的表面，第十五过孔V15被配置为使后续形成的第四信号连接线通过该过孔与第2j条第二扫描信号线G2(2j)连接。
在示例性实施方式中，如图18所示，第十七过孔V17在基底上的正投影位于第2j-1条发光信号线EM(2j-1)在基底上的正投影的范围之内，第十七过孔V17内的第三绝缘层被去掉，暴露出第2j-1条发光信号线EM(2j-1)的表面，第十七过孔V17被配置为使后续形成的第六信号连接线通过该过孔与第2j-1条发光信号线EM(2j-1)连接。
在示例性实施方式中，如图18所示，第十八过孔V18在基底上的正投影位于第2j条发光信号线EM(2j)的第二发光连接部在基底上的正投影的范围之内，第十八过孔V18内的第三绝缘层被去掉，暴露出第2j条发光信号线EM(2j)的表面，第十八过孔V18被配置为使后续形成的第七信号连接线通过该过孔与第2j条发光信号线EM(2j)连接。
在示例性实施方式中，如图18所示，第十九过孔V19在基底上的正投影位于第二信号连接线在基底上的正投影的范围之内，第十九过孔V19内的第三绝缘层被去掉，暴露出第二信号连接线的表面，第十九过孔V19被配置为使后续形成的第j条第二扫描输出线、第三连接信号线和第四连接信号线通过该过孔与第二信号连接线连接。
在示例性实施方式中，如图18所示，第二十过孔V20在基底上的正投 影位于第五信号连接线在基底上的正投影的范围之内，第二十过孔V20内的第三绝缘层被去掉，暴露出第五信号连接线的表面，第二十过孔V20被配置为使后续形成的第j条发光输出线、第六连接信号线和第七连接信号线通过该过孔与第五信号连接线连接。
在示例性实施方式中，如图18所示，第二十一过孔V21在基底上的正投影位于参考供电线在基底上的正投影的范围之内，第二十一过孔V21内的第三绝缘层被去掉，暴露出参考供电线的表面，第二十一过孔V21被配置为使后续形成的参考输出线通过该过孔与参考供电线连接。
在示例性实施方式中，如图19所示，图7提供的显示面板中的多个过孔可以至少包括：位于显示区域AA的每个子像素的第一过孔V1至第九过孔V9以及位于非显示区域AA’的第十过孔V10至第十九过孔V19。
在示例性方式中，第十过孔V10至第十九过孔V19中的任一过孔的数量可以为多个，且可以阵列排布，本公开对此不做任何限定。
在示例性实施方式中，如图19所示，图19中的第一过孔V1至第十二过孔V12、第十七过孔V17以及第十九过孔V19分别与图17中的第一过孔V1至第十二过孔V12、第十七过孔V17以及第十九过孔V19开设的位置以及连接的结构均相同。
在示例性实施方式中，如图19所示，第十三过孔V13在基底上的正投影位于第二信号连接线基底上的正投影的范围之内，第十三过孔V13内的第三绝缘层被去掉，暴露出第二信号连接线的表面，第十三过孔V13被配置为使后续形成的第2j条第一扫描输出线通过该过孔与第二信号连接线连接。
在示例性实施方式中，如图19所示，第十四过孔V14在基底上的正投影位于第2j-1条第二扫描信号线G2(2j-1)的第二扫描连接部在基底上的正投影的范围之内，第十四过孔V14内的第三绝缘层被去掉，暴露出第2j-1条第二扫描信号线G2(2j-1)的表面，第十四过孔V14被配置为使后续形成的第j条第二扫描输出线通过该过孔与第2j-1条第二扫描信号线G2(2j-1)连接。
在示例性实施方式中，如图19所示，第十五过孔V15在基底上的正投影位于第2j条第二扫描信号线G2(2j)在基底上的正投影的范围之内，第十五过孔V15内的第三绝缘层被去掉，暴露出第2j条第二扫描信号线G2(2j)的表 面，第十五过孔V15被配置为使后续形成的第j条第二扫描输出线和第二信号连接线通过该过孔与第2j条第二扫描信号线G2(2j)连接。
在示例性实施方式中，如图19所示，第十六过孔V16在基底上的正投影位于第一信号连接线在基底上的正投影的范围之内，第十六过孔V16内的第三绝缘层被去掉，暴露出第一信号连接线的表面，第十六过孔V16被配置为使后续形成的第j条第三扫描输出线通过该过孔与第一信号连接线连接。
在示例性实施方式中，如图19所示，第十八过孔V18在基底上的正投影位于第2j条发光信号线EM(2j)在基底上的正投影的范围之内，第十八过孔V18内的第三绝缘层被去掉，暴露出第2j条发光信号线EM(2j)的表面，第十八过孔V18被配置为使后续形成的第j条发光输出线通过该过孔与第2j条发光信号线EM(2j)连接。
(5)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，沉积第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，在第三绝缘层上形成第二导电层图案，如图20至图25所示，图20为图5提供的显示面板的第二导电层图案的示意图，图21为图5提供的显示面板的形成第二导电层图案后的示意图，图22为图6提供的显示面板的第二导电层图案后的示意图，图23为图6提供的显示面板的形成第二导电层图案的示意图，图24为图7提供的显示面板的第二导电层图案的示意图，图25为图7提供的显示面板的形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为源漏金属(SD)层。
在示例性实施方式中，如图20至图25所示，第二导电层图案至少可以包括：位于显示区域的每个子像素的第一晶体管的第一极T13和第二极T14至第五晶体管的第一极T53和第二极T54、存储电容的第三极板C3、至少部分位于显示区域的第一电源线VDD、数据信号线Data和第二连接线VL2以及位于非显示区域的第一扫描输出线、第二扫描输出线、第三扫描输出线、发光输出线和参考输出线。图20至图25仅示出了第2j-1条第一扫描输出线GOUTL1(2j-1)、第2j条第一扫描输出线GOUTL1(2j)、第j条第二扫描输出线GOUTL2(j)、第j条第三扫描输出线GOUTL3(j)、第j条发光输出线EMOUTL(j)、第2j-1条参考输出线REFOUTL(2j-1)和第2j条参考输出线 REFOUTL(2j)。
在示例性实施方式中，数据信号线Data和第一电源线VDD至少部分沿第二方向VDD延伸。
在示例性实施方式中，数据信号线Data与第一晶体管的第一极T13为一体结构，第一晶体管的第一极T13通过第一过孔与第一晶体管的有源层的第一区电连接。
在示例性实施方式中，第一电源线VDD与靠近第一电源线VDD的像素驱动电路的第四晶体管的第一极T43为一体结构，第四晶体管的第一极T43通过第七过孔与第四晶体管的有源层的第一区和第一连接线连接。
在示例性实施方式中，远离第一电源线VDD的像素驱动电路的第四晶体管的第一极T43单独设置，第四晶体管的第一极T43通过第七过孔与第四晶体管的有源层的第一区和第一连接线连接。远离第一电源线VDD的像素驱动电路的第四晶体管的第一极T43通过第一连接线和靠近第一电源线VDD的像素驱动电路的第四晶体管的第一极T43与第一电源线VDD电连接。
在示例性实施方式中，第二晶体管的第一极可以单独设置，或者可以与第二连接线VL2为一体成型结构。第二连接线VL2可以与参考信号线形成网状结构，可以提升参考信号的均一性。
在示例性实施方式中，第三晶体管的第二极T34、第五晶体管的第二极T54和第三极板C3为一体结构，第四晶体管的第二极T44和第五晶体管的第一极T53为一体结构，第一晶体管的第二极T14、第二晶体管的第一极T23和第三晶体管的第一极T33可以单独设置。
在示例性实施方式中，第四晶体管的第二极T44和第五晶体管的第一极T53为一体结构沿第二方向D2延伸。第一晶体管的第二极T14和第二晶体管的第一极T23沿第二方向D2延伸。第三晶体管的第一极T33沿第一方向D1延伸。
在示例性实施方式中，第一晶体管的第二极T14通过第二过孔与第一晶体管的有源层的第二区和第五晶体管的控制极电连接，第二晶体管的第 一极T23通过第三过孔与第二晶体管的有源层的第一区和子像素电连接的参考信号线电连接，第三晶体管的第一极T33通过第五过孔与第三晶体管的有源层的第一区和子像素电连接的初始信号线电连接，第三晶体管的第二极T34(也是第五晶体管的第二极T54和第三极板C3)通过第四过孔与第三晶体管的有源层的第二区电连接，且通过第九过孔与第五晶体管的有源层的第二区和第一极板电连接，第四晶体管的第二极T44(也是第五晶体管的第一极T53)通过第八过孔与第五晶体管的有源层的第一区电连接，且通过第六过孔与第四晶体管的有源层的第二区电连接。
在示例性实施方式中，第一扫描输出线、第二扫描输出线、第三扫描输出线、发光输出线和参考输出线至少部分沿第一方向D1延伸。
在示例性实施方式中，如图20和图21所示，第二导电层图案至少还可以包括：第二信号连接线12和第三信号连接线13。
在示例性实施方式中，第二信号连接线12和第三信号连接线13沿第一方向D1延伸。
在示例性实施方式中，如图20和图21所示，参考输出线靠近显示区域的边界与显示区域之间的距离小于第一扫描输出线靠近显示区域的边界与显示区域之间的距离。
在示例性实施方式中，如图20和图21所示，第二扫描输出线和发光输出线靠近显示区域的边界与显示区域之间的距离大于第一扫描输出线靠近显示区域的边界与显示区域之间的距离。
在示例性实施方式中，如图20和图21所示，第三扫描输出线、第二信号连接线13和第三信号连接线13靠近显示区域的边界与显示区域之间的距离等于第一扫描输出线靠近显示区域的边界与显示区域之间的距离。
示例性实施方式中，如图20和图21所示，第2j-1条第一扫描输出线GOUTL1(2j-1)在基底上的正投影分别与第一信号连接线11、第2j条第二扫描信号线G2(2j)的第二扫描连接部和第2j-1条第一扫描信号线G1(2j-1)在基底上的正投影至少部分交叠，且通过第十二过孔与第2j-1条第一扫描信号线G1(2j-1)电连接。
示例性实施方式中，如图20和图21所示，第2j条第一扫描输出线GOUTL1(2j)在基底上的正投影分别与第2j条发光信号线EM(2j)的第二发光连接部和第2j条第一扫描信号线G1(2j)在基底上的正投影至少部分交叠，且通过第十三过孔与第2j条第一扫描信号线G1(2j)电连接。
在示例性实施方式中，如图20和图21所示，第j条第三扫描输出线GOUTL3(j)在基底上的正投影与第2j条第三扫描信号线G3(2j)在基底上的正投影至少部分交叠，且通过第十六过孔与第2j条第三扫描信号线G3(2j)电连接。在示例性实施方式中，第j条第三扫描输出线GOUTL3(j)通过第2j条第三扫描信号线G3(2j)和第一信号连接线11与第2j-1条第三扫描信号线G3(2j-1)电连接。
在示例性实施方式中，如图20和图21所示，第二扫描连接部在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)、第j条第二扫描输出线GOUTL2(j)、第j条第三扫描输出线GOUTL3(j)和第二信号连接线12在基底上的正投影至少部分交叠，且通过第十五过孔分别与第j条第二扫描输出线GOUTL2(j)和第二信号连接线12电连接。
在示例性实施方式中，如图20和图21所示，第二信号连接线12在基底上的正投影与第2j-1条第二扫描信号线G2(2j-1)和第一信号连接线11在基底上的正投影至少部分交叠，且通过第十四过孔与第2j-1条第二扫描信号线G2(2j-1)电连接。
在示例性实施方式中，如图20和图21所示，第二发光连接部EMB在基底上的正投影与第j条发光输出线EMOUTL(j)、第j条第三扫描输出线GOUTL3(j)、第2j条第一扫描输出线GOUTL1(2j)和第三信号连接线13在基底上的正投影至少部分交叠，且通过第十八过孔分别与第j条发光输出线EMOUTL(j)和第三信号连接线13电连接。
在示例性实施方式中，如图20和图21所示，第三信号连接线13在基底上的正投影与第2j-1条发光信号线EM(2j-1)、第一信号连接线11和第二扫描连接部G2B在基底上的正投影至少部分交叠，且通过第十七过孔与第2j-1条发光信号线EM(2j-1)电连接。第j条发光输出线EMOUTL(j)通过第二发光连接部EMB和第三信号连接线13与第2j-1条发光信号线EM(2j-1)电连接。
在示例性实施方式中，第二发光连接部沿第一方向D1的长度大于第一发光连接部沿第二方向D2的长度。
在示例性实施方式中，如图20和图21所示，第2j-1条参考输出线REFOUTL(2j-1)在基底上的正投影与第一信号连接线11和第2j-1条参考信号线REF(2j-1)在基底的正投影至少部分交叠，且通过第十过孔与第2j-1条参考信号线REF(2j-1)电连接，通过第十九过孔与参考供电线电连接。
在示例性实施方式中，如图20和图21所示，第2j条参考输出线REFOUTL(2j)在基底上的正投影与第二扫描连接部G2B、第二发光连接部和第2j条参考信号线REF(2j)在基底的正投影至少部分交叠，且通过第十一过孔与第2j条参考输出线REFOUTL(2j)电连接，通过第十九过孔与参考供电线电连接。
在示例性实施方式中，如图22和图23所示，第二导电层图案至少还可以包括：第三信号连接线23、第四信号连接线24、第六信号连接线26和第七信号连接线27。
在示例性实施方式中，第三信号连接线23、第四信号连接线24、第六信号连接线26和第七信号连接线27可以沿第一方向D1延伸。
在示例性实施方式中，如图22和图23所示，参考输出线靠近显示区域的边界与显示区域之间的距离小于第一扫描输出线靠近显示区域的边界与显示区域之间的距离。
在示例性实施方式中，如图22和图23所示，第二扫描输出线、第三扫描输出线和发光输出线靠近显示区域的边界与显示区域之间的距离大于第一扫描输出线靠近显示区域的边界与显示区域之间的距离，且第三扫描输出线靠近显示区域的边界与显示区域之间的距离小于第二扫描输出线和发光输出线靠近显示区域的边界与显示区域之间的距离。
在示例性实施方式中，如图22和图23所示，第三信号连接线23、第四信号连接线24、第六信号连接线26和第七信号连接线27靠近显示区域的边界与显示区域之间的距离等于第一扫描输出线靠近显示区域的边界与显示区域之间的距离。
在示例性实施方式中，如图22和图23所示，第2j-1条第一扫描输出线GOUTL1(2j-1)在基底上的正投影分别与第一信号连接线21、第二信号连接线22、第五信号连接线25和第2j-1条第一扫描信号线G1(2j-1)在基底上的正投影至少部分交叠，且通过第十二过孔与第2j-1条第一扫描信号线G1(2j-1)电连接。
在示例性实施方式中，如图22和图23所示，第2j条第一扫描输出线GOUTL1(2j)在基底上的正投影分别与第一信号连接线21、第二信号连接线22、第五信号连接线25和第2j条第一扫描信号线G1(2j)在基底上的正投影至少部分交叠，且通过第十三过孔与第2j条第一扫描信号线G1(2j)电连接。
在示例性实施方式中，如图22和图23所示，第j条第三扫描输出线GOUTL3(j)在基底上的正投影与第2j条第三扫描信号线G3(2j)在基底上的正投影至少部分交叠，且通过第十六过孔与第2j条第三扫描信号线G3(2j)电连接。第j条第三扫描输出线GOUTL3(j)通过第2j条第三扫描信号线G3(2j)和第一信号连接线与第2j-1条第三扫描信号线G3(2j-1)电连接。
在示例性实施方式中，如图22和图23所示，第二信号连接线22在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)、第2j条第一扫描输出线GOUTL1(2j)、第j条第二扫描输出线GOUTL2(j)、第j条第三扫描输出线GOUTL3(j)、第三信号连接线23和第四信号连接线24在基底上的正投影至少部分交叠，且通过第十九过孔分别与第j条第二扫描输出线GOUTL2(j)、第三信号连接线23和第四信号连接线24电连接。
在示例性实施方式中，如图22和图23所示，第三信号连接线23在基底上的正投影与第一信号连接线21和第2j-1条第二扫描信号线G2(2j-1)电连接，且通过第十四过孔与第2j-1条第二扫描信号线G2(2j-1)电连接。第j条第二扫描输出线GOUTL2(j)通过第二信号连接线22和第三信号连接线23与第2j-1条第二扫描信号线G2(2j-1)电连接。
在示例性实施方式中，如图22和图23所示，第四信号连接线24在基底上的正投影与第一信号连接线21和第2j条第二扫描信号线G2(2j)电连接，且通过第十五过孔与第2j条第二扫描信号线G2(2j)电连接。第j条第二扫描 输出线GOUTL2(j)通过第二信号连接线22和第四信号连接线24与第2j-1条第二扫描信号线G2(2j)电连接。
在示例性实施方式中，如图22和图23所示，第五信号连接线25在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)、第2j条第一扫描输出线GOUTL1(2j)、第j条第二扫描输出线GOUTL2(j)、第j条第三扫描输出线GOUTL3(j)、第j条发光输出线EMOUTL(j)、第六信号连接线26和第七信号连接线27在基底上的正投影至少部分交叠，且通过第二十过孔分别与第j条发光输出线EMOUTL(j)、第六信号连接线26和第七信号连接线27电连接。
在示例性实施方式中，如图22和图23所示，第六信号连接线26在基底上的正投影与第一信号连接线21、第二信号连接线22和第2j-1条发光信号线EM(2j-1)在基底上的正投影至少部分交叠，且通过第十七过孔与第2j-1条发光信号线EM(2j-1)电连接。
在示例性实施方式中，如图22和图23所示，第七信号连接线27在基底上的正投影与第一信号连接线21、第二信号连接线22和第2j条发光信号线EM(2j)电连接，且通过第十八过孔与第2j条发光信号线EM(2j)电连接。
在示例性实施方式中，如图22和图23所示，第2j-1条参考输出线REFOUTL(2j-1)在基底上的正投影与第一信号连接线21、第二信号连接线22、第五信号连接线25和第2j-1条参考信号线REF(2j-1)在基底的正投影至少部分交叠，且通过第十过孔与第2j-1条参考信号线REF(2j-1)电连接，通过第二十一过孔与参考供电线电连接。
在示例性实施方式中，如图22和图23所示，第2j条参考输出线REFOUTL(2j)在基底上的正投影与第一信号连接线21、第二信号连接线22、第五信号连接线25和第2j条参考信号线REF(2j)在基底的正投影至少部分交叠，且通过第十八过孔与第2j条参考输出线REFOUTL(2j)电连接，通过第二十一过孔与参考供电线电连接。
在示例性实施方式中，如图24和图25所示，第j条第二扫描输出线GOUTL2(j)包括：相互连接的第一扫描输出连接部GOLA和第二扫描输出连接部GOLB，第一扫描输出连接部GOLA沿第一方向D1延伸，第二扫描输 出连接部GOLB沿第二方向D2延伸，沿第二方向D2延伸的虚拟直线穿过第二扫描连接部G2D和第二扫描输出连接部GOLB，第二扫描连接部位于第一信号连接线靠近显示区域AA的一侧。
在示例性实施方式中，如图24和图25所示，第j条发光输出线EMOUTL(j)包括：相互连接的第一发光输出连接部EOLA和第二发光输出连接部EOLB，第一发光输出连接部EOLA沿第一方向D1延伸，第二发光输出连接部EOLB沿第二方向D2延伸；第二发光输出连接部EOLB位于第二扫描输出连接部GOLB靠近显示区域AA的一侧。
在示例性实施方式中，如图24和图25所示，参考输出线靠近显示区域的边界与显示区域之间的距离大于第一扫描输出线靠近显示区域的边界与显示区域之间的距离。
在示例性实施方式中，如图24和图25所示，第2j-1条第一扫描输出线GOUTL1(2j-1)靠近显示区域的边界与显示区域之间的距离小于第j条发光输出线EMOUTL(j)靠近显示区域的边界与显示区域之间的距离，第j条发光输出线EMOUTL(j)靠近显示区域的边界与显示区域之间的距离小于第2j条第一扫描输出线GOUTL1(2j)和第j条第二扫描输出线GOUTL2(j)靠近显示区域的边界与显示区域之间的距离，第j条第二扫描输出线GOUTL2(j)靠近显示区域的边界与显示区域之间的距离小于第j条第三扫描输出线GOUTL3(j)靠近显示区域的边界与显示区域之间的距离，第j条第三扫描输出线GOUTL3(j)靠近显示区域的边界与显示区域之间的距离小于参考输出线靠近显示区域的边界与显示区域之间的距离。
在示例性实施方式中，如图24和图25所示，第2j-1条第一扫描输出线GOUTL1(2j-1)在基底上的正投影分别与第一信号连接线21、第2j-1条第二扫描信号线G2(2j-1)的第二扫描连接部和第2j-1条第一扫描信号线G1(2j-1)在基底上的正投影至少部分交叠，且通过第十二过孔与第2j-1条第一扫描信号线G1(2j-1)电连接。
在示例性实施方式中，如图24和图25所示，第2j条第一扫描输出线GOUTL1(2j)在基底上的正投影与第二信号连接线32在基底上的正投影至少部分交叠，且通过第十三过孔与第二信号连接线32电连接。
在示例性实施方式中，如图24和图25所示，第一信号连接线31在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)、第j条第二扫描输出线GOUTL2(j)和第j条第三扫描输出线GOUTL3(j)在基底上的正投影至少部分交叠，且通过第十六过孔与第j条第三扫描输出线GOUTL3(j)电连接。第j条第三扫描输出线GOUTL3(j)通过第一信号连接线31分别与第2j-1条第三扫描信号线G3(2j-1)和第2j条第三扫描信号线G3(2j)电连接。
在示例性实施方式中，如图24和图25所示，第二扫描连接部在基底上的正投影与第2j-1条第一扫描输出线GOUTL1(2j-1)和第一扫描输出连接部GOLA在基底上的正投影至少部分交叠，且通过第十四过孔与第一扫描输出连接部GOLA电连接。
在示例性实施方式中，如图24和图25所示，第二扫描输出连接部GOLB在基底上的正投影与第2j条第三扫描信号线G3(2j)和第2j条第二扫描信号线G2(2j)在基底上的正投影至少部分交叠，且通过第十五过孔与第2j条第二扫描信号线G2(2j)电连接。
在示例性实施方式中，如图24和图25所示，第二信号连接线32在基底上的正投影与第2j条第一扫描输出线GOUTL1(2j)在基底上的正投影至少部分交叠，且分别与第2j条第一扫描输出线GOUTL1(2j)和第2j条第一扫描信号线G1(2j)电连接。
在示例性实施方式中，如图24和图25所示，第二信号连接线32沿第二方向D2的长度大于第一扫描信号线沿第二方向D2的长度。
在示例性实施方式中，如图24和图25所示，第二发光输出连接部EOLB在基底上的正投影与第二信号连接线32、第2j-1条发光信号线EM(2j-1)第2j条发光信号线EM(2j，第2j条第三扫描信号线G3(2j)和第2j条第二扫描信号线G2(2j)在基底上的正投影至少部分交叠，且通过第十七过孔分别与第2j-1条发光信号线EM(2j-1)，通过第十八过孔与第2j条发光信号线EM(2j)电连接。
在示例性实施方式中，如图24和图25所示，第2j-1条参考输出线REFOUTL(2j-1)在基底上的正投影与第2j-1条参考信号线REF(2j-1)在基底的正投影至少部分交叠，且通过第十过孔与第2j-1条参考信号线REF(2j-1)电连 接，通过第十九过孔与参考供电线电连接。
在示例性实施方式中，如图24和图25所示，第2j条参考输出线REFOUTL(2j)在基底上的正投影与第2j条参考信号线REF(2j)在基底的正投影至少部分交叠，且通过第十过孔与第2j条参考输出线REFOUTL(2j)电连接，通过第十九过孔与参考供电线电连接。
(6)形成平坦层图案。在示例性实施方式中，形成平坦层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，在第四绝缘层上涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第四绝缘层的平坦层图案。
在示例性实施方式中，第四绝缘层和平坦层设置有暴露出第五晶体管的第二极(也是第三晶体管的第二极和第三极板)的过孔，该过孔被配置为使得后续形成的阳极与第五晶体管的第二极(也是第三晶体管的第二极和第三极板)连接。
至此，在基底上制备完成驱动电路层。在平行于显示面板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，像素驱动电路与第一扫描信号线、第二扫描信号线、第三扫描信号线、发光信号线、初始信号线、参考信号线、数据信号线和第一电源线连接。在垂直于显示面板的平面内，驱动电路层可以设置在基底上。
驱动电路层可以包括在基底上依次设置的遮挡层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层和平坦层。遮挡层至少可以包括：参考信号线、初始信号线和存储电容的第一极板，半导体层可以至少包括第一晶体管至第五晶体管的有源层以及存储电容的第二极板，第一导电层可以至少包括第一晶体管至第七晶体管的栅电极、第一扫描信号线、第二扫描信号线、第三扫描信号线、发光信号线以及参考供电线，第二导电层可以至少包括数据信号线、第一电源线、多个晶体管的第一极和第二极，存储电容的第三极板、第一扫描输出线、第二扫描输出线、第三扫描输出线、发光输出线和参考输出线。
在示例性实施方式中，第一导电层和第二导电层可以采用金属材料，如 银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层可以称为栅绝缘(GI)层，第三绝缘层可以称为层间绝缘(ILD)层，第四绝缘层可以成为钝化(PVX)层，平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(7)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第二平坦层上的阳极导电层，阳极导电层至少包括多个阳极图案。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，多个阳极图案可以包括红色发光器件的第一阳极、蓝色发光器件的第二阳极、第一绿色发光器件的第三阳极和第二绿色发光器件的第四阳极，第一阳极可以位于出射红色光线的红色子像素，第二阳极可以位于出射蓝色光线的蓝色子像素，第三阳极可以位于出射绿色光线的第一绿色子像素，第四阳极可以位于出射绿色光线的第二绿色子像素。
在示例性实施方式中，第一阳极和第二阳极可以沿着第一方向依次设置，第三阳极和第四阳极可以沿着第一方向依次设置，第三阳极和第四阳极可以设置在第一阳极和第二阳极第二方向的一侧。或者，第一阳极和第二阳极可以沿着第二方向依次设置，第三阳极和第四阳极可以沿着第二方向Y依次设置，第三阳极和第四阳极可以设置在第一阳极和第二阳极第一方向X的一侧。
在示例性实施方式中，第一阳极、第二阳极、第三阳极和第四阳极可以分别通过阳极过孔与所在子像素的驱动晶体管的第二极连接，一个像素单元 中四个子像素的阳极形状和面积可以相同，或者可以不同。
在示例性实施方式中，第一阳极、第二阳极、第三阳极和第四阳极中的至少一个可以包括相互连接的阳极主体部和阳极连接部。
在示例性实施方式中，第一阳极可以包括相互连接的第一阳极主体部和第一阳极连接部，第一阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角。在示例性实施方式中，第二阳极可以包括相互连接的第二阳极主体部和第二阳极连接部，第二阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第二阳极连接部的形状可以为条形状。在示例性实施方式中，第三阳极可以包括相互连接的第三阳极主体部和第三阳极连接部，第三阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第三阳极连接部的形状可以为条形状。在示例性实施方式中，第四阳极可以包括相互连接的第四阳极主体部和第四阳极连接部，第四阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第四阳极连接部的形状可以为条形状。
(8)形成像素定义层图案。在示例性实施方式中，形成像素定义层图案可以包括：在形成前述图案的基底上，涂覆像素定义薄膜，采用图案化工艺对像素定义薄膜进行图案化，形成像素定义层，每个子像素的像素定义层上设置有像素开口，像素开口内的像素定义薄膜被去掉，暴露出所在子像素的阳极。
在示例性实施方式中，像素开口在基底上的正投影与阳极过孔在基底上的正投影没有交叠。
在示例性实施方式中，至少一个子像素中，像素开口靠近阳极过孔一侧的边缘与阳极过孔靠近像素开口一侧的边缘之间的第二距离可以大于或等于3.0μm，第二距离可以是像素开口与阳极过孔之间的最小距离。例如，至少一个子像素中，像素开口与阳极过孔之间的第二距离可以约为7.88μm左右。由于阳极过孔为贯通平坦层的过孔，本公开通过将像素开口设置在阳极过孔设定距离之外，可以保证像素开口内阳极的平坦性，可以提高像素的平坦性，提高显示品质。
在示例性实施方式中，后续制备流程可以包括：先采用蒸镀或喷墨打印 工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，部分搭接过孔可以设置在远离第一中心线的子像素中，增加相邻搭接过孔之间的间距，减少相互干扰，保证显示画面不串扰，本公开在此不做限定。
在示例性实施方式中，本公开显示面板可以应用于具有像素驱动电路的其它显示装置中，如如量子点显示等，本公开在此不做限定。
本公开还提供一种显示装置，显示装置包括前述的显示面板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (28)

  1. 一种显示面板，包括：基底以及设置在基底上的驱动电路层，所述基底包括显示区域和非显示区域，所述驱动电路层包括：设置在所述显示区域的多个像素驱动电路以及设置在显示区域和非显示区域的多条第一扫描信号线，所述第一扫描信号线至少部分沿第一方向延伸，所述像素驱动电路与所述第一扫描信号线电连接，且相邻行像素驱动电路连接的第一扫描信号线电气隔离；
    所述驱动电路层还包括：位于非显示区域的第一信号线和与所述第一信号线对应的第二信号线，所述第一信号线，与第一扫描信号线电连接，被配置为向第一扫描信号线提供信号，所述第一信号线在基底上的正投影与对应的第二信号线在基底上的正投影至少部分交叠；
    相邻第一扫描信号线电连接的第一信号线的电阻大致相等和/或相邻第一扫描信号线电连接的第一信号线与对应的第二信号线之间的电容值大致相等。
  2. 根据权利要求1所述的显示面板，其中，所述驱动电路层还包括：设置在显示区域和非显示区域的多条第二扫描信号线、多条第三扫描信号线、多条发光信号线和多条参考信号线，所述像素驱动电路分别与第二扫描信号线、第三扫描信号线、发光信号线和参考信号线电连接，所述第二扫描信号线、所述第三扫描信号线、所述发光信号线和所述参考信号线至少部分沿第一方向延伸；
    第i行像素驱动电路，分别与第i条第一扫描信号线、第i条第二扫描信号线、第i条第三扫描信号线、第i条发光信号线和第i条参考信号线电连接，1≤i≤M，M为像素驱动电路的总行数；
    第i条第三扫描信号线、第i条参考信号线、第i条第二扫描信号线、第i条第一扫描信号线和第i条发光信号线沿第二方向依次排布，第i条第三扫描信号线位于第i条参考信号线靠近第i-1条发光信号线的一侧，第i条发光信号线位于第i条第一扫描信号线靠近第i+1条第三扫描信号线的一侧，所述第二方向与所述第一方向相交；
    所述第二信号线与第二扫描信号线、第三扫描信号线和发光信号线中的至少一种信号线电连接。
  3. 根据权利要求2所述的显示面板，其中，所述驱动电路层还包括：位于非显示区域的M条第一扫描输出线、M/2条第二扫描输出线、M/2条第三扫描输出线、M条参考输出线和M/2条发光输出线，所述第一扫描输出线、所述第二扫描输出线、所述第三扫描输出线、所述参考输出线和所述发光输出线至少部分沿第一方向延伸；
    第i条第一扫描输出线与第i条第一扫描信号线电连接，第i条参考输出线与第i条参考信号线电连接，第j条第二扫描输出线分别与第2j-1条第二扫描信号线和第2j条第二扫描信号线电连接，第j条第三扫描输出线分别与第2j-1条第三扫描信号线和第2j条第三扫描信号线电连接，第j条发光输出线分别与第2j-1条发光信号线和第2j条发光信号线电连接，1≤j≤M/2；
    第2j-1条参考输出线、第2j-1条第一扫描输出线、第j条第二扫描输出线、第j条第三扫描输出线、第2j条参考输出线、第j条发光输出线和第2j条第一扫描输出线沿第二方向依次排布。
  4. 根据权利要求3所述的显示面板，其中，所述驱动电路层还包括：位于非显示区域的参考供电线以及位于至少部分位于显示区域的数据信号线和第一电源线，所述参考供电线、所述数据信号线和所述第一电源线至少部分沿第二方向延伸；
    所述像素驱动电路分别与数据信号线和第一电源线电连接，所述参考供电线在基底上的正投影与所述参考输出线在基底上的正投影至少部分重叠，且与参考输出线电连接。
  5. 根据权利要求4所述的显示面板，其中，所述驱动电路层包括：依次叠设在基底上的第一导电层和第二导电层；
    所述第一导电层至少包括：第一扫描信号线、第二扫描信号线、第三扫描信号线、发光信号线和参考供电线；
    所述第二导电层至少包括：第一扫描输出线、第二扫描输出线、第三扫描输出线、参考输出线、发光输出线、数据信号线和第一电源线。
  6. 根据权利要求5所述的显示面板，其中，所述第一导电层和所述第二导电层的方阻大致相等。
  7. 根据权利要求6所述的显示面板，其中，所述第一导电层和所述第二导电层的制作材料和厚度相同。
  8. 根据权利要求6或7所述的显示面板，其中，相邻第一扫描信号线电连接的第一信号线靠近显示区域的边界与显示区域之间的距离大致相等，相邻第一扫描信号线电连接的第一信号线沿第二方向的平均长度大致相等。
  9. 根据权利要求8所述的显示面板，其中，相邻第一扫描信号线电连接的第一信号线与对应的第二信号线之间的交叠区域的面积大致相等。
  10. 根据权利要求5至9任一项所述的显示面板，其中，所述驱动电路层还包括：位于第一导电层的第一信号连接线，所述第一信号连接线沿第二方向延伸，且分别与第2j-1条第三扫描信号线和第2j条第三扫描信号线电连接；
    所述第一信号连接线在基底上的正投影与第2j-1条第一扫描输出线在基底上的正投影至少部分交叠；
    第j条第三扫描输出线在基底上的正投影与第2j条第三扫描信号线在基底上的正投影至少部分交叠，且与第2j条第三扫描信号线电连接。
  11. 根据权利要求10所述的显示面板，其中，所述驱动电路层还包括：位于第二导电层的第二信号连接线，所述第二信号连接线沿第一方向延伸；
    第2j条第二扫描信号线包括：相互连接的第一扫描连接部和第二扫描连接部，所述第一扫描连接部沿第一方向延伸，所述第二扫描连接部沿第二方向延伸，所述第一信号连接线位于所述第二扫描连接部靠近显示区域的一侧；
    所述第二扫描连接部在基底上的正投影与第2j-1条第一扫描输出线、第j条第二扫描输出线、第j条第三扫描输出线和第二信号连接线在基底上的正投影至少部分交叠，且分别与第j条第二扫描输出线和第二信号连接线电连接；
    所述第二信号连接线在基底上的正投影与第2j-1条第二扫描信号线和第一信号连接线在基底上的正投影至少部分交叠，且与第2j-1条第二扫描信号 线电连接。
  12. 根据权利要求11所述的显示面板，其中，所述驱动电路层还包括：位于第二导电层的第三信号连接线，所述第三信号连接线沿第一方向延伸；
    第2j条发光信号线包括：相互连接的第一发光连接部和第二发光连接部，所述第一发光连接部沿第一方向延伸，所述第二发光连接部沿第二方向延伸，所述第二发光连接部位于所述参考供电线和所述第二扫描连接部之间；
    所述第二发光连接部在基底上的正投影与第j条发光输出线、第j条第三扫描输出线、第2j条第一扫描输出线和第三信号连接线在基底上的正投影至少部分交叠，且分别与第j条发光输出线和第三信号连接线电连接；
    所述第三信号连接线在基底上的正投影与第2j-1条发光信号线、第一信号连接线和第二扫描连接部在基底上的正投影至少部分交叠，且与第2j-1条发光信号线电连接；
    所述第二发光连接部与第2j条第一扫描输出线交叠区域沿第一方向的长度大于所述第一发光连接部沿第二方向的长度。
  13. 根据权利要求12所述的显示面板，其中，第i条第一扫描信号线电连接的第一信号线包括：第i条第一扫描输出线；
    第2j-1条第一扫描信号线电连接的第一信号线对应的第二信号线包括第一信号连接线和第2j条第二扫描信号线，第2j条第一扫描信号线电连接的第一信号线对应的第二信号线包括第2j条发光信号线。
  14. 根据权利要求13所述的显示面板，其中，第2j-1条参考输出线在基底上的正投影与第一信号连接线和第2j-1条参考信号线在基底的正投影至少部分交叠，且与第2j-1条参考信号线电连接；第2j条参考输出线在基底上的正投影与第二扫描连接部、第二发光连接部和第2j条参考信号线在基底的正投影至少部分交叠，且与第2j条参考输出线电连接。
  15. 根据权利要求5至9任一项所述的显示面板，其中，所述驱动电路层还包括：位于第一导电层的第一信号连接线，所述第一信号连接线沿第二方向延伸，且分别与第2j-1条第三扫描信号线和第2j条第三扫描信号线电连接；
    所述第一信号连接线在基底上的正投影与第2j-1条第一扫描输出线和第2j条第一扫描输出线在基底上的正投影至少部分交叠；
    第j条第三扫描输出线在基底上的正投影与第2j条第三扫描信号线在基底上的正投影至少部分交叠，且与第2j条第三扫描信号线电连接。
  16. 根据权利要求15所述的显示面板，其中，所述驱动电路层还包括：位于第一导电层的第二信号连接线以及位于第二导电层的第三信号连接线和第四信号连接线，所述第二信号连接线沿第二方向延伸，所述第三信号连接线和所述第四信号连接线至少部分沿第一方向延伸，所述第二信号连接线位于第一信号连接线远离显示区域的一侧；
    所述第二信号连接线在基底上的正投影与第2j-1条第一扫描输出线、第2j条第一扫描输出线、第j条第二扫描输出线、第j条第三扫描输出线、第三信号连接线和第四信号连接线在基底上的正投影至少部分交叠，且分别与第j条第二扫描输出线、第三信号连接线和第四信号连接线电连接；
    所述第三信号连接线在基底上的正投影与第一信号连接线和第2j-1条第二扫描信号线在基底上的正投影至少部分交叠，且与第2j-1条第二扫描信号线电连接；
    所述第四信号连接线在基底上的正投影与第一信号连接线和第2j条第二扫描信号线在基底上的正投影至少部分交叠，且与第2j条第二扫描信号线电连接。
  17. 根据权利要求16所述的显示面板，其中，所述驱动电路层还包括：位于第一导电层的第五信号连接线以及位于第二导电层的第六信号连接线和第七信号连接线，所述第五信号连接线沿第二方向延伸，所述第六信号连接线和所述第七信号连接线至少部分沿第一方向延伸，所述第五信号连接线位于第二信号连接线远离显示区域的一侧；
    所述第五信号连接线在基底上的正投影与第2j-1条第一扫描输出线、第2j条第一扫描输出线、第j条第二扫描输出线、第j条第三扫描输出线、第j条发光输出线、第六信号连接线和第七信号连接线在基底上的正投影至少部分交叠，且分别与第j条发光输出线、第六信号连接线和第七信号连接线电连接；
    所述第六信号连接线在基底上的正投影与第一信号连接线、第二信号连接线和第2j-1条发光信号线在基底上的正投影至少部分交叠，且与第2j-1条发光信号线电连接；
    所述第七信号连接线在基底上的正投影与第一信号连接线、第二信号连接线和第2j条发光信号线在基底上的正投影至少部分交叠，且与第2j条发光信号线电连接。
  18. 根据权利要求17所述的显示面板，其中，第i条第一扫描信号线电连接的第一信号线包括：第i条第一扫描输出线；
    第2j-1条第一扫描信号线电连接的第一信号线对应的第二信号线包括第一信号连接线、第二信号连接线和第五信号连接线，第2j条第一扫描信号线电连接的第一信号线对应的第二信号线包括第一信号连接线、第二信号连接线和第五信号连接线。
  19. 根据权利要求18所述的显示面板，其中，第2j-1条参考输出线在基底上的正投影与第一信号连接线、第二信号连接线、第五信号连接线和第2j-1条参考信号线在基底的正投影至少部分交叠，且与第2j-1条参考信号线电连接；第2j条参考输出线在基底上的正投影与第一信号连接线、第二信号连接线、第五信号连接线和第2j条参考信号线在基底的正投影至少部分交叠，且与第2j条参考输出线电连接。
  20. 根据权利要求19所述的显示面板，其中，所述第三连接信号线、所述第四连接信号线、所述第六连接信号线、所述第七连接信号线和所述第2j-1条第一扫描输出线靠近显示区域的边界与显示区域之间的距离大致相等。
  21. 根据权利要求5至9任一项所述的显示面板，其中，所述驱动电路层还包括：位于第一导电层的第一信号连接线，所述第一信号连接线沿第二方向延伸，且分别与第2j-1条第三扫描信号线和第2j条第三扫描信号线电连接；
    所述第一信号连接线在基底上的正投影与第2j-1条第一扫描输出线、第j条第二扫描输出线和第j条第三扫描输出线在基底上的正投影至少部分交叠，且与第j条第三扫描输出线电连接。
  22. 根据权利要求21所述的显示面板，其中，第2j-1条第二扫描信号线包括：相互连接的第一扫描连接部和第二扫描连接部，所述第一扫描连接部沿第一方向延伸，所述第二扫描连接部沿第二方向延伸，第j条第二扫描输出线包括：相互连接的第一扫描输出连接部和第二扫描输出连接部，所述第一扫描输出连接部沿第一方向延伸，所述第二扫描输出连接部沿第二方向延伸，沿第二方向延伸的虚拟直线穿过所述第二扫描连接部和所述第二扫描输出连接部，第二扫描连接部位于第一信号连接线靠近显示区域的一侧；
    所述第二扫描连接部在基底上的正投影与第2j-1条第一扫描输出线和第一扫描输出连接部在基底上的正投影至少部分交叠，且与第一扫描输出连接部电连接；
    所述第一扫描输出连接部在基底上的正投影与第一信号连接线在基底上的正投影至少部分交叠；
    所述第二扫描输出连接部在基底上的正投影与第2j条第三扫描信号线和第2j条第二扫描信号线在基底上的正投影至少部分交叠，且与第2j条第二扫描信号线电连接。
  23. 根据权利要求22所述的显示面板，其中，所述驱动电路层还包括：位于第一导电层的第二信号连接线，所述第二信号连接线沿第一方向延伸；
    所述第二信号连接线在基底上的正投影与第2j条第一扫描输出线在基底上的正投影至少部分交叠，且分别与第2j条第一扫描输出线和第2j条第一扫描信号线电连接，所述第二信号连接线沿第二方向的长度大于所述第一扫描信号线沿第二方向的长度。
  24. 根据权利要求23所述的显示面板，其中，第j条发光输出线包括：相互连接的第一发光输出连接部和第二发光输出连接部，所述第一发光输出连接部沿第一方向延伸，所述第二发光输出连接部沿第二方向延伸；所述第二发光输出连接部位于所述第二扫描输出连接部靠近显示区域的一侧；
    所述第二发光输出连接部在基底上的正投影与第二信号连接线、第2j-1条发光信号线、第2j条发光信号线，第2j条第三扫描信号线和第2j条第二扫描信号线在基底上的正投影至少部分交叠，且分别与第2j-1条发光信号线和第2j条发光信号线电连接。
  25. 根据权利要求24所述的显示面板，其中，第2j-1条第一扫描信号线电连接的第一信号线包括第2j-1条第一扫描输出线、第2j条第一扫描信号线电连接的第一信号线包括第2j条第一扫描输出线和第二信号连接线；
    第2j-1条第一扫描信号线电连接的第一信号线对应的第二信号线包括第一信号连接线和第2j-1条第二扫描信号线，第2j条第一扫描信号线电连接的第一信号线对应的第二信号线包括第j条发光输出线。
  26. 根据权利要求25所述的显示面板，其中，第2j-1条参考输出线在基底上的正投影与第2j-1条参考信号线在基底的正投影至少部分交叠，且与第2j-1条参考信号线电连接；第2j条参考输出线在基底上的正投影与第2j条参考信号线在基底的正投影至少部分交叠，且与第2j条参考输出线电连接。
  27. 根据权利要求2至9任一项所述的显示面板，其中，所述驱动电路层还包括：遮挡层，所述遮挡层位于第一导电层靠近基底的一侧；
    所述遮挡层至少包括：参考信号线。
  28. 一种显示装置，包括：如权利要求1至27任一项所述的显示面板。
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