SN74LVC1G34 Single Buffer Gate: 1 Features 3 Description

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SN74LVC1G34
SCES519M – DECEMBER 2003 – REVISED APRIL 2016
SN74LVC1G34 Single Buffer Gate

1 Features 3 Description
1• Available in the Ultra Small 0.64-mm 2 This single buffer gate is designed for 1.65-V to 5.5-V
Package (DPW) with 0.5-mm Pitch VCC operation.
• Supports 5-V VCC Operation The SN74LVC1G34 device performs the Boolean
• Inputs Accept Voltages to 5.5 V function Y = A in positive logic.
• Provides Down Translation to VCC The CMOS device has high output drive while
maintaining low static power dissipation over a broad
• Max tpd of 3.5 ns at 3.3 V
VCC Operating range.
• Low Power Consumption, 1-μA Max ICC
The SN74LVC1G34 is available in a variety of
• ±24-mA Output Drive at 3.3 V
packages, including the ultra-small DPW package
• Ioff Supports Live Insertion, Partial Power Down with a body size of 0.8 mm × 0.8 mm.
Mode, and Back Drive Protection
• Latch-Up Performance Exceeds 100 mA Device Information(1)
Per JESD 78, Class II DEVICE NAME PACKAGE (PINS) BODY SIZE
• ESD Protection Exceeds JESD 22 SN74LVC1G34YFP DSBGA (4) 0.76 mm × 0.76 mm
– 2000-V Human-Body Model (A114-A) SN74LVC1G34YZP DSBGA (5) 1.38 mm × 0.88 mm

SN74LVC1G34YZV DSBGA (4) 0.88 mm × 0.88 mm
– 200-V Machine Model (A115-A)
SN74LVC1G34DPW X2SON (5) 0.80 mm × 0.80 mm
– 1000-V Charged-Device Model (C101)
SN74LVC1G34DBV SOT-23 (5) 2.90 mm × 2.80 mm
2 Applications SN74LVC1G34DCK SC70 (5) 2.00 mm × 2.10 mm

SN74LVC1G34DRL SOT (5) 1.60 mm × 1.60 mm
• AV Receiver
SN74LVC1G34DRY SON (6) 1.45 mm ×1.00 mm
• Audio Dock: Portable
SN74LVC1G34DSF SON(6) 1.00 mm × 1.00 mm
• Blu-ray Player and Home Theater
(1) For all available packages, see the orderable addendum at
• DVD Recorder and Player the end of the datasheet.
• Embedded PC
• MP3 Player/Recorder (Portable Audio)
• Personal Digital Assistant (PDA)
• Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
• Solid State Drive (SSD): Client and Enterprise
• TV: LCD/Digital and High-Definition (HDTV)
• Tablet: Enterprise
• Video Analytics: Server
• Wireless Headset, Keyboard, and Mouse
4 Simplified Schematic
A Y
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G34
SCES519M – DECEMBER 2003 – REVISED APRIL 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 9 Detailed Description ............................................ 11
2 Applications ........................................................... 1 9.1 Overview ................................................................. 11
3 Description ............................................................. 1 9.2 Functional Block Diagram ....................................... 11
4 Simplified Schematic............................................. 1 9.3 Feature Description................................................. 11
9.4 Device Functional Modes........................................ 11
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 4 10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
7 Specifications......................................................... 5
10.2 Typical Application ............................................... 12
7.1 Absolute Maximum Ratings ..................................... 5
7.2 ESD Ratings.............................................................. 5 11 Power Supply Recommendations ..................... 13
7.3 Recommended Operating Conditions ...................... 6 12 Layout................................................................... 13
7.4 Thermal Information .................................................. 6 12.1 Layout Guidelines ................................................. 13
7.5 Electrical Characteristics........................................... 7 12.2 Layout Example .................................................... 13
7.6 Switching Characteristics, CL = 15 pF ...................... 8 13 Device and Documentation Support ................. 14
7.7 Switching Characteristics, –40°C to 85°C................. 8 13.1 Community Resources.......................................... 14
7.8 Switching Characteristics, –40°C to 125°C............... 8 13.2 Trademarks ........................................................... 14
7.9 Operating Characteristics.......................................... 8 13.3 Electrostatic Discharge Caution ............................ 14
7.10 Typical Characteristics ............................................ 8 13.4 Glossary ................................................................ 14
8 Parameter Measurement Information .................. 9 14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
Changes from Revision L (April 2014) to Revision M Page
• Changed X2SON from 4 pin to 5 pin on Device Information table ........................................................................................ 1

• Moved Storage temperature range from ESD Ratings table to Absolute Maximum Ratings table........................................ 5
• Added Junction temperature to Absolute Maximum Ratings table ....................................................................................... 5
• Added package temperature specification for DSBGA package ........................................................................................... 6
Changes from Revision K (March 2014) to Revision L Page
• Added Device Information table. ............................................................................................................................................ 1

• Added Pin Functions table. .................................................................................................................................................... 4
• Updated Handling Ratings table. ........................................................................................................................................... 5
• Updated operating temperature range. .................................................................................................................................. 6
• Added Thermal Information table. ......................................................................................................................................... 6
• Added Typical Characteristics. .............................................................................................................................................. 8
• Added Detailed Description section. .................................................................................................................................... 11
• Added Application and Implementation section. ................................................................................................................. 12
Changes from Revision J (December 2013) to Revision K Page
• Added Applications. ................................................................................................................................................................ 1

• DPW Package. ...................................................................................................................................................................... 4
• Moved Tstg to Handling Ratings table. .................................................................................................................................... 5
2 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G34

SN74LVC1G34
www.ti.com SCES519M – DECEMBER 2003 – REVISED APRIL 2016
Changes from Revision I (June2011) to Revision J Page
• Updated document to new TI data sheet format. ................................................................................................................... 1

• Removed Ordering Information table. .................................................................................................................................... 1
Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

SN74LVC1G34
6 Pin Configuration and Functions

DBV PACKAGE DCK PACKAGE DRL PACKAGE DRY PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW) (TOP VIEW)
N.C. 1 5 VCC N.C. 1 5 VCC N.C. 1 6 VCC

N.C. 1 5 VCC
A 2 A 2 5 N.C.
A 2
GND 3 4 Y GND 3 4 Y
A 2
GND 3 4 Y
GND 3 4 Y
DPW PACKAGE YZV PACKAGE YFP PACKAGE DSF PACKAGE YZP PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW) (TOP VIEW) (TOP VIEW)
N.C. 1 5 VCC A VCC A VCC N.C. 1 VCC
GND 3 A1 A2 A1 A2 6 DNU A1 A2 VCC
A 2 4 Y GND B1 B2 Y A 2 5 N.C.
GND B1 B2 Y A B1
GND 3 4 Y
GND C1 C2 Y
See mechanical drawings for dimensions.
N.C. – No internal connection
DNU – Do not use
Pin Functions
PIN
DRL, DESCRIPTION
NAME DPW DRY, DSF YZP YFP, YZV
DCK, DBV
NC 1 1 1, 5 A1 – Not connected
A 2 2 2 B1 A1 Input
GND 3 3 3 C1 B1 Ground
Y 4 4 4 C2 B2 Output
VCC 5 5 6 A2 A2 Power pin

SN74LVC1G34
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VI Input voltage range –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature range -65 150 °C
TJ Max Junction temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
7.2 ESD Ratings

MIN MAX UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
±2
pins (1)
V(ESD) Electrostatic discharge kV
Charged device model (CDM), per JEDEC specification
±1
JESD22-C101, all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

SN74LVC1G34
7.3 Recommended Operating Conditions (1)

MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 10
TA Operating free-air temperature DSBGA package –40 85 °C
All other packages -40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information

SN74LVC1G34
THERMAL METRIC (1) DBV DCK DRL DRY YZP DPW UNIT
5 PINS 5 PINS 5 PINS 6 PINS 5 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 229 278 243 439 130 340
RθJC(top) Junction-to-case (top) thermal resistance 164 93 78 277 54 215
RθJB Junction-to-board thermal resistance 62 65 78 271 51 294
°C/W
ψJT Junction-to-top characterization parameter 44 2 10 84 1 41
ψJB Junction-to-board characterization parameter 62 64 77 271 50 294
RθJC(bot) Junction-to-case (bottom) thermal resistance – – – – – 250
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

SN74LVC1G34
7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP (1) MAX MIN TYP (1) MAX
IOH = –100 μA 1.65 V to 5.5 V VCC – 0.1 VCC – 0.1
IOH = –4 mA 1.65 V 1.2 1.2
IOH = –8 mA 2.3 V 1.9 1.9
VOH V
IOH = –16 mA 2.4 2.4
3V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
VOL V
IOL = 16 mA 0.4 0.4
3V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
II VI = 5.5 V or GND 0 to 5.5 V ±1 ±2 μA
Ioff VI or VO = 5.5 V 0 ±10 ±10 μA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 1 10 μA
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 500 μA
Other inputs at VCC or GND
Ci VI = VCC or GND 3.3 V 3.5 pF
(1) All typical values are at VCC = 3.3 V, TA = 25°C.

SN74LVC1G34
7.6 Switching Characteristics, CL = 15 pF

over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3)
–40°C to 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 2 9.9 1.5 6 1 3.5 1 2.9 ns
7.7 Switching Characteristics, –40°C to 85°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
–40°C to 85°C
PARAMETER UNIT
tpd A Y 3.2 8.6 1.5 4.4 1.5 4.1 1 3.2 ns
7.8 Switching Characteristics, –40°C to 125°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
–40°C to 125°C
PARAMETER UNIT
tpd A Y 3.2 9.5 1.5 5.1 1.5 4.7 1 3.9 ns
7.9 Operating Characteristics

TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 16 16 16 18 pF
7.10 Typical Characteristics
2.5 5
TPD TPD
2 4
1.5 3
TPD - ns
TPD - ns
1 2
0.5 1
0 0
-100 -50 0 50 100 150 0 1 2 3 4 5 6
Temperature - °C D001
Vcc - V D002
Figure 1. TPD Across Temperature at 3.3V Vcc Figure 2. TPD Across Vcc at 25°C

SN74LVC1G34
8 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND
LOAD CIRCUIT
INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 15 pF 1 MΩ 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.3 V
VI
Timing Input VM
0V
tw
VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES
VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH − V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms

SN74LVC1G34
Parameter Measurement Information (continued)

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND
LOAD CIRCUIT
INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 50 pF 500 Ω 0.3 V
VI
Timing Input VM
0V
tw
VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
PULSE DURATION SETUP AND HOLD TIMES
VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH − V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms

SN74LVC1G34
9 Detailed Description
9.1 Overview
The SN74LVC1G34 device contains one buffer gate device and performs the Boolean function Y = A. This
device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves
significant board space over other package options while still retaining the traditional manufacturing friendly lead
pitch of 0.5 mm.
9.2 Functional Block Diagram
A Y
9.3 Feature Description

• Wide operating voltage range.
– Operates from 1.65 V to 5.5 V.
• Allows down voltage translation.
• Inputs accept voltages to 5.5 V.
• Ioff feature allows voltages on the inputs and outputs when VCC is 0 V.
9.4 Device Functional Modes
Function Table
INPUT OUTPUT
A Y
H H
L L

SN74LVC1G34
10 Application and Implementation

10.1 Application Information
The SN74LVC1G34 is a high drive CMOS device that can be used as a buffer with a high output drive, such as
an LED application. It can produce 24 mA of drive current at 3.3 V making it ideal for driving multiple outputs and
good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowing it to translate down to
VCC.
10.2 Typical Application

Basic LED Driver
Buffer Function
VCC VCC
uC or Logic uC or Logic uC or Logic

LVC1G34 LVC1G34
10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure

1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Max Ratings table.
– Outputs should not be pulled above VCC.

SN74LVC1G34
Typical Application (continued)

10.2.3 Application Curves
10
Icc 1.8V
9 Icc 2.5V
8 Icc 3.3V
Icc 5V
7
6
Icc - mA 5
4
3
2
1
0
0 20 40 60 80
Frequency - MHz D003
Figure 5. Icc vs Frequency
11 Power Supply Recommendations

The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or is more
convenient.
12.2 Layout Example
VCC Input
Unused Input Output Unused Input Output
Input

SN74LVC1G34
13 Device and Documentation Support
13.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SN74LVC1G34DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C345, C34F, C34J,
C34K, C34R)
(C34H, C34P, C34S)
SN74LVC1G34DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C345
C34S
SN74LVC1G34DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C345
C34S
SN74LVC1G34DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C345, C34J, C34K,
C34R)
(C34H, C34S)
SN74LVC1G34DBVTE4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C345
C34S
SN74LVC1G34DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C345
C34S
SN74LVC1G34DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C95, C9F, C9J, C9
K, C9R)
(C9H, C9P, C9S)
SN74LVC1G34DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C95
C9S
SN74LVC1G34DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C95
C9S
SN74LVC1G34DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C95, C9J, C9K, C9
R)
(C9H, C9S)
SN74LVC1G34DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C95
C9S
SN74LVC1G34DPWR ACTIVE X2SON DPW 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 P4
SN74LVC1G34DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (C97, C9R)
SN74LVC1G34DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 C9
SN74LVC1G34DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 C9
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SN74LVC1G34YFPR ACTIVE DSBGA YFP 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 C9
N
SN74LVC1G34YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 C9N
SN74LVC1G34YZVR ACTIVE DSBGA YZV 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 C9
N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G34DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G34DBVRG4 SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G34DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G34DBVTG4 SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G34DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G34DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G34DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LVC1G34DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G34DPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q3
SN74LVC1G34DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G34DRLR SOT-5X3 DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
SN74LVC1G34DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC1G34DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1G34YFPR DSBGA YFP 4 3000 178.0 9.2 0.89 0.89 0.58 4.0 8.0 Q1
SN74LVC1G34YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
SN74LVC1G34YZVR DSBGA YZV 4 3000 178.0 9.2 1.0 1.0 0.63 4.0 8.0 Q1
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G34DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G34DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G34DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G34DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G34DCKR SC70 DCK 5 3000 180.0 180.0 18.0
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G34DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G34DCKT SC70 DCK 5 250 202.0 201.0 28.0
SN74LVC1G34DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G34DPWR X2SON DPW 5 3000 205.0 200.0 33.0
SN74LVC1G34DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
SN74LVC1G34DRLR SOT-5X3 DRL 5 4000 184.0 184.0 19.0
SN74LVC1G34DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G34DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74LVC1G34YFPR DSBGA YFP 4 3000 220.0 220.0 35.0
SN74LVC1G34YZPR DSBGA YZP 5 3000 220.0 220.0 35.0
SN74LVC1G34YZVR DSBGA YZV 4 3000 220.0 220.0 35.0
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA
1 5
2X 0.95
3.05
2.75
1.9 1.9
2
4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A SCALE 12.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
0.85 A
B
0.75
PIN 1 INDEX AREA 0.85

0.75
0.4 MAX C
SEATING PLANE
NOTE 3
(0.1)
(0.25) 0.05
4X (0.05) 0.00
0.25 0.1
2
4
NOTE 3
2X 3
2X (0.26)
0.48
5
1
0.27
0.27 4X
0.17
0.17
0.1 C A B
(0.06)
0.05 C
0.32
3X
0.23
4223102/B 09/2017
NOTES:
per ASME Y14.5M.
3. The size and shape of this feature may vary.
www.ti.com
DPW0005A X2SON - 0.4 mm max height
(0.78)
SYMM ( 0.1)
4X (0.42) VIA 0.05 MIN
ALL AROUND
1 TYP
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2 4
(R0.05) TYP
SOLDER MASK
4X (0.06) OPENING, TYP
( 0.25)
(0.21) TYP METAL UNDER
EXPOSED METAL SOLDER MASK
CLEARANCE TYP

SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
DPW0005A X2SON - 0.4 mm max height
4X (0.42) 4X (0.06)
5
4X (0.22) 1
( 0.24)
4X (0.26)
SYMM
(0.21) (0.48)
TYP
SOLDER MASK
EDGE 3
2
4
(R0.05) TYP
SYMM
(0.78)

EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
YZP0005 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
B E A
BALL A1
CORNER
C
0.5 MAX
SEATING PLANE
0.19
0.15 0.05 C
BALL TYP
0.5 TYP
SYMM
1
TYP
B D: Max = 1.418 mm, Min =1.357 mm
0.5
TYP E: Max = 0.918 mm, Min =0.857 mm
A
0.25
5X 1 2
0.21
0.015 C A B
SYMM
4219492/A 05/2017
NOTES:
per ASME Y14.5M.
www.ti.com
YZP0005 DSBGA - 0.5 mm max height
(0.5) TYP
5X ( 0.23)
1 2
(0.5) TYP
SYMM
B
SYMM

SCALE:40X
SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23)

OPENING SOLDER MASK
OPENING
( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS

NOT TO SCALE
4219492/A 05/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
YZP0005 DSBGA - 0.5 mm max height
(0.5) TYP
5X ( 0.25)
(R0.05) TYP
1 2
(0.5)
TYP
B SYMM
METAL SYMM
TYP

SCALE:40X
4219492/A 05/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
D: Max = 0.918 mm, Min =0.858 mm
E: Max = 0.918 mm, Min =0.858 mm

PACKAGE OUTLINE
YFP0004 SCALE 10.000
DSBGA - 0.5 mm max height
B E A
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.13 BALL TYP
0.05 C
0.4
TYP
B D: Max = 0.79 mm, Min = 0.73 mm

SYMM
0.4 E: Max = 0.79 mm, Min = 0.73 mm
TYP
A
0.25
4X
0.21 1 2
0.015 C A B
SYMM
4223507/A 01/2017
NOTES:
per ASME Y14.5M.
www.ti.com
YFP0004 DSBGA - 0.5 mm max height
(0.4) TYP
4X ( 0.23)
1 2
SYMM
(0.4) TYP
SYMM

EXPOSED METAL SHOWN
SCALE:50X
( 0.23) 0.05 MAX 0.05 MIN METAL UNDER

METAL SOLDER MASK
EXPOSED ( 0.23)
SOLDER MASK METAL EXPOSED
OPENING METAL SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS

NOT TO SCALE
4223507/A 01/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
YFP0004 DSBGA - 0.5 mm max height
(0.4) TYP
4X ( 0.25) (R0.05) TYP
1 2
SYMM
(0.4) TYP
METAL
TYP SYMM

SCALE:50X
4223507/A 01/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DRL0005A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1 A
ID AREA
1
5
2X 0.5
1.7
1.5
2X 1 NOTE 3
4
3
1.3 0.3 0.05

B 5X TYP
1.1 0.1 0.00
0.6 MAX
C
SEATING PLANE
0.18
5X 0.05 C
0.08
SYMM
SYMM
0.27
5X
0.15
0.1 C A B
0.4
5X 0.05
0.2
4220753/B 12/2020
NOTES:
per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1
www.ti.com
DRL0005A SOT - 0.6 mm max height
5X (0.67) SYMM
1
5
5X (0.3)
SYMM
(1)
2X (0.5)
3 4
(R0.05) TYP
(1.48)

SCALE:30X
0.05 MAX 0.05 MIN

AROUND AROUND
SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
DEFINED DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4220753/B 12/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
DRL0005A SOT - 0.6 mm max height
5X (0.67)
SYMM
1
5
5X (0.3)
SYMM
(1)
2X (0.5)
3 4
(R0.05) TYP
(1.48)

SCALE:30X
4220753/B 12/2020
NOTES: (continued)
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DSF0006A SCALE 10.000
X2SON - 0.4 mm max height
1.05
B A
0.95
PIN 1 INDEX AREA

1.05
0.95
0.4 MAX C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM 0.05
0.00
3
4
2X SYMM
0.7
4X
0.35
6
1
0.22
6X
0.12
(0.1)
PIN 1 ID 0.45 0.07 C B A
6X
0.35 0.05 C
4220597/A 06/2017
NOTES:
per ASME Y14.5M.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
DSF0006A X2SON - 0.4 mm max height
6X (0.6)
(R0.05) TYP
1
6X (0.17) 6
SYMM
4X (0.35)
4
3
SYMM
(0.8)

EXPOSED METAL SHOWN
SCALE:40X
0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL


DEFINED DEFINED
SOLDER MASK DETAILS
4220597/A 06/2017
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
DSF0006A X2SON - 0.4 mm max height
6X (0.6)
(R0.05) TYP
1
6X (0.17) 6
SYMM
4X (0.35)
4
3
SYMM
(0.8)

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:40X
4220597/A 06/2017
www.ti.com
GENERIC PACKAGE VIEW
DRY 6 USON - 0.6 mm max height
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A SCALE 8.500
USON - 0.6 mm max height
1.05 A
B
0.95
PIN 1 INDEX AREA

1.5
1.4
0.6 MAX C
SEATING PLANE
0.05
0.00 0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.4 0.15
0.3 0.1 C A B
0.05 C
PIN 1 ID
(OPTIONAL) 0.35
5X
0.25
4222894/A 01/2018
NOTES:
per ASME Y14.5M.
www.ti.com
DRY0006A USON - 0.6 mm max height
SYMM
(0.35)
5X (0.3)
1 6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)

1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
EXPOSED
EXPOSED
METAL
METAL

NON SOLDER MASK
DEFINED SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
DRY0006A USON - 0.6 mm max height
SYMM
(0.35) 5X (0.3)
1 6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP (0.6)

BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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SN74LVC1G34 Single Buffer Gate: 1 Features 3 Description

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SN74LVC1G34 Single Buffer Gate

– 2000-V Human-Body Model (A114-A) SN74LVC1G34YZP DSBGA (5) 1.38 mm × 0.88 mm

2 Applications SN74LVC1G34DCK SC70 (5) 2.00 mm × 2.10 mm

• Changed X2SON from 4 pin to 5 pin on Device Information table ........................................................................................ 1

Changes from Revision K (March 2014) to Revision L Page

• Added Device Information table. ............................................................................................................................................ 1

Changes from Revision J (December 2013) to Revision K Page

• Added Applications. ................................................................................................................................................................ 1

2 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G34

Changes from Revision I (June2011) to Revision J Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

6 Pin Configuration and Functions

N.C. 1 5 VCC N.C. 1 5 VCC N.C. 1 6 VCC

4 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G34

7.2 ESD Ratings

Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback 5

7.3 Recommended Operating Conditions (1)

7.4 Thermal Information

6 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G34

7.5 Electrical Characteristics

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback 7

7.6 Switching Characteristics, CL = 15 pF

7.7 Switching Characteristics, –40°C to 85°C

7.8 Switching Characteristics, –40°C to 125°C

7.9 Operating Characteristics

7.10 Typical Characteristics

8 Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G34

8 Parameter Measurement Information

NOTES: A. CL includes probe and jig capacitance.

Figure 3. Load Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

NOTES: A. CL includes probe and jig capacitance.

Figure 4. Load Circuit and Voltage Waveforms

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9.2 Functional Block Diagram

9.3 Feature Description

9.4 Device Functional Modes

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10 Application and Implementation

10.2 Typical Application

uC or Logic uC or Logic uC or Logic

10.2.1 Design Requirements

10.2.2 Detailed Design Procedure

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Typical Application (continued)

Figure 5. Icc vs Frequency