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SN74LVC1G86
SCES222Q – APRIL 1999 – REVISED JUNE 2017

SN74LVC1G86 Single 2-Input Exclusive-OR Gate

1 Features 3 Description
1• ESD Protection Exceeds JESD 22 The SN74LVC1G86 device performs the Boolean
function Y = AB + AB in positive logic. This single 2-
– 2000-V Human-Body Model (A114-A) input exclusive-OR gate is designed for 1.65-V to 5.5-
– 1000-V Charged-Device Model (C101) V VCC operation.
• Qualified from –40°C to +125°C If the input is low, the other input is reproduced in
• Supports 5-V VCC Operation true form at the output. If the input is high, the signal
• Inputs Are Over Voltage Tolerant up to 5.5 V on the other input is reproduced inverted at the
output. This device has low power consumption with
• Supports Down Translation to VCC
maximum tpd of 4 ns at 3.3 V and 15-pF capacitive
• Maximum tpd of 4 ns at 3.3 V and 15-pF load load. The maximum output drive is ±32-mA at 4.5 V
• Low Power Consumption, 10-µA Maximum ICC At and ±24-mA at 3.3 V.
85°C This device is fully specified for partial-power-down
• ±24-mA Output Drive at 3.3 V applications using Ioff. The Ioff circuitry disables the
• Ioff Supports Partial-Power-Down Mode, and Back- outputs, preventing damaging current back flow
Drive Protection through the device when it is powered down.
• Available in the Texas Instruments Device Information(1)
NanoFree™ Package PART NUMBER PACKAGE BODY SIZE (NOM)
• Latch-Up Performance Exceeds 100 mA Per SN74LVC1G86DBV SOT-23 (5) 2.90 mm × 1.60 mm
JESD 78, Class II SN74LVC1G86DCK SC70 (5) 2.00 mm × 1.25 mm
SN74LVC1G86DRL SOT (5) 1.60 mm × 1.20 mm
2 Applications SN74LVC1G86YZP DSBGA (5) 1.44 mm × 0.94 mm
• Wireless Headsets (1) For all available packages, see the orderable addendum at
• Motor Drives and Controls the end of the data sheet.

• TVs
• Set-Top Boxes
• Audio
Functional Block Diagram
EXCLUSIVE OR
=1

Copyright © 2017, Texas Instruments Incorporated

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.
These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be
shown at any two ports.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G86
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Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 8
2 Applications ........................................................... 1 8.3 Feature Description................................................... 8
3 Description ............................................................. 1 8.4 Function Table .......................................................... 9
4 Revision History..................................................... 2 9 Application and Implementation ........................ 10
9.1 Application Information............................................ 10
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 10
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Power Supply Recommendations ..................... 11
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 12
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 12
6.4 Thermal Information .................................................. 5 11.2 Layout Example .................................................... 12
6.5 Electrical Characteristics........................................... 5 12 Device and Documentation Support ................. 13
6.6 Switching Characteristics, CL = 15 pF ...................... 6 12.1 Receiving Notification of Documentation Updates 13
6.7 Switching Characteristics, CL = 30 pF or 50 pF........ 6 12.2 Community Resources.......................................... 13
6.8 Operating Characteristics.......................................... 6 12.3 Trademarks ........................................................... 13
6.9 Typical Characteristics .............................................. 6 12.4 Electrostatic Discharge Caution ............................ 13
7 Parameter Measurement Information .................. 7 12.5 Glossary ................................................................ 13
8 Detailed Description .............................................. 8 13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................... 8
Information ........................................................... 13

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision P (September 2015) to Revision Q Page

• Changed YZP (DSBGA) package pinout diagram and added DSBGA column ..................................................................... 3
• Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down
(Ioff), and Over-voltage Tolerant Inputs sections..................................................................................................................... 8

Changes from Revision O (December 2013) to Revision P Page

• Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

Changes from Revision N (January 2007) to Revision O Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

• Removed Ordering Information table. .................................................................................................................................... 1
• Updated Ioff in Features. ......................................................................................................................................................... 1
• Updated operating temperature range. .................................................................................................................................. 4

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5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23 DCK Package
Top View 5-Pin SC70
Top View

A 1 5 VCC A 1 5 VCC

B 2
B 2
GND 3 4 Y

GND 3 4 Y
YZP Package
5-Pin DSBGA
DRL Package Bottom View
5-Pin SOT 1 2
Top View
C GND Y
A 1 5 VCC
B 2
B B

GND 3 4 Y
A A VCC

Not to scale

Pin Functions (1)

PIN
I/O DESCRIPTION
NAME DBV, DRL, DCK DSBGA
A 1 A1 I Input A
B 2 B1 I Input B
GND 3 C1 — Ground
VCC 5 A2 — Positive Supply
Y 4 C2 O Output Y

(1) See mechanical drawings for dimensions.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
(2)
VI Input voltage –0.5 6.5 V
VO Voltage applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

VALUE UNIT
(1)
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 2000
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
YZP package –40 85
TA Operating free-air temperature °C
DCK, DBV, and DRL packages –40 125

6.4 Thermal Information

SN74LVC1G86
(1)
THERMAL METRIC DBV (SOT-23) DCK (SC70) YZP (DSBGA) UNIT
5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 206 252 132 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
VOH V
IOH = –16 mA 2.4
3V
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100 µA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
VOL V
IOL = 16 mA 0.4
3V
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
II A or B input VI = 5.5 V or GND 0 to 5.5 V ±5 µA
Ioff VI or VO = 5.5 V 0 ±10 µA
–40°C to 85°C 10
ICC VI = VCC or GND, IO = 0 1.65 V to 5.5 V µA
–40°C to 125°C 15
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 µA
Other inputs at VCC or GND
Ci VI = VCC or GND 3.3 V 6 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

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6.6 Switching Characteristics, CL = 15 pF

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETE FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
TEST CONDITIONS UNIT
R (INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y TA = –40°C to +85°C 2.1 9.1 1 4.5 0.6 4 0.8 3.3 ns

6.7 Switching Characteristics, CL = 30 pF or 50 pF

over recommended operating free-air temperature range (unless otherwise noted)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
–40°C to +85°C temperature
3.5 9.9 1.8 5.5 1.3 5 1 4
range, see Figure 2
tpd A or B Y ns
–40°C to +125°C temperature
3.5 12 1.8 7 1.3 6 1 5
range, see Figure 2

6.8 Operating Characteristics

TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 22 22 22 24 pF

6.9 Typical Characteristics

VOH(V) 5

4.5

3.5

2.5
VCC =4.5 V
VIH =3.1 V
VIL =1.35 V
2

1.5
85o C

1
25o C
0.5
-40o C
0

-0.5

-1
0 20 40 60 80 100 120 140 160 180 200
IOH(mA)

Figure 1. Voh vs Ioh at 4.5 V

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7 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 15 pF 1 MΩ 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input
exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
A common application is as a true and complement element. If the input is low, the other input is reproduced in
true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

EXCLUSIVE OR
=1

Copyright © 2017, Texas Instruments Incorporated

These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be
shown at any two ports.

8.3 Feature Description

8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must
be followed at all times.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Recommended Operating Conditions, and the maximum input leakage current, given
in the Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If tolerance to a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS
input.

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Feature Description (continued)

8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.

CAUTION
Avoid any voltage below or above the input or output voltage specified in the Absolute
Maximum Ratings. In this event, the current must be limited to the maximum input or
output clamp current value indicated in the Absolute Maximum Ratings to avoid
damage to the device.

VCC
Device

Input Logic Output

-IIK -IOK

GND

Figure 3. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.4 Partial Power Down (Ioff)

The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.

8.3.5 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.

8.4 Function Table

Table 1 lists the functional modes of the SN74LVC1G86 device.

Table 1. Function Table

INPUTS OUTPUT
A B Y
L L L
L H H
H L H
H H L

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC1G86 device can accept input voltages up to 5.5 V at any valid VCC which makes the device
suitable for down translation. This feature of the SN74LVC1G86 makes it ideal for various bus interface
applications.

9.2 Typical Application

5-V accessory 3.3-V or 5-V regulated

0.1 µF

5-V µC or
System System
Logic Logic

Figure 4. Typical Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads,
so routing and load conditions should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed 32 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.

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Typical Application (continued)

9.2.3 Application Curve

100

90

80

70

60

VIH = 4.5V
ICC (mA)

50 VIL= 0V
VCC = 5.5V
40
Temp =25o C

Low->High
30

High->Low
20

10

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VIN (V)

Figure 5. ICC vs. VIN

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µF is recommended. If there are multiple VCC pins, 0.01 µF or 0.022 µF is recommended for each power pin.
It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1-µF and 1-µF are
commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best
results.

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11 Layout

11.1 Layout Guidelines

Even low data rate digital signals can have high frequency signal components due to fast edge rates. When a
PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the
change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 6 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.

11.2 Layout Example

WORST BETTER BEST
2W

1W min.

W
Figure 6. Trace Example

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC1G86DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C865, C86F, C86J, Samples
C86K, C86R)
SN74LVC1G86DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C86F Samples

SN74LVC1G86DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C86F Samples

SN74LVC1G86DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C865, C86F, C86J, Samples
C86K, C86R)
SN74LVC1G86DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CH5, CHF, CHJ, CH Samples
K, CHR)
SN74LVC1G86DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CH5 Samples

SN74LVC1G86DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CH5 Samples

SN74LVC1G86DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CH5, CHF, CHJ, CH Samples
K, CHR)
SN74LVC1G86DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CH5 Samples

SN74LVC1G86DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CH7, CHR) Samples

SN74LVC1G86YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (CH7, CHN) Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC1G86 :

• Automotive : SN74LVC1G86-Q1
• Enhanced Product : SN74LVC1G86-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G86DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G86DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G86DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G86DCKR SC70 DCK 5 3000 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3
SN74LVC1G86DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G86DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G86DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G86DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LVC1G86DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G86DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G86YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G86DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
SN74LVC1G86DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G86DBVT SOT-23 DBV 5 250 210.0 185.0 35.0
SN74LVC1G86DCKR SC70 DCK 5 3000 210.0 185.0 35.0
SN74LVC1G86DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G86DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G86DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G86DCKT SC70 DCK 5 250 202.0 201.0 28.0
SN74LVC1G86DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G86DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
SN74LVC1G86YZPR DSBGA YZP 5 3000 220.0 220.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
YZP0005 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

C
0.5 MAX

SEATING PLANE
0.19
0.15 0.05 C
BALL TYP

0.5 TYP

SYMM
1
TYP
B D: Max = 1.44 mm, Min = 1.38 mm
0.5
TYP E: Max = 0.94 mm, Min = 0.88 mm
A

0.25
5X 1 2
0.21
0.015 C A B
SYMM

4219492/A 05/2017
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
5X ( 0.23)
1 2

(0.5) TYP

SYMM
B

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23)

OPENING SOLDER MASK
OPENING

( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219492/A 05/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

5X ( 0.25)
(R0.05) TYP
1 2

(0.5)
TYP

B SYMM

METAL SYMM
TYP

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4219492/A 05/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214839/J 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/J 02/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/J 02/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.15
0.1
0.1 C A B (0.9) TYP
0.0
NOTE 5

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/D 07/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.

www.ti.com
 EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/D 07/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/D 07/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DRL0005A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
5

2X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3 0.3 0.05

B 5X TYP
1.1 0.1 0.00

0.6 MAX
C

SEATING PLANE
0.18
5X 0.05 C
0.08
SYMM

SYMM

0.27
5X
0.15
0.1 C A B
0.4
5X 0.05
0.2
4220753/B 12/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67) SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4220753/B 12/2020

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67)
SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4220753/B 12/2020

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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