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SN74LVC1G17
SCES351V – JULY 2001 – REVISED APRIL 2014

SN74LVC1G17 Single Schmitt-Trigger Buffer

1 Features 3 Description
1• Available in Ultra Small 0.64-mm 2 This single Schmitt-trigger buffer is designed for
Package (DPW) With 0.5-mm Pitch 1.65-V to 5.5-V VCC operation.
• Supports 5-V VCC Operation The SN74LVC1G17 device contains one buffer and
• Inputs Accept Voltages to 5.5 V performs the Boolean function Y = A.
• Max tpd of 4.6 ns at 3.3 V The CMOS device has high output drive while
maintaining low static power dissipation over a broad
• Low Power Consumption, 10-μA Max ICC
Vcc operating range.
• ±24-mA Output Drive at 3.3 V
The SN74LVC1G17 is available in a variety of
• Ioff Supports Live Insertion, Partial-Power-Down
packages, including the ultra-small DPW package
Mode, and Back-Drive Protection with a body size of 0.8 mm × 0.8mm.
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II Device Information(1)
• ESD Protection Exceeds JESD 22 DEVICE NAME PACKAGE BODY SIZE
– 2000-V Human-Body Model (A114-A) SOT-23 (5) 2.9mm × 1.6mm

– 200-V Machine Model (A115-A) SC70 (5) 2.0mm × 1.25mm

SN74LVC1G17 X2SON (4) 0.8mm × 0.8mm
– 1000-V Charged-Device Model (C101)
SON (6) 1.45mm × 1.0mm
2 Applications SON (6) 1.0mm × 1.0mm

• AV Receiver (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• Audio Dock: Portable
• Blu-ray Player and Home Theater
• MP3 Player/Recorder
• Personal Digital Assistant (PDA)
• Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
• Solid State Drive (SSD): Client and Enterprise
• TV: LCD/Digital and High-Definition (HDTV)
• Tablet: Enterprise
• Video Analytics: Server
• Wireless Headset, Keyboard, and Mouse

4 Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 9 Detailed Description ............................................ 10
2 Applications ........................................................... 1 9.1 Overview ................................................................. 10
3 Description ............................................................. 1 9.2 Functional Block Diagram ....................................... 10
4 Simplified Schematic............................................. 1 9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 10
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3 10 Applications and Implementation...................... 11
10.1 Application Information.......................................... 11
7 Specifications......................................................... 4
10.2 Typical Application ............................................... 11
7.1 Absolute Maximum Ratings ..................................... 4
7.2 Handling Ratings....................................................... 4 11 Power Supply Recommendations ..................... 12
7.3 Recommended Operating Conditions ...................... 5 12 Layout................................................................... 12
7.4 Thermal Information .................................................. 5 12.1 Layout Guidelines ................................................. 12
7.5 Electrical Characteristics—DC Limit Changes.......... 6 12.2 Layout Example .................................................... 12
7.6 Switching Characteristics, CL = 15 pF ...................... 7 13 Device and Documentation Support ................. 13
7.7 Switching Characteristics AC Limit, –40°C TO 85°C 7 13.1 Trademarks ........................................................... 13
7.8 Switching Characteristics AC Limit, –40°C TO 13.2 Electrostatic Discharge Caution ............................ 13
125°C ......................................................................... 7 13.3 Glossary ................................................................ 13
7.9 Operating Characteristics.......................................... 7 14 Mechanical, Packaging, and Orderable
7.10 Typical Characteristics ............................................ 7 Information ........................................................... 13
8 Parameter Measurement Information .................. 8

5 Revision History
Changes from Revision U (February 2014) to Revision V Page

• Added Pin Functions table. .................................................................................................................................................... 3

• Added Handling Ratings table. .............................................................................................................................................. 4
• Added Thermal Information table. ......................................................................................................................................... 5
• Added Typical Characteristics. .............................................................................................................................................. 7
• Added Detailed Description section. .................................................................................................................................... 10
• Added Application and Implementation section. ................................................................................................................. 11
• Added Power Supply Recommendations section. .............................................................................................................. 12
• Added Layout section. ......................................................................................................................................................... 12

Changes from Revision T (November 2012) to Revision U Page

• Added Applications. ................................................................................................................................................................ 1

• Moved Tstg to Handling Ratings table. .................................................................................................................................... 4
• Changed MAX operating free-air temperature from 85°C to 125°C....................................................................................... 5
• Added –40°C to 125°C to Electrical Characteristics table...................................................................................................... 6
• Added Switching Characteristics table for –40°C to 125°C temperature range. .................................................................... 7

Changes from Revision S (June 2011) to Revision T Page

• Removed Ordering Information table. .................................................................................................................................... 3

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6 Pin Configuration and Functions

DBV PACKAGE DCK PACKAGE DRL PACKAGE DRY PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW) (TOP VIEW)

N.C. 1 5 VCC N.C. 1 5 VCC N.C. 1 6 VCC

N.C. 1 5 VCC
A 2 A 2 5 N.C.
A 2
A 2 GND 3 4 Y GND 3 4 Y
GND 3 4 Y

GND 3 4 Y
YZP PACKAGE YZV PACKAGE DSF PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW)
DPW PACKAGE
(TOP VIEW) N.C. 1 6 VCC
DNU A1 A2 VCC A A1 A2 VCC
N.C. 1 5 VCC A 2 5 N.C.
GND 3 A B1 B2
GND B1 B2 Y GND 3 4 Y
A 2 4 Y
GND C1 C2 Y
N.C. – No internal connection
See mechanical drawings for dimensions.
DNU – Do not use

Pin Functions
PIN
DBV, DCK, DESCRIPTION
NAME DRY, DSF YZP YZV
DRL, DPW
NC 1 1, 5 A1, B2 – Not connected
A 2 2 B1 A1 Input
GND 3 3 C1 B1 Ground
Y 4 4 C2 B2 Output
VCC 5 6 A2 A2 Power terminal

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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
(2)
VI Input voltage range –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions tables is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C

(1)
Human-Body Model (HBM) (2) 0 2 kV
VESD
Charged-Device Model (CDM) (3) 0 1 kV

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions (1)

MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

7.4 Thermal Information

SN74LVC1G17
THERMAL METRIC (1) DBV DCK DRL DRY YZP DPW YZV UNIT
5 PINS 5 PINS 5 PINS 6 PINS 5 PINS 4 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 229 280 350 608 130 340 181
RθJC(top) Junction-to-case (top) thermal resistance 164 66 121 432 54 215 1
RθJB Junction-to-board thermal resistance 62 67 171 446 51 294 39
°C/W
ψJT Junction-to-top characterization parameter 44 2 11 191 1 41 8
ψJB Junction-to-board characterization parameter 62 66 169 442 50 294 38
RθJC(bot) Junction-to-case (bottom) thermal resistance – – – 198 – 250 –

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 Electrical Characteristics—DC Limit Changes

over recommended operating free-air temperature range (unless otherwise noted)
25°C –40°C TO 85°C –40°C TO 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP (1) MAX MIN TYP (1) MAX MIN TYP MAX
1.65 V 0.76 1.13 0.76 1.13
VT+ 2.3 V 1.08 1.56 1.08 1.56
(Positive-going
3V 1.48 1.92 1.48 1.92 V
input threshold
voltage) 4.5 V 2.19 2.74 2.19 2.74
5.5 V 2.65 3.33 2.65 3.33
1.65 V 0.35 0.59 0.35 0.59
VT– 2.3 V 0.56 0.88 0.56 0.88
(Negative-going
3V 0.89 1.2 0.89 1.2 V
input threshold
voltage) 4.5 V 1.51 1.97 1.51 1.97
5.5 V 1.88 2.4 1.88 2.4
1.65 V 0.36 0.64 0.36 0.64
2.3 V 0.45 0.78 0.45 0.78
ΔVT
Hysteresis 3V 0.51 0.83 0.51 0.83 V
(VT+ – VT–)
4.5 V 0.58 0.93 0.58 0.93
5.5 V 0.69 1.04 0.69 1.04
1.65 V to
IOH = –100 μA VCC – 0.1 VCC – 0.1
5.5 V
IOH = –4 mA 1.65 V 1.2 1.2

VOH IOH = –8 mA 2.3 V 1.9 1.9 V

IOH = –16 mA 2.4 2.4
3V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
1.65 V to
IOL = 100 μA 0.1 0.1
5.5 V
IOL = 4 mA 1.65 V 0.45 0.45

VOL IOL = 8 mA 2.3 V 0.3 0.3 V

IOL = 16 mA 0.4 0.4
3V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
0 to
II A input VI = 5.5 V or GND ±5 ±5 μA
5.5 V
Ioff VI or VO = 5.5 V 0 ±10 ±10 μA
1.65 V to
VI = 5.5 V or GND, 10 10
5.5 V
ICC IO = 0 μA
3 V to
VI = 3.6 V or GND, 0.5 1.5
3.6 V
One input at VCC – 0.6 V, 3 V to
ΔICC 500 500 μA
Other inputs at VCC or GND 5.5 V
CI VI = VCC or GND 3.3 V 4.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

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7.6 Switching Characteristics, CL = 15 pF

over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 )
–40°C TO 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 2.8 9.9 1.6 5.5 1.5 4.6 0.9 4.4 ns

7.7 Switching Characteristics AC Limit, –40°C TO 85°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
–40°C TO 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 3.8 11 2 6.5 1.8 5.5 1.2 5 ns

7.8 Switching Characteristics AC Limit, –40°C TO 125°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
–40°C TO 125°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 3.8 13 2 8 1.8 6.5 1.2 6 ns

7.9 Operating Characteristics

TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 20 21 22 26 pF

7.10 Typical Characteristics

3.8 8
TPD TPD
3.7 7

6
3.6
5
TPD - ns

TPD - ns

3.5
4
3.4
3
3.3
2

3.2 1

3.1 0
-100 -50 0 50 100 150 0 1 2 3 4 5 6
Temperature - °C D001
Vcc - V D002

Figure 1. Across Temperature at 3.3V Vcc Figure 2. Across Vcc at 25°C

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8 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 15 pF 1 MW 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 15 pF 1 MW 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 50 pF 500 W 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

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9 Detailed Description

9.1 Overview
The SN74LVC1G17 device contains one Schmitt trigger buffer and performs the Boolean function Y = A. The
device functions as an independent buffer, but because of Schmitt action, it will have different input threshold
levels for a positive-going (VT+) and negative-going signals.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves
significant board space over other package options while still retaining the traditional manufacturing friendly lead
pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.

9.2 Functional Block Diagram

9.3 Feature Description

• Wide operating voltage range.
– Operates From 1.65 V to 5.5 V.
• Allows Down voltage translation.
• Inputs accept voltages to 5.5 V.
• Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V.

9.4 Device Functional Modes

Table 1. Function Table

INPUT OUTPUT
A Y
H H
L L

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10 Applications and Implementation

10.1 Application Information
The SN74LVC1G14 is a high drive CMOS device that can be used for a multitude of buffer type functions where
the input is slow or noisy. It can produce 24 mA of drive current at 3.3 V making it Ideal for driving multiple
outputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowing it to translate
down to VCC.

10.2 Typical Application

RF
~2.2 MΩ

SN74LVC1G17

C
RS 50 pF
~1 kΩ

CL
C1 C2
16 pF
~32 pF ~32 pF

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC .
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed (continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Max Ratings table.
– Outputs should not be pulled above VCC.

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Typical Application (continued)

10.2.3 Application Curves

10
Icc 1.8V
9 Icc 2.5V
8 Icc 3.3V
Icc 5V
7
6

Icc - mA
5
4
3
2
1
0
0 20 40 60 80
Frequency - MHz D003

Figure 5. ICC vs Frequency

11 Power Supply Recommendations

The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. Specified below are the rules that must
be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or
low bias to prevent them from floating. The logic level that should be applied to any particular unused input
depends on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or
is more convenient.

12.2 Layout Example

VCC Input
Unused Input Output Unused Input Output

Input

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13 Device and Documentation Support

13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC1G17DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C175, C17F, C17J,
& no Sb/Br) C17K, C17R)
(C17H, C17P, C17S)

SN74LVC1G17DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C17F
& no Sb/Br)
SN74LVC1G17DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C17F
& no Sb/Br)
SN74LVC1G17DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C175, C17F, C17J,
& no Sb/Br) C17K, C17R)
(C17H, C17P, C17S)

SN74LVC1G17DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C17F
& no Sb/Br)
SN74LVC1G17DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C17F
& no Sb/Br)
SN74LVC1G17DCK3 ACTIVE SC70 DCK 5 3000 Pb-Free SNBI Level-1-260C-UNLIM -40 to 85 (C7F, C7Z)
(RoHS)
SN74LVC1G17DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C75, C7F, C7J, C7
& no Sb/Br) K, C7R, C7T)
(C7H, C7P, C7S)
SN74LVC1G17DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C75
& no Sb/Br) C7S
SN74LVC1G17DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C75
& no Sb/Br) C7S
SN74LVC1G17DCKT ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C75, C7F, C7J, C7
& no Sb/Br) K, C7R, C7T)
(C7H, C7P, C7S)
SN74LVC1G17DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C75
& no Sb/Br) C7S
SN74LVC1G17DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C75
& no Sb/Br) C7S
SN74LVC1G17DPWR ACTIVE X2SON DPW 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 S4
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC1G17DRLR ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (C77, C7R)
& no Sb/Br)
SN74LVC1G17DRLRG4 ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 (C77, C7R)
& no Sb/Br)
SN74LVC1G17DRYR ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C7
& no Sb/Br)
SN74LVC1G17DSFR ACTIVE SON DSF 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 C7
& no Sb/Br)
SN74LVC1G17YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 C7N
& no Sb/Br)
SN74LVC1G17YZVR ACTIVE DSBGA YZV 4 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 C7
& no Sb/Br) (7, N)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC1G17 :

• Automotive: SN74LVC1G17-Q1
• Enhanced Product: SN74LVC1G17-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Apr-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G17DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G17DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G17DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G17DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G17DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G17DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G17DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G17DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G17DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G17DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G17DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G17DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LVC1G17DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G17DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G17DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G17DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G17DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LVC1G17DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Apr-2020

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G17DPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q3
SN74LVC1G17DRLR SOT-5X3 DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
SN74LVC1G17DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G17DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC1G17DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1G17YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
SN74LVC1G17YZVR DSBGA YZV 4 3000 178.0 9.2 1.0 1.0 0.63 4.0 8.0 Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G17DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G17DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G17DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74LVC1G17DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G17DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G17DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G17DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
SN74LVC1G17DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G17DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G17DCKR SC70 DCK 5 3000 180.0 180.0 18.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Apr-2020

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G17DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G17DCKR SC70 DCK 5 3000 202.0 201.0 28.0
SN74LVC1G17DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G17DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G17DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G17DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G17DCKT SC70 DCK 5 250 202.0 201.0 28.0
SN74LVC1G17DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G17DPWR X2SON DPW 5 3000 205.0 200.0 33.0
SN74LVC1G17DRLR SOT-5X3 DRL 5 4000 184.0 184.0 19.0
SN74LVC1G17DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
SN74LVC1G17DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G17DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74LVC1G17YZPR DSBGA YZP 5 3000 220.0 220.0 35.0
SN74LVC1G17YZVR DSBGA YZV 4 3000 220.0 220.0 35.0

Pack Materials-Page 3
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/E 09/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DPW0005A SCALE 12.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

0.85 A
B
0.75

PIN 1 INDEX AREA 0.85

0.75

0.4 MAX C

SEATING PLANE

NOTE 3

(0.1)

(0.25) 0.05
4X (0.05) 0.00

0.25 0.1
2
4
NOTE 3
2X 3
2X (0.26)
0.48

5
1
0.27
0.27 4X
0.17
0.17
0.1 C A B
(0.06)
0.05 C
0.32
3X
0.23

4223102/B 09/2017
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.

www.ti.com
 EXAMPLE BOARD LAYOUT
DPW0005A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.78)

SYMM ( 0.1)
4X (0.42) VIA 0.05 MIN
ALL AROUND
1 TYP

5
4X (0.22)

SYMM
4X (0.26)
(0.48)
3

2 4

(R0.05) TYP
SOLDER MASK
4X (0.06) OPENING, TYP
( 0.25)
(0.21) TYP METAL UNDER
EXPOSED METAL SOLDER MASK
CLEARANCE TYP

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED
SCALE:60X

4223102/B 09/2017
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DPW0005A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

4X (0.42) 4X (0.06)

5
4X (0.22) 1

( 0.24)

4X (0.26)
SYMM
(0.21) (0.48)
TYP
SOLDER MASK
EDGE 3

2
4

(R0.05) TYP
SYMM

(0.78)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X

4223102/B 09/2017
NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
YZP0005 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

C
0.5 MAX

SEATING PLANE
0.19
0.15 0.05 C
BALL TYP

0.5 TYP

SYMM
1
TYP
B D: Max = 1.418 mm, Min =1.357 mm
0.5
TYP E: Max = 0.918 mm, Min =0.857 mm
A

0.25
5X 1 2
0.21
0.015 C A B
SYMM

4219492/A 05/2017
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
5X ( 0.23)
1 2

(0.5) TYP

SYMM
B

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23)

OPENING SOLDER MASK
OPENING

( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219492/A 05/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

5X ( 0.25)
(R0.05) TYP
1 2

(0.5)
TYP

B SYMM

METAL SYMM
TYP

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4219492/A 05/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
D: Max = 0.918 mm, Min =0.858 mm

E: Max = 0.918 mm, Min =0.858 mm

 PACKAGE OUTLINE
DSF0006A SCALE 10.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05
B A
0.95

PIN 1 INDEX AREA

1.05
0.95

0.4 MAX C

SEATING PLANE

0.05 C

(0.11) TYP
SYMM 0.05
0.00

3
4

2X SYMM
0.7
4X
0.35
6
1
0.22
6X
0.12
(0.1)
PIN 1 ID 0.45 0.07 C B A
6X
0.35 0.05 C

4220597/A 06/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.

www.ti.com
 EXAMPLE BOARD LAYOUT
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.6)
(R0.05) TYP
1
6X (0.17) 6

SYMM

4X (0.35)

4
3

SYMM

(0.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:40X

0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND

EXPOSED METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220597/A 06/2017

NOTES: (continued)

4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.6)
(R0.05) TYP
1
6X (0.17) 6

SYMM

4X (0.35)

4
3

SYMM

(0.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:40X

4220597/A 06/2017

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 GENERIC PACKAGE VIEW
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4207181/G
 PACKAGE OUTLINE
DRY0006A SCALE 8.500
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05 A
B
0.95

PIN 1 INDEX AREA

1.5
1.4

0.6 MAX C

SEATING PLANE
0.05
0.00 0.08 C

3X 0.6
SYMM
(0.127) TYP
(0.05) TYP

3
4
4X
0.5
SYMM
2X
1

6
1
0.25
6X
0.4 0.15
0.3 0.1 C A B
0.05 C
PIN 1 ID
(OPTIONAL) 0.35
5X
0.25
4222894/A 01/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.35)
5X (0.3)

1 6

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP
(0.6)

LAND PATTERN EXAMPLE

1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

EXPOSED
EXPOSED
METAL
METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
DEFINED SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4222894/A 01/2018
NOTES: (continued)

3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.35) 5X (0.3)

1 6

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP (0.6)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X

4222894/A 01/2018

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
YZT0004 SCALE 10.000
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

0.625 MAX
C

SEATING PLANE
0.19 BALL TYP
0.15 0.05 C

0.5
TYP

B
SYMM
0.5
TYP D: Max = 0.918 mm, Min =0.858 mm

E: Max = 0.918 mm, Min =0.858 mm

A

0.25 1 2
4X SYMM
0.21
0.015 C A B

4219477/A 05/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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 EXAMPLE BOARD LAYOUT
YZT0004 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

4X ( 0.23) 1 2

SYMM
(0.5) TYP

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:50X

( 0.23) 0.05 MAX METAL

0.05 MIN
METAL UNDER
MASK

EXPOSED EXPOSED
SOLDER MASK ( 0.23)
METAL METAL
OPENING SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4219477/A 05/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

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 EXAMPLE STENCIL DESIGN
YZT0004 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

4X ( 0.25)
(R0.05) TYP
1 2

(0.5) SYMM
TYP

METAL
TYP SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:50X

4219477/A 05/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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