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OP07C, OP07D
SLOS099G – OCTOBER 1983 – REVISED NOVEMBER 2014

OP07x Precision Operational Amplifiers

1 Features 3 Description
•
1 Low Noise These devices offer low offset and long-term stability
by means of a low-noise, chopperless,
• No External Components Required bipolar-input-transistor amplifier circuit. For most
• Replace Chopper Amplifiers at a Lower Cost applications, external components are not required
• Wide Input-Voltage Range: 0 to ±14 V (Typ) for offset nulling and frequency compensation. The
• Wide Supply-Voltage Range: ±3 V to ±18 V true differential input, with a wide input-voltage range
and outstanding common-mode rejection, provides
maximum flexibility and performance in high-noise
2 Applications environments and in noninverting applications. Low
• Wireless Base Station Control Circuits bias currents and extremely high input impedances
• Optical Network Control Circuits are maintained over the entire temperature range.
• Instrumentation Device Information(1)
• Sensors and Controls PART NUMBER PACKAGE (PIN) BODY SIZE
• Precision Filters SO (8) 6.20 mm × 5.30 mm
OP07x SOIC (8) 4.90 mm × 3.91 mm
PDIP (8) 9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

4 Simplified Schematic
OFFSET N1 1

3
IN+ +
6
OUT
2
IN− −
8
OFFSET N2

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OP07C, OP07D
SLOS099G – OCTOBER 1983 – REVISED NOVEMBER 2014 www.ti.com

Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagram ......................................... 7
2 Applications ........................................................... 1 9.3 Feature Description................................................... 7
3 Description ............................................................. 1 9.4 Device Functional Modes.......................................... 7
4 Simplified Schematic............................................. 1 10 Application and Implementation.......................... 8
10.1 General Application................................................. 8
5 Revision History..................................................... 2
10.2 Typical Application ................................................. 8
6 Pin Functions ......................................................... 3
11 Power Supply Recommendations ..................... 10
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4 12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
7.2 Handling Ratings....................................................... 4
12.2 Layout Example .................................................... 11
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 4 13 Device and Documentation Support ................. 12
7.5 Electrical Characteristics........................................... 5 13.1 Related Links ........................................................ 12
7.6 Operating Characteristics.......................................... 6 13.2 Trademarks ........................................................... 12
13.3 Electrostatic Discharge Caution ............................ 12
8 Typical Characteristics.......................................... 6
13.4 Glossary ................................................................ 12
9 Detailed Description .............................................. 7
9.1 Overview ................................................................... 7 14 Mechanical, Packaging, and Orderable
Information ........................................................... 12

5 Revision History
Changes from Revision F (January 2014) to Revision G Page

• Added Applications, Device Information table, Pin Functions table, Handling Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1

Changes from Revision E (May 2004) to Revision F Page

• Deleted Ordering Information table. ....................................................................................................................................... 1

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6 Pin Functions
D OR P PACKAGE
(TOP VIEW)

OFFSET N1 1 8 OFFSET N2
IN− 2 7 VCC+
IN+ 3 6 OUT
VCC− 4 5 NC

NC −No internal connection

Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
IN+ 3 I Noninverting input
IN– 2 I Inverting input
NC 5 — Do not connect
OFFSET N1 1 I External input offset voltage adjustment
OFFSET N2 8 I External input offset voltage adjustment
OUT 6 O Output
VCC+ 7 — Positive supply
VCC– 4 — Negative supply

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC+ (2) 0 22
Supply voltage V
VCC– (2) –22 0
Differential input voltage (3) ±30 V
VI Input voltage range (either input) (4) ±22 V
(5)
Duration of output short circuit Unlimited
TJ Operating virtual-junction temperature 150 °C
Lead temperature 1.6 mm (1/16 in) from case for 10 s 260 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC−.
(3) Differential voltages are at IN+ with respect to IN−.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) The output may be shorted to ground or to either power supply.

7.2 Handling Ratings

PARAMETER DEFINITION MIN MAX UNIT
TSTG Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
0 1000
Electrostatic pins (1)
V(ESD) V
Discharge Charged device model (CDM), per JEDEC specification JESD22-
0 1000
C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC+ 3 18
Supply voltage
VCC– –3 –18 V
VIC Common-mode input voltage VCC± = ±15 V –13 13
TA Operating free-air temperature 0 70 °C

7.4 Thermal Information

THERMAL METRIC (1) D P UNIT
RθJA Junction-to-ambient thermal resistance 97 85 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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7.5 Electrical Characteristics

at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) (1)
OP07C OP07D
PARAMETER TEST CONDITIONS TA (2) UNIT
MIN TYP MAX MIN TYP MAX
25°C 60 150
VIO Input offset voltage VO = 0 V RS = 50 Ω µV
0°C to 70°C 85 250
Temperature coefficient
αVIO VO = 0 V RS = 50 Ω 0°C to 70°C 0.5 2.5 µV/°C
of input offset voltage
Long-term drift of input
See 0.4 µV/mo
offset voltage
Offset adjustment range RS = 20 kΩ, See Figure 2 25°C ±4 mV
25°C 0.8 6
IIO Input offset current nA
0°C to 70°C 1.6 8
Temperature coefficient
αIIO 0°C to 70°C 12 50 pA/°C
of input offset current
25°C ±1.8 ±12
IIB Input bias current nA
0°C to 70°C ±2.2 ±14
Temperature coefficient
αIIB 0°C to 70°C 18 50 pA/°C
of input bias current

Common-mode input 25°C ±13 ±14 ±13 ±14

VICR V
voltage range 0°C to 70°C ±13 ±13.5 ±13 ±13.5
RL ≥ 10 kΩ ±12 ±13 ±12 ±13
RL ≥ 2 kΩ 25°C ±11.5 ±12.8 ±11.5 ±12.8
VOM Peak output voltage V
RL ≥ 1 kΩ ±12 ±12
RL ≥ 2 kΩ 0°C to 70°C ±11 ±12.6 ±11 ±12.6
VCC = 15 V, VO = 1.4 V to 11.4 V,
25°C 100 400 400
RL ≥ 500 kΩ
Large-signal differential
AVD V/mV
voltage amplification 25°C 120 400 120 400
VO = ±10, RL = 2 kΩ
0°C to 70°C 100 400 100 400
B1 Unity-gain bandwidth 25°C 0.4 0.6 0.4 0.6 MHz
ri Input resistance 25°C 8 33 7 31 MΩ

Common-mode 25°C 100 120 94 110

CMRR VIC = ±13 V, RS = 50 Ω dB
rejection ratio 0°C to 70°C 97 120 94 106

Supply-voltage sensitivity 25°C 7 32 7 32

kSVS VCC+ = ±3 V to ±18 V, RS = 50 Ω µV/V
(ΔVIO/ΔVCC) 0°C to 70°C 10 51 10 51
VO = 0, No load 80 150 80 150
PD Power dissipation 25°C mW
VCC+ = ±3 V, VO = 0, No load 4 8 4 8

(1) Because long-term drift cannot be measured on the individual devices prior to shipment, this specification is not intended to be a
warranty. It is an engineering estimate of the averaged trend line of drift versus time over extended periods after the first 30 days of
operation.
(2) All characteristics are measured with zero common-mode input voltage, unless otherwise specified.

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7.6 Operating Characteristics

at specified free-air temperature, VCC = 5 V (unless otherwise noted)
OP07C OP07D
PARAMETER TEST CONDITIONS (1) UNIT
TYP TYP
f = 10 Hz 10.5 10.5
Vn Input offset voltage f = 100 Hz 10.2 10.3 nV/√Hz
f = 1 kHz 9.8 9.8
VN(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 0.38 0.38 µV
f = 10 Hz 0.35 0.35
In Equivalent input noise current f = 100 Hz 0.15 0.15 nV/√Hz
f = 1 kHz 0.13 0.13
IN(PP) Peak-to-peak equivalent input noise current f = 0.1 Hz to 10 Hz 15 15 pA
SR Slew rate RL ≥ 2 kΩ 0.3 0.3 V/µs

(1) All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise noted.
8 Typical Characteristics

200
Low
Mean
150 High

100
VIO (µV)

50

-50
-50 0 50 100 150
T (°C) D001
Figure 1. Input-Offset Voltage vs. Temperature

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9 Detailed Description

9.1 Overview
These devices offer low offset and long-term stability by means of a low-noise, chopperless, bipolar-input-
transistor amplifier circuit. For most applications, external components are not required for offset nulling and
frequency compensation. The true differential input, with a wide input-voltage range and outstanding common-
mode rejection, provides maximum flexibility and performance in high-noise environments and in noninverting
applications. Low bias currents and extremely high input impedances are maintained over the entire temperature
range.
These devices are characterized for operation from 0°C to 70°C.

9.2 Functional Block Diagram

VCC+

IN –

OUT
IN+

OFFSET N1
OFFSET N2

VCC –

Component Count
Transistors 22
Resistors 11
Diode 1
Capacitor 1

9.3 Feature Description

9.3.1 Offset-Voltage Null Capability
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors, et cetera. The input offset pins allow the designer to adjust for these
mismatches by external circuitry. See the Application and Implementation section for more details on design
techniques.

9.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. The OP07 has a 0.3-V/μs slew rate.

9.4 Device Functional Modes

The OP07 is powered on when the supply is connected. It can be operated as a single supply operational
amplifier or dual supply amplifier depending on the application.
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10 Application and Implementation

10.1 General Application
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for these
mismatches by external circuitry. These input mismatches can be adjusted by putting resistors or a potentiometer
between the inputs as shown in Figure 2. A potentiometer can be used to fine tune the circuit during testing or for
applications which require precision offset control. More information about designing using the input-offset pins,
see Nulling Input Offset Voltage of Operational Amplifiers (SLOA045).

20 kΩ
VCC+
OFFSET N1 OFFSET
1 N2
8
3
IN+ + 7
6
OUT
2 −
IN−
4
VCC –

Figure 2. Input Offset-Voltage Null Circuit

10.2 Typical Application

The voltage follower configuration of the operational amplifier is used for applications where a weak signal is
used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The
inputs of an operational amplifier have a very high resistance which puts a negligible current load on the voltage
source. The output resistance of the operational amplifier is almost negligible, so it can provide as much current
as necessary to the output load.
10 k

12 V

VOUT
+

VIN

Figure 3. Voltage Follower Schematic

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Typical Application (continued)

10.2.1 Design Requirements
• Output range of 2 V to 11 V
• Input range of 2 V to 11 V

10.2.2 Detailed Design Procedure

10.2.2.1 Output Voltage Swing

The output voltage of an operational amplifier is limited by its internal circuitry to some level below the supply
rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output
voltage requirements.

10.2.2.2 Supply and Input Voltage

For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail
voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to
operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to
11 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail, rather than ground, allows the
amplifier to maintain linearity for inputs below 2 V.

10.2.3 Application Curves for Output Characteristics

12 0.4

10 0.3

0.2
8
VOUT (V)

IIO (mA)

0.1
6
0.0
4
±0.1

2 ±0.2

0 ±0.3
0 2 4 6 8 10 12 0 2 4 6 8 10 12
VIN (V) C001 VIN (V) C002

Figure 4. Output Voltage vs Input Voltage Figure 5. Current Drawn by the Input of the Voltage
Follower (IIO) vs the Input Voltage

3.0

2.5

2.0
ICC (mA)

1.5

1.0

0.5

0.0
0 2 4 6 8 10 12
VIN (V) C003

Figure 6. Current Drawn from Supply (ICC) vs the Input Voltage

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11 Power Supply Recommendations

The OP07 is specified for operation from ±3 to ±18 V; many specifications apply from 0°C to 70°C.

CAUTION
Supply voltages larger than ±22 V can permanently damage the device (see the
Absolute Maximum Ratings).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.

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12 Layout

12.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. On multilayer PCBs, one or more layers are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicularly, as
opposed to in parallel, with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

12.2 Layout Example

RIN
VIN +
VOUT
RG
RF

Figure 7. Operational Amplifier Schematic for Noninverting Configuration

Place components close to

device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines RF
as possible
OFFSET N1 OFFSET N2 VS+
Use low-ESR, ceramic
RG bypass capacitor
GND IN1í VCC+

VIN IN1+ OUT

RIN
VCCí NC GND
Only needed for
dual-supply
operation
GND VS-
(or GND for single supply) VOUT Ground (GND) plane on another layer

Figure 8. Operational Amplifier Board Layout for Noninverting Configuration

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13 Device and Documentation Support

13.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

Technical Support &
Parts Product Folder Sample & Buy Tools & Software
Documents Community
OP07C Click here Click here Click here Click here Click here
OP07D Click here Click here Click here Click here Click here
13.2 Trademarks
All trademarks are the property of their respective owners.

13.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OP-07DP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 OP-07DP

OP-07DPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP-07D

OP-07DPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP-07D

OP-07DPSRG4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP-07D

OP07-W ACTIVE WAFERSALE YS 0 3603 TBD Call TI Call TI

OP07CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C

OP07CDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C

OP07CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C

OP07CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 OP07C

OP07CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C

OP07CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C

OP07CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 OP07CP

OP07CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 OP07CP

OP07DD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D

OP07DDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D

OP07DDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D

OP07DP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 OP07DP

OP07DPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 OP07DP

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OP07CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OP07CDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OP07DDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OP07CDR SOIC D 8 2500 340.5 338.1 20.6
OP07CDRG4 SOIC D 8 2500 340.5 338.1 20.6
OP07DDR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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