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NE5534, NE5534A, SA5534, SA5534A

SLOS070D – JULY 1979 – REVISED NOVEMBER 2014

NE5534x, SA5534x Low-Noise Operational Amplifiers

1 Features 3 Description
1• Equivalent Input Noise Voltage The NE5534, NE5534A, SA5534, and SA5534A
3.5 nV/√Hz Typ devices are high-performance operational amplifiers
combining excellent dc and ac characteristics. Some
• Unity-Gain Bandwidth 10 MHz Typ of the features include very low noise, high output-
• Common-Mode Rejection Ratio 100 dB Typ drive capability, high unity-gain and maximum-output-
• High DC Voltage Gain 100 V/mV Typ swing bandwidths, low distortion, and high slew rate.
• Peak-to-Peak Output Voltage Swing 32 V Typ These operational amplifiers are compensated
With VCC± = ±18 V and RL = 600 Ω internally for a gain equal to or greater than three.
• High Slew Rate 13 V/μs Typ Optimization of the frequency response for various
applications can be obtained by use of an external
• Wide Supply-Voltage Range ±3 V to ±20 V compensation capacitor between COMP and
• Low Harmonic Distortion COMP/BAL. The devices feature input-protection
• Offset Nulling Capability diodes, output short-circuit protection, and offset-
voltage nulling capability with use of the BALANCE
• External Compensation Capability
and COMP/BAL pins (see Figure 10).
2 Applications For the NE5534A and SA5534A devices, a maximum
limit is specified for the equivalent input noise
• Audio Preamplifiers voltage.
• Servo Error Amplifiers
• Medical Equipment Device Information
• Telephone Channel Amplifiers PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)
NE5534x SOIC (8) 4.90 mm × 3.91 mm
SOIC (8) 4.90 mm × 3.91 mm
SA5534x
SO (8) 6.20 mm × 5.30 mm

4 Simplified Schematic
COMP

COMP/BAL

IN− −
OUT
IN+ +

BALANCE

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
NE5534, NE5534A, SA5534, SA5534A
SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 9
2 Applications ........................................................... 1 8.3 Feature Description................................................. 10
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 10
4 Simplified Schematic............................................. 1 9 Application and Implementation ........................ 11
9.1 General Application................................................. 11
5 Revision History..................................................... 2
9.2 Typical Application ................................................. 12
6 Pin Configuration and Functions ......................... 3
10 Power Supply Recommendations ..................... 14
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
7.2 Handling Ratings....................................................... 4
11.2 Layout Example .................................................... 15
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 4 12 Device and Documentation Support ................. 16
7.5 Electrical Characteristics........................................... 5 12.1 Related Links ........................................................ 16
7.6 Operating Characteristics.......................................... 6 12.2 Trademarks ........................................................... 16
7.7 Typical Characteristics .............................................. 7 12.3 Electrostatic Discharge Caution ............................ 16
12.4 Glossary ................................................................ 16
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9 13 Mechanical, Packaging, and Orderable
Information ........................................................... 16

5 Revision History
Changes from Revision C (September 2004) to Revision D Page

• Added Applications,Device Information table, Handling Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
• Deleted Ordering Information table. ....................................................................................................................................... 1

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6 Pin Configuration and Functions

NE5534, SA5534 . . . D (SOIC), P (PDIP),
OR PS (SOP) PACKAGE
NE5534A, SA5534A . . . D (SOIC) OR P (PDIP) PACKAGE
(TOP VIEW)

BALANCE 1 8 COMP/BAL
IN− 2 7 VCC+
IN+ 3 6 OUT
VCC− 4 5 COMP

Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
BALANCE 1 I External frequency compensation
COMP/BAL 8 I External offset voltage adjustment/External frequency compensation
COMP 5 O External offset voltage adjustment
IN+ 3 I Noninverting input
IN- 2 I Inverting Input
OUT 6 O Output
VCC+ 7 — Positive Supply
VCC- 4 — Negative Supply

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN TYP MAX UNIT
VCC+ 0 22 V
VCC Supply voltage (2)
VCC– –22 0 V
Input voltage, either input (2) (3) VCC– VCC+ V
Input current (4) –10 10 mA
Duration of output short circuit (5) Unlimited
TJ Operating virtual-junction temperature 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
(3) The magnitude of the input voltage must never exceed the magnitude of the supply voltage.
(4) Excessive current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless some
limiting resistance is used.
(5) The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the
maximum dissipation rating is not exceeded.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
0 2000
all pins
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification
0 200
JESD22-C101, all pins

7.3 Recommended Operating Conditions

MIN MAX UNIT
VCC+ 5 15 V
VCC Supply voltage
VCC– –5 –15 V
NE5534, NE5534A 0 70
TA Operating free-air temperature °C
SA5534, SA5534A –40 85

7.4 Thermal Information

NE5534, NE5534A
SA5534, and SA5534A
(1)
THERMAL METRIC UNIT
D P PS
8 PINS
(2) (3)
RθJA Package thermal impedance 97 85 95 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.

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7.5 Electrical Characteristics

VCC± = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
VO = 0 TA = 25°C 0.5 4
VIO Input offset voltage mV
RS = 50 Ω TA = Full range 5
TA = 25°C 20 300
IIO Input offset current VO = 0 nA
TA = Full range 400
TA = 25°C 500 1500
IIB Input bias current VO = 0 nA
TA = Full range 2000
VICR Common-mode input-voltage range ±12 ±13 V
VCC± = ±15 V 24 26
VO(PP) Maximum peak-to-peak output-voltage swing RL ≥ 600 Ω V
VCC± = ±18 V 30 32
VO = ±10 V TA = 25°C 25 100
RL ≥ 600 Ω, TA = Full range 15
AVD Large-signal differential-voltage amplification V/mV
TA = 25°C 25 100
RL ≥ 2 kΩ, VO±10 V
TA = Full range 15
CC = 0 6
Avd Small-signal differential-voltage amplification f = 10 kHz V/mV
CC = 22 pF 2.2
CC = 0 200
VO = ±10 V
CC = 22 pF 95
BOM Maximum output-swing bandwidth kHz
VCC± 18 V, VO = ±14 V
70
RL = 600 Ω CC = 22 pF
B1 Unity-gain bandwidth CC = 22 pF CL = 100 pF 10 MHz
ri Input resistance 30 100 kΩ
AVD = 30 dB, RL = 600 Ω,
zo Output impedance 0.3 Ω
CC = 22 pF f = 10 kHz
VO = 0,
CMRR Common-mode rejection ratio VIC = VICRmin 70 100 dB
RS = 50 Ω
VCC± = ±9 V to ±15 V,
kSVR Supply-voltage rejection ratio (ΔVCC or ΔVIO) RS = 50 Ω 80 100 dB
VO = 0
IOS Output short-circuit current 38 mA
ICC Total supply current VO = 0, No load TA = 25°C 4 8 mA

(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. For
NE5534 and NE5534A, full range is 0°C to 70°C. For SA5534 and SA5534A, full range is –40°C to 85°C.

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7.6 Operating Characteristics

VCC± = ±15 V, TA = 25°C (unless otherwise noted)
NE5534,
NE5534A, SA5534A
PARAMETER TEST CONDITIONS SA5534 UNIT
TYP MIN TYP MAX
CC = 0 13 13
SR Slew rate V/μs
CC = 22 pF 6 6
Rise time VI = 50 mV, 20 20 ns
AVD = 1,
RL = 600 Ω,
Overshoot factor CC = 22 pF 20 20 %
CL = 100 pF
tr
Rise time VI = 50 mV, 50 50 ns
AVD = 1,
RL = 600 Ω,
Overshoot factor CC = 47 pF 35% 35% —
CL = 500 pF
f = 30 Hz 7 5.5 7
Vn Equivalent input noise voltage nV/√Hz
f = 1 kHz 4 3.5 4.5
f = 30 Hz 2.5 1.5
In Equivalent input noise current pA/√Hz
f = 1 kHz 0.6 0.4
F Average noise figure RS = 5 kΩ f = 10Hz to 20 kHz 0.9 dB

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7.7 Typical Characteristics

Normalized Input Bias Current and Input Offset Current

VOPP − Maximum Peak-to-Peak Output Voltage − V

1.6 30
VCC± = ±15 V CC = 0

1.4 Offset 25

1.2 20

Bias

1 15

0.8 10
CC = 22 pF

0.6 5

VO(PP)
VCC± = ±15 V CC = 47 pF
TA = 25°C
0.4 0
−75 −50 −25 0 25 50 75 100 125 100 1k 10 k 100 k 1M
TA − Free-Air Temperature − °C f − Frequency − Hz
Figure 1. Normalized Input Bias Current and Input Offset Figure 2. Maximum Peak-to-Peak Output Voltage
Current vs Frequency
vs Free-Air Temperature
106 1.2

Normalized Slew Rate and Unity-Gain Bandwidth

AVD − Differential Voltage Amplification − V/mV

VCC± = ±15 V TA = 25°C

TA = 25°C 1.1
105 Unity-Gain
1 Bandwidth

104
0.9

103 0.8
CC = 0 pF

0.7
102 Slew Rate
0.6
CC = 22 pF
10
0.5

1 0.4
10 100 1k 10 k 100 k 1 M 10 M 100 M 0 5 10 15 20
f − Frequency − Hz | VCC± | − Supply Voltage − V
Figure 3. Large-Signal Differential Voltage Amplification Figure 4. Normalized Slew Rate and Unity-Gain Bandwidth
vs Frequency vs Supply Voltage

Figure 5. Normalized Slew Rate and Unity-Gain Bandwidth Figure 6. Total Harmonic Distortion
vs Free-Air Temperature vs Frequency

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Typical Characteristics (continued)

Figure 7. Equivalent Input Noise Voltage Figure 8. Equivalent Input Noise Current
vs Frequency vs Frequency

Figure 9. Total Equivalent Input Noise Voltage

vs Source Resistance

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8 Detailed Description

8.1 Overview
The NE5534, NE5534A, SA5534, and SA5534A devices are high-performance operational amplifiers combining
excellent dc and ac characteristics. Some of the features include very low noise, high output-drive capability, high
unity-gain and maximum-output-swing bandwidths, low distortion, and high slew rate.
These operational amplifiers are compensated internally for a gain equal to or greater than three. Optimization of
the frequency response for various applications can be obtained by use of an external compensation capacitor
between COMP and COMP/BAL. The devices feature input-protection diodes, output short-circuit protection, and
offset-voltage nulling capability with use of the BALANCE and COMP/BAL pins (see the Application Circuit
Diagram).
For the NE5534A and SA5534A devices, a maximum limit is specified for the equivalent input noise voltage.

8.2 Functional Block Diagram

BALANCE COMP/BAL COMP

1 8 5 7
VCC+

100 pF 12 kΩ 12 kΩ

IN+
3

40 pF
15 Ω
6
2 OUT
IN−

12 pF 7 pF 15 Ω

4
VCC−

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8.3 Feature Description

8.3.1 Offset-Voltage Null Capability
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for
these mismatches by external circuitry. See the Application and Implementation section for more details on
design techniques.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. The NE5534 and SA5534 devices have a 13-V/μs slew rate.

8.3.3 Common-Mode Rejection Ratio

The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted
input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to
the change in the input voltage and converting to decibels. Ideally the CMRR is infinite, but in practice, amplifiers
are designed to have it as high as possible. The CMRR of the NE5534 and SA5534 devices is 100 dB.

8.3.4 Unity-Gain Bandwidth

The unity-gain bandwidth is the frequency up to which an amplifier with a unity gain may be operated without
greatly distorting the signal. The NE5534 and SA5534 devices have a 10-MHz unity-gain bandwidth.

8.3.5 External Compensation Capability

Frequency compensation with a capacitor may be used to increase the gain-bandwidth product (GBW) of the
amplifier. See the Application and Implementation section for more details on design techniques.

8.4 Device Functional Modes

The NE5534 and SA5534 devices are powered on when the supply is connected. Each of these devices can be
operated as a single supply operational amplifier or dual supply amplifier depending on the application.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 General Application

The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for
these mismatches by external circuitry. These input mismatches can be adjusted by putting resistors or a
potentiometer between the inputs as shown in Figure 10. A potentiometer can be used to fine tune the circuit
during testing or for applications which require precision offset control. More information about designing using
the input-offset pins, see Offset Voltage of Operational Amplifiers (SLOA045).
VCC+

22 kΩ
100 kΩ
CC

5534

VCC−
Frequency Compensation and Offset-Voltage Nulling Circuit

Figure 10. Application Circuit

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9.2 Typical Application

The voltage follower configuration of the operational amplifier is used for applications where a weak signal is
used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The
inputs of an operational amplifier have a very high resistance which puts a negligible current load on the voltage
source. The output resistance of the operational amplifier is almost negligible, so it can provide as much current
as necessary to the output load.
10 k

12 V

VOUT
+

VIN

Figure 11. Voltage Follower Schematic

9.2.1 Design Requirements

• Output range of 2 V to 11 V
• Input range of 2 V to 11 V

9.2.2 Detailed Design Procedure

9.2.2.1 Output Voltage Swing

The output voltage of an operational amplifier is limited by its internal circuitry to some level below the supply
rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output
voltage requirements.

9.2.2.2 Supply and Input Voltage

For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail
voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to
operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to
11 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail rather than ground, allows the
amplifier to maintain linearity for inputs below 2 V.

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Typical Application (continued)

9.2.3 Application Curves for Output Characteristics

12 4

2
10
0
8
±2
VOUT (V)

IIN (mA)
6 ±4

±6
4
±8
2
±10

0 ±12
0 2 4 6 8 10 12 0 2 4 6 8 10 12
VIN (V) C001 VIN (V) C002

Figure 12. Output Voltage vs Input Voltage Figure 13. Current Drawn by the Input of the Voltage
Follower (IIN) vs the Input Voltage

20
18
16
14
12
ICC (mA)

10
8
6
4
2
0
0 2 4 6 8 10 12
VIN (V) C003

Figure 14. Current Drawn from Supply (ICC) vs the Input Voltage

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10 Power Supply Recommendations

The NE5534 and SA5534 devices are specified for operation from ±5 to ±15 V; many specifications apply from
0°C to 70°C for the NE5534 device and –40°C to 85°C for the SA5534 device.

CAUTION
Supply voltages larger than ±22 V can permanently damage the device (see the
Absolute Maximum Ratings).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.

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11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. On multilayer PCBs, one or more layers are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicularly, as
opposed to in parallel, with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in .
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

RIN
VIN +
VOUT
RG
RF

Figure 15. Operational Amplifier Schematic for Noninverting Configuration

Place components close to

device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines RF
as possible
BALANCE COMP/BAL VS+
Use low-ESR, ceramic
RG bypass capacitor
GND IN1í VCC+

VIN IN1+ OUT

RIN
VCCí COMP GND
Only needed for
dual-supply
operation
GND VS-
(or GND for single supply) VOUT Ground (GND) plane on another layer

Figure 16. Operational Amplifier Board Layout for Noninverting Configuration

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12 Device and Documentation Support

12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
NE5534 Click here Click here Click here Click here Click here
NE5534A Click here Click here Click here Click here Click here
SA5534 Click here Click here Click here Click here Click here
SA5534A Click here Click here Click here Click here Click here

12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

NE5534AD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 5534A

NE5534ADR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 5534A

NE5534ADRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 5534A

NE5534ADRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 5534A

NE5534AP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 NE5534AP

NE5534APE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 NE5534AP

NE5534D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 NE5534

NE5534DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 NE5534

NE5534DRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 NE5534

NE5534DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 NE5534

NE5534P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 NE5534P

NE5534PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 NE5534P

SA5534AD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534A

SA5534ADR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534A

SA5534AP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SA5534AP

SA5534APE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SA5534AP

SA5534D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534

SA5534DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534

SA5534P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SA5534P

SA5534PSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SA5534

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Jul-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
NE5534ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE5534DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SA5534ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SA5534DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SA5534PSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Jul-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
NE5534ADR SOIC D 8 2500 340.5 336.1 25.0
NE5534DR SOIC D 8 2500 340.5 336.1 25.0
SA5534ADR SOIC D 8 2500 340.5 336.1 25.0
SA5534DR SOIC D 8 2500 340.5 336.1 25.0
SA5534PSR SO PS 8 2000 853.0 449.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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