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SN65LBC184, SN75LBC184
SLLS236I – OCTOBER 1996 – REVISED JUNE 2015

SNx5LBC184 Differential Transceiver With Transient Voltage Suppression

1 Features 3 Description
•
1 Integrated Transient Voltage Suppression The SN75LBC184 and SN65LBC184 devices are
differential data line transceivers in the trade-standard
• ESD Protection for Bus Terminals Exceeds: footprint of the SN75176 with built-in protection
±30 kV IEC 61000-4-2, Contact Discharge against high-energy noise transients. This feature
±15 kV IEC 61000-4-2, Air-Gap Discharge provides a substantial increase in reliability for better
±15 kV EIA/JEDEC Human Body Model immunity to noise transients coupled to the data
• Circuit Damage Protection of 400-W Peak cable over most existing devices. Use of these
(Typical) Per IEC 61000-4-5 circuits provides a reliable low-cost direct-coupled
(with no isolation transformer) data line interface
• Controlled Driver Output-Voltage Slew Rates
without requiring any external components.
Allow Longer Cable Stub Lengths
• 250-kbps in Electrically Noisy Environments The SN75LBC184 and SN65LBC184 can withstand
overvoltage transients of 400-W peak (typical). The
• Open-Circuit Fail-Safe Receiver Design conventional combination wave called out in IEC
• 1/4 Unit Load Allows for 128 Devices Connected 61000-4-5 simulates the overvoltage transient and
on Bus models a unidirectional surge caused by overvoltages
• Thermal Shutdown Protection from switching and secondary lightning transients.
• Power-Up and Power-Down Glitch Protection Device Information(1)
• Each Transceiver Meets or Exceeds the PART NUMBER PACKAGE BODY SIZE (NOM)
Requirements of TIA/EIA-485 (RS-485) and SOIC (8) 4.90 mm × 3.91 mm
SN65LBC184,
ISO/IEC 8482:1993(E) Standards SN75LBC184 PDIP (8) 9.81 mm × 6.35 mm
• Low Disabled Supply Current 300 μA Maximum
(1) For all available packages, see the orderable addendum at
• Pin Compatible With SN75176 the end of the datasheet.

2 Applications
• Industrial Networks
• Utility Meters
• Motor Control
Logic Symbol

NOTE: This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65LBC184, SN75LBC184
SLLS236I – OCTOBER 1996 – REVISED JUNE 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 12
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 12
3 Description ............................................................. 1 8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 9 Application and Implementation ........................ 15
9.1 Application Information............................................ 15
6 Specifications......................................................... 3
9.2 Typical Application ................................................. 15
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 3 10 Power Supply Recommendations ..................... 19
6.3 Recommended Operating Conditions....................... 4 11 Layout................................................................... 19
6.4 Thermal Information .................................................. 4 11.1 Layout Guidelines ................................................. 19
6.5 Electrical Characteristics: Driver ............................... 5 11.2 Layout Example .................................................... 19
6.6 Electrical Characteristics: Receiver .......................... 5 12 Device and Documentation Support ................. 20
6.7 Driver Switching Characteristics ............................... 6 12.1 Related Links ........................................................ 20
6.8 Receiver Switching Characteristics........................... 6 12.2 Community Resources.......................................... 20
6.9 Dissipation Ratings ................................................... 6 12.3 Trademarks ........................................................... 20
6.10 Typical Characteristics ............................................ 7 12.4 Electrostatic Discharge Caution ............................ 20
7 Parameter Measurement Information .................. 8 12.5 Glossary ................................................................ 20
8 Detailed Description ............................................ 12 13 Mechanical, Packaging, and Orderable
Information ........................................................... 20

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (February 2009) to Revision I Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

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5 Pin Configuration and Functions

D Package, P Package
8-Pin SOIC, 8-Pin PDIP
Top View

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
A 6 Bus input/output Driver output or receiver input (complementary to B)
B 7 Bus input/output Driver output or receiver input (complementary to A)
D 4 Digital input Driver data input
DE 3 Digital input Active-HIGH driver enable
GND 5 Reference potential Local device ground
R 1 Digital output Receiver data output
RE 2 Digital input Active-LOW receiver enable
VCC 8 Supply 4.75-V to 5.25-V supply

6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
(2)
VCC Supply voltage –0.5 7 V
Continuous voltage range at any bus terminal –15 15 V
Data input/output voltage –0.3 7 V
IO Receiver output current –20 20 mA
Continuous total power dissipation (3) Internally Limited
Tstg Storage temperature 160 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
(3) The driver shuts down at a junction temperature of approximately 160°C. To operate below this temperature, see the Dissipation
Ratings.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC A, B, GND ±15000
JS-001 (1) All pins ±3000
Electrostatic Contact discharge (IEC61000-4-2) A, B, GND (2) ±30000
V(ESD) V
discharge Air discharge (IEC61000-4-2) A, B, GND(3) ±15000
All pins (Class 3A) ±8000
All pins (Class 3B) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) GND and bus pin ESD protection is beyond readily available test equipment capabilities for IEC 61000-4-2, EIA/JEDEC test method
A114-A and MIL-STD-883C method 3015. Ratings listed are limits of test equipment; device performance exceeds these limits.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN (1) TYP MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VI or VIC Voltage at any bus terminal (separately or common mode) –7 12 V
VIH High-level input voltage D, DE, and RE 2 V
VIL Low-level input voltage D, DE, and RE 0.8 V
|VID| Differential input voltage 12 V
Driver –60
IOH High-level output current mA
Receiver –8
Driver 60
IOL Low-level output current mA
Receiver 4
SN75LBC184 0 70
TA Operating free-air temperature °C
SN65LBC184 –40 85

(1) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet.

6.4 Thermal Information

SNx5LBC184
THERMAL METRIC (1) P [PDIP] D [SOIC] UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 108.7 172.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.8 42.5 °C/W
RθJB Junction-to-board thermal resistance 23.6 41.4 °C/W
ψJT Junction-to-top characterization parameter 12 4.6 °C/W
ψJB Junction-to-board characterization parameter 23.5 40.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics: Driver

over recommended operating conditions (unless otherwise noted)
ALTERNATE
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
SYMBOLS
DE = RE = 5 V No Load 12 25 mA
ICC Supply current NA DE = 0 V
No Load 175 300 μA
RE = 5 V
High-level input current
IIH NA VI = 2.4 V 50 μA
(D, DE, RE)
Low-level input current
IIL NA VI = 0.4 V –50 μA
(D, DE, RE)
VO = –7 V –250 –120
Short-circuit output
IOS NA VO = VCC 250 mA
current OS (2)
VO = 12 V 250
High-impedance output
IOZ NA See Receiver II mA
current
VO Output voltage Voa, Vob IO = 0 0 VCC V
Peak-to-peak change in
common-mode output
VOC(PP) NA See Figure 9 and Figure 10 0.8 V
voltage during state
transitions
Common-mode output
VOC |Vos| See Figure 8 1 3 V
voltage
Magnitude of change,
|ΔVOC(SS)| common-mode steady- |Vos – Vos| See Figure 10 0.1 V
state output voltage
Magnitude of IO = 0 1.5 6 V
|VOD| differential output Vo
voltage |VA – VB| RL = 54 Ω, See Figure 8 1.5 V
Change in differential
Δ|VOD| voltage magnitude ||Vt| – |Vt|| RL = 54 Ω 0.1 V
between logic states

(1) All typical values are measured with TA = 25°C and VCC = 5 V.
(2) This parameter is measured with only one output being driven at a time.

6.6 Electrical Characteristics: Receiver

over recommended operation conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
DE = RE = 0 V, No Load 3.9 mA
ICC Supply current (total package)
RE = 5 V, DE = 0 V, No Load 300 μA
VI = 12 V 250
VI = 12 V, VCC = 0 250
II Input current Other input = 0 V μA
VI = –7 V –200
VI = –7 V, VCC = 0 –200
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±100 μA
Vhys Input hysteresis voltage 70 mV
VIT+ Positive-going input threshold voltage 200 V
VIT– Negative-going input threshold voltage –200 mV
VOH High-level output voltage IOH = –8 mA, See Figure 11 2.8 V
VOL Low-level output voltage IOL = 4 mA, See Figure 11 0.4 V

(1) All typical values are at VCC = 5 V, TA = 25°C.

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6.7 Driver Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(DH) Differential output delay time, low-to-high-level output 1.3 μs
td(DL) Differential output delay time, high-to-low-level output 1.3 μs
tPLH Propagation delay time, low-to-high-level output 0.5 1.3 μs
RL = 54 Ω
tPHL Propagation delay time, high-to-low-level output See Figure 9 0.5 1.3 μs
CL = 50 pF
tsk(p) Pulse skew (| td(DH) – td(DL)|) 75 150 ns
tr Rise time, single-ended 0.25 1.2 μs
tf Fall time, single-ended 0.25 1.2 μs
tPZH Output enable time to high level RL = 110 Ω See Figure 6 3.5 μs
tPZL Output enable time to low level RL = 110 Ω See Figure 7 3.5 μs
tPHZ Output disable time from high level RL = 110 Ω See Figure 6 2 μs
tPLZ Output disable time from low level RL = 110 Ω See Figure 7 2 μs

6.8 Receiver Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output 150 ns
CL = 50 pF, See Figure 11
tPHL Propagation delay time, high-to-low-level output 150 ns
tsk(p) Pulse skew (|tPHL– tPLH|) 50 ns
tr Rise time, single-ended 20 ns
See Figure 11
tf Fall time, single-ended 20 ns
tPZH Output enable time to high level 100 ns
tPZL Output enable time to low level 100 ns
See Figure 12
tPHZ Output disable time from high level 100 ns
tPLZ Output disable time from low level 100 ns

6.9 Dissipation Ratings

PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW
P 1150 mW 9.2 mW/°C 736 mW 598 mW

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6.10 Typical Characteristics

Figure 1. Driver Differential Output Voltage vs Free-Air Figure 2. Driver Propagation Delay Time vs Free-Air
Temperature Temperature

Figure 3. Driver Transition Time vs Free-Air Temperature Figure 4. Differential Output Voltage vs Output Current

Figure 5. Receiver Input Current vs Input Voltage

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7 Parameter Measurement Information

A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤
10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 6. Driver tPZH and tPHZ Test Circuit and Voltage Waveforms

A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤
10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 7. Driver tPZL and tPLZ Test Circuit and Voltage Waveforms

A. Resistance values are in ohms and are 1% tolerance.

B. CL includes probe and jig capacitance.

Figure 8. Driver Test Circuit, Voltage, and Current Definitions

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Parameter Measurement Information (continued)

Figure 9. Driver Timing, Voltage, and Current Waveforms

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Parameter Measurement Information (continued)

A. Resistance values are in ohms and are 1% tolerance.

B. CL includes probe and jig capacitance (±10%).

Figure 10. Driver VOC(PP) Test Circuit and Waveforms

A. This value includes probe and jig capacitance (±10%).

Figure 11. Receiver tPLH and tPHL Test Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

A. This value includes probe and jig capacitance (±10%).

Figure 12. Receiver tPZL, tPLZ, tPZH, and tPHZ Test Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
The SNx5LBC184 device is a 5-V, half-duplex, RS-485 transceiver with integrated transient voltage suppressors
that prevent circuit damage in the presence of high-energy transients of up to 400-W peak power. This
transceiver has an active-HIGH driver enable and active-LOW receiver enable. The differential driver is suitable
for data transmission up to 250 kbps.

8.2 Functional Block Diagram

VCC

R
/RE A
DE B

GND
Figure 13. Functional Logic Diagram

8.3 Feature Description

Integrated transient voltage suppressors protect the transceiver against Electrostatic Discharges (ESD) according
to IEC 61000-4-2 of up to ±30 kV and surge transients according to IEC 61000-4-5 of up to 400-W peak.
The differential driver incorporates slew-rate controlled outputs sufficient to transmit data up to 250 kbps. Slew-
rate control allows for longer unterminated cable runs and longer stub lengths from the main cable trunk than
with faster voltage transitions. A unique receiver design provides a high level failsafe output when the inputs are
left floating.
The SN65LBC184 is characterized from –40°C to 85°C and the SN75LBC184 is characterized from 0°C to 70°C.

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8.4 Device Functional Modes

When the driver enable pin (DE) is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined
as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant.

Table 1. Driver Functions (1)

INPUT ENABLE OUTPUTS
FUNCTION
D DE A B
H H H L Actively drive
bus High
L H L H Actively drive
bus Low
X L Z Z Driver disabled

(1) H = high level, L = low level, ? = indeterminate, X = irrelevant,

Z = high impedance (off)

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output (R)
turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output turns low.
If VID is between VIT+ and VIT–, the output is indeterminate.
When RE is logic high, the receiver output is high-impedance and the magnitude and polarity of VID are
irrelevant. When the transceiver is disconnected from the bus, the receiver provides a failsafe high output.

Table 2. Receiver Functions (1)

DIFFERENTIAL ENABLE OUTPUT
INPUT FUNCTION
VID = VA – VB RE R
VID > VIT+ L H Receive valid bus
High
VIT– < VID < VIT+ L ? Indeterminate bus
state
VID < VIT– L L Receive valid bus Low
X H Z Receiver disabled
OPEN L H Receiver failsafe High

(1) H = high level, L = low level, ? = indeterminate, X = irrelevant, Z =

high impedance (off)

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Figure 14. Schematic of Inputs and Outputs

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN65LBC184 and SN75LBC184 devices are half-duplex, RS-485 transceivers commonly used for
asynchronous data transmissions. The driver and receiver enable pins allow for the configuration of different
operating modes.

R R R
R R R
RE A RE A RE A
DE B DE B DE B
D D D
D D D

a) Independent driver and b) Combined enable signals for c) Receiver always on

receiver enable signals use as directional control pin
Figure 15. Half-Duplex Transceiver Configurations

a. Using independent enable lines provides the most flexible control as it allows for the driver and the receiver
to be turned on and off individually. While this configuration requires two control lines, it allows for selective
listening into the bus traffic, whether the driver is transmitting data or not.
b. Combining the enable signals simplifies the interface to the controller by forming a single direction-control
signal. In this configuration, the transceiver operates as a driver when the direction-control line is high, and
as a receiver when the direction-control line is low.
c. Only one line is required when connecting the receiver-enable input to ground and controlling only the driver-
enable input. In this configuration, a node not only receives the data from the bus, but also the data it sends
and can verify that the correct data have been transmitted.

9.2 Typical Application

An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over a
longer cable length.

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Typical Application (continued)

R R R R
A A
RE RE
RT RT
B B
DE DE
D D D D
A B A B

R R
D D

R RE DE D R RE DE D

Figure 16. Typical RS-485 Network With Half-Duplex Transceivers

9.2.1 Design Requirements

RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.

9.2.1.1 Data Rate and Bus Length

There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
5%, 10%, and 20% Jitter
Cable Length (ft)

1000
Conservative
Characteristics

100

10
100 1k 10k 100k 1M 10M 100M
Data Rate (bps)

Figure 17. Cable Length vs Data Rate Characteristic

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Typical Application (continued)

9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a nonterminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c
where
• tr is the 10/90 rise time of the driver
• v is the signal velocity of the cable or trace as a factor of c
• c is the speed of light (3 × 108 m/s) (1)
Per Equation 1, cable-stub lengths when using the SN65LBC184 driver must be not greater than 5.85 meters (19
feet) for a signal velocity of 78% and minimum driver output rise or fall time of 250 ns.

9.2.1.3 Bus Loading

The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the SN65LBC184 is a 1/4 UL transceiver, it
is possible to connect up to 128 receivers to the bus.

9.2.2 Detailed Design Procedure

9.2.2.1 SN65LBC184 Test Description

The SN65LBC184 is tested against the IEC 61000-4-5 recommended transient identified as the combination
wave. The combination wave provides a 1.2-/50-μs open-circuit voltage waveform and a 8-/20-μs short-circuit
current waveform shown in Figure 18. The testing is performed with a combination/hybrid pulse generator with an
effective output impedance of 2 Ω. The setup for the overvoltage stress is shown in Figure 19 with all testing
performed with power applied to the SN65LBC184 circuit.
1.0 1.0

0.8 0.8

0.6 0.6
V(t) / VP

I(t) / IP

0.4 0.4

0.2 0.2

0.0 0.0
0 20 40 60 80 100 0 10 20 30 40 50
Time - µs Time - µs

Figure 18. Open-Circuit Voltage and Short-Circuit Current Waveforms

The SN65LBC184 is tested and evaluated for both maximum (single pulse) as well as life test (multiple pulse)
capabilities. The SN65LBC184 is evaluated against transients of both positive and negative polarity and all
testing is performed with the worst-case transient polarity. Transient pulses are applied to the bus pins (A and B)
across ground as shown in Figure 19.

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Typical Application (continued)

41.9 Ω IP
Key Tech HIGH
A/B
1.2/50 – 8/20
Combination Pulse
Generator 3Ω VP SN75LBC184

LOW
GND
2Ω Internal Impedance
Impedance Matching
And Wave Shaping

Figure 19. Overvoltage Stress Test Circuit

9.2.3 Application Curve

An example waveform as seen by the SN65LBC184 is shown in Figure 20. The bottom trace is current, the
middle trace shows the clamping voltage of the device and the top trace is power as calculated from the voltage
and current waveforms. This example shows a peak clamping voltage of 33.6 V and peak current of 16 A, thus
yielding an absorbed peak power of 538 W.

Figure 20. Typical Surge Waveform Measured at Pins 5 and 7

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10 Power Supply Recommendations

To assure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS76350 is a linear voltage regulator
suitable for the 5-V supply.

11 Layout

11.1 Layout Guidelines

Because ESD transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency
layout techniques must be applied during PCB design.
• Use VCC and ground planes to provide low inductance. High frequency currents follow the path of least
inductance and not the path of least impedance.
• Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, or
controller ICs on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors to minimize effective via-
inductance.
• Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during
transient events.

11.2 Layout Example

3
Via to ground
Via to VCC C 2
R

4 R

JMP
MCU
4 R
LBC184 3

Figure 21. Layout Schematic

Copyright © 1996–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: SN65LBC184 SN75LBC184
SN65LBC184, SN75LBC184
SLLS236I – OCTOBER 1996 – REVISED JUNE 2015 www.ti.com

12 Device and Documentation Support

12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 3. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN65LBC184 Click here Click here Click here Click here Click here
SN75LBC184 Click here Click here Click here Click here Click here

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

20 Submit Documentation Feedback Copyright © 1996–2015, Texas Instruments Incorporated

Product Folder Links: SN65LBC184 SN75LBC184

 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN65LBC184D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 6LB184

& no Sb/Br)
SN65LBC184DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 6LB184
& no Sb/Br)
SN65LBC184DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 6LB184
& no Sb/Br)
SN65LBC184DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 6LB184
& no Sb/Br)
SN65LBC184P ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 65LBC184
(RoHS)
SN75LBC184D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7LB184
& no Sb/Br)
SN75LBC184DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7LB184
& no Sb/Br)
SN75LBC184DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7LB184
& no Sb/Br)
SN75LBC184DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7LB184
& no Sb/Br)
SN75LBC184P ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 75LBC184
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Oct-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LBC184DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75LBC184DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Oct-2014

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC184DR SOIC D 8 2500 340.5 338.1 20.6
SN75LBC184DR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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