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SN74AHC1G14
SCLS321Q – MARCH 1996 – REVISED SEPTEMBER 2015

SN74AHC1G14 Single Schmitt-Trigger Inverter Gate

1 Features 3 Description
•
1 Operating Range 2 V to 5.5 V The SN74AHC1G14 device is a single inverter gate.
The device performs the Boolean function
• Maximum tpd of 10 ns at 5 V Y = A.
• Low Power Consumption, 10-μA Max ICC
The device functions as an independent inverter gate,
• ±8-mA Output Drive at 5 V but because of the Schmitt action, gates may have
• Latch-Up Performance Exceeds 250 mA Per different input threshold levels for positive- (VT+) and
JESD 17 negative-going (VT−) signals.

2 Applications Device Information

ORDER NUMBER PACKAGE (PIN) BODY SIZE (NOM)
• Barcode Scanners
SN74AHC1G14DBV SOT-23 (5) 2.90 mm × 1.60 mm
• Cable Solutions
SN74AHC1G14DCK SC70 (5) 2.00 mm × 1.25 mm
• E-Books
SN74AHC1G14DRL SOT (5) 1.60 mm × 1.20 mm
• Embedded PCs
(1) For all available packages, see the orderable addendum at
• Field Transmitter: Temperature or Pressure the end of the data sheet.
Sensors
• Fingerprint Biometrics Logic Diagram (Positive Side)
• HVAC: Heating, Ventilating, and Air Conditioning
2 4
• Network-Attached Storage (NAS) A Y
• Sever Motherboard and PSU
• Software Defined Radios (SDR)
• TV: High Definition (HDTV), LCD, and Digital
• Video Communications Systems
• Wireless Data Access Cards, Headsets,
Keyboards, Mice, and LAN Cards

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1G14
SCLS321Q – MARCH 1996 – REVISED SEPTEMBER 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 8
2 Applications ........................................................... 1 8.3 Feature Description................................................... 8
3 Description ............................................................. 1 8.4 Device Functional Modes.......................................... 8
4 Revision History..................................................... 2 9 Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................... 9
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Power Supply Recommendations ..................... 11
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 11
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 11
6.4 Thermal Information .................................................. 5 11.2 Layout Example .................................................... 11
6.5 Electrical Characteristics........................................... 5 12 Device and Documentation Support ................. 12
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ 6 12.1 Documentation Support ........................................ 12
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V ........... 6 12.2 Community Resources.......................................... 12
6.8 Operating Characteristics.......................................... 6 12.3 Trademarks ........................................................... 12
6.9 Typical Characteristics .............................................. 6 12.4 Electrostatic Discharge Caution ............................ 12
7 Parameter Measurement Information .................. 7 12.5 Glossary ................................................................ 12
8 Detailed Description .............................................. 8 13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................... 8
Information ........................................................... 12

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision P (August 2013) to Revision Q Page

• Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1

Changes from Revision O (May 2013) to Revision P Page

• Updated document to new TI data sheet format - no specification changes ........................................................................ 1

Changes from Revision N (June 2005) to Revision O Page

• Changed document format from Quicksilver to DocZone. ..................................................................................................... 1

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5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23 DCK Package
Top View 5-Pin SC70
Top View

NC 1 5 VCC NC 1 5 VCC

A 2
A 2
GND 3 4 Y

GND 3 4 Y

DRL Package
5-Pin SOT
Top View

NC 1 5 VCC
A 2

GND 3 4 Y

Pin Functions (1)

PIN
I/O DESCRIPTION
NO. NAME
1 NC — No connect
2 A I Data Input
3 GND — Ground
4 Y O Data Output
5 VCC — Power

(1) NC – No internal connection.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
(2)
VI Input voltage –0.5 7 V
VO Output voltage (2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
Tj Maximum junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±1500
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 2 V –50 µA
IOH High-level output current VCC = 3.3 V ± 0.3 V –4
mA
VCC = 5 V ± 0.5 V –8
VCC = 2 V 50 µA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4
mA
VCC = 5 V ± 0.5 V 8
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.

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6.4 Thermal Information

SN74AHC1G14
THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) DRL (SOT) UNIT
5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 225.7 252 271.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 160.3 — 116.6 °C/W
RθJB Junction-to-board thermal resistance 59.4 — 89.9 °C/W
ψJT Junction-to-top characterization parameter 41.0 — 17.3 °C/W
ψJB Junction-to-board characterization parameter 58.7 — 89.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
RECOMMENDED
TEST TA = 25°C TA = –40°C to 85°C
PARAMETER VCC TA = –40°C to 125°C UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
VT+ 3V 1.2 2.2 1.2 2.2 1.2 2.2
Positive-going
4.5 V 1.75 3.15 1.75 3.15 1.75 3.15 V
input threshold
voltage 5.5 V 2.15 3.85 2.15 2.85 2.15 3.85
VT– 3V 0.9 1.9 0.9 1.9 0.9 1.9
Negative-going
4.5 V 1.35 2.75 1.35 2.75 1.35 2.75 V
input threshold
voltage 5.5 V 1.65 3.35 1.65 3.35 1.65 3.35
3V 0.3 1.2 0.3 1.2 0.25 1.2
ΔVT
Hysteresis 4.5 V 0.4 1.4 0.4 1.4 0.35 1.4 V
(VT+ – VT–)
5.5 V 0.5 1.6 0.5 1.6 0.45 1.6
2V 1.9 2 1.9 1.9
IOH = –50 µA 3V 2.9 3 2.9 2.9
VOH 4.5 V 4.4 4.5 4.4 4.4 V
IOH = –4 mA 3V 2.58 2.48 2.4
IOL = –8 mA 4.5 V 3.94 3.8 3.7
2V 0.1 0.1 0.1
IOH = 50 µA 3V 0.1 0.1 0.1
VOL 4.5 V 0.1 0.1 0.1 V
IOH = 4 mA 3V 0.36 0.44 0.55
IOL = 8 mA 4.5 V 0.36 0.44 0.55
VI = 5.5 V or 0 V to
II ±0.1 ±1 ±1 µA
GND 5.5 V
VI = VCC or
ICC 5.5 V 1 10 10 µA
GND, IO = 0
VI = VCC or
Ci 5V 2 10 10 10 pF
GND

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6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
RECOMMENDED
FROM TO OUTPUT TA = 25°C TA = –40°C to 85°C TA = –40°C to
PARAMETER 125°C UNIT
(INPUT) (OUTPUT) CAPACITANCE
TYP MAX MIN MAX MIN MAX
tPLH 8.3 12.8 1 15 1 16 ns
A Y CL = 15 pF
tPHL 8.3 12.8 1 15 1 16 ns
tPLH 10.8 16.3 1 18.5 1 19.5 ns
A Y CL = 50 pF
tPHL 10.8 16.3 1 18.5 1 19.5 ns

6.7 Switching Characteristics, VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
RECOMMENDED
TA = –40°C to
FROM TO OUTPUT TA = 25°C TA = –40°C to
PARAMETER 85°C UNIT
(INPUT) (OUTPUT) CAPACITANCE 125°C
TYP MAX MIN MAX MIN MAX
tPLH 5.5 8.6 1 10 1 11 ns
A or B Y CL = 15 pF
tPHL 5.5 8.6 1 10 1 11 ns
tPLH 7 10.6 1 12 1 11 ns
A or B Y CL = 50 pF
tPHL 7 10.6 1 12 1 11 ns

6.8 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 9 pF

6.9 Typical Characteristics

4
Signal Voltage (V)

0
0 5 10 15 20 25 30 35 40 45 50
Time (ns)
C001

TA = 25°C, VA = 5 V
Figure 1. Response Time vs Output Voltage

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7 Parameter Measurement Information

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

VCC
Timing Input 50% VCC
tw 0V
th
VCC tsu
VCC
Input 50% VCC 50% VCC
Data Input 50% VCC 50% VCC
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input 50% VCC 50% VCC 50% VCC 50% VCC
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈VCC
In-Phase 50% VCC 50% VCC 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2
50% VCC 50% VCC 50% VCC VOH − 0.3 V
Output S1 at GND
VOL (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
The SN74AHC1G14 device is a single inverter gate. The device performs the Boolean function
Y = A.
The device functions as an independent inverter gate, but because of the Schmitt action, gates may have
different input threshold levels for positive- (VT+) and negative-going (VT−) signals.

8.2 Functional Block Diagram

2 4
A Y

Figure 3. Logic Diagram (Positive Side)

8.3 Feature Description

The SN74AHC1G14 device has a wide operating VCC range of 2 V to 5.5 V, which allows it to be used in a broad
range of systems. The low propagation delay allows fast switching and higher speeds of operation. In addition,
the low-power consumption makes this device a good choice for portable and battery power-sensitive
applications.

8.4 Device Functional Modes

Table 1 lists the functional modes for SN74AHC1G14.

Table 1. Function Table

INPUT A OUTPUT Y
H L
L H

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

Physically interactive interface elements like push buttons or rotary knobs offer simple and easy ways to interact
with an electronic system. Many of these physical interface elements often have issues with bouncing, or where
the physical conductive contact can connect and disconnect multiple times during a button push or release. This
bouncing can cause one or more faulty transient signals to be passed during this transitional period. These faulty
signals can be observed in many common applications, for example, a television remote with bouncing error can
adjust the TV channel multiple times despite the button being pushed only once. To mitigate these faulty signals,
we can use a Schmitt-trigger, or a device with hysteresis, to remove these faulty signals. Hysteresis allows a
device to remember its history, and in this case, the SN74AHC1G14 uses this memory to debounce the signal of
the physical element, or filter the faulty transient signals and pass only the valid signal each time the element is
used. In this example, we show a push-button signal passed through an SN74AHC1G14 that is debounced and
inverted to the microprocessor for push detection.

9.2 Typical Application

VCC

Physical Push
Button
Microprocessor

SN74AHC1G14
Figure 4. Switch Debouncer

9.2.1 Design Requirements

The SN74AHC1G14 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits. The SN74AHC1G14 allows for
performing logical Boolean functions with hysteresis using digital signals. All input signals must remain as close
as possible to either 0 V or VCC for optimal operation.

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Typical Application (continued)

9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
2. Recommended output conditions:
– Load currents must not exceed ±50 mA.
3. Frequency selection criterion:
– The effects of frequency upon the power consumption of the device can be studied in CMOS Power
Consumption and CPD Calculation, SCAA035.
– Added trace resistance and capacitance can reduce maximum frequency capability; follow the layout
practices listed in the Layout Guidelines section.

9.2.3 Application Curves

VCC = 5.5 V VCC = 5.5 V

Figure 5. AHC Family VOH vs IOH Figure 6. AHC Family VOL vs IOL

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual-
supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must be installed as close
as possible to the power terminal for best results.

11 Layout

11.1 Layout Guidelines

Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self-inductance of the trace, which results in the reflection. Not all PCB traces can be straight;
therefore some traces must turn corners. Figure 7 shows progressively better techniques of rounding corners.
Only the last example (BEST) maintains constant trace width and minimizes reflections.

11.2 Layout Example

WORST BETTER BEST
2W

1W min.

W
Figure 7. Trace Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• CMOS Power Consumption and CPD Calculation, SCAA035
• Selecting the Right Texas Instruments Signal Switch, SZZA030

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74AHC1G14DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (A143, A14G, A14J, Samples
A14L, A14S)
SN74AHC1G14DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A14G Samples

SN74AHC1G14DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A14G Samples

SN74AHC1G14DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (A143, A14G, A14J, Samples
A14L, A14S)
SN74AHC1G14DCK3 ACTIVE SC70 DCK 5 3000 RoHS & SNBI Level-1-260C-UNLIM -40 to 125 AFY Samples
Non-Green
SN74AHC1G14DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (AF3, AFG, AFJ, AF Samples
L, AFS)
SN74AHC1G14DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AF3 Samples

SN74AHC1G14DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AF3 Samples

SN74AHC1G14DCKTE4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AF3 Samples

SN74AHC1G14DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AF3 Samples

SN74AHC1G14DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 AFS Samples

SN74AHC1G14DRLRG4 ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 AFS Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

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(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHC1G14DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74AHC1G14DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G14DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74AHC1G14DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G14DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G14DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74AHC1G14DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G14DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74AHC1G14DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74AHC1G14DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G14DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AHC1G14DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G14DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G14DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-May-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC1G14DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G14DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74AHC1G14DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G14DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G14DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
SN74AHC1G14DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G14DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G14DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G14DCKR SC70 DCK 5 3000 202.0 201.0 28.0
SN74AHC1G14DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G14DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G14DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G14DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74AHC1G14DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/G 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/G 03/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/G 03/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DRL0005A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
5

2X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3 0.3 0.05

B 5X TYP
1.1 0.1 0.00

0.6 MAX
C

SEATING PLANE
0.18
5X 0.05 C
0.08
SYMM

SYMM

0.27
5X
0.15
0.1 C A B
0.4
5X 0.05
0.2
4220753/B 12/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67) SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4220753/B 12/2020

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67)
SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4220753/B 12/2020

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.23
0.1
0.1 C A B (0.9) TYP
0.0

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/C 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/C 03/2023

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/C 03/2023

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
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