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SN74AHC1G04
SCLS318T – MARCH 1996 – REVISED JANUARY 2016

SN74AHC1G04 Single Inverter Gate

1 Features 3 Description
•
1 Operating Range 2 V to 5.5 V The SN74AHC1G04 contains one inverter gate. The
device performs the Boolean function Y = A.
• Max tpd of 6.5 ns at 5 V
• Low Power Consumption, 10-μA Max ICC Device Information(1)
• ±8-mA Output Drive at 5 V PART NUMBER PACKAGE BODY SIZE (NOM)
• Schmitt-Trigger Action at All Inputs Makes the SOT-23 (5) 2.90 x 1.60 mm
Circuit Tolerant for Slower Input Rise and Fall SN74AHC1G04 SC-70 (5) 2.00 x 1.30 mm
Time SOT-553 (5) 1.65 x 1.20 mm
• Latch-Up Performance Exceeds 250 mA Per (1) For all available packages, see the orderable addendum at
JESD 17 the end of the data sheet.

2 Applications
• Cameras
• E-Meters
• Ethernet Switches
• Infotainment
Simplified Schematic

A Y

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1G04
SCLS318T – MARCH 1996 – REVISED JANUARY 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................... 8
2 Applications ........................................................... 1 8.2 Functional Block Diagram ......................................... 8
3 Description ............................................................. 1 8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 9 Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
6 Specifications......................................................... 4
9.2 Typical Application ................................................... 9
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4 10 Power Supply Recommendations ..................... 10
6.3 Recommended Operating Conditions....................... 4 11 Layout................................................................... 11
6.4 Thermal Information .................................................. 5 11.1 Layout Guidelines ................................................. 11
6.5 Electrical Characteristics........................................... 5 11.2 Layout Example .................................................... 11
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ 5 12 Device and Documentation Support ................. 11
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V ........... 5 12.1 Trademarks ........................................................... 11
6.8 Operating Characteristics.......................................... 6 12.2 Electrostatic Discharge Caution ............................ 11
6.9 Typical Characteristics .............................................. 6 12.3 Glossary ................................................................ 11
7 Parameter Measurement Information .................. 7 13 Mechanical, Packaging, and Orderable
8 Detailed Description .............................................. 8 Information ........................................................... 11

4 Revision History
Changes from Revision S (December 2014) to Revision T Page

• Removed "Schmitt-Trigger" from the data sheet title ............................................................................................................ 1

• Added TJ Junction temperature to the Absolute Maximum Ratings ...................................................................................... 4

Changes from Revision R (January 2013) to Revision S Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
• Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 4

Changes from Revision Q (June 2005) to Revision R Page

• Changed document format from Quicksilver to DocZone. ..................................................................................................... 1

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5 Pin Configuration and Functions

DBV PACKAGE DCK PACKAGE DRL PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW)

NC 1 5 VCC NC 1 5 VCC
NC 1 5 VCC
A 2 A 2

A 2
GND 3 4 Y
GND 3 4 Y

GND 3 4 Y

NC – No internal connection
See mechanical drawings for dimensions.

Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
1 NC — No Connection
2 A I Input A
3 GND — Ground Pin
4 Y O Output Y
5 VCC — Power Pin

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
(2)
VI Input voltage range –0.5 7 V
VO Output voltage range (2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through each VCC or GND ±50 mA
Tstg Storage temperature range –65 150 °C
TJ Junction temperature 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 3500
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, V
1000
all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 3 V 2.1 V
VCC = 5.5 V 3.85
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 3 V 0.9 V
VCC = 5.5 V 1.65
VIH Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 2 V –50 µA
IOH High-level output current VCC = 3.3 V ± 0.3 V –4
mA
VCC = 5 V ± 0.5 V –8
VCC = 2 V 50 µA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4
mA
VCC = 5 V ± 0.5 V 8
VCC = 3.3 V ± 0.3 V 100
Δt/Δv Input transition rise or fall rate ns/V
VCC = 5 V ± 0.5 V 20
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).

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6.4 Thermal Information

SN74AHC1G04
THERMAL METRIC (1) DBV DCK DRL UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance 231.3 287.6 328.7
RθJC(top) Junction-to-case (top) thermal resistance 119.9 97.7 105.1
RθJB Junction-to-board thermal resistance 60.6 65.0 150.3 °C/W
ψJT Junction-to-top characterization parameter 17.8 2.0 6.9
ψJB Junction-to-board characterization parameter 60.1 64.2 148.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 1.9 2 1.9 1.9
IOH = –50 µA 3V 2.9 3 2.9 2.9
VOH 4.5 V 4.4 4.5 4.4 4.4 V
IOH = –4 mA 3V 2.58 2.48 2.48
IOH = –8 mA 4.5 V 3.94 3.8 3.8
2V 0.1 0.1 0.1
IOH = 50 µA 3V 0.1 0.1 0.1
VOL 4.5 V 0.1 0.1 0.1 V
IOL = 4 mA 3V 0.36 0.44 0.44
IOL = 8 mA 4.5 V 0.36 0.44 0.44
0 V to
II VI = 5.5 V or GND ±0.1 ±1 ±1 µA
5.5 V
ICC VI = VCC or GND, IO = 0 5.5 V 1 10 10 µA
Ci VI = VCC or GND 5V 2 10 10 10 pF

6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM TO OUTPUT TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 5 7.1 1 8.5 1 9.5
A Y CL = 15 pF ns
tPHL 5 7.1 1 8.5 1 9.5
tPLH 7.5 10.6 1 12 1 13
A Y CL = 50 pF ns
tPHL 7.5 10.6 1 12 1 13

6.7 Switching Characteristics, VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM TO OUTPUT TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 3.8 5.5 1 6.5 1 7
A Y CL = 15 pF ns
tPHL 3.8 5.5 1 6.5 1 7
tPLH 5.3 7.5 1 6.5 1 7
A Y CL = 50 pF ns
tPHL 5.3 7.5 1 6.5 1 7

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6.8 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 12 pF

6.9 Typical Characteristics

4 5

3.5
4
3

2.5
3
TPD (ns)

TPD (ns)
2

1.5 2

1
1
0.5
TPD in ns TPD in ns
0 0
-100 -50 0 50 100 150 0 1 2 3 4 5 6
Temperature (qC) D001
VCC D002
Figure 1. TPD vs Temperature at 5 V Figure 2. TPD vs VCC at 25°C

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7 Parameter Measurement Information

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

VCC
Timing Input 50% VCC
tw 0V
th
VCC tsu
VCC
Input 50% VCC 50% VCC
Data Input 50% VCC 50% VCC
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input 50% VCC 50% VCC 50% VCC 50% VCC
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈VCC
In-Phase 50% VCC 50% VCC 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2
50% VCC 50% VCC 50% VCC VOH − 0.3 V
Output S1 at GND
VOL (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit And Voltage Waveforms

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8 Detailed Description

8.1 Overview
The SN74AHC1G04 device contains one inverter gate. The device performs the Boolean function Y = A.
This single gate inverter has Schmitt-Trigger action on its input, allowing for slower rise and fall times and some
noise rejection. This is not a true Schmitt-Trigger, so there is a limit on rise and fall times.

8.2 Functional Block Diagram

A Y

Figure 4. Logic Diagram (Positive Logic)

8.3 Feature Description

• Wide operating voltage range
– Operates from 2 V to 5.5 V
• Allows down-voltage translation
– Inputs accept voltages to 5.5 V
• Lower drive
– This will produce slower edges and help prevent ringing on outputs

8.4 Device Functional Modes

Table 1. Function Table

INPUT OUTPUT
A Y
H L
L H

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

SN74AHC1G04 is a low-drive CMOS device that can be used for a multitude of inverting buffer type functions. It
can produce 8 mA of drive current at 5 V, making it Ideal for driving multiple outputs and good for low-noise
applications. The inputs are 5.5-V tolerant, allowing it to translate down to VCC.

9.2 Typical Application

5-V accessory 3.3-V or 5-V regulated

0.1 µF

Figure 5. Typical Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.

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Typical Application (continued)

9.2.3 Application Curves

Figure 6. Typical Application Curve

10 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.

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11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.

11.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 7. Layout Diagram

12 Device and Documentation Support

12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74AHC1G04DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (A043, A04G, A04J,
& no Sb/Br) A04L, A04S)
SN74AHC1G04DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 A04G
& no Sb/Br)
SN74AHC1G04DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 A04G
& no Sb/Br)
SN74AHC1G04DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (A043, A04G, A04J,
& no Sb/Br) A04L, A04S)
SN74AHC1G04DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 A04G
& no Sb/Br)
SN74AHC1G04DCK3 ACTIVE SC70 DCK 5 3000 Pb-Free CU SNBI Level-1-260C-UNLIM -40 to 85 ACY
(RoHS)
SN74AHC1G04DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (AC3, ACG, ACJ, AC
& no Sb/Br) L, ACS)
SN74AHC1G04DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 AC3
& no Sb/Br)
SN74AHC1G04DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 AC3
& no Sb/Br)
SN74AHC1G04DCKT ACTIVE SC70 DCK 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (AC3, ACG, ACJ, AC
& no Sb/Br) L, ACS)
SN74AHC1G04DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 AC3
& no Sb/Br)
SN74AHC1G04DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 AC3
& no Sb/Br)
SN74AHC1G04DRLR ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM -40 to 125 (ACB, ACS)
& no Sb/Br) CU NIPDAUAG
SN74AHC1G04DRLRG4 ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (ACB, ACS)
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
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(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AHC1G04 :

• Automotive: SN74AHC1G04-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHC1G04DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74AHC1G04DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G04DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74AHC1G04DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G04DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G04DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74AHC1G04DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74AHC1G04DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G04DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AHC1G04DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G04DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AHC1G04DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G04DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G04DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AHC1G04DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AHC1G04DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G04DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

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*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC1G04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G04DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G04DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G04DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G04DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G04DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G04DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G04DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G04DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74AHC1G04DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74AHC1G04DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74AHC1G04DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74AHC1G04DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

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 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/E 09/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

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