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LM555
SNAS548D – FEBRUARY 2000 – REVISED JANUARY 2015

LM555 Timer
1 Features 3 Description
•
1 Direct Replacement for SE555/NE555 The LM555 is a highly stable device for generating
accurate time delays or oscillation. Additional
• Timing from Microseconds through Hours terminals are provided for triggering or resetting if
• Operates in Both Astable and Monostable Modes desired. In the time delay mode of operation, the time
• Adjustable Duty Cycle is precisely controlled by one external resistor and
• Output Can Source or Sink 200 mA capacitor. For a stable operation as an oscillator, the
free running frequency and duty cycle are accurately
• Output and Supply TTL Compatible controlled with two external resistors and one
• Temperature Stability Better than 0.005% per °C capacitor. The circuit may be triggered and reset on
• Normally On and Normally Off Output falling waveforms, and the output circuit can source
or sink up to 200 mA or drive TTL circuits.
• Available in 8-pin VSSOP Package
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
• Precision Timing SOIC (8) 4.90 mm × 3.91 mm
• Pulse Generation LM555 PDIP (8) 9.81 mm × 6.35 mm
• Sequential Timing VSSOP (8) 3.00 mm × 3.00 mm
• Time Delay Generation (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• Pulse Width Modulation
• Pulse Position Modulation
• Linear Ramp Generator
Schematic Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................... 8
2 Applications ........................................................... 1 7.4 Device Functional Modes.......................................... 9
3 Description ............................................................. 1 8 Application and Implementation ........................ 12
4 Revision History..................................................... 2 8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 15
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 15
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 15
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 15
6.4 Thermal Information ................................................. 4 11 Device and Documentation Support ................. 16
6.5 Electrical Characteristics .......................................... 5 11.1 Trademarks ........................................................... 16
6.6 Typical Characteristics .............................................. 6 11.2 Electrostatic Discharge Caution ............................ 16
7 Detailed Description .............................................. 8 11.3 Glossary ................................................................ 16
7.1 Overview ................................................................... 8 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ......................................... 8 Information ........................................................... 16

4 Revision History
Changes from Revision C (March 2013) to Revision D Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision B (March 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 13

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5 Pin Configuration and Functions

D, P, and DGK Packages

8-Pin PDIP, SOIC, and VSSOP
Top View

1 8
GND +VCC

2 COMPAR- 7
TRIGGER R DISCHARGE
ATOR

FLIP FLOP R

3 OUTPUT COMPAR-
6
OUTPUT R THRESHOLD
STAGE ATOR

4 VREF (INT) 5 CONTROL

RESET
VOLTAGE

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
Control Controls the threshold and trigger levels. It determines the pulse width of the output
5 Voltage I waveform. An external voltage applied to this pin can also be used to modulate the output
waveform
Discharge Open collector output which discharges a capacitor between intervals (in phase with output).
7 I
It toggles the output from high to low when voltage reaches 2/3 of the supply voltage
1 GND O Ground reference voltage
3 Output O Output driven waveform
Reset Negative pulse applied to this pin to disable or reset the timer. When not used for reset
4 I
purposes, it should be connected to VCC to avoid false triggering
Threshold Compares the voltage applied to the terminal with a reference voltage of 2/3 Vcc. The
6 I
amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop
Trigger Responsible for transition of the flip-flop from set to reset. The output of the timer depends
2 I
on the amplitude of the external trigger pulse applied to this pin
8 V+ I Supply voltage with respect to GND

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
LM555CM, LM555CN (4) 1180 mW
Power Dissipation (3)
LM555CMM 613 mW
PDIP Package Soldering (10 Seconds) 260 °C
Soldering
Small Outline Packages (SOIC and Vapor Phase (60 Seconds) 215 °C
Information
VSSOP) Infrared (15 Seconds) 220 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) For operating at elevated temperatures the device must be derated above 25°C based on a 150°C maximum junction temperature and a
thermal resistance of 106°C/W (PDIP), 170°C/W (S0IC-8), and 204°C/W (VSSOP) junction to ambient.
(4) Refer to RETS555X drawing of military LM555H and LM555J versions for specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±500 (2) V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The ESD information listed is for the SOIC package.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage 18 V
Temperature, TA 0 70 °C
Operating junction temperature, TJ 70 °C

6.4 Thermal Information

LM555
THERMAL METRIC (1) PDIP SOIC VSSOP UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 106 170 204 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.5 Electrical Characteristics

(TA = 25°C, VCC = 5 V to 15 V, unless otherwise specified) (1) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Voltage 4.5 16 V
Supply Current VCC = 5 V, RL = ∞ 3 6
VCC = 15 V, RL = ∞ 10 15 mA
(Low State) (3)
Timing Error, Monostable
Initial Accuracy 1%
Drift with Temperature RA = 1 k to 100 kΩ, 50 ppm/°C
(4)
C = 0.1 μF,
Accuracy over Temperature 1.5 %
Drift with Supply 0.1 % V
Timing Error, Astable
Initial Accuracy 2.25
Drift with Temperature RA, RB =1 k to 100 kΩ, 150 ppm/°C
(4)
C = 0.1 μF,
Accuracy over Temperature 3.0%
Drift with Supply 0.30 % /V
Threshold Voltage 0.667 x VCC
Trigger Voltage VCC = 15 V 5 V
VCC = 5 V 1.67 V
Trigger Current 0.5 0.9 μA
Reset Voltage 0.4 0.5 1 V
Reset Current 0.1 0.4 mA
(5)
Threshold Current 0.1 0.25 μA
Control Voltage Level VCC = 15 V 9 10 11
V
VCC = 5 V 2.6 3.33 4
Pin 7 Leakage Output High 1 100 nA
(6)
Pin 7 Sat
Output Low VCC = 15 V, I7 = 15 mA 180 mV
Output Low VCC = 4.5 V, I7 = 4.5 mA 80 200 mV
Output Voltage Drop (Low) VCC = 15 V
ISINK = 10 mA 0.1 0.25 V
ISINK = 50 mA 0.4 0.75 V
ISINK = 100 mA 2 2.5 V
ISINK = 200 mA 2.5 V
VCC = 5 V
ISINK = 8 mA V
ISINK = 5 mA 0.25 0.35 V

(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC
electrical specifications under particular test conditions which ensures specific performance limits. This assumes that the device is within
the Recommended Operating Conditions. Specifications are not ensured for parameters where no limit is given, however, the typical
value is a good indication of device performance.
(3) Supply current when output high typically 1 mA less at VCC = 5 V.
(4) Tested at VCC = 5 V and VCC = 15 V.
(5) This will determine the maximum value of RA + RB for 15 V operation. The maximum total (RA + RB) is 20 MΩ.
(6) No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded.

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Electrical Characteristics (continued)

(TA = 25°C, VCC = 5 V to 15 V, unless otherwise specified)(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output Voltage Drop (High) ISOURCE = 200 mA, VCC = 15 V 12.5 V
ISOURCE = 100 mA, VCC = 15 V 12.75 13.3 V
VCC = 5 V 2.75 3.3 V
Rise Time of Output 100 ns
Fall Time of Output 100 ns

6.6 Typical Characteristics

Figure 1. Minimum Pulse Width Required For Triggering Figure 2. Supply Current vs. Supply Voltage

Figure 3. High Output Voltage vs. Output Source Current Figure 4. Low Output Voltage vs. Output Sink Current

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Typical Characteristics (continued)

Figure 5. Low Output Voltage vs. Output Sink Current Figure 6. Low Output Voltage vs. Output Sink Current

Figure 7. Output Propagation Delay vs. Voltage Level of Figure 8. Output Propagation Delay vs. Voltage Level of
Trigger Pulse Trigger Pulse

Figure 9. Discharge Transistor (Pin 7) Voltage vs. Sink Figure 10. Discharge Transistor (Pin 7) Voltage vs. Sink
Current Current

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7 Detailed Description

7.1 Overview
The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are
provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled
by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty
cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output circuit can source or sink up to 200mA or driver TTL circuits. The
LM555 are available in 8-pin PDIP, SOIC, and VSSOP packages and is a direct replacement for SE555/NE555.

7.2 Functional Block Diagram

CONTROL
THRESHOLD VOLTAGE +Vcc

COMPARATOR
RESET

Vref (int)

TRIGGER
FLIP FLOP COMPARATOR

DISCHARGE
OUTPUT
OUTPUT
STAGE

7.3 Feature Description

7.3.1 Direct Replacement for SE555/NE555
The LM555 timer is a direct replacement for SE555 and NE555. It is pin-to-pin compatible so that no schematic
or layout changes are necessary. The LM555 come in an 8-pin PDIP, SOIC, and VSSOP package.

7.3.2 Timing From Microseconds Through Hours

The LM555 has the ability to have timing parameters from the microseconds range to hours. The time delay of
the system can be determined by the time constant of the R and C value used for either the monostable or
astable configuration. A nomograph is available for easy determination of R and C values for various time delays.

7.3.3 Operates in Both Astable and Monostable Mode

The LM555 can operate in both astable and monostable mode depending on the application requirements.
• Monostable mode: The LM555 timer acts as a “one-shot” pulse generator. The pulse beings when the LM555
timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the output
pulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the
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Feature Description (continued)

capacitor equals 2/3 of the supply voltage. The output pulse width can be extended or shortened depending
on the application by adjusting the R and C values.
• Astable (free-running) mode: The LM555 timer can operate as an oscillator and puts out a continuous stream
of rectangular pulses having a specified frequency. The frequency of the pulse stream depends on the values
of RA, RB, and C.

7.4 Device Functional Modes

7.4.1 Monostable Operation
In this mode of operation, the timer functions as a one-shot (Figure 11). The external capacitor is initially held
discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC to
pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.

Figure 11. Monostable

The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which
time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor
and drives the output to its low state. Figure 12 shows the waveforms generated in this mode of operation. Since
the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing
interval is independent of supply.

VCC = 5 V Top Trace: Input 5V/Div.

TIME = 0.1 ms/DIV. Middle Trace: Output 5V/Div.
RA = 9.1 kΩ Bottom Trace: Capacitor Voltage 2V/Div.
C = 0.01 μF

Figure 12. Monostable Waveforms

During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit
so long as the trigger input is returned high at least 10 μs before the end of the timing interval. However the
circuit can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output
will then remain in the low state until a trigger pulse is again applied.
When the reset function is not in use, TI recommends connecting the Reset pin to VCC to avoid any possibility of
false triggering.

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Device Functional Modes (continued)

Figure 13 is a nomograph for easy determination of R, C values for various time delays.

Figure 13. Time Delay

7.4.2 Astable Operation

If the circuit is connected as shown in Figure 14 (pins 2 and 6 connected) it will trigger itself and free run as a
multivibrator. The external capacitor charges through RA + RB and discharges through RB. Thus the duty cycle
may be precisely set by the ratio of these two resistors.

Figure 14. Astable

In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in the
triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply
voltage.
Figure 15 shows the waveforms generated in this mode of operation.

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Device Functional Modes (continued)

VCC = 5 V Top Trace: Output 5V/Div.

TIME = 20μs/DIV. Bottom Trace: Capacitor Voltage 1V/Div.
RA = 3.9 kΩ
RB = 3 kΩ
C = 0.01 μF

Figure 15. Astable Waveforms

The charge time (output high) is given by:

t1 = 0.693 (RA + RB) C (1)
And the discharge time (output low) by:
t2 = 0.693 (RB) C (2)
Thus the total period is:
T = t1 + t2 = 0.693 (RA +2RB) C (3)
The frequency of oscillation is:

(4)
Figure 16 may be used for quick determination of these RC values.
The duty cycle is:

(5)

Figure 16. Free Running Frequency

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM555 timer can be used a various configurations, but the most commonly used configuration is in
monostable mode. A typical application for the LM555 timer in monostable mode is to turn on an LED for a
specific time duration. A pushbutton is used as the trigger to output a high pulse when trigger pin is pulsed low.
This simple application can be modified to fit any application requirement.

8.2 Typical Application

Figure 17 shows the schematic of the LM555 that flashes an LED in monostable mode.

Figure 17. Schematic of Monostable Mode to Flash an LED

8.2.1 Design Requirements

The main design requirement for this application requires calculating the duration of time for which the output
stays high. The duration of time is dependent on the R and C values (as shown in Figure 17) and can be
calculated by:
t = 1.1 × R × C seconds (6)

8.2.2 Detailed Design Procedure

To allow the LED to flash on for a noticeable amount of time, a 5 second time delay was chosen for this
application. By using Equation 6, RC equals 4.545. If R is selected as 100 kΩ, C = 45.4 µF. The values of R =
100 kΩ and C = 47 µF was selected based on standard values of resistors and capacitors. A momentary push
button switch connected to ground is connected to the trigger input with a 10-K current limiting resistor pullup to
the supply voltage. When the push button is pressed, the trigger pin goes to GND. An LED is connected to the
output pin with a current limiting resistor in series from the output of the LM555 to GND. The reset pin is not used
and was connected to the supply voltage.

8.2.2.1 Frequency Divider

The monostable circuit of Figure 11 can be used as a frequency divider by adjusting the length of the timing
cycle. Figure 18 shows the waveforms generated in a divide by three circuit.

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Typical Application (continued)

VCC = 5 V Top Trace: Input 4 V/Div.

TIME = 20 μs/DIV. Middle Trace: Output 2V/Div.
RA = 9.1 kΩ Bottom Trace: Capa citor 2V/Div.
C = 0.01 μF

Figure 18. Frequency Divider

8.2.2.2 Additional Information

Lower comparator storage time can be as long as 10 μs when pin 2 is driven fully to ground for triggering. This
limits the monostable pulse width to 10 μs minimum.
Delay time reset to output is 0.47 μs typical. Minimum reset pulse width must be 0.3 μs, typical.
Pin 7 current switches within 30 ns of the output (pin 3) voltage.

8.2.3 Application Curves

The data shown below was collected with the circuit used in the typical applications section. The LM555 was
configured in the monostable mode with a time delay of 5.17 s. The waveforms correspond to:
• Top Waveform (Yellow) – Capacitor voltage
• Middle Waveform (Green) – Trigger
• Bottom Waveform (Purple) – Output
As the trigger pin pulses low, the capacitor voltage starts charging and the output goes high. The output goes low
as soon as the capacitor voltage reaches 2/3 of the supply voltage, which is the time delay set by the R and C
value. For this example, the time delay is 5.17 s.

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Typical Application (continued)

Figure 19. Trigger, Capacitor Voltage, and Output Waveforms in Monostable Mode

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9 Power Supply Recommendations

The LM555 requires a voltage supply within 4.5 V to 16 V. Adequate power supply bypassing is necessary to
protect associated circuitry. The minimum recommended capacitor value is 0.1 μF in parallel with a 1-μF
electrolytic capacitor. Place the bypass capacitors as close as possible to the LM555 and minimize the trace
length.

10 Layout

10.1 Layout Guidelines

Standard PCB rules apply to routing the LM555. The 0.1-µF capacitor in parallel with a 1-µF electrolytic capacitor
should be as close as possible to the LM555. The capacitor used for the time delay should also be placed as
close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and
signal integrity.
Figure 20 is the basic layout for various applications.
• C1 – based on time delay calculations
• C2 – 0.01-µF bypass capacitor for control voltage pin
• C3 – 0.1-µF bypass ceramic capacitor
• C4 – 1-µF electrolytic bypass capacitor
• R1 – based on time delay calculations
• U1 – LMC555

10.2 Layout Example

Figure 20. Layout Example

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11 Device and Documentation Support

11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

LM555CM NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LM

555CM
LM555CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS SN Level-1-260C-UNLIM 0 to 70 LM
& no Sb/Br) 555CM
LM555CMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI 0 to 70 Z55
LM555CMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS SN Level-1-260C-UNLIM 0 to 70 Z55
& no Sb/Br)
LM555CMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS SN Level-1-260C-UNLIM 0 to 70 Z55
& no Sb/Br)
LM555CMX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 LM
555CM
LM555CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS SN Level-1-260C-UNLIM 0 to 70 LM
& no Sb/Br) 555CM
LM555CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS Call TI | SN Level-1-NA-UNLIM 0 to 70 LM
& no Sb/Br) 555CN

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM555CMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM555CMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM555CMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM555CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM555CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

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*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM555CMM VSSOP DGK 8 1000 210.0 185.0 35.0
LM555CMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM555CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LM555CMX SOIC D 8 2500 367.0 367.0 35.0
LM555CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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