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SN74LVC1G08
SCES217Z – APRIL 1999 – REVISED MAY 2019

SN74LVC1G08 Single 2-Input Positive-AND Gate

1 Features 3 Description
1• Available in the Ultra Small 0.64-mm 2 This single 2-input positive-AND gate is designed for
Package (DPW) With 0.5-mm Pitch 1.65-V to 5.5-V VCC operation.
• Supports 5-V VCC Operation The SN74LVC1G08 device performs the Boolean
• Inputs Accept Voltages to 5.5 V function or Y = A • B or Y = A + B in positive logic.
• Provides Down Translation to VCC The CMOS device has high output drive while
• Max tpd of 3.6 ns at 3.3 V maintaining low static power dissipation over a broad
VCC operating range.
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V The SN74LVC1G08 is available in a variety of
packages, including the ultra-small DPW package
• Ioff Supports Live Insertion, Partial-Power-Down with a body size of 0.8 mm × 0.8 mm.
Mode, and Back Drive Protection
white space
• Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II white space
• ESD Protection Exceeds JESD 22
Device Information(1)
– 2000-V Human-Body Model (A114-A)
DEVICE NAME PACKAGE BODY SIZE
– 200-V Machine Model (A115-A) SOT-23 (5) 2.9mm × 1.6mm
– 1000-V Charged-Device Model (C101) SC70 (5) 2.0mm × 1.25mm
SN74LVC1G08 X2SON (4) 0.8mm × 0.8mm
2 Applications SON (6) 1.45mm × 1.0mm
• ATCA Solutions SON (6) 1.0mm × 1.0mm
• Active Noise Cancellation (ANC) (1) For all available packages, see the orderable addendum at
• Barcode Scanner the end of the datasheet.
• Blood Pressure Monitor
• CPAP Machine
• Cable Solutions
• DLP 3D Machine Vision, Hyperspectral Imaging,
Optical Networking, and Spectroscopy
• E-Book
• Embedded PC
• Field Transmitter: Temperature or Pressure
Sensor
• Fingerprint Biometrics
• HVAC: Heating, Ventilating, and Air Conditioning
• Network-Attached Storage (NAS)
• Server Motherboard and PSU
• Software Defined Radio (SDR)
• TV: High-Definition (HDTV), LCD, and Digital
• Video Communications System
• Wireless Data Access Card, Headset, Keyboard,
Mouse, and LAN Card
• X-ray: Baggage Scanner, Medical, and Dental

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 10
2 Applications ........................................................... 1 8.1 Overview ................................................................. 10
3 Description ............................................................. 1 8.2 Functional Block Diagram ....................................... 10
4 Revision History..................................................... 2 8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
6.1 Absolute Maximum Ratings ..................................... 4
9.2 Typical Application ................................................. 11
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 5 10 Power Supply Recommendations ..................... 12
6.4 Thermal Information .................................................. 5 11 Layout................................................................... 12
6.5 Electrical Characteristics........................................... 6 11.1 Layout Guidelines ................................................. 12
6.6 Switching Characteristics, CL = 15 pF ...................... 6 11.2 Layout Example .................................................... 12
6.7 Switching Characteristics, 1.8 V and 2.5 V .............. 6 12 Device and Documentation Support ................. 13
6.8 Switching Characteristics, 3.3 V and 5 V ................. 7 12.1 Trademarks ........................................................... 13
6.9 Operating Characteristics.......................................... 7 12.2 Electrostatic Discharge Caution ............................ 13
6.10 Typical Characteristics ............................................ 7 12.3 Glossary ................................................................ 13
7 Parameter Measurement Information .................. 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 13

4 Revision History
Changes from Revision Y (April 2014) to Revision Z Page

• Added TJ(max) spec to Absolute Maximum Ratings table ..................................................................................................... 4

• Moved Tstg spec from Handling Ratings table to Absolute Maximum Ratings table. ............................................................. 4
• Renamed Handling Ratings table to ESD Ratings table ....................................................................................................... 4

Changes from Revision X (March 2014) to Revision Y Page

• Updated Handling Ratings table. ........................................................................................................................................... 4

• Added Thermal Information table. ......................................................................................................................................... 5
• Added Typical Characteristics. .............................................................................................................................................. 7
• Added Detailed Description section. .................................................................................................................................... 10
• Added Application and Implementation section. ................................................................................................................. 11
• Added Power Supply Recommendations section. .............................................................................................................. 12
• Added Layout section. ......................................................................................................................................................... 12

Changes from Revision W (July 2013) to Revision X Page

• Added Applications. ................................................................................................................................................................ 1

• Added Device Information table. ............................................................................................................................................ 1
• Moved Tstg to Handling Ratings table. .................................................................................................................................... 4

Changes from Revision V (November 2012) to Revision W Page

• Added parameter values for –40 to 125°C temperature ratings............................................................................................. 6

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5 Pin Configuration and Functions

DBV PACKAGE DCK PACKAGE DRL PACKAGE DSF PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW) (TOP VIEW)

A 1 5 VCC A 1 5 VCC A 1 6 VCC

A 1 5 VCC
B 2 B 2 5 NC
B 2 GND 3 4 Y
B 2 GND 3 4 Y
GND 3 4 Y

GND 3 4 Y
DPW PACKAGE YZP PACKAGE DRY PACKAGE
(TOP VIEW) (BOTTOM VIEW) (TOP VIEW)
B 1 5 VCC GND 3 4 Y
GND 3 A 1 6 VCC
A 2 4 Y
B 2
B 2 5 NC
A 1 5 VCC GND 3 4 Y

NC – No internal connection
See mechanical drawings for dimensions.

Pin Functions
PIN
DBV, DCK, DESCRIPTION
NAME DRY, DSF DPW
DRL, YZP
A 1 1 2 Input
B 2 2 1 Input
GND 3 3 3 Ground
Y 4 4 4 Output
VCC 5 6 5 Power pin
NC 5 Not connected

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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
(2)
VI Input voltage range –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
TJ(max) Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

MIN MAX UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
0 2000
pins (1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification
0 1000
JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions (1)

MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.4 Thermal Information

SN74LVC1G08
THERMAL METRIC (1) DBV DCK DRL DRY YZP DPW UNIT
5 PINS 5 PINS 5 PINS 6 PINS 5 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 207.6 283.1 242.9 438.8 130 340 °C/W
RθJCtop Junction-to-case (top) thermal resistance 145.2 92.3 77.5 276.8 54 215 °C/W
RθJB Junction-to-board thermal resistance 53.5 60.9 77.5 271.7 51 294 °C/W
ψJT Junction-to-top characterization parameter 37.5 1.7 9.6 83.8 1 41 °C/W
ψJB Junction-to-board characterization parameter 53.1 60.1 77.3 271.4 50 294 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance – – – – – 250 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 125°C
–40°C to 85°C
PARAMETER TEST CONDITIONS VCC RECOMMENDED UNIT
MIN TYP (1) MAX MIN TYP MAX
IOH = –100 μA 1.65 V to 5.5 V VCC – 0.1 VCC – 0.15
IOH = –4 mA 1.65 V 1.2 1.2
IOH = –8 mA 2.3 V 1.9 1.9
VOH V
IOH = –16 mA 2.4 2.4
3V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
VOL V
IOL = 16 mA 0.4 0.4
3V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
A or B
II VI = 5.5 V or GND 0 to 5.5 V ±5 ±5 μA
inputs
Ioff VI or VO = 5.5 V 0 ±10 ±10 μA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 10 μA
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 500 μA
Other inputs at VC C or GND
Ci VI = VCC or GND 3.3 V 4 4 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

6.6 Switching Characteristics, CL = 15 pF

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 1.5 7.2 0.7 4.4 0.8 3.6 0.8 3.4 ns

6.7 Switching Characteristics, 1.8 V and 2.5 V (1)

over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 4)
–40°C to 125°C –40°C to 125°C
–40°C to 85°C –40°C to 85°C
RECOMMENDED RECOMMENDED
FROM TO
PARAMETER VCC = 1.8 V VCC = 1.8 V VCC = 2.5 V VCC = 2.5 V UNIT
(INPUT) (OUTPUT)
± 0.15 V ± 0.15 V ± 0.2 V ± 0.2 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 2.4 8 2.4 10 1.1 5.5 1.1 7 ns

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

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6.8 Switching Characteristics, 3.3 V and 5 V (1)

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
–40°C to 125°C –40°C to 125°C
–40°C to 85°C –40°C to 85°C
RECOMMENDED RECOMMENDED
FROM TO
PARAMETER VCC = 3.3 V VCC = 3.3 V VCC = 5 V VCC = 5 V UNIT
(INPUT) (OUTPUT)
± 0.3 V ± 0.3 V ± 0.5 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 1 4.5 1 6 1 4 1 5 ns

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.9 Operating Characteristics

TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 21 24 26 31 pF

6.10 Typical Characteristics

6 8
TPD
7
5
6
4
5
TPD - ns
TPD - ns

3 4

3
2
2
1
1
TPD
0 0
-100 -50 0 50 100 150 0 1 2 3 4 5 6
Temperature - °C D001
Vcc - V D002

Figure 1. TPD Across Temperature at 3.3V Vcc Figure 2. TPD Across Vcc at 25°C

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7 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 15 pF 1 MW 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 15 pF 1 MW 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 50 pF 500 W 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
The SN74LVC1G08 device contains one 2-input positive AND gate device and performs the Boolean function
Y = A • B or Y = A + B . This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves
significant board space over other package options while still retaining the traditional manufacturing friendly lead
pitch of 0.5 mm.

8.2 Functional Block Diagram

8.3 Feature Description

• Wide operating voltage range.
– Operates from 1.65 V to 5.5 V.
• Allows down voltage translation.
• Inputs accept voltages to 5.5 V.
• Ioff feature allows voltages on the inputs and outputs when VCC is 0 V.

8.4 Device Functional Modes

Table 1. Function Table

INPUTS OUTPUT
A B Y
H H H
L X L
X L L

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9 Application and Implementation

9.1 Application Information
The SN74LVC1G08 is a high drive CMOS device that can be used for implementing AND logic with a high output
drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for driving
multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowing it to
translate down to VCC.

9.2 Typical Application

AND Logic Function Basic LED Driver

VCC VCC

A- uC or Logic A- uC or Logic
Y- uC or Logic
LVC1G08 LVC1G08
B- uC or Logic B- uC or Logic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings
table.
– Outputs should not be pulled above VCC.

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Typical Application (continued)

9.2.3 Application Curves

10
Icc 1.8V
Icc 2.5V
8 Icc 3.3V
Icc 5V
6

Icc - mA 4

-2
-20 0 20 40 60 80
Frequency - MHz D003

Figure 5. Icc vs Frequency

10 Power Supply Recommendations

The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then 0.01-μF or 0.022-μF capacitor
is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies
of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as
close to the power pin as possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or is more
convenient.

11.2 Layout Example

VCC Input
Unused Input Output Unused Input Output

Input

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12 Device and Documentation Support

12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC1G08DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C085, C08F, C08J, Samples
C08K, C08R, C
08T)
(C08P, C08S)
SN74LVC1G08DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C08 Samples
C08P
SN74LVC1G08DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM C08 Samples
C08P
SN74LVC1G08DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C085, C08F, C08J, Samples
C08K, C08R)
(C08H, C08P, C08S)

SN74LVC1G08DBVTE4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C08 Samples
C08P
SN74LVC1G08DCK3 ACTIVE SC70 DCK 5 3000 RoHS & SNBI Level-1-260C-UNLIM -40 to 125 (CEF, CEZ) Samples
Non-Green
SN74LVC1G08DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CE5, CEF, CEJ, CE Samples
K, CER, CET)
(CEH, CEP, CES)
SN74LVC1G08DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CE5 Samples
CES
SN74LVC1G08DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CE5 Samples
CES
SN74LVC1G08DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CE5, CEF, CEJ, CE Samples
K, CER, CET)
(CEH, CEP, CES)
SN74LVC1G08DCKTE4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CE5 Samples
CES
SN74LVC1G08DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CE5 Samples
CES
SN74LVC1G08DPWR ACTIVE X2SON DPW 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 M4 Samples

SN74LVC1G08DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CE7, CER) Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 1-Jun-2022

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC1G08DRLRG4 ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CE7, CER) Samples

SN74LVC1G08DRY2 ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CE Samples

SN74LVC1G08DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CE Samples

SN74LVC1G08DSF2 ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CE Samples

SN74LVC1G08DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CE Samples

SN74LVC1G08YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (CE, CE7) Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 1-Jun-2022

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC1G08 :

• Automotive : SN74LVC1G08-Q1
• Enhanced Product : SN74LVC1G08-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G08DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G08DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G08DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G08DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G08DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G08DCKR SC70 DCK 5 3000 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3
SN74LVC1G08DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G08DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G08DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G08DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LVC1G08DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G08DPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q3
SN74LVC1G08DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G08DRY2 SON DRY 6 5000 180.0 8.4 1.65 1.2 0.7 4.0 8.0 Q3
SN74LVC1G08DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3
SN74LVC1G08DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G08DSF2 SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3
SN74LVC1G08DSF2 SON DSF 6 5000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q3
SN74LVC1G08DSFR SON DSF 6 5000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1G08YZPR DSBGA YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G08DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
SN74LVC1G08DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G08DBVT SOT-23 DBV 5 250 210.0 185.0 35.0
SN74LVC1G08DBVT SOT-23 DBV 5 250 210.0 185.0 35.0
SN74LVC1G08DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G08DCKR SC70 DCK 5 3000 210.0 185.0 35.0
SN74LVC1G08DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G08DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G08DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G08DCKT SC70 DCK 5 250 202.0 201.0 28.0
SN74LVC1G08DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G08DPWR X2SON DPW 5 3000 205.0 200.0 33.0
SN74LVC1G08DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
SN74LVC1G08DRY2 SON DRY 6 5000 202.0 201.0 28.0
SN74LVC1G08DRY2 SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G08DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G08DSF2 SON DSF 6 5000 184.0 184.0 19.0
SN74LVC1G08DSF2 SON DSF 6 5000 202.0 201.0 28.0

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G08DSFR SON DSF 6 5000 210.0 185.0 35.0
SN74LVC1G08YZPR DSBGA YZP 5 3000 182.0 182.0 20.0

Pack Materials-Page 4
 PACKAGE OUTLINE
DPW0005A SCALE 12.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

0.85 A
B
0.75

PIN 1 INDEX AREA 0.85

0.75

0.4 MAX C

SEATING PLANE

NOTE 3

(0.1)

4X (0.05) (0.324) 0.05

0.00

2 0.25 0.1

4
NOTE 3
2X 3
2X (0.26)
0.48

5
1
0.27
0.239 4X
0.17
0.139
0.1 C A B
0.288
3X 0.05 C
0.188

4223102/D 03/2022
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.

www.ti.com
 EXAMPLE BOARD LAYOUT
DPW0005A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.78)

SYMM ( 0.1)
4X (0.42) VIA 0.05 MIN
ALL AROUND
1 TYP

5
4X (0.22)

SYMM
4X (0.26)
(0.48)
3

2 4

(R0.05) TYP
SOLDER MASK
4X (0.06) OPENING, TYP
( 0.25)
(0.21) TYP METAL UNDER
EXPOSED METAL SOLDER MASK
CLEARANCE TYP

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED
SCALE:60X

4223102/D 03/2022
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DPW0005A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

4X (0.42) 4X (0.06)

5
4X (0.22) 1

( 0.24)

4X (0.26)
SYMM
(0.21) (0.48)
TYP
SOLDER MASK
EDGE 3

2
4

(R0.05) TYP
SYMM

(0.78)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X

4223102/D 03/2022
NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
YZP0005 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

C
0.5 MAX

SEATING PLANE
0.19
0.15 0.05 C
BALL TYP

0.5 TYP

SYMM
1
TYP
B D: Max = 1.418 mm, Min =1.358 mm
0.5
TYP E: Max = 0.918 mm, Min =0.858 mm
A

0.25
5X 1 2
0.21
0.015 C A B
SYMM

4219492/A 05/2017
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
5X ( 0.23)
1 2

(0.5) TYP

SYMM
B

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23)

OPENING SOLDER MASK
OPENING

( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219492/A 05/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

5X ( 0.25)
(R0.05) TYP
1 2

(0.5)
TYP

B SYMM

METAL SYMM
TYP

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4219492/A 05/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
 PACKAGE OUTLINE
DRL0005A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
5

2X 0.5

1.7
2X 1
1.5
NOTE 3

4 2X 0 -10
3

1.3 0.3 0.05

B 5X TYP
1.1 0.1 0.00

2X 4 -10

0.6 MAX C

SEATING PLANE
0.18
5X 0.05 C
0.08
SYMM

SYMM

0.27
5X
0.15
0.4 0.1 C A B
5X
0.2 0.05 C
4220753/D 07/2024
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67) SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4220753/D 07/2024

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67)
SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4220753/D 07/2024

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.15
0.1 C A B 4X 0 -12 0.1
(0.9) TYP
NOTE 5 0.0

4X 4 -14

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/F 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.
6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.25mm per side

www.ti.com
 EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/F 08/2024

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/F 08/2024

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/K 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4207181/G
 PACKAGE OUTLINE
DRY0006A SCALE 8.500
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05 A
B
0.95

PIN 1 INDEX AREA

1.5
1.4

0.6 MAX C

SEATING PLANE
0.05
0.00 0.08 C

3X 0.6
SYMM
(0.127) TYP
(0.05) TYP

3
4
4X
0.5
SYMM
2X
1

6
1
0.25
6X
0.4 0.15
0.3 0.1 C A B
0.05 C
PIN 1 ID
(OPTIONAL) 0.35
5X
0.25
4222894/A 01/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.35)
5X (0.3)

1 6

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP
(0.6)

LAND PATTERN EXAMPLE

1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

EXPOSED
EXPOSED
METAL
METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
DEFINED SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4222894/A 01/2018
NOTES: (continued)

3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.35) 5X (0.3)

1 6

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP (0.6)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X

4222894/A 01/2018

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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 PACKAGE OUTLINE
DSF0006A SCALE 10.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05
B A
0.95

PIN 1 INDEX AREA

1.05
0.95

0.4 MAX C

SEATING PLANE

0.05 C

(0.11) TYP
SYMM 0.05
0.00

3
4

2X SYMM
0.7
4X
0.35
6
1
0.22
6X
0.12
(0.1)
PIN 1 ID 0.45 0.07 C B A
6X
0.35 0.05 C

4220597/B 06/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.

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 EXAMPLE BOARD LAYOUT
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.6)
(R0.05) TYP
1
6X (0.17) 6

SYMM

4X (0.35)

4
3

SYMM

(0.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:40X

0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND

EXPOSED METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220597/B 06/2022

NOTES: (continued)

4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.6)
(R0.05) TYP
1
6X (0.15) 6

SYMM

4X (0.35)

4
3

SYMM

(0.8)

SOLDER PASTE EXAMPLE

BASED ON 0.09 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:40X

4220597/B 06/2022

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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