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SN74LVC2G04
SCES195N – APRIL 1999 – REVISED AUGUST 2015

SN74LVC2G04 Dual Inverter Gate

1 Features Amplifiers (TMA)
1• Available in the Texas Instruments • Vector Signal Analyzers and Generators
NanoFree™ Package • Video Converencing: IP-Based HD
• Supports 5-V VCC Operation • WiMAX and Wireless Infrastructure Equipment
• Inputs Accept Voltages to 5.5 V • Wireless Communications Testers and Wireless
• Max tpd of 4.1 ns at 3.3 V Repeaters
• Low Power Consumption, 10-μA Max ICC • xDSL Modems and DSLAM
• ±24-mA Output Drive at 3.3 V
3 Description
• Typical VOLP (Output Ground Bounce)
This dual inverter is designed for 1.65-V to 5.5-V VCC
<0.8 V at VCC = 3.3 V, TA = 25°C
operation. The SN74LVC2G04 device performs the
• Typical VOHV (Output VOH Undershoot) Boolean function Y = A.
>2 V at VCC = 3.3 V, TA = 25°C
NanoFree package technology is a major
• Ioff Supports Partial-Power-Down Mode Operation breakthrough in IC packaging concepts, using the die
• Latch-Up Performance Exceeds 100 mA Per as the package.
JESD 78, Class II
This device is fully specified for partial-power-down
• ESD Protection Exceeds JESD 22 applications using Ioff. The Ioff circuitry disables the
– 2000-V Human-Body Model (A114-A) outputs, preventing damaging current backflow
– 200-V Machine Model (A115-A) through the device when it is powered down.
– 1000-V Charged-Device Model (C101) Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications SN74LVC2G04DBV SOT-23 (6) 2.90 mm × 1.60 mm
• IP Phones: Wired and Wireless SN74LVC2G04DCK SC70 (6) 2.00 mm × 1.25 mm
• Optical Modules SN74LVC2G04DRL SOT (6) 1.60 mm × 1.20 mm
• Optical Networking: EPON and Video Over Fiber SN74LVC2G04YZP DSBGA (6) 1.41 mm × 0.91 mm
• Point-to-Point Microwave Backhaul (1) For all available packages, see the orderable addendum at
• Power: Telecom DC/DC Module: Analog and the end of the datasheet.
Digital
Logic Diagram (Positive Logic)
• Private Branch Exchanges (PBX)
1 6
• TETRA Base Exchanges 1A 1Y
• Telecom Base Band Units
• Telecom Shelters: Power Distribution Units (PDU), 3 4
2A 2Y
Power Monitoring Units (PMU), Wireless Battery
Monitoring, Remote Electrical Tilt Units (RET),
Remote Radio Units (RRU), Tower Mounted

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G04
SCES195N – APRIL 1999 – REVISED AUGUST 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 8
2 Applications ........................................................... 1 8.3 Feature Description................................................... 8
3 Description ............................................................. 1 8.4 Device Functional Modes.......................................... 8
4 Revision History..................................................... 2 9 Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................... 9
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Power Supply Recommendations ..................... 10
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 11
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 11
6.4 Thermal Information .................................................. 5 11.2 Layout Example .................................................... 11
6.5 Electrical Characteristics........................................... 5 12 Device and Documentation Support ................. 12
6.6 Switching Characteristics .......................................... 6 12.1 Documentation Support ........................................ 12
6.7 Operating Characteristics.......................................... 6 12.2 Community Resources.......................................... 12
6.8 Typical Characteristics .............................................. 6 12.3 Trademarks ........................................................... 12
7 Parameter Measurement Information .................. 7 12.4 Electrostatic Discharge Caution ............................ 12
12.5 Glossary ................................................................ 12
8 Detailed Description .............................................. 8
8.1 Overview ................................................................... 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 12

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision M (November 2013) to Revision N Page

• Removed the Ordering Information table, added the Device Information table, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1

Changes from Revision L (January 2007) to Revision M Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

• Added ESD warning .............................................................................................................................................................. 4
• Updated operating temperature range. .................................................................................................................................. 4

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5 Pin Configuration and Functions

DBV Package
6-Pin SOT-23 DCK Package
Top View 6-Pin SC70
Top View

1A 1 6 1Y 1A 1 6 1Y

GND 2 5 VCC
GND 2 5 VCC
2A 3 4 2Y

2A 3 4 2Y

DRL Package YZP Package

6-Pin SOT 6-Pin DSBGA
Top View Bottom View

1A 1 6 1Y 2A 3 4 2Y
GND 2 5 VCC GND 2 5 VCC

2A 3 4 2Y 1A 1 6
1Y

Pin Functions (1)

PIN
I/O DESCRIPTION
NAME NO.
1A 1 I Inverter 1 input
1Y 6 O Inverter 1 output
2A 3 I Inverter 2 input
2Y 4 O Inverter 2 output
GND 2 — Ground
VCC 5 — Power

(1) See Mechanical, Packaging, and Orderable Information for dimensions.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
(2)
VI Input voltage –0.5 6.5 V
VO Voltage applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) +2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
+1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

(1)
See .
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Recommended Operating Conditions (continued)

See (1).
MIN MAX UNIT
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

SN74LVC2G04
THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) DRL (SOT) YZP (DSBGA) UNIT
6 PINS 6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 165 259 142 123 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOH = –100 μA 1.65 V to 5.5 V VCC – 0.1
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
VOH V
IOH = –16 mA 2.4
3V
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100 μA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
VOL V
IOL = 16 mA 0.4
3V
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
II A inputs VI = 5.5 V or GND 0 to 5.5 V ±5 μA
Ioff VI or VO = 5.5 V 0 ±10 μA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 μA
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 μA
Other inputs at VCC or GND
Ci VI = VCC or GND, –40°C to 85°C 3.3 V 3.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

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6.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
–40°C to 85°C 3.1 8 1.5 4.4 1.2 4.1 1 3.2 ns
tpd A Y
–40°C to 125°C 3.1 8 1.5 4.9 1.2 4.6 1 3.7 ns

6.7 Operating Characteristics

TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 14 14 14 16 pF

6.8 Typical Characteristics

5.0

4.5 VCC: 4.5 V

VIH: 3.10 V
4.0 VIL: 1.35 V
VOH vs IOH 1Y
3.5

3.0

2.5
VOH (V)

2.0

1.5

1.0

0.5

0.0 -40 C
25 C
-0.5 85 C

-1.0
0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

IOH (mA)
Figure 1. IOH vs VOH

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7 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + VD
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH − VD
Output VM
S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
The SN74LVC2G04 contains two identical inverters that operate from 1.65-V to 5.5-V VCC. Each inverter has a
balanced output capable of outputting 32 mA at VCC = 4.5 V. The overvoltage tolerant inputs allow for down-
translation of up to 6.5 V, and the partial power-off feature ensures that the inputs and outputs can be any value
from –0.5 V to 6.5 V when VCC is 0 V

8.2 Functional Block Diagram

1 6
1A 1Y

3 4
2A 2Y

8.3 Feature Description

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device supports 5-V VCC operation and up to 5.5-V inputs. It has a low propagation delay of only 4.1 ns at
3.3 V.
Power consumption is low with only 10-μA Max ICC. Balanced drive output at 3.3 V can put out ±24-mA.
Typical output ground bounce is less than 0.8 V at 3.3-V VCC and typical output undershoot is greater than 2 V at
3.3-V VCC.
This device supports partial-power-down mode operation.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SN74LVC2G04.

Table 1. Function Table (Each Inverter)

INPUT OUTPUT
A Y
H L
L H

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC2G04 contains two logic inverters. It can be used in a wide variety of applications, with this being
one example. Because this part has overvoltage tolerant inputs, it can be used for down translating logic levels.
This example explains the method used for down-translating with this logic gate.

9.2 Typical Application

VCC

1A 1Y
X 1 6 X

2A 2Y
Y 3 4 Y

Figure 3. Application Schematic

9.2.1 Design Requirements

The inputs, X and Y in Figure 3, to this device can be any value from –0.5 V to 6.5 V, according to Absolute
Maximum Ratings. Because the input limits are not associated with VCC, down-translation is simple. The output
voltage is selected with VCC, and so long as the input logic voltage is larger than VIH, found in Recommended
Operating Conditions, the output will trigger properly.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions
– For rise time and fall time specifications, see (Δt/ΔV) in the Recommended Operating Conditions
table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended
Operating Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings
table.
– Outputs should not be pulled above VCC.

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Typical Application (continued)

9.2.3 Application Curve
There is a slight delay from input to output in addition to the voltage change. Figure 4 shows the expected output
of the SN74LVC2G04 when an input is switched from 0 to 5 V and VCC is set at 1.8 V. With VCC set to 1.8 V, the
output switches at 1.17 V (0.65 × VCC), and therefore the input can be anything from 1.18 V up to 6.5 V and the
SN74LVC2G04 will work perfectly.
6

4
Voltage (V)
3

0 VIN
VOUT
±1
0 1 2 3 4 5 6 7 8 9 10
Time (ns) C001

Figure 4. Simulated Voltage Down-Translation from 5-V Input to 1.8-V Output With t pd = 3.4 ns.

10 Power Supply Recommendations

The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.

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11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 5 are the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient.

11.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 5. Layout Diagram

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC2G04DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C045, C04F, C04K, Samples
C04R)
SN74LVC2G04DBVRE4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C04F, C04R) Samples

SN74LVC2G04DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C04F, C04R) Samples

SN74LVC2G04DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C045, C04F, C04K, Samples
C04R)
SN74LVC2G04DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C04F, C04R) Samples

SN74LVC2G04DCK3 ACTIVE SC70 DCK 6 3000 RoHS & SNBI Level-1-260C-UNLIM -40 to 125 CCZ Samples
Non-Green
SN74LVC2G04DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CC5, CCF, CCJ, CC Samples
K, CCR)
SN74LVC2G04DCKRE4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CC5 Samples

SN74LVC2G04DCKRG4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CC5 Samples

SN74LVC2G04DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CC5, CCF, CCJ, CC Samples
K, CCR)
SN74LVC2G04DCKTG4 ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CC5 Samples

SN74LVC2G04DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (1K7, CC7, CCR) Samples

SN74LVC2G04YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 (CC7, CCN) Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".

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RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC2G04 :

• Enhanced Product : SN74LVC2G04-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC2G04DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC2G04DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G04DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G04DBVRG4 SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G04DBVT SOT-23 DBV 6 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G04DBVT SOT-23 DBV 6 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC2G04DBVTG4 SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G04DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G04DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC2G04DCKR SC70 DCK 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3
SN74LVC2G04DCKRG4 SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G04DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC2G04DCKT SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G04DCKT SC70 DCK 6 250 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3
SN74LVC2G04DCKTG4 SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G04DRLR SOT-5X3 DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC2G04DRLR SOT-5X3 DRL 6 4000 180.0 8.4 2.0 1.8 0.75 4.0 8.0 Q3
SN74LVC2G04YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC2G04DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC2G04DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC2G04DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0
SN74LVC2G04DBVRG4 SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC2G04DBVT SOT-23 DBV 6 250 202.0 201.0 28.0
SN74LVC2G04DBVT SOT-23 DBV 6 250 180.0 180.0 18.0
SN74LVC2G04DBVTG4 SOT-23 DBV 6 250 180.0 180.0 18.0
SN74LVC2G04DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC2G04DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC2G04DCKR SC70 DCK 6 3000 202.0 201.0 28.0
SN74LVC2G04DCKRG4 SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC2G04DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC2G04DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC2G04DCKT SC70 DCK 6 250 202.0 201.0 28.0
SN74LVC2G04DCKTG4 SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC2G04DRLR SOT-5X3 DRL 6 4000 202.0 201.0 28.0
SN74LVC2G04DRLR SOT-5X3 DRL 6 4000 210.0 185.0 35.0
SN74LVC2G04YZPR DSBGA YZP 6 3000 220.0 220.0 35.0

Pack Materials-Page 3
 PACKAGE OUTLINE
DRL0006A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
6

4X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3 0.3 0.05

B 6X TYP
1.1 0.1 0.00

0.6 MAX
C

SEATING PLANE
0.18
6X 0.05 C
0.08 SYMM

SYMM

0.27
6X
0.15
0.1 C A B
0.4
6X 0.05
0.2
4223266/C 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4223266/C 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4223266/C 12/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214840/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/C 06/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/C 06/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
YZP0006 SCALE 9.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

0.5 MAX C

SEATING PLANE
0.19 BALL TYP 0.05 C
0.15

0.5 TYP

SYMM
1 D: Max = 1.418 mm, Min =1.358 mm
B TYP
0.5 E: Max = 0.918 mm, Min =0.858 mm
TYP
A

0.25 1 2
6X SYMM
0.21
0.015 C A B

4219524/A 06/2014

NOTES: NanoFree Is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0006 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
6X ( 0.225)
1 2

(0.5) TYP

B SYMM

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

( 0.225) 0.05 MAX 0.05 MIN METAL

METAL UNDER
MASK

SOLDER MASK ( 0.225)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4219524/A 06/2014

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0006 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

6X ( 0.25)
(R0.05) TYP
1 2
A

(0.5)
TYP

B SYMM

METAL
TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4219524/A 06/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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