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SN74LVC2G07
SCES308L – AUGUST 2001 – REVISED MAY 2015

SN74LVC2G07 Dual Buffer and Driver With Open-Drain Outputs

1 Features 3 Description
•
1 Dual Open-Drain Buffer Configuration This dual buffer and driver is designed for 1.65-V to
5.5-V VCC operation. The output of the
• -24-mA Output Drive at 3.3 V SN74LVC2G07 device is open drain and can be
• Support Translation-Up and Down connected to other open-drain outputs to implement
• Available in the Texas Instruments active-low wired-OR or active-high wired-AND
NanoFree™ Package functions. The maximum sink current is 32 mA.
• Supports 5-V VCC Operation NanoFree package technology is a major
• Inputs and Open-Drain Outputs Accept Voltages breakthrough in IC packaging concepts, using the die
Up to 5.5 V as the package.
• Max tpd of 3.7 ns at 3.3 V This device is fully specified for partial-power-down
• Low Power Consumption, 10-μA Max ICC applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
• Typical VOLP (Output Ground Bounce) through the device when it is powered down.
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) Device Information(1)
>2 V at VCC = 3.3 V, TA = 25°C PART NUMBER PACKAGE BODY SIZE (NOM)
• Ioff Supports Live Insertion, Partial-Power-Down SOT-23 (6) 2.90 mm × 1.60 mm
Mode, and Back-Drive Protection SC70 (6) 2.00 mm × 1.25 mm
• Latch-Up Performance Exceeds 100 mA SN74LVC2G07 DRY SON (6) 1.45 mm × 1.00 mm
Per JESD 78, Class II DSF SON (6) 1.00 mm × 1.00 mm
• ESD Protection Exceeds JESD 22 DSBGA (6) 1.41 mm × 0.91 mm
– 2000-V Human-Body Model (A114-A) (1) For all available packages, see the orderable addendum at
– 200-V Machine Model (A115-A) the end of the datasheet.

– 1000-V Charged-Device Model (C101) Functional Block Diagram

2 Applications 1A
1 6
1Y
• Blu-ray Players and Home Theaters
• DVD Recorders and Players 2A
3 4
2Y
• Desktops or Notebook PCs
• Digital Video Cameras (DVC)
• Embedded PCs
• GPS: Personal Navigation Devices
• Mobile Phones
• Network Projector Front Ends
• Portable Media Players
• Solid State Drive (SSD): Enterprise
• High-Definition (HDTV)
• Tablet: Enterprise
• Audio Dock: Portable
• DLP Front Projection System

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G07
SCES308L – AUGUST 2001 – REVISED MAY 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................... 8
2 Applications ........................................................... 1 8.2 Functional Block Diagram ......................................... 8
3 Description ............................................................. 1 8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 9 Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
6 Specifications......................................................... 4
9.2 Typical Application ................................................... 9
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4 10 Power Supply Recommendations ..................... 10
6.3 Recommended Operating Conditions ...................... 4 11 Layout................................................................... 10
6.4 Thermal Information .................................................. 5 11.1 Layout Guidelines ................................................. 10
6.5 Electrical Characteristics........................................... 5 11.2 Layout Examples................................................... 10
6.6 Switching Characteristics from –40°C to 85°C ......... 5 12 Device and Documentation Support ................. 11
6.7 Switching Characteristics from –40°C to 125°C ....... 5 12.1 Documentation Support ........................................ 11
6.8 Operating Characteristics.......................................... 5 12.2 Community Resources.......................................... 11
6.9 Typical Characteristics .............................................. 6 12.3 Trademarks ........................................................... 11
7 Parameter Measurement Information .................. 7 12.4 Electrostatic Discharge Caution ............................ 11
7.1 (Open-Drain) ............................................................. 7 12.5 Glossary ................................................................ 11
8 Detailed Description .............................................. 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 11

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision K (November 2013) to Revision L Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision J (August 2012) to Revision K Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

• Updated operating temperature range. .................................................................................................................................. 4

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5 Pin Configuration and Functions

DBV Package
6-Pin SOT-23 YZP Package
Top View 6-Pin DSBGA
Bottom View

1A 1 6 1Y
2A 3 4 2Y

GND 2 5 VCC
GND 2 5 VCC
1A 1 6 1Y

2A 3 4 2Y
DRY Package
6-Pin SON
Top View
DCK Package
6-Pin SC70 1A 1 6 1Y
Top View
GND 2 5 VCC
1A 1 6 1Y
2A 3 4 2Y

GND 2 5 VCC

DSF Package
2A 3 4 2Y 6-Pin SON
Top View

1A 1 6 1Y

GND 2 5 VCC

2A 3 4 2Y

Pin Functions
PIN
I/O DESCRIPTION
NAME NO
1A 1 I Input 1
GND 2 — Ground
2A 3 I Input 2
2Y 4 O Open-drain output 2
VCC 5 — Power pin
1Y 6 O Open-drain output 1

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
(2)
VI Input voltage –0.5 6.5 V
VO Voltage applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage applied to any output in the high or low state (2) (3) –0.5 6.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage Temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) +2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
+1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions (1)

MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 5.5 V
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Recommended Operating Conditions(1) (continued)

MIN MAX UNIT
TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

SN74LVC2G07
THERMAL METRIC (1) SOT-23 SC70 DRY (SON) DSBGA DSF (SON) UNIT
6 PINS 6 PINS 6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 165 259 234 123 300 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP (1) MAX MIN TYP (1) MAX
IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
VOL V
IOL = 16 mA 0.4 0.4
3V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
II A inputs VI = 5.5 V or GND 0 to 5.5 V ±5 ±5 μA
Ioff VI or VO = 5.5 V 0 ±10 ±10 μA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 10 μA
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 500 μA
Other inputs at VCC or GND
CI VI = VCC or GND 3.3 V 3.5 3.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

6.6 Switching Characteristics from –40°C to 85°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C to 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 1.5 8.6 1 4.4 1 3.7 1 2.9 ns

6.7 Switching Characteristics from –40°C to 125°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C to 125°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 1.5 8.6 1 4.9 1 4.2 1 3.4 ns

6.8 Operating Characteristics

TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 3 3 4 4 pF

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6.9 Typical Characteristics

2.5
TPD

1.5

TPD - ns
1

0.5

0
-100 -50 0 50 100 150
Temperature - °C D001

Figure 1. TPD Across Temperature at 3.3V Vcc

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7 Parameter Measurement Information

7.1 (Open-Drain)
VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPZL (see Notes E and F) VLOAD
CL
RL tPLZ (see Notes E and G) VLOAD
(see Note A)
tPHZ/tPZH VLOAD

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
VOL S1 at VLOAD VOL + V∆
(see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – V∆
Output VM VM VM
VOL S1 at GND ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. Because this device has open-drain outputs, tPLZ and tPZL are the same as tPD.
F. tPZL is measured at VM.
G. tPLZ is measured at VOL + V∆.
H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
The SN74LVC2G07 device contains two open drain buffer with a maximum sink current of 32 mA. This device is
fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing
damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

1 6
1A 1Y

3 4
2A 2Y

8.3 Feature Description

The open-drain configuration means that the device cannot provide its own output drive current; instead, it relies
on pullup resistors to provide the "high" bus state. It can only drive the bus low. In the "Hi-Z" state, the
SN74LVC2G07 acts as an open circuit and allows the external pullup to pull the bus high. Therefore, the pullup
voltage determines the output level and therefore the SN74LVC2g07 can be used for up or down-translation. The
device can sink 24 mA at 3 V while retaining an output voltage (VOL) of 0.55 V or lower.

8.4 Device Functional Modes

Table 1 shows the device functional modes of the SN74LVC2G07 device.

Table 1. Function Table

INPUT OUTPUT
A Y
L L
H H

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC2G07 is a high-drive CMOS device that can be used to implement a high output drive buffer, such
as an LED application. It can sink 32 mA of current at 4.5 V making it ideal for high-drive and wired-OR/AND
functions. The inputs are 5.5 V tolerant allowing it to translate up and down to VCC.

9.2 Typical Application

VCC
0.1 F

1A 1Y

From
MCU
2A 2Y

GND
Figure 3. Typical Application

9.2.1 Design Requirements

1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above 5.5 V.

9.2.2 Detailed Design Procedure

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions should be considered to prevent ringing.

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Typical Application (continued)

9.2.3 Application Curve

6
TPD

TPD - ns
3

0
0 1 2 3 4 5 6
Vcc - V D002

Figure 4. TPD Across VCC at 25°C

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient.

11.2 Layout Examples

VCC Input
Unused Input Output Unused Input Output

Input

Figure 5. Layout Examples for SN74LVC2G07

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC2G07DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C075, C07F, C07K,
C07R)
SN74LVC2G07DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C07F, C07R)

SN74LVC2G07DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CV5, CVF, CVJ, CV
K, CVR)
SN74LVC2G07DCKRE4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CV5

SN74LVC2G07DCKRG4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CV5

SN74LVC2G07DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CV5, CVF, CVJ, CV
K, CVR)
SN74LVC2G07DCKTG4 ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CV5

SN74LVC2G07DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CV

SN74LVC2G07DSF2 ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CV

SN74LVC2G07DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CV

SN74LVC2G07YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 (CV7, CVN)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC2G07 :

• Enhanced Product: SN74LVC2G07-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC2G07DBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC2G07DBVRG4 SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G07DCKR SC70 DCK 6 3000 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3
SN74LVC2G07DCKRG4 SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G07DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC2G07DCKT SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G07DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC2G07DCKT SC70 DCK 6 250 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3
SN74LVC2G07DCKTG4 SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G07DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC2G07DSF2 SON DSF 6 5000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q3
SN74LVC2G07DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC2G07YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Mar-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC2G07DBVR SOT-23 DBV 6 3000 210.0 185.0 35.0
SN74LVC2G07DBVRG4 SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC2G07DCKR SC70 DCK 6 3000 210.0 185.0 35.0
SN74LVC2G07DCKRG4 SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC2G07DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC2G07DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC2G07DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC2G07DCKT SC70 DCK 6 250 202.0 201.0 28.0
SN74LVC2G07DCKTG4 SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC2G07DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC2G07DSF2 SON DSF 6 5000 210.0 185.0 35.0
SN74LVC2G07DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74LVC2G07YZPR DSBGA YZP 6 3000 220.0 220.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214840/G 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/G 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/G 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
YZP0006 SCALE 9.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

0.5 MAX C

SEATING PLANE
0.19 BALL TYP 0.05 C
0.15

0.5 TYP

SYMM
1 D: Max = 1.418 mm, Min =1.357 mm
B TYP
0.5 E: Max = 0.918 mm, Min =0.857 mm
TYP
A

0.25 1 2
6X SYMM
0.21
0.015 C A B

4219524/A 06/2014

NOTES: NanoFree Is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0006 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
6X ( 0.225)
1 2

(0.5) TYP

B SYMM

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

( 0.225) 0.05 MAX 0.05 MIN METAL

METAL UNDER
MASK

SOLDER MASK ( 0.225)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4219524/A 06/2014

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0006 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

6X ( 0.25)
(R0.05) TYP
1 2
A

(0.5)
TYP

B SYMM

METAL
TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4219524/A 06/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
 PACKAGE OUTLINE
DCK0006A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B
1.1 A 1.1
PIN 1 0.8
INDEX AREA

1
6

4X 0.65
2.15
1.3
2 1.85

0.30 3
6X
0.15
0.1 C A B 4X 0 -12 0.1
TYP
0.0
NOTE 5

4X 4 -14

0.15
0.22
GAGE PLANE TYP
0.08

8
TYP 0.46
0 TYP SEATING PLANE
0.26

4214835/C 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Falls within JEDEC MO-203 variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
DCK0006A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
6X (0.9)

1
6X (0.4) 6

SYMM
2
4X (0.65)

4
3

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214835/C 08/2024

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DCK0006A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
6X (0.9)
1
6X (0.4) 6

SYMM
2
4X(0.65)

4
3

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214835/C 08/2024

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4207181/G
 PACKAGE OUTLINE
DRY0006A SCALE 8.500
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05 A
B
0.95

PIN 1 INDEX AREA

1.5
1.4

0.6 MAX C

SEATING PLANE
0.05
0.00 0.08 C

3X 0.6
SYMM
(0.127) TYP
(0.05) TYP

3
4
4X
0.5
SYMM
2X
1

6
1
0.25
6X
0.4 0.15
0.3 0.1 C A B
0.05 C
PIN 1 ID
(OPTIONAL) 0.35
5X
0.25
4222894/A 01/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.35)
5X (0.3)

1 6

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP
(0.6)

LAND PATTERN EXAMPLE

1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

EXPOSED
EXPOSED
METAL
METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
DEFINED SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4222894/A 01/2018
NOTES: (continued)

3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.35) 5X (0.3)

1 6

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP (0.6)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X

4222894/A 01/2018

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DSF0006A SCALE 10.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05
B A
0.95

PIN 1 INDEX AREA

1.05
0.95

0.4 MAX C

SEATING PLANE

0.05 C

(0.11) TYP
SYMM 0.05
0.00

3
4

2X SYMM
0.7
4X
0.35
6
1
0.22
6X
0.12
(0.1)
PIN 1 ID 0.45 0.07 C B A
6X
0.35 0.05 C

4220597/B 06/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.

www.ti.com
 EXAMPLE BOARD LAYOUT
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.6)
(R0.05) TYP
1
6X (0.17) 6

SYMM

4X (0.35)

4
3

SYMM

(0.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:40X

0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND

EXPOSED METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220597/B 06/2022

NOTES: (continued)

4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.6)
(R0.05) TYP
1
6X (0.15) 6

SYMM

4X (0.35)

4
3

SYMM

(0.8)

SOLDER PASTE EXAMPLE

BASED ON 0.09 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:40X

4220597/B 06/2022

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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