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SN74LVC1G19
SCES464G – JUNE 2003 – REVISED AUGUST 2015

SN74LVC1G19 1-of-2 Decoder and Demultiplexer

1 Features 2 Applications
1• Available in the Texas Instruments • AV Receivers
NanoFree™ Package • Audio Docks: Portable
• Supports 5-V VCC Operation • Blu-ray® Players and Home Theater
• Inputs Accept Voltages to 5.5 V • MP3 Players/Recorders
• Supports Down Translation to VCC • Personal Digital Assistants (PDAs)
• Maximum tpd of 4 ns at 3.3 V • Power: Telecom/Server AC/DC Supply: Single
• Low Power Consumption, 10-µA Maximum ICC Controller: Analog and Digital
• ±24-mA Output Drive at 3.3 V • Solid State Drives (SSDs): Client and Enterprise
• VOLP (Output Ground Bounce) • TVs: LCD/Digital and High-Definition (HDTVs)
<0.8 V Typical at VCC = 3.3 V, TA = 25°C • Tablets: Enterprise
• VOHV (Output VOH Undershoot) • Video Analytics: Server
>2 V Typical at VCC = 3.3 V, TA = 25°C • Wireless Headsets, Keyboards, and Mice
• Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection 3 Description
• Latch-Up Performance Exceeds 100 mA Per This decoder/demultiplexer is designed for 1.65-V to
JESD 78, Class II 5.5-V VCC operation.
• ESD Protection Exceeds JESD 22 The SN74LVC1G19 device is a 1-of-2 decoder /
– 2000-V Human Body Model (A114-A) demultiplexer. When E input is high, the decoder will
– 200-V Machine Model (A115-A) be disabled and both outputs will be high. When E
input is low, the A input selects which output will be
– 1000-V Charged-Device Model (C101) low.
This device is fully specified for partial-power-down
applications using Ioff.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1G19DBV SOT-23 (6) 2.9 mm × 1.6 mm
SN74LVC1G19DCK SC70 (6) 2.0 mm × 1.25 mm
SN74LVC1G19DRL SOT (6) 1.6 mm × 1.2 mm
SN74LVC1G19DRY SON (6) 1.45 mm × 1.0 mm
SN74LVC1G19YZP DSBGA (6) 1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Schematic

Y0

Y1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 10
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 10
3 Description ............................................................. 1 8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
6 Specifications......................................................... 4
9.2 Typical Application ................................................. 11
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4 10 Power Supply Recommendations ..................... 12
6.3 Recommended Operating Conditions ...................... 5 11 Layout................................................................... 12
6.4 Thermal Information .................................................. 5 11.1 Layout Guidelines ................................................. 12
6.5 Electrical Characteristics........................................... 6 11.2 Layout Example .................................................... 12
6.6 Switching Characteristics, CL = 15 pF ...................... 6 12 Device and Documentation Support ................. 13
6.7 Switching Characteristics, CL = 30 pF or 50 pF........ 6 12.1 Community Resources.......................................... 13
6.8 Operating Characteristics.......................................... 6 12.2 Trademarks ........................................................... 13
6.9 Typical Characteristics .............................................. 7 12.3 Electrostatic Discharge Caution ............................ 13
7 Parameter Measurement Information .................. 8 12.4 Glossary ................................................................ 13
8 Detailed Description ............................................ 10 13 Mechanical, Packaging, and Orderable
Information ........................................................... 13

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (July 2012) to Revision G Page

• Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
• Updated Ioff in Features. ......................................................................................................................................................... 1

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5 Pin Configuration and Functions

DBV Package
6-Pin SOT-23 DCK Package
Top View 6-Pin SC70
Top View

A 1 6 Y0 A 1 6 Y0

GND 2 5 VCC
GND 2 5 VCC
E 3 4 Y1
E 3 4 Y1

DRY Package
6-Pin SON
DRL Package Top View
6-Pin SOT
Top View A 1 6 Y0

A 1 6 Y0 GND 2 5 VCC

GND 2 5 VCC E 3 4 Y1

E 3 4 Y1

YZP Package
6-Pin DSBGA
Bottom View

E 3 4 Y1
GND 2 5 VCC
A 1 6 Y0

Pin Functions (1)

PIN
I/O DESCRIPTION
NAME NO.
A 1 I Adress input, selects which output goes low.
GND 2 — Ground
E 3 I Enable input, active low
Y1 4 O Output 1, low when selected by A high and E low
VCC 5 — Power pin
Y0 6 O Output 0, low when selected by A low and E low

(1) See mechanical drawings for dimensions

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
(2)
VI Input voltage –0.5 6.5 V
VO Voltage applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

VALUE UNIT
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000
Electrostatic Charged-Device Model (CDM), per JEDEC specification JESD22-C101, all
VESD ±1000 V
discharge pins (2)
Machine model ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TA Operating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.

6.4 Thermal Information

SN74LVC1G19
DBV (SOT- DCK (SC70) DRL (SOT) DRY (SON) YZP
THERMAL METRIC (1) UNIT
23) (DSBGA)
6 PINS 6 PINS 6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 165 259 142 234 123 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
VOH V
IOH = –16 mA 2.4
3V
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100 µA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
VOL V
IOL = 16 mA 0.4
3V
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
II VI = 5.5 V or GND 0 to 5.5 V ±1 µA
Ioff VI or VO = 5.5 V 0 ±10 µA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 µA
ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 µA
CI VI = VCC or GND 3.3 V 3.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

6.6 Switching Characteristics, CL = 15 pF

over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or E Y 2.5 16.1 1.5 5.9 1 4 0.5 2.8 ns

6.7 Switching Characteristics, CL = 30 pF or 50 pF

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or E Y 3.2 16.1 1.5 6.5 1.1 5.2 0.5 3.9 ns

6.8 Operating Characteristics

TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 15.5 16 16 18 pF

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6.9 Typical Characteristics

16.00 16.00

12.00 12.00
Max tpd (ns)

Max tpd (ns)

8.00 8.00

4.00 4.00
tpd (Œ}u}Œ"š}z tpd (Œ}u}Œ"š}z
CL= 15 pF CL= 30 pF to 50 pF
0.00 0.00
0.00 1.00 2.00 3.00 4.00 5.00 6.00 0.00 1.00 2.00 3.00 4.00 5.00 6.00
VCC Supply Voltage (V) C001 VCC Supply Voltage (V) C001

Figure 1. Time Propagation Delay vs VCC, CL= 15 pF Figure 2. Time Propagation Delay vs VCC, CL= 30 pF or
50 pF

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7 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 15 pF 1 MW 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 15 pF 1 MW 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 50 pF 500 W 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
This decoder/demultiplexer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G19 device is a 1-of-2 decoder/demultiplexer. This device decodes the 1-bit address on input A
and places a logic low on the matching address output, Y0 or Y1 , when the enable (E) input signal is low.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

8.2 Functional Block Diagram

Y0

Y1

8.3 Feature Description

SN74LVC1G19 is available in NanoFree package. NanoFree is a major breakthrough in IC packaging concepts,
it is a bare die package developed for applications that require the smallest possible package. The device
supports 5-V VCC Operation. All Inputs accept voltages up to 5.5 V. ±24-mA output drive at 3.3 V. The maximum
time propagation delay (tpd ) is 5.4 ns at 3.3 V. Low Power Consumption, 10-μA Max ICC. Typical output ground
bounce (VOLP ) and Output VOH Undershoot (VOHV). This device is fully specified for partial-power-down
applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it
is powered down. The SN74LVC1G19 device has isolation during power off. Ioff supports live insertion, partial-
power-down mode and back drive protection.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SN74LVC1G19.

Table 1. Function Table

INPUTS OUTPUTS
E A Y0 Y1
L L L H
L H H L
H X H H

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC1G19 device is a 1-of-2 decoder/demultiplexer. This device decodes the 1 bit address on input A
and places a logic low on the matching address output, Y0 or Y1 , when the enable (E) input signal is low. It can
produce 24 mA of drive current at 3.3 V making it ideal for driving multiple outputs.

9.2 Typical Application

VCC
9
0.1 PF
VCC
1 5
PCU
E 3 6
0
Device

2 4 Device

Figure 5. Typical Application Diagram

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the
high drive will also create faster edges into light loads so routing and load conditions should be considered to
prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions:
– For rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents must not exceed 50 mA per output and 100 mA total for the part.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.

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Typical Application (continued)

9.2.3 Application Curve
10
Icc 1.8V
9 Icc 2.5V
8 Icc 3.3V
Icc 5V
7
6

Icc - mA
5
4
3
2
1
0
0 20 40 60 80
Frequency - MHz D003

Figure 6. ICC vs Frequency

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Absolute Maximum Ratings table.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor must be installed as close to the power terminal as possible for the best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.

11.2 Layout Example

VCC Input
Unused Input Output Unused Input Output

Input

Figure 7. Layout Diagram

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12 Device and Documentation Support

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.2 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
Blu-ray is a registered trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC1G19DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (C195, C19R) Samples

SN74LVC1G19DBVRE4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (C195, C19R) Samples

SN74LVC1G19DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (C195, C19R) Samples

SN74LVC1G19DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (CY5, CYF, CYK, CY Samples
R)
SN74LVC1G19DCKRE4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CY5 Samples

SN74LVC1G19DCKRG4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CY5 Samples

SN74LVC1G19DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (1JZ, CY7, CYR) Samples

SN74LVC1G19DRLRG4 ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (1JZ, CY7, CYR) Samples

SN74LVC1G19DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CY Samples

SN74LVC1G19YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (CY7, CYN) Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2023

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Feb-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G19DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G19DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G19DBVT SOT-23 DBV 6 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G19DBVT SOT-23 DBV 6 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G19DCKR SC70 DCK 6 3000 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3
SN74LVC1G19DCKRG4 SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G19DRLR SOT-5X3 DRL 6 4000 180.0 8.4 2.0 1.8 0.75 4.0 8.0 Q3
SN74LVC1G19DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC1G19YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G19DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0
SN74LVC1G19DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G19DBVT SOT-23 DBV 6 250 202.0 201.0 28.0
SN74LVC1G19DBVT SOT-23 DBV 6 250 180.0 180.0 18.0
SN74LVC1G19DCKR SC70 DCK 6 3000 210.0 185.0 35.0
SN74LVC1G19DCKRG4 SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC1G19DRLR SOT-5X3 DRL 6 4000 210.0 185.0 35.0
SN74LVC1G19DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G19YZPR DSBGA YZP 6 3000 220.0 220.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DRL0006A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
6

4X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3 0.3 0.05

B 6X TYP
1.1 0.1 0.00

0.6 MAX
C

SEATING PLANE
0.18
6X 0.05 C
0.08 SYMM

SYMM

0.27
6X
0.15
0.1 C A B
0.4
6X 0.05
0.2
4223266/C 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4223266/C 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4223266/C 12/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4207181/G
 PACKAGE OUTLINE
DRY0006A SCALE 8.500
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05 A
B
0.95

PIN 1 INDEX AREA

1.5
1.4

0.6 MAX C

SEATING PLANE
0.05
0.00 0.08 C

3X 0.6
SYMM
(0.127) TYP
(0.05) TYP

3
4
4X
0.5
SYMM
2X
1

6
1
0.25
6X
0.4 0.15
0.3 0.1 C A B
0.05 C
PIN 1 ID
(OPTIONAL) 0.35
5X
0.25
4222894/A 01/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.35)
5X (0.3)

1 6

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP
(0.6)

LAND PATTERN EXAMPLE

1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

EXPOSED
EXPOSED
METAL
METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
DEFINED SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4222894/A 01/2018
NOTES: (continued)

3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.35) 5X (0.3)

1 6

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP (0.6)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X

4222894/A 01/2018

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
1.45 MAX

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214840/E 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/E 02/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/E 02/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
YZP0006 SCALE 9.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

0.5 MAX C

SEATING PLANE
0.19 BALL TYP 0.05 C
0.15

0.5 TYP

SYMM
1 D: Max = 1.418 mm, Min =1.357 mm
B TYP
0.5 E: Max = 0.918 mm, Min =0.857 mm
TYP
A

0.25 1 2
6X SYMM
0.21
0.015 C A B

4219524/A 06/2014

NOTES: NanoFree Is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0006 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
6X ( 0.225)
1 2

(0.5) TYP

B SYMM

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

( 0.225) 0.05 MAX 0.05 MIN METAL

METAL UNDER
MASK

SOLDER MASK ( 0.225)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4219524/A 06/2014

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0006 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

6X ( 0.25)
(R0.05) TYP
1 2
A

(0.5)
TYP

B SYMM

METAL
TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4219524/A 06/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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