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uA741
SLOS094G – NOVEMBER 1970 – REVISED JANUARY 2018

µA741 General-Purpose Operational Amplifiers

1 Features 3 Description
•
1 Short-Circuit Protection The µA741 device is a general-purpose operational
amplifier featuring offset-voltage null capability.
• Offset-Voltage Null Capability
• Large Common-Mode and Differential Voltage The high common-mode input voltage range and the
Ranges absence of latch-up make the amplifier ideal for
voltage-follower applications. The device is
• No Frequency Compensation Required short-circuit protected and the internal frequency
• No Latch-Up compensation ensures stability without external
components. A low-value potentiometer may be
2 Applications connected between the offset null inputs to null out
the offset voltage as shown in Figure 12.
• DVD Recorders and Players
• Pro Audio Mixers The µA741C device is characterized for operation
from 0°C to 70°C.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
µA741CD SOIC (8) 4.90 mm × 3.91 mm
µA741CP PDIP (8) 9.81 mm × 6.35 mm
µA741CPS SO (8) 6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Schematic
OFFSET N1

IN + +
OUT
IN – –

OFFSET N2

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 10
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 11
3 Description ............................................................. 1 7.5 µA741Y Chip Information........................................ 11
4 Revision History..................................................... 2 8 Application and Implementation ........................ 12
8.1 Application Information............................................ 12
5 Pin Configurations and Functions ....................... 4
8.2 Typical Application .................................................. 12
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5 9 Power Supply Recommendations...................... 14
6.2 Recommended Operating Conditions....................... 5 10 Layout................................................................... 14
6.3 Thermal Information .................................................. 5 10.1 Layout Guidelines ................................................. 14
6.4 Electrical Characteristics: μA741C............................ 6 10.2 Layout Example .................................................... 14
6.5 Electrical Characteristics: μA741Y ............................ 7 11 Device and Documentation Support ................. 16
6.6 Switching Characteristics: μA741C ........................... 7 11.1 Receiving Notification of Documentation Updates 16
6.7 Switching Characteristics: μA741Y ........................... 7 11.2 Trademarks ........................................................... 16
6.8 Typical Characteristics .............................................. 8 11.3 Electrostatic Discharge Caution ............................ 16
7 Detailed Description ............................................ 10 11.4 Glossary ................................................................ 16
7.1 Overview ................................................................. 10 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 10 Information ........................................................... 16

4 Revision History
Changes from Revision F (May 2017) to Revision G Page

• Changed supply voltage unit from "°C" to "V" in Absolute Maximum Ratings table ............................................................. 5

Changes from Revision E (January 2015) to Revision F Page

• Updated data sheet text to the latest documentation and translation standards .................................................................. 1
• Deleted text regarding µA741M device (obsolete package) from Description section........................................................... 1
• Added µA741CD, µA741CP, and µA741CPS devices to Device Information table .............................................................. 1
• Deleted µA741x device from Device Information table ......................................................................................................... 1
• Updated pinout diagrams and Pin Functions tables in the Pin Configurations and Functions section .................................. 4
• Deleted µA741M pinout drawings information from Pin Configurations and Functions section ............................................ 4
• Deleted Electrical Characteristics: µA741M table from Specifications section ...................................................................... 5
• Added operating junction temperature (TJ) and values to Absolute Maximum Ratings table ............................................... 5
• Deleted text regarding µA741M from Absolute Maximum Ratings table .............................................................................. 5
• Deleted text regarding µA741M device from Recommended Operating Conditions table .................................................... 5
• Deleted Dissipation Ratings table .......................................................................................................................................... 5
• Added Thermal Information table and values ........................................................................................................................ 5
• Deleted µA741M in Switching Characteristics table .............................................................................................................. 7
• Correct typo in Figure 1 ......................................................................................................................................................... 8
• Deleted text regarding µA741M device from Detailed Description section .......................................................................... 10
• Updated text in Overview section ........................................................................................................................................ 10
• Added 2017 copyright to Functional Block Diagram ........................................................................................................... 10
• Added caption to Figure 11 in Device Functional Modes section ........................................................................................ 11
• Changed pins 1 and 5 from "NC" to "Offset N1" and "Offset N2" in Figure 18 .................................................................... 15

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Changes from Revision D (February 2014) to Revision E Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
• Moved Typical Characteristics into Specifications section. ................................................................................................... 8

Changes from Revision C (January 2014) to Revision D Page

• Fixed Typical Characteristics graphs to remove extra lines. ................................................................................................. 8

Changes from Revision B (September 2000) to Revision C Page

• Updated document to new TI data sheet format - no specification changes. ........................................................................ 1

• Deleted Ordering Information table. ....................................................................................................................................... 1

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5 Pin Configurations and Functions

uA741C D, P, or PS Package
8-Pin SOIC, PDIP, SO
Top View

OFFSET N1 1 8 NC

IN± 2 7 VCC+

IN+ 3 6 OUT

VCC± 4 5 OFFSET N2

Not to scale

NC- no internal connection

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
IN+ 3 I Noninverting input
IN– 2 I Inverting input
NC 8 — No internal connection
OFFSET N1 1 I External input offset voltage adjustment
OFFSET N2 5 I External input offset voltage adjustment
OUT 6 O Output
VCC+ 7 — Positive supply
VCC– 4 — Negative supply

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6 Specifications
6.1 Absolute Maximum Ratings
over virtual junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VCC (2) µA741C –18 18 V
Differential input voltage, VID (3) µA741C –15 15 V
(2) (4)
Input voltage, VI (any input) µA741C –15 15 V
Voltage between offset null (either OFFSET N1 or
µA741C –15 15 V
OFFSET N2) and VCC–
(5)
Duration of output short circuit Unlimited
Continuous total power dissipation See Thermal Information
Case temperature for 60 seconds µA741C N/A N/A °C
Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds µA741C N/A N/A °C
Lead temperature 1.6 mm (1/16 inch) from case for 10
D, P, or PS package µA741C 260 °C
seconds
Operating junction temperature, TJ 150 °C
Storage temperature range, Tstg µA741C –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC–.
(3) Differential voltages are at IN+ with respect to IN –.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) The output may be shorted to ground or either power supply.

6.2 Recommended Operating Conditions

MIN MAX UNIT
VCC+ 5 15
Supply voltage V
VCC– –5 –15
TA Operating free-air temperature µA741C 0 70 °C

6.3 Thermal Information

µA741
THERMAL METRIC (1) D (SOIC) P (PDIP) PS (SO) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 129.2 87.4 119.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 73.6 89.3 66 °C/W
RθJB Junction-to-board thermal resistance 72.4 64.4 70 °C/W
ψJT Junction-to-top characterization parameter 25.9 49.8 27.2 °C/W
ψJB Junction-to-board characterization parameter 71.7 64.1 69 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.4 Electrical Characteristics: μA741C

at specified virtual junction temperature, VCC± = ±15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
25°C 1 6
VIO Input offset voltage VO = 0 mV
Full range 7.5
ΔVIO(adj) Offset voltage adjust range VO = 0 25°C ±15 mV
25°C 20 200
IIO Input offset current VO = 0 nA
Full range 300
25°C 80 500
IIB Input bias current VO = 0 nA
Full range 800
25°C ±12 ±13
VICR Common-mode input voltage range V
Full range ±12
RL = 10 kΩ 25°C ±12 ±14
RL ≥ 10 kΩ Full range ±12
VOM Maximum peak output voltage swing V
RL = 2 kΩ 25°C ±10
RL ≥ 2 kΩ Full range ±10

Large-signal differential voltage RL ≥ 2 kΩ 25°C 20 200

AVD V/mV
amplification VO = ±10 V Full range 15
ri Input resistance 25°C 0.3 2 MΩ
ro Output resistance VO = 0; see (2) 25°C 75 Ω
Ci Input capacitance 25°C 1.4 pF
25°C 70 90
CMRR Common-mode rejection ratio VIC = VICRmin dB
Full range 70
25°C 30 150
kSVS Supply voltage sensitivity (ΔVIO/ΔVCC) VCC = ±9 V to ±15 V µV/V
Full range 150
IOS Short-circuit output current 25°C ±25 ±40 mA
25°C 1.7 2.8
ICC Supply current VO = 0; no load mA
Full range 3.3
25°C 50 85
PD Total power dissipation VO = 0; no load mW
Full range 100

(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified.
Full range for the µA741C is 0°C to 70°C.
(2) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.

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6.5 Electrical Characteristics: μA741Y

at specified virtual junction temperature, VCC± = ±15 V, TA = 25°C (unless otherwise noted) (1)
(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage VO = 0 1 5 mV
ΔVIO(adj) Offset voltage adjust range VO = 0 ±15 mV
IIO Input offset current VO = 0 20 200 nA
IIB Input bias current VO = 0 80 500 nA
VICR Common-mode input voltage range ±12 ±13 V
RL = 10 kΩ ±12 ±14
VOM Maximum peak output voltage swing V
RL = 2 kΩ ±10 ±13
AVD Large-signal differential voltage amplification RL ≥ 2 kΩ 20 200 V/mV
ri Input resistance 0.3 2 MΩ
ro Output resistance VO = 0; see (1) 75 Ω
Ci Input capacitance 1.4 pF
CMRR Common-mode rejection ratio VIC = VICRmin 70 90 dB
kSVS Supply voltage sensitivity (ΔVIO/ΔVCC) VCC = ±9 V to ±15 V 30 150 µV/V
IOS Short-circuit output current ±25 ±40 mA
ICC Supply current VO = 0; no load 1.7 2.8 mA
PD Total power dissipation VO = 0; no load 50 85 mW

(1) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified.

6.6 Switching Characteristics: μA741C

over operating free-air temperature range, VCC± = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Rise time VI = 20 mV, RL = 2 kΩ 0.3 µs
Overshoot factor CL = 100 pF; see Figure 1 5%
VI = 10 V, RL = 2 kΩ
SR Slew rate at unity gain 0.5 V/µs
CL = 100 pF; see Figure 1

6.7 Switching Characteristics: μA741Y

over operating free-air temperature range, VCC± = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Rise time VI = 20 mV, RL = 2 kΩ 0.3 µs
Overshoot factor CL = 100 pF; see Figure 1 5%
VI = 10 V, RL = 2 kΩ
SR Slew rate at unity gain 0.5 V/µs
CL = 100 pF; see Figure 1

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6.8 Typical Characteristics

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.

VI
– OUT
IN
+
0V

INPUT VOLTAGE
WAVEFORM
CL = 100 pF RL = 2 kΩ

TEST CIRCUIT
Figure 1. Rise Time, Overshoot, and Slew Rate

100 400
VCC+ = 15 V
VCC+ = 15 V
90 VCC – = –15 V
350 VCC – = –15 V
I IO – Input Offset Current – nA

I IB – Input Bias Current – nA

80
300
70

60 250

50 200

40
150
30
100
20
50
10

0 0
– 60 – 40 – 20 0 20 40 60 80 100 120 140 – 60 – 40 – 20 0 20 40 60 80 100 120 140

TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C

Figure 2. Input Offset Current vs Free-Air Temperature Figure 3. Input Bias Current vs Free-Air Temperature
±14 ±20
VCC+ = 15 V VCC+ = 15 V
VOM – Maximum Peak Output Voltage – V

VOM – Maximum Peak Output Voltage – V

±13 VCC – = –15 V ±18 VCC – = –15 V

TA = 25°C RL = 10 kΩ
±12 ±16 TA = 25°C

± 11 ±14

±10 ±12

±9 ±10

±8 ±8

±7 ±6

±6 ±4

±5 ±2

±4 0
0.1 0.2 0.4 0.7 1 2 4 7 10 100 1k 10k 100k 1M
RL – Load Resistance – kΩ f – Frequency – Hz
Figure 4. Maximum Output Voltage vs Load Resistance Figure 5. Maximum Peak Output Voltage vs Frequency

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Typical Characteristics (continued)

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
400 110
VO = ±10 V
RL = 2 kΩ 100 VCC+ = 15 V
TA = 25°C VCC – = –15 V
AVD – Open-Loop Signal Differential

AVD – Open-Loop Signal Differential

200 90 VO = ±10 V
Voltage Amplification – V/mV

80 RL = 2 kΩ

Voltage Amplification – dB
TA = 25°C
70
100
60

50

40 40
30
20
20
10
0
10 –10
0 2 4 6 8 10 12 14 16 18 20 1 10 100 1k 10k 100k 1M 10M
VCC ± – Supply Voltage – V f – Frequency – Hz
Figure 6. Open-Loop Signal Differential Voltage Figure 7. Open-Loop Large-Signal Differential Voltage
Amplification vs Supply Voltage Amplification vs Frequency
100 28
CMRR – Common-Mode Rejection Ratio – dB

VCC+ = 15 V
90 VCC– = –15 V 24
BS = 10 kΩ
80
TA = 25°C
20
VO – Output Voltage – mV

70
90%
16
60

50 12

40 8
30 VCC+ = 15 V
4
VCC– = –15 V
20 10% RL = 2 kΩ
0
10 CL = 100 pF
tr TA = 25°C
0 –4
1 100 10k 1M 100M 0 0.5 1 1.5 2 2.5
f – Frequency – Hz t – Time - µs
Figure 8. Common-Mode Rejection Ratio vs Frequency Figure 9. Output Voltage vs Elapsed Time
8
VCC+ = 15 V
6 VCC– = –15 V
RL = 2 kΩ
CL = 100 pF
Input and Output Voltage – V

4
TA = 25°C
VO
2

0
VI
–2

–4

–6

–8
0 10 20 30 40 50 60 70 80 90

t – Time – ms
Figure 10. Voltage-Follower Large-Signal Pulse Response

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7 Detailed Description

7.1 Overview
The μA741 has been a popular operational amplifier for over four decades. Typical open loop gain is 106 dB
while driving a 2000-Ω load. Short circuit tolerance, offset voltage trimming, and unity-gain stability makes the
μA741 useful for many applications.

7.2 Functional Block Diagram

VCC+

IN –

OUT
IN+

OFFSET N1
OFFSET N2

VCC –

Component Count
Transistors 22
Resistors 11
Diode 1
Capacitor 1 Copyright © 2017, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Offset-Voltage Null Capability
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors and so forth. The input offset pins allow the designer to adjust for
mismatches caused by external circuitry. See Application and Implementation for more details on design
techniques.

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Feature Description (continued)

7.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change an output when there is a change on the
input. The µA741 device has a 0.5-V/μs slew rate. Parameters that vary significantly with operating voltages or
temperature are shown in Typical Characteristics.

7.4 Device Functional Modes

The µA741 device is powered on when the power supply is connected. The device can operate as a single-
supply or dual-supply operational amplifier depending on the application.

7.5 µA741Y Chip Information

When properly assembled, this chip displays characteristics similar to the µA741C device. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips can be mounted with conductive
epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

VCC+
(7)
(7) (6) IN +
(3)
+ (6)
(2) OUT
IN – –
OFFSET N1 (1) (4)
(8)
OFFSET N2 (5) VCC –

45
(5)

(1) CHIP THICKNESS: 15 TYPICAL

(4)
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150 °C.
(2) (3) TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
36

Figure 11. Bonding Pad Assignments

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors and so forth. The input offset pins allow the designer to adjust for
mismatches resulting from external circuitry. These input mismatches can be adjusted by placing resistors or a
potentiometer between the inputs as shown in Figure 12. A potentiometer can fine-tune the circuit during testing
or for applications which require precision offset control. For more information about designing using the input-
offset pins, see Nulling Input Offset Voltage of Operational Amplifiers.

IN + +
OUT
IN – – OFFSET N2

OFFSET N1
10 kΩ

To VCC –

Figure 12. Input Offset Voltage Null Circuit

8.2 Typical Application

The voltage follower configuration of the operational amplifier is used for applications where a weak signal drives
a relatively high current load. This circuit is also called a buffer amplifier or unity-gain amplifier. The inputs of an
operational amplifier have a very high resistance which puts a negligible current load on the voltage source. The
output resistance of the operational amplifier is almost negligible, so the resistance can provide as much current
as necessary to the output load.
10 k

12 V

VOUT
+

VIN

Figure 13. Voltage Follower Schematic

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Typical Application (continued)

8.2.1 Design Requirements
• Output range from 2 V to 11.5 V
• Input range from 2 V to 11.5 V
• Resistive feedback to negative input

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Swing

The output voltage of an operational amplifier is limited by the internal circuitry to some level below the supply
rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output
voltage requirements.

8.2.2.2 Supply and Input Voltage

For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail
voltage or lower than the recommended negative supply rail voltage. The selected amplifier must be able to
operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to
11.5 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail rather than ground allows the
amplifier to maintain linearity for inputs below 2 V.

8.2.3 Application Curves for Output Characteristics

12 0.045
0.040
10
0.035
0.030
8
0.025
VOUT (V)

IIO (mA)

6 0.020
0.015
4
0.010
0.005
2
0.000
0 ±0.005
0 2 4 6 8 10 12 0 2 4 6 8 10 12
VIN (V) C001 VIN (V) C002

Figure 14. Output Voltage vs Input Voltage Figure 15. Current Drawn Input of Voltage Follower (IIO)
vs Input Voltage

0.45

0.40

0.35

0.30
ICC (mA)

0.25

0.20

0.15

0.10

0.05

0.00
0 2 4 6 8 10 12
VIN (V) C003

Figure 16. Current Drawn from Supply (ICC)

vs Input Voltage

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9 Power Supply Recommendations

The μA741 device is specified for operation from ±5 to ±15 V; many specifications apply from 0°C to 70°C.
Typical Characteristics presents parameters that can exhibit significant variance with regard to operating voltage
or temperature.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.

CAUTION
Supply voltages larger than ±18 V can permanently damage the device (see Absolute
Maximum Ratings).

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors reduce the coupled noise by providing low impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close as possible to the device. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

10.2 Layout Example

RIN
VIN +
VOUT
RG
RF

Figure 17. Operational Amplifier Schematic for Noninverting Configuration

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Layout Example (continued)

Place components close to

device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines RF
as possible
OFFSET N1 NC VS+
Use low-ESR, ceramic
RG bypass capacitor
GND IN1í VCC+

VIN IN1+ OUT

RIN
VCCí OFFSET N2 GND
Only needed for
dual-supply
operation
GND VS-
(or GND for single supply) VOUT Ground (GND) plane on another layer

Figure 18. Operational Amplifier Board Layout for Noninverting Configuration

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11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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Product Folder Links: uA741

 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

UA741CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C

& no Sb/Br)
UA741CDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C
& no Sb/Br)
UA741CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C
& no Sb/Br)
UA741CP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UA741CP
& no Sb/Br)
UA741CPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UA741CP
& no Sb/Br)
UA741CPSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 U741
& no Sb/Br)
UA741CPSRE4 ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 U741
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UA741CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2018

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UA741CDR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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