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RC4558
SLOS073G – MARCH 1976 – REVISED OCTOBER 2014

RC4558 Dual General-Purpose Operational Amplifier

1 Features 3 Description
•
1 Continuous Short-Circuit Protection The RC4558 device is a dual general-purpose
operational amplifier, with each half electrically similar
• Wide Common-Mode and Differential Voltage to the μA741, except that offset null capability is not
Ranges provided.
• No Frequency Compensation Required
The high common-mode input voltage range and the
• Low Power Consumption absence of latch-up make this amplifier ideal for
• No Latch-Up voltage-follower applications. The device is short-
• Unity-Gain Bandwidth: 3 MHz Typ circuit protected, and the internal frequency
compensation ensures stability without external
• Gain and Phase Match Between Amplifiers components.
• Low Noise: 8 nV/√Hz Typ at 1 kHz
Device Information(1)
2 Applications PART NUMBER PACKAGE (PIN) BODY SIZE
• DVD Recorders and Players SOIC (8) 4.90 mm × 3.91 mm
• Pro Audio Mixers SOIC (8) 3.00 mm × 3.00 mm
RC4558 PDIP (8) 9.81 mm × 6.35 mm
TSSOP (8) 3.00 mm × 4.40 mm
SOP (8) 6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.

Noninverting Amplifier Schematic

RIN
VIN +
VOUT
RG
RF

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
RC4558
SLOS073G – MARCH 1976 – REVISED OCTOBER 2014 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.2 Functional Block Diagram ......................................... 9
2 Applications ........................................................... 1 7.3 Feature Description................................................... 9
3 Description ............................................................. 1 7.4 Device Functional Modes.......................................... 9
4 Revision History..................................................... 2 8 Application and Implementation ........................ 10
8.1 Typical Application ................................................. 10
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 13
6.1 Absolute Maximum Ratings ..................................... 4 10 Layout................................................................... 14
6.2 Handling Ratings....................................................... 4 10.1 Layout Guidelines ................................................. 14
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 14
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 15
6.5 Electrical Characteristics........................................... 5 11.1 Trademarks ........................................................... 15
6.6 Operating Characteristics.......................................... 5 11.2 Electrostatic Discharge Caution ............................ 15
6.7 Typical Characteristics .............................................. 6 11.3 Glossary ................................................................ 15
7 Detailed Description .............................................. 9 12 Mechanical, Packaging, and Orderable
7.1 Overview ................................................................... 9 Information ........................................................... 15

4 Revision History
Changes from Revision F (September 2010) to Revision G Page

• Added Applications, Device Information table, Handling Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
• Removed Ordering Information table. .................................................................................................................................... 1

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5 Pin Configuration and Functions

D, DGK, P, PS, OR PW PACKAGE
(TOP VIEW)

1OUT 1 8 VCC+
1IN− 2 7 2OUT
1IN+ 3 6 2IN−
VCC− 4 5 2IN+

Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
1IN+ 3 I Noninverting input
1IN- 2 I Inverting Input
1OUT 1 O Output
2IN+ 5 I Noninverting input
2IN- 6 I Inverting Input
2OUT 7 O Output
VCC+ 8 — Positive Supply
VCC- 4 — Negative Supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC+ 18
Supply voltage (2) V
VCC– –18
VID Differential input voltage (3) ±30 V
VI Input voltage (any input) (2) (4) ±15 V
(5)
Duration of output short circuit to ground, one amplifier at a time Unlimited
TJ Operating virtual junction temperature 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC–.
(3) Differential voltages are at IN+ with respect to IN–.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded.

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range -65 150 °C
Human body model (HBM), per AEC Q100-002 (1) 0 500
V(ESD) Electrostatic discharge (2)
V
Charged device model (CDM), per AEC Q100-011 0 1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC+ 5 15
Supply voltage V
VCC– –5 –15
RC4558 0 70
TA Operating free-air temperature °C
RC4558I –40 85

6.4 Thermal Information

RC4558
THERMAL METRIC (1) D DGK P PS PW UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 97 172 85 95 149 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.5 Electrical Characteristics

at specified free-air temperature, VCC+ = 15 V, VCC– = –15 V
TEST (2)
PARAMETER TA MIN TYP MAX UNIT
CONDITIONS (1)
25°C 0.5 6
VIO Input offset voltage VO = 0 mV
Full range 7.5
25°C 5 200
IIO Input offset current VO = 0 nA
Full range 300
25°C 150 500
IIB Input bias current VO = 0 nA
Full range 800
VICR Common-mode input voltage range 25°C ±12 ±14 V
RL = 10 kΩ 25°C ±12 ±14
VOM Maximum output voltage swing 25°C ±10 ±13 V
RL = 2 kΩ
Full range ±10
RL ≥ 2 kΩ, 25°C 20 300
AVD Large-signal differential voltage amplification V/mV
VO = ±10 V Full range 15
B1 Unity-gain bandwidth 25°C 3 MHz
ri Input resistance 25°C 0.3 5 MΩ
CMRR Common-mode rejection ratio 25°C 70 90 dB
VCC = ±15 V
kSVS Supply-voltage sensitivity (ΔVIO/ΔVCC) 25°C 30 150 μV/V
to ±9 V
AVD = 100,
RS = 100 Ω,
Vn Equivalent input noise voltage (closed loop) 25°C 8 nV/√Hz
f = 1 kHz,
BW = 1 Hz
25°C 2.5 5.6
VO = 0,
ICC Supply current (both amplifiers) TA min 3 6.6 mA
No load
TA max 2.3 5
25°C 75 170
VO = 0,
PD Total power dissipation (both amplifiers) TA min 90 200 mW
No load
TA max 70 150
Open loop RS = 1 kΩ, 85
VO1/VO2 Crosstalk attenuation 25°C dB
AVD = 100 f = 10 kHz 105

(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified.
(2) Full range is 0°C to 70°C for RC4558 and –40°C to 85°C for RC4558I.

6.6 Operating Characteristics

VCC+ = 15 V, VCC– = –15 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Rise time VI = 20 mV, RL = 2 kΩ, CL = 100 pF 0.13 ns
Overshoot VI = 20 mV, RL = 2 kΩ, CL = 100 pF 5%
SR Slew rate at unity gain VI = 10 V, RL = 2 kΩ, CL = 100 pF 1.1 1.7 V/μs

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6.7 Typical Characteristics

6 6

5 5
ICC – Supply Current – mA

ICC – Supply Current – mA

4 4

3 3

2 2

1 1

0 0
0 2 4 6 8 10 12 14 16 18 20 -55 -35 -15 5 25 45 65 85 105 125
VCC – Supply Voltage – V TA – Temperature – °C

Figure 1. Supply Current vs Supply Voltage Figure 2. Supply Current vs Temperature

(TA = 25°C) (VCC = ±15 V)

40 0 40 0

-20 -20
30 30
-40 -40

-60 -60
20 20
-80

Phase – deg
-80
Phase – deg

Gain Gain
Gain – dB
Gain – dB

10 -100 10 -100

-120 -120
Phase Phase
0 0
-140 -140

-160 -160
-10 -10
-180 -180

-20 -200 -20 -200

100 1000 10000 100 1000 10000
f – Frequency – kHz f – Frequency – kHz

Figure 3. Gain and Phase vs Frequency Figure 4. Gain and Phase vs Frequency
(VCC = ±15 V, RL = 2 kΩ, CL = 22 pF) (VCC = ±15 V, RL = 10 kΩ, CL = 22 pF)

15 30

10 25
VOM – Output Voltage Swing – V

VOM – Output Voltage Swing – V

5 20

0 15

-5 10

-10
5

-15
0
6 8 10 12 14 16 18
1.E+00
1 1.E+01
10 1.E+02
100 1.E+03
1k 1.E+04
10k 1.E+05
100k 1.E+06
1M
VCC – Supply Voltage – V
f – Frequency – Hz

Figure 5. Output Voltage Swing vs Supply Voltage Figure 6. Output Voltage Swing vs Frequency
(RL = 2 kΩ, TA = 25°C) (VCC = ±15 V, RL = 2 kΩ, TA = 25°C)

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Typical Characteristics (continued)

32 15

30
14.75
28

VOM – Output Voltage Swing – V

VOM – Output Voltage Swing – V

14.5
26
14.25
24

22 14

20 13.75
18
13.5
16
13.25
14

12 13
100 1000 10000 -55 -35 -15 5 25 45 65 85 105 125

RloadR– –Load TA – Temperature – °C

L LoadResistance
Resistance–– W

Figure 7. Output Voltage Swing vs Load Resistance Figure 8. Output Voltage Swing vs Temperature
(VCC = ±15 V, TA = 25°C) (VCC = ±15 V, RL = 10 kΩ)

-12 120

110
-12.25
100
–V OM – Output Voltage Swing – V

-12.5 90
G M – Open Loop Gain – dB
80
-12.75
70
-13 60
50
-13.25
40
-13.5 30

20
-13.75
10
-14 0
-55 -35 -15 5 25 45 65 85 105 125 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06 10M
1.E+07
TA – Temperature – °C f – Frequency – Hz

Figure 9. Negative Output Voltage Swing vs Temperature Figure 10. Open Loop Gain vs Frequency
(VCC = ±15 V, RL = 10 kΩ) (VCC = ±15 V, RL = 2 kΩ, CL = 22 pF, TA = 25°C)

200 0.003

190
0.002
180
VIO – Input Offset Voltage – V
IIB – Input Bias Current – nA

170
0.001
160

150 0

140
-0.001
130

120
-0.002
110

100 -0.003
-55 -35 -15 5 25 45 65 85 105 125 -55 -35 -15 5 25 45 65 85 105 125

TA – Temperature – °C TA – Temperature – °C

Figure 11. Input Bias Current vs Temperature Figure 12. Input Offset Voltage vs Temperature
(VCC = ±15 V) (VCC = ±15 V)

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Typical Characteristics (continued)

14

12

Voltage––nV/rt(Hz)
nV/ÖHz
10

NoiseVoltage
8

Noise
6

– Input
Vn V–n Input
4

0
10
1.E+01 100
1.E+02 1.E+03
1k 10k
1.E+04 100k
1.E+05
f – Frequency – Hz

Figure 13. Input Noise Voltage vs Frequency

(VCC = ±15 V, TA = 25°C)

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7 Detailed Description

7.1 Overview
The RC4558 device is a dual general-purpose operational amplifier, with each half electrically similar to the
μA741, except that offset null capability is not provided.
The high common-mode input voltage range and the absence of latch-up make this amplifier ideal for voltage-
follower applications. The device is short-circuit protected, and the internal frequency compensation ensures
stability without external components.

7.2 Functional Block Diagram

VCC+

IN−

IN+

OUT

VCC−

7.3 Feature Description

7.3.1 Unity-Gain Bandwidth
The unity-gain bandwidth is the frequency up to which an amplifier with a unity gain may be operated without
greatly distorting the signal. The RC4558 device has a 3-MHz unity-gain bandwidth.

7.3.2 Common-Mode Rejection Ratio

The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted
input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to
the change in the input voltage, then converting to decibels. Ideally the CMRR is infinite, but in practice,
amplifiers are designed to have it as high as possible. The CMRR of the RC4558 device is 90 dB.

7.3.3 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. The RC4558 device has a 1.7 V/μs slew rate.

7.4 Device Functional Modes

The RC4558 device is powered on when the supply is connected. Each of these devices can be operated as a
single supply operational amplifier or dual supply amplifier depending on the application.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Typical Application

Some applications require differential signals. Figure 14 shows a simple circuit to convert a single-ended input of
2 V to 10 V into differential output of ±8 V on a single 15-V supply. The output range is intentionally limited to
maximize linearity. The circuit is composed of two amplifiers. One amplifier acts as a buffer and creates a
voltage, VOUT+. The second amplifier inverts the input and adds a reference voltage to generate VOUT–. Both
VOUT+ and VOUT– range from 2 V to 10 V. The difference, VDIFF, is the difference between VOUT+ and VOUT–.
R2

R1 15 V

VOUT-
+
R3 +
VREF
R4
12 V
VDIFF

±
VOUT+
+

VIN

Figure 14. Schematic for Single-Ended Input to Differential Output Conversion

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Typical Application (continued)

8.1.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 15 V
• Reference voltage: 12V
• Input: 2 V to 10 V
• Output differential: ±8 V

8.1.2 Detailed Design Procedure

The circuit in Figure 14 takes a single-ended input signal, VIN, and generates two output signals, VOUT+ and
VOUT– using two amplifiers and a reference voltage, VREF. VOUT+ is the output of the first amplifier and is a
buffered version of the input signal, VIN (see Equation 1). VOUT– is the output of the second amplifier which uses
VREF to add an offset voltage to VIN and feedback to add inverting gain. The transfer function for VOUT– is
Equation 2.
VOUT+ = VIN (1)
æ R 44 ö æ R22 ö R2
out - = VREF
VOUT ref ´ ç ÷ ´ ç1 + ÷ - VINin ´ 2
è R33+
+ R 44 ø è R11 ø R11 (2)
The differential output signal, VDIFF, is the difference between the two single-ended output signals, VOUT+ and
VOUT–. Equation 3 shows the transfer function for VDIFF. By applying the conditions that R1 = R2 and R3 = R4, the
transfer function is simplified into Equation 6. Using this configuration, the maximum input signal is equal to the
reference voltage and the maximum output of each amplifier is equal to the VREF. The differential output range is
2×VREF. Furthermore, the common mode voltage will be one half of VREF (see Equation 7).
æ R ö æ R4 öæ R2 ö
VD IF F = V O U T + - V O U T - = VIN ´ ç 1 + 2 ÷ - VR E F ´ ç ÷ ç1 + ÷
è R1 ø è R3 + R4 ø è R1 ø (3)
VOUT+ = VIN (4)
VOUT– = VREF – VIN (5)
VDIFF = 2×VIN – VREF (6)
æV + VOUT - ö 1
Vcm = ç OUT + ÷ = VREF
è 2 ø 2 (7)

8.1.2.1 Amplifier Selection

Linearity over the input range is key for good dc accuracy. The common mode input range and the output swing
limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required.
Bandwidth is a key concern for this design. Because RC4558 has a bandwidth of 3 MHz, this circuit will only be
able to process signals with frequencies of less than 3 MHz.

8.1.2.2 Passive Component Selection

Because the transfer function of VOUT– is heavily reliant on resistors (R1, R2, R3, and R4), use resistors with low
tolerances to maximize performance and minimize error. This design used resistors with resistance values of
36 kΩ with tolerances measured to be within 2%. But, if the noise of the system is a key parameter, the user can
select smaller resistance values (6 kΩ or lower) to keep the overall system noise low. This ensures that the noise
from the resistors is lower than the amplifier noise.

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Typical Application (continued)

8.1.3 Application Curves
The measured transfer functions in Figure 15, Figure 16, and Figure 17 were generated by sweeping the input
voltage from 0 V to 12 V. However, this design should only be used between 2 V and 10 V for optimum linearity.

16 16

12 14

12
8
10

VOUT+ (V)
VDIFF (V)

4
8
0
6
±4
4
±8 2

±12 0
0 2 4 6 8 10 12 0 2 4 6 8 10 12
VIN (V) C003 VIN (V) C001

Figure 15. Differential Output Voltage Node vs Input Figure 16. Positive Output Voltage Node vs Input Voltage
Voltage

12

10

8
VOUTt (V)

0
0 2 4 6 8 10 12
VIN (V) C002

Figure 17. Positive Output Voltage Node vs Input Voltage

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9 Power Supply Recommendations

The RC4558 device is specified for operation from ±5 V to ±15 V; many specifications apply from –0°C to 70°C.
The Typical Characteristics section presents parameters that can exhibit significant variance with regard to
operating voltage or temperature.

CAUTION
Supply voltages outside of the ±18-V range can permanently damage the device (see
the Absolute Maximum Ratings ).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.

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10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

10.2 Layout Example

RIN
VIN +
VOUT
RG
RF

Figure 18. Operational Amplifier Schematic for Noninverting Configuration

Place components close to

device and to each other to
reduce parasitic errors
Run the input traces as far
VS+
away from the supply lines
as possible RF
OUT1 VCC+
RG
GND IN1í OUT2

GND
VIN IN1+ IN2í
RIN
VCCí IN2+
Only needed for Use low-ESR, ceramic
dual-supply bypass capacitor
operation
GND VS-
(or GND for single supply) Ground (GND) plane on another layer

Figure 19. Operational Amplifier Board Layout for Noninverting Configuration

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11 Device and Documentation Support

11.1 Trademarks
All trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

RC4558D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 RC4558

& no Sb/Br)
RC4558DE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 RC4558
& no Sb/Br)
RC4558DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM 0 to 70 (YRP, YRS, YRU)
& no Sb/Br) CU NIPDAUAG
RC4558DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 (YRP, YRS, YRU)
& no Sb/Br)
RC4558DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 RC4558
& no Sb/Br)
RC4558DRG3 ACTIVE SOIC D 8 2500 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 RC4558
& no Sb/Br)
RC4558DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 RC4558
& no Sb/Br)
RC4558ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I
& no Sb/Br)
RC4558IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM -40 to 85 (YSP, YSS, YSU)
& no Sb/Br) CU NIPDAUAG
RC4558IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 (YSP, YSS, YSU)
& no Sb/Br)
RC4558IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I
& no Sb/Br)
RC4558IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I
& no Sb/Br)
RC4558IP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 RC4558IP
& no Sb/Br)
RC4558IPW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I
& no Sb/Br)
RC4558IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 R4558I
& no Sb/Br)
RC4558P ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 RC4558P
& no Sb/Br)
RC4558PE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 RC4558P
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

RC4558PSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 R4558

& no Sb/Br)
RC4558PSRG4 ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 R4558
& no Sb/Br)
RC4558PW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 R4558
& no Sb/Br)
RC4558PWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 R4558
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Aug-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
RC4558DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
RC4558DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
RC4558DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
RC4558DRG3 SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
RC4558DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
RC4558DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
RC4558IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
RC4558IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
RC4558IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
RC4558IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
RC4558PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
RC4558PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Aug-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
RC4558DGKR VSSOP DGK 8 2500 364.0 364.0 27.0
RC4558DR SOIC D 8 2500 340.5 338.1 20.6
RC4558DR SOIC D 8 2500 364.0 364.0 27.0
RC4558DRG3 SOIC D 8 2500 364.0 364.0 27.0
RC4558DRG4 SOIC D 8 2500 340.5 338.1 20.6
RC4558DRG4 SOIC D 8 2500 367.0 367.0 35.0
RC4558IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
RC4558IDR SOIC D 8 2500 340.5 338.1 20.6
RC4558IPWR TSSOP PW 8 2000 367.0 367.0 35.0
RC4558IPWR TSSOP PW 8 2000 364.0 364.0 27.0
RC4558PWR TSSOP PW 8 2000 367.0 367.0 35.0
RC4558PWR TSSOP PW 8 2000 364.0 364.0 27.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
6.6 SEATING PLANE
TYP
6.2

A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1

3.1 2X
2.9
NOTE 3 1.95

4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE

0.75 0.15
0 -8 0.05
0.50

DETAIL A
TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8

SYMM

6X (0.65)
5
4

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8

SYMM

6X (0.65)
5
4

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221848/A 02/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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