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WO2016061961A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2016061961A1
WO2016061961A1 PCT/CN2015/072901 CN2015072901W WO2016061961A1 WO 2016061961 A1 WO2016061961 A1 WO 2016061961A1 CN 2015072901 W CN2015072901 W CN 2015072901W WO 2016061961 A1 WO2016061961 A1 WO 2016061961A1
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Prior art keywords
doped region
layer
array substrate
pattern
low doped
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PCT/CN2015/072901
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English (en)
French (fr)
Inventor
谢振宇
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US14/769,765 priority Critical patent/US9917198B2/en
Publication of WO2016061961A1 publication Critical patent/WO2016061961A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6719—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions having significant overlap between the lightly-doped drains and the gate electrodes, e.g. gate-overlapped LDD [GOLDD] TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6721—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions having lightly-doped extensions consisting of multiple lightly doped zones or having non-homogeneous dopant distributions, e.g. graded LDD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • LTPS Low Temperature Poly-Silicon
  • TFT Thin Film Transistor
  • LTPS TFTs Although LTPS technology has been vigorously developed, LTPS TFTs still have problems in that leakage current cannot be effectively suppressed and excessive heat is generated. Among them, the problem that the LTPS TFT generates excessive heat is caused by the large electric field in the horizontal direction of the LTPS TFT and the collision ionization caused by the acceleration of the electron under the action of the electric field.
  • the excessive heat generated by the LTPS TFT causes the following effects: excessive heat causes lattice scattering, causing diffusion of sodium metal into the active region in the glass substrate, thereby affecting the threshold voltage (Vth) of the LTPS TFT;
  • Vth threshold voltage
  • the negative resistance phenomenon causes the carrier mobility and the conduction current to decrease; the long-term influence will cause the LTPS TFT characteristics to deteriorate and affect the product quality.
  • the active region of the LTPS TFT adopts a lightly doped drain (LDD) structure, which can effectively reduce the heat generation of the LTPS TFT, and the leakage current of the LTPS TFT also decreases.
  • LDD lightly doped drain
  • the resistance of the LDD is relatively high, it is equivalent to connecting a resistor with a large resistance value in series, thereby reducing the electric field strength in the horizontal direction of the LTPS TFT, improving the electric field distribution of the LTPS TFT channel, thereby reducing the electric field acceleration.
  • the probability of causing hot carriers generated by impact ionization while effectively suppressing the generation of leakage current.
  • the present disclosure provides an array substrate, a manufacturing method thereof, and a display device, thereby effectively reducing heat generation of a low-temperature polysilicon thin film transistor and effectively suppressing leakage current of the polysilicon thin film transistor under the premise of ensuring an aperture ratio.
  • An embodiment of the first aspect of the present disclosure provides an array substrate, including:
  • An active layer, a gate insulating layer, and a gate electrode layer are sequentially disposed on the substrate, wherein the active layer is sequentially disposed with a first heavily doped region, a first low doped region, and a first undoped layer in a horizontal direction a region, a second low doped region, a second undoped region, a third lowly doped region, and a second heavily doped region.
  • the second low doped region is disposed at an intermediate position in a horizontal direction of the active layer.
  • a projection area of the gate electrode layer on the array substrate covers the first low doped region, the first undoped region, the second low doped region, a projection area of the second undoped region and the third lowly doped region on the array substrate.
  • the pattern of the gate electrode layer includes a pattern of the first gate electrode and a pattern of the second gate electrode, wherein
  • a projection area of the second gate electrode on the array substrate covers a projection area of the second undoped area on the array substrate.
  • the array substrate further includes:
  • a first insulating layer disposed between the substrate and the active layer.
  • the array substrate further includes:
  • a source/drain electrode layer disposed on the second insulating layer, wherein the source/drain electrode layer includes a source electrode line and a drain electrode line, wherein the source electrode line passes through the second insulating layer and the gate a first via hole in the insulating layer is electrically connected to the first heavily doped region, the drain electrode line via a second via hole penetrating the second insulating layer and the gate insulating layer, and the second weight Doped region electrical connection;
  • a pixel electrode layer disposed on the passivation layer, the pixel electrode layer being electrically connected to the drain electrode line via a third via provided in the passivation layer.
  • the array substrate further includes:
  • a common electrode layer disposed over the protective layer.
  • the first low doped region, the second low doped region, and the third low doped region have lengths of about 1 micrometer to about 3 micrometers, respectively; the first low doped region
  • the ion implantation concentration of the second low doped region and the third low doped region is about 5 ions/cm 2 to about 30 ions/cm 2 .
  • the first heavily doped region and the second heavily doped region have an ion implantation concentration of about 10 ions/cm 2 to about 15 ions/cm 2 ; the first heavily doped region and the first The length of the double doped region is from about 2 microns to about 5 microns, respectively.
  • An embodiment of the second aspect of the present disclosure further provides a method of fabricating an array substrate, comprising the steps of:
  • an active layer, a gate insulating layer, and a gate electrode layer pattern on the substrate wherein the active layer is sequentially provided with a first heavily doped region, a first low doped region, and a first undoped layer in the horizontal direction. a hetero region, a second low doped region, a second undoped region, a third low doped region, and a second heavily doped region.
  • the second low doped region is formed at an intermediate position in a horizontal direction of the active layer.
  • Coating a photoresist on the silicon island forming a plurality of notches in the photoresist by a patterning process, the plurality of notches being located in the first low doped region in the silicon island, Above the position where the second low doped region and the third low doped region are located;
  • a gate insulating layer film and a gate layer film on the silicon island Forming a gate insulating layer film and a gate layer film on the silicon island, and forming a pattern of the gate insulating layer and a pattern of the gate electrode layer by a patterning process, wherein a pattern of the gate electrode layer is a projection area on the array substrate covering the first low doped region, the first undoped region, the second low doped region, and the second undoped region in the active layer a projection area of the third low doped region on the array substrate;
  • the method of sequentially forming an active layer, a gate insulating layer, and a gate electrode layer on the substrate also include:
  • the pattern of the gate electrode layer includes the first a pattern of a gate electrode and a pattern of a second gate electrode, a pattern of the first gate electrode on a projection area on the array substrate, covering the first undoped region in the active layer on the array substrate a projection area on the upper surface, a projection area of the second gate electrode on the array substrate, and a projection area of the second undoped area on the array substrate in the active layer;
  • the step of sequentially forming the patterns of the active layer, the gate insulating layer and the gate electrode layer on the substrate before the photoresist is coated on the silicon island further comprises:
  • Ion implantation is performed on the silicon island.
  • the method further includes:
  • a pattern of a first insulating layer is formed over the substrate, and a pattern of the active layer is disposed over the first insulating layer.
  • the method further includes:
  • first via and a second via in the second insulating layer and the gate insulating layer, the first via being located above the first heavily doped region, the second via being located Above the second heavily doped region;
  • the source-drain electrode layer including a source electrode line and a drain electrode line, wherein the source electrode line and the first weight via the first via hole
  • the doped region is electrically connected, and the drain electrode line is electrically connected to the second heavily doped region via the second via hole;
  • a pattern of a pixel electrode layer is formed over the passivation layer, and the pixel electrode layer is electrically connected to the drain electrode line via the third via.
  • the method further includes:
  • a pattern of a common electrode layer is formed over the protective layer.
  • the first low doped region, the second low doped region, and the third low doped region have lengths of about 1 micrometer to about 3 micrometers, respectively; the first low doped region
  • the ion implantation concentration of the second low doped region and the third low doped region is about 5 ions/cm 2 to about 30 ions/cm 2 .
  • the first heavily doped region and the second heavily doped region have an ion implantation concentration of about 10 ions/cm 2 to about 15 ions/cm 2 ; the first heavily doped region and the first The length of the double doped region is from about 2 microns to about 5 microns, respectively.
  • the embodiment of the third aspect of the present disclosure further provides a display device, which may specifically include the array substrate provided by the embodiment of the present disclosure.
  • the array substrate provided by the present disclosure, the manufacturing method thereof, and the display device are provided with an active layer, a gate insulating layer and a gate electrode layer, which are sequentially disposed on the substrate of the array substrate.
  • the first heavily doped region, the first low doped region, the first undoped region, the second low doped region, the second undoped region, and the third lowly doped region are sequentially disposed in the horizontal direction. Double doped area. Therefore, under the premise of ensuring the aperture ratio, the heat generation of the low-temperature polysilicon thin film transistor can be effectively reduced and the leakage current of the polysilicon thin film transistor can be effectively suppressed.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a state of an array substrate in an implementation process of an array substrate according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a state of an array substrate during implementation of an array substrate manufacturing method according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a state of an array substrate during implementation of an array substrate manufacturing method according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a state of an array substrate during implementation of an array substrate manufacturing method according to an embodiment of the present disclosure
  • FIG. 11 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a state of an array substrate during implementation of an array substrate manufacturing method according to an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of a state of an array substrate in an implementation process of an array substrate manufacturing method according to an embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of a state of an array substrate in an implementation process of an array substrate manufacturing method according to an embodiment of the present disclosure
  • FIG. 15 is a schematic diagram of a state of an array substrate during implementation of an array substrate manufacturing method according to an embodiment of the present disclosure.
  • an array substrate As shown in FIG. 1 , the array substrate may specifically include:
  • the active layer, the gate insulating layer 3, and the gate electrode layer 4 of the substrate 1 are sequentially disposed, wherein the active layer
  • the first heavily doped region 21, the first low doped region 22, the first undoped region 23, the second low doped region 24, the second undoped region 25, and the third low are sequentially disposed in the horizontal direction.
  • a plurality of low-doped regions having high resistance values are disposed at a position in the middle of the communication region of the thin film transistor and at predetermined positions on both sides, thereby reducing the acceleration distance of the electron under the electric field. Therefore, the kinetic energy of the electron and the probability of colliding with the hot carrier generated by the ion are reduced, which can effectively reduce the heat generation of the low temperature polysilicon thin film transistor and effectively suppress the leakage current.
  • the second low doping region 24 may be specifically disposed at an intermediate position of the active layer in a horizontal direction, such that when electrons are transmitted in two undoped regions, It is inevitably passed through the second low-doped region 24, so that the speed of electron transport and kinetic energy can be reduced to achieve the purpose of reducing heat and suppressing leakage current.
  • the second low doping region 24 may also be disposed at a preset position near the first low doping region 22 or the third low doping region 26.
  • the length of the low-doped region is controlled so that the aperture ratio can be improved while satisfying the characteristics of the channel region characteristics of the thin film transistor.
  • control of the length of the low doped region can also be achieved by adjusting the ion implantation type and concentration.
  • the channel region structure in the array substrate provided by the embodiment of the present disclosure may be an NMOS structure or a PMOS structure.
  • an NMOS is taken as an example to provide an array according to an embodiment of the present disclosure.
  • the structure of the substrate will be described in detail.
  • the array substrate provided by the embodiment of the present disclosure may specifically be a single gate array substrate or a double gate array substrate.
  • the projection area of the gate electrode layer 4 (ie, the gate) on the array substrate can cover the first low.
  • the doped region 22, the first undoped region 23, the second lowly doped region 24, the second undoped region 25, and the third lowly doped region 26 are projected on the array substrate, thereby achieving low leakage current
  • the feature of small graphic area is beneficial to enhance the design of the product and achieve higher resolution (PPI).
  • the pattern of the gate electrode layer 4 may specifically include a pattern of the first gate electrode 41 (ie, the first gate) and a second A pattern of gate electrode 42 (ie, the second gate).
  • the projection area of the pattern of the first gate electrode 41 on the array substrate may cover the projection area of the first undoped area 23 on the array substrate; the projection area of the pattern of the second gate electrode 42 on the array substrate may A projection area of the second undoped region 25 on the array substrate is covered.
  • the three low-doped regions are respectively located on the two sides and the middle of the two undoped regions. Therefore, the pattern of the gate electrode layer 4 is used to block the structural arrangement of the undoped regions, which is beneficial in the manufacturing process. The length of the position of the low doped region is precisely controlled.
  • the array substrate provided by the embodiment of the present disclosure may further include:
  • the first insulating layer 5 is disposed between the substrate 1 and the active layer.
  • the arrangement of the first insulating layer 5 can serve the purpose of isolating the substrate 1 from the active layer.
  • the array substrate provided by the embodiment of the present disclosure may further include:
  • a second insulating layer 6 disposed on the gate insulating layer 3 and the gate electrode layer 4;
  • the source/drain electrode layer disposed on the second insulating layer 6 specifically includes a source electrode line 71 (ie, a source) and a drain electrode line 72 (ie, a drain), wherein the source electrode line 71 passes through The first via 61 of the second insulating layer 6 and the gate insulating layer 3 is electrically connected to the first heavily doped region 21, and the drain electrode line 72 passes through the second via 62 penetrating the second insulating layer 6 and the gate insulating layer 3. It is electrically connected to the second heavily doped region 27.
  • the positions at which the source electrode line 71 and the drain electrode line 72 are disposed are interchangeable.
  • the array substrate provided by the embodiment of the present disclosure may further include:
  • a passivation layer 8 disposed on the source/drain electrode layer, and a third via 81 disposed in the passivation layer 8;
  • the pixel electrode layer 9 is disposed on the passivation layer 8, and the pixel electrode layer 9 is electrically connected to the drain electrode line 72 via a third via 81 provided in the passivation layer 8.
  • the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 2 or 3, may further include:
  • a protective layer 10 disposed over the passivation layer 8 and the pixel electrode layer 9;
  • the common electrode layer 11 is disposed on the protective layer 10.
  • the lengths of the low doped regions may specifically be about 1 micrometer to about 3 micrometers, respectively.
  • the ion implantation concentration of the first low doped region 22, the second low doped region 24, and the third low doped region 26 may specifically be about 5 ions/cm 2 to about 30 ions/cm 2 , for example, about 10ions/cm 2 .
  • the ion implantation concentration of the first heavily doped region 21 and the second heavily doped region 27 may specifically range from about 10 ions/cm 2 to about 15 ions/cm 2 , which belongs to the heavy doping category and the length thereof. Specifically, they may be from about 2 microns to about 5 microns, respectively.
  • the embodiment of the second aspect of the present disclosure further provides a method for fabricating an array substrate. As shown in FIG. 4, the method may specifically include:
  • a pattern of an active layer, a gate insulating layer 3, and a gate electrode layer 4 are sequentially formed, wherein the active layer is sequentially provided with a first heavily doped region 21 and a first lowly doped region 22 in the horizontal direction. a first undoped region 23, a second lowly doped region 24, a second undoped region 25, a third lowly doped region 26, and a second heavily doped region 27.
  • the method for fabricating an array substrate may further include:
  • a pattern of the first insulating layer 5 is formed on the substrate 1.
  • the method for fabricating an array substrate may further include:
  • a first via 61 and a second via 62 are formed in the second insulating layer 6 and the gate insulating layer 3, the first via 61 is located above the first heavily doped region 21, and the second via 62 is located at the second weight Above the doped region 27;
  • a source/drain electrode layer is formed over the second insulating layer 6, and the source and drain electrode layers include a source electrode line 71 and a drain electrode line 72, wherein the source electrode line 71 passes through the first via 61 and the first heavily doped region 21 Electrically connected, the drain electrode line 72 is electrically connected to the second heavily doped region 27 via the second via 62;
  • the passivation layer 8 includes a third via 81;
  • a pattern of the pixel electrode layer 9 is formed on the passivation layer 8, and the pixel electrode layer 9 is electrically connected to the drain electrode line 72 via the third via 81.
  • the method for fabricating the array substrate provided by the embodiment of the present disclosure may further include:
  • a pattern of the common electrode layer 11 is formed over the protective layer 10.
  • the array substrate provided by the embodiment of the present disclosure may be a single gate type array substrate or a double gate type array substrate. Therefore, the fabrication of the array provided by the embodiments of the present disclosure is exemplified below by taking a single gate type and a double gate type array substrate as an example. The method of the substrate will be described in detail.
  • the method may specifically include:
  • step 51 a pattern of the first insulating layer 5 is formed on the substrate 1.
  • the first insulating layer 5 and the second insulating layer 6 involved in the embodiments of the present disclosure are generally made of a SiNx/SiO 2 film combination or a SiO 2 film, and are subjected to high temperature treatment for dehydrogenation after deposition is completed, so as not to affect The semiconductor characteristics of the active layer formed thereon.
  • Step 52 depositing an amorphous silicon film on the first insulating layer 5, and after crystallization of the amorphous silicon film, forming a silicon island 2 of the active layer by a patterning process.
  • an amorphous silicon film layer may be deposited on the first insulating layer 5, and after the laser annealing and crystallization, a polysilicon film layer is formed, and the polysilicon film layer is patterned (including coating, exposure, and development of the photoresist). And an etching process) forming the silicon island 2 of the active layer.
  • the schematic diagram of the state of the array substrate after this step can be specifically as shown in FIG. 6.
  • Step 53 coating a photoresist (PR) on the silicon island 2, and forming a plurality of notches in the photoresist by a patterning process, the plurality of notches being located in the first low doping region 22 of the active layer
  • the second low doped region 24 and the third low doped region 26 are located above.
  • Step 54 performing ion implantation into the first low doped region 22, the second low doped region 24, and the third low doped region 26 of the silicon island 2 through a plurality of gaps to form an active layer.
  • the lengths of the low doped regions may specifically be about 1 micrometer to about 3 micrometers, respectively. For example about 1.5 microns.
  • the ion implantation concentration of the low doping region may specifically be about 5 ions/cm 2 to about 30 ions/cm 2 , for example, about 10 ions/cm 2 .
  • the ion to which the embodiment of the present disclosure relates may specifically be a phosphine (PH 3 ) ion or the like.
  • the low-doped region and the undoped region are spaced apart, and the non-doped region does not need to be ion-implanted, that is, the material of the undoped region is the material of the silicon island 2, so when the first low-doping After the fabrication of the second region 22, the second lowly doped region 24, and the third lowly doped region 26 is completed, the first undoped region 23 and the second undoped region 25 are also simultaneously completed.
  • the schematic diagram of the state of the array substrate after this step can be specifically as shown in FIG. 7.
  • step 55 a thin film of the gate insulating layer 3 and a thin film of the gate layer 5 are sequentially deposited on the silicon island 2, and a pattern of the gate insulating layer 3 and a pattern of the gate electrode layer 4 are formed by a patterning process.
  • the projection area of the gate electrode layer 4 on the array substrate covers the first low doped region 22, the first undoped region 23, the second low doped region 24, and the second undoped layer in the active layer.
  • this step may adopt a conventional patterning process to form a pattern of the gate insulating layer 3 and the gate electrode layer 4 by a process such as gluing, exposure, development, etching, lift-off, or the like.
  • the schematic diagram of the state of the array substrate after this step can be specifically as shown in FIG. 8.
  • Step 56 performing ion implantation at a position of the first heavily doped region 21 and the second heavily doped region 27 in the silicon island 2 to form a first heavily doped region 21 and a second heavily doped region in the active layer 27.
  • the ion implantation concentration of the heavily doped region may specifically range from about 10 ions/cm 2 to about 15 ions/cm 2 , which belongs to the heavy doping category.
  • the length of the heavily doped region can be the same as in the prior art.
  • FIG. 1 A schematic diagram of the state of the array substrate after this step can be specifically shown in FIG.
  • step 57 the patterns of the second insulating layer 6, the source/drain electrode layer, the passivation layer 8, and the pixel electrode layer 9 are sequentially formed.
  • the specific steps in this step may include:
  • a first via 61 and a second via 62 are formed in the second insulating layer 6 and the gate insulating layer 3, the first via 61 is located above the first heavily doped region 21, and the second via 62 is located at the second weight Above the doped region 27;
  • a source/drain electrode layer is formed over the second insulating layer 6, and the source and drain electrode layers include a source electrode line 71 and a drain electrode line 72, wherein the source electrode line 71 passes through the first via 61 and the first heavily doped region 21 Electrically connected, the drain electrode line 72 is electrically connected to the second heavily doped region 27 via the second via 62.
  • the state of the array substrate can be as shown in FIG. 10 (top view);
  • the passivation layer 8 includes a third via 81;
  • a pattern of the pixel electrode layer 9 is formed on the passivation layer 8, and the pixel electrode layer 9 is electrically connected to the drain electrode line 72 via the third via 81.
  • each layer in step 57 can be completed by a conventional patterning process.
  • step 58 a pattern of the protective layer 10 and the common electrode layer 11 is formed.
  • This step may specifically include:
  • a pattern of the common electrode layer 11 is formed over the protective layer 10.
  • each layer in step 58 can be accomplished using a conventional patterning process.
  • the single-gate array substrate provided by the embodiment of the present disclosure can be fabricated by the above-mentioned fabrication process.
  • the specific structure of the array substrate can be as shown in FIG. 2 .
  • the method may specifically include:
  • step 111 a pattern of the first insulating layer 5 is formed on the substrate 1.
  • Step 112 depositing an amorphous silicon film on the first insulating layer 5, after crystallization of the amorphous silicon film,
  • the silicon island 2 of the active layer is formed by a patterning process.
  • a schematic diagram of the state of the array substrate after this step can be as shown in FIG. 6.
  • step 113 a photoresist is coated on the silicon island 2, and the photoresist above the first heavily doped region 21 and the second heavily doped region 27 in the silicon island 2 is etched away by a patterning process.
  • Step 114 performing ion implantation on the first heavily doped region 21 and the second heavily doped region 27 in the silicon island 2 to form a first heavily doped region 21 and a second heavily doped region in the active layer. 27.
  • the phosphine (PH 3 ) ions may be implanted into the silicon island 2 at the position of the first heavily doped region 21 and the second heavily doped region 27 to form the first heavily doped region 21 (N + SI) and a second heavily doped region 27 (N + SI).
  • step 115 a thin film of the gate insulating layer 3 and a thin film of the gate electrode layer 4 are sequentially deposited on the silicon island 2, and a pattern of the gate insulating layer 3 and a pattern of the gate electrode layer 4 are formed by a patterning process.
  • the pattern of the gate electrode layer 4 includes a pattern of the first gate electrode 41 and a pattern of the second gate electrode 42, wherein the pattern of the first gate electrode 41 on the array substrate may cover the first undoped region 23 at a projection area on the array substrate; a projection area of the pattern of the second gate electrode 42 on the array substrate may cover a projection area of the second undoped area 25 on the array substrate.
  • the three low-doped regions are respectively located on the two sides and the middle of the two undoped regions, so that the structure of the undoped region is blocked by the gate electrode pattern, which is favorable for precise control in the subsequent manufacturing process.
  • the position and width of the low doped region are respectively located on the two sides and the middle of the two undoped regions, so that the structure of the undoped region is blocked by the gate electrode pattern, which is favorable for precise control in the subsequent manufacturing process.
  • this step may adopt a conventional patterning process to form a pattern of the gate insulating layer 3 and the gate electrode layer 4 by a process such as gluing, exposure, development, etching, lift-off, or the like.
  • the etching process involved in this step can be specifically performed by a dry etching process.
  • High resolution photoresists can be used on photoresist material selection in mask pattern selection.
  • a phase mask technique or a Wing Pattern Mask technique can be used, or a combination of the above mask techniques can be used, so that the position and width of the pattern of the gate layer 4 can be precisely controlled, thereby facilitating precise control of low The position and width of the doped region.
  • the schematic diagram of the state of the array substrate after this step can be specifically as shown in FIG.
  • Step 116 performing ion implantation at a position of the first low doping region 22, the second low doping region 24, and the third low doping region 26 in the silicon island 2 to form a first low doping region in the active layer 22.
  • the pattern of the first gate electrode 41 is located above the first undoped region 23 and covers the first undoped layer
  • the pattern of the second gate electrode 42 is located above the second undoped region 25 and covers the second undoped region 25. Therefore, in this step, the pattern of the gate electrode layer 4 that has been completed can be used as a reference. From the pattern of the first gate electrode 41 and the two sides of the pattern of the second gate electrode 42 and intermediate positions, ions are implanted into the silicon island 2, thereby forming a first low doped region 22 in the active layer, and a second low doping Region 24, third low doped region 26.
  • the schematic diagram of the state of the array substrate after this step can be specifically as shown in FIG.
  • This step may be the same as or similar to step 57, but after the source electrode line 71 and the drain electrode line 72 are formed over the second insulating layer 6, the state of the array substrate may be as shown in FIG. 15 (top view).
  • Step 118 forming a pattern of the protective layer 10 and the common electrode layer 11.
  • This step may specifically include:
  • a pattern of the common electrode layer 11 is formed over the protective layer 10.
  • each layer in step 118 can be accomplished using a conventional patterning process.
  • the double-gate array substrate provided by the embodiment of the present disclosure can be fabricated by the above-mentioned fabrication process.
  • the specific structure of the array substrate can be as shown in FIG. 3 .
  • the array substrate channel region ie, thin film transistor TFT
  • threshold voltage (Vth) doping Vth
  • the Doping process is to achieve the purpose of adjusting the threshold voltage setting of the channel region of the array substrate by injecting ions of the corresponding type and number of levels of concentration into the active layer silicon island 2 that has been formed.
  • the display device may specifically be a display device such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED display, a plasma display, or an electronic paper.
  • a display device such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED display, a plasma display, or an electronic paper.
  • the array substrate provided by the present disclosure, the manufacturing method thereof, and the display device are provided with an active layer, a gate insulating layer and a gate electrode layer, which are sequentially disposed on the substrate of the array substrate.
  • the first heavily doped region, the first low doped region, the first undoped region, the second low doped region, the second undoped region, and the third lowly doped region are sequentially disposed in the horizontal direction. Double doped area. Therefore, under the premise of ensuring the aperture ratio, the heat generation of the low-temperature polysilicon thin film transistor can be effectively reduced and the leakage current of the polysilicon thin film transistor can be effectively suppressed.

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Abstract

一种阵列基板及其制作方法、显示装置。所述阵列基板包括：依次设置在基板（1）上的有源层、栅绝缘层（3）以及栅电极层（4），所述有源层在水平方向上依次设置有第一重掺杂区（21）、第一低掺杂区（22）、第一非掺杂区（23）、第二低掺杂区（24）、第二非掺杂区（25）、第三低掺杂区（26）、第二重掺杂区（27）。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2014年10月22日在中国提交的中国专利申请号No.201410566635.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，具体可以涉及一种阵列基板及其制作方法、显示装置。
背景技术
低温多晶硅(LTPS：Low Temperature Poly-Silicon)技术是新一代的薄膜晶体管(TFT：Thin Film Transistor)显示装置制造工艺，LTPS TFT显示装置具有更快的响应时间，更高的分辨率，因此具有更佳的画面显示品质。在形成显示装置外围的电路时使用LTPS技术，能够减少集成电路(IC)，简化显示装置的外围，进而实现窄边框技术。
LTPS技术虽然得到大力发展，但是LTPS TFT仍然存在漏电流(leakage Current)无法有效抑制以及产生热量过大的问题。其中，LTPS TFT产生热量过大的问题是由于LTPS TFT在水平方向电场较大，电子在电场加速的作用下，引起碰撞电离所导致的。LTPS TFT产生热量过大会导致以下几方面的影响：过多的热导致晶格散射，造成玻璃基板中如钠金属扩散至有源区，从而影响LTPS TFT的阈值电压(Vth)；在饱和区产生负阻现象，使得载流子迁移率与导通电流下降；长期的影响会导致LTPS TFT特性恶化，影响产品品质。
通过研究发现，在LTPS TFT的有源区采用轻掺杂漏区(LDD：Lightly Doped Drain)的结构设置，可有效降低LTPS TFT热量的产生，且LTPS TFT的漏电流也随着降低。这是因为，由于LDD的阻值相对较高，等效于串联了一个阻值较大的电阻，因此降低了LTPS TFT水平方向的电场强度，改善了LTPS TFT沟道电场分布，从而降低电场加速引起的碰撞电离产生的热载流子的几率，同时有效抑制漏电流的产生。
但是，现有技术存在一个技术矛盾点，即当LDD长度过短时，LDD失去了降低热量产生以及抑制漏电流的效果，而当LDD过长时，增加LTPS TFT 功率的消耗，并影响了显示装置的开口率。
发明内容
本公开提供一种阵列基板及其制作方法、显示装置，从而可在确保开口率的前提下，有效降低低温多晶硅薄膜晶体管的热量产生以及有效抑制多晶硅薄膜晶体管的漏电流。
本公开第一方面的实施例提供了一种阵列基板，包括：
依次设置在基板上的有源层、栅绝缘层以及栅电极层，其中所述有源层在水平方向上依次设置有第一重掺杂区、第一低掺杂区、第一非掺杂区、第二低掺杂区、第二非掺杂区、第三低掺杂区、第二重掺杂区。
可选的，所述第二低掺杂区设置于所述有源层水平方向上的中间位置。
可选的，所述栅电极层的图案在所述阵列基板上的投影区域，覆盖于所述第一低掺杂区、所述第一非掺杂区、所述第二低掺杂区、所述第二非掺杂区、所述第三低掺杂区在所述阵列基板上的投影区域。
可选的，所述栅电极层的图案包括第一栅电极的图案和第二栅电极的图案，其中
所述第一栅电极的图案在所述阵列基板上的投影区域，覆盖所述第一非掺杂区在所述阵列基板上的投影区域；
所述第二栅电极的图案在所述阵列基板上的投影区域，覆盖所述第二非掺杂区在所述阵列基板上的投影区域。
可选的，所述阵列基板还包括：
设置于所述基板与所述有源层之间的第一绝缘层。
可选的，所述阵列基板还包括：
设置于所述栅绝缘层以及所述栅电极层之上的第二绝缘层；
设置于所述第二绝缘层之上的源漏电极层，所述源漏电极层中包括源电极线和漏电极线，其中所述源电极线经由贯穿所述第二绝缘层和所述栅绝缘层中的第一过孔与所述第一重掺杂区电连接，所述漏电极线经由贯穿所述第二绝缘层和所述栅绝缘层的第二过孔与所述第二重掺杂区电连接；
设置于所述源漏电极层之上的钝化层；和
设置于所述钝化层之上的像素电极层，所述像素电极层经由设置于所述钝化层中的第三过孔与所述漏电极线电连接。
可选的，所述阵列基板还包括：
设置于所述钝化层和所述像素电极层之上的保护层；和
设置于所述保护层之上的公共电极层。
可选的，所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区的长度分别为约1微米至约3微米；所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区的离子注入浓度为约5ions/厘米2至约30ions/厘米2。
可选地，所述第一重掺杂区和所述第二重掺杂区的离子注入浓度为约10ions/厘米2至约15ions/厘米2；所述第一重掺杂区和所述第二重掺杂区的长度分别为约2微米至约5微米。
本公开第二方面的实施例还提供了一种制作阵列基板的方法，包括以下步骤：
在基板上依次形成有源层、栅绝缘层以及栅电极层的图案，其中所述有源层在水平方向上依次设置有第一重掺杂区、第一低掺杂区、第一非掺杂区、第二低掺杂区、第二非掺杂区、第三低掺杂区、第二重掺杂区。
可选的，所述第二低掺杂区形成于所述有源层水平方向上的中间位置。
可选的，所述在基板之上依次形成有源层、栅绝缘层以及栅电极层的图案的步骤包括：
在所述基板上沉积非晶硅薄膜，在所述非晶硅薄膜晶化后，通过构图工艺，形成所述有源层的硅岛；
在所述硅岛上涂覆光刻胶，通过构图工艺，在所述光刻胶中形成多个缺口，所述多个缺口位于所述硅岛中所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区所在位置处的上方；
经由所述多个缺口，向所述硅岛中所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区所在位置进行离子注入，形成所述有源层中的所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区；
在所述硅岛之上依次沉积栅绝缘层薄膜和栅极层薄膜，通过构图工艺，形成所述栅绝缘层的图案和所述栅电极层的图案，所述栅电极层的图案在所述阵列基板上的投影区域，覆盖于所述有源层中所述第一低掺杂区、所述第一非掺杂区、所述第二低掺杂区、所述第二非掺杂区、所述第三低掺杂区在所述阵列基板上的投影区域；
向所述硅岛中所述第一重掺杂区和所述第二重掺杂区所在位置处进行离子注入，形成所述有源层中的所述第一重掺杂区和所述第二重掺杂区。
可选的，所述在基板之上依次形成有源层、栅绝缘层以及栅电极层的图 案的步骤还包括：
在所述基板上沉积非晶硅薄膜，在所述非晶硅薄膜晶化后，通过构图工艺，形成所述有源层的硅岛；
在所述硅岛上涂覆光刻胶，通过构图工艺，刻蚀掉所述硅岛中所述第一重掺杂区和所述第二重掺杂区所在位置处上方的所述光刻胶；
对所述硅岛中所述第一重掺杂区和所述第二重掺杂区所在位置处进行离子注入，形成所述有源层中的所述第一重掺杂区和所述第二重掺杂区；
在所述硅岛之上依次沉积栅绝缘层薄膜和栅极层薄膜，通过构图工艺，形成所述栅绝缘层的图案和所述栅电极层的图案，所述栅电极层的图案包括第一栅电极的图案和第二栅电极的图案，所述第一栅电极的图案在所述阵列基板上的投影区域，覆盖所述有源层中所述第一非掺杂区在所述阵列基板上的投影区域，所述第二栅电极的图案在所述阵列基板上的投影区域，覆盖所述有源层中所述第二非掺杂区在所述阵列基板上的投影区域；
透过所述栅绝缘层的图案，向所述硅岛中所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区所在位置处进行离子注入，形成所述有源层中的所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区。
可选的，在所述硅岛上涂覆光刻胶之前，所述在基板之上依次形成有源层、栅绝缘层以及栅电极层的图案的步骤还包括：
对所述硅岛进行离子注入。
可选的，在所述在基板之上依次形成有源层、栅绝缘层以及栅电极层的图案的步骤之前，所述方法还包括：
在所述基板之上形成第一绝缘层的图案，所述有源层的图案设置于所述第一绝缘层之上。
可选的，所述方法还包括：
在所述栅绝缘层以及所述栅电极层之上形成第二绝缘层的图案；
在所述第二绝缘层和所述栅绝缘层中形成第一过孔和第二过孔，所述第一过孔位于所述第一重掺杂区之上，所述第二过孔位于所述第二重掺杂区之上；
在所述第二绝缘层之上形成源漏电极层，所述源漏电极层中包括源电极线和漏电极线，其中所述源电极线经由所述第一过孔与所述第一重掺杂区电连接，所述漏电极线经由所述第二过孔与所述第二重掺杂区电连接；
在所述源漏电极层之上形成钝化层的图案，所述钝化层的图案中包括第 三过孔；
在所述钝化层之上形成像素电极层的图案，所述像素电极层经由所述第三过孔与漏电极线电连接。
可选的，所述方法还包括：
在所述钝化层和所述像素电极层之上形成保护层的图案；
在所述保护层之上形成公共电极层的图案。
可选的，所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区的长度分别为约1微米至约3微米；所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区的离子注入浓度为约5ions/厘米2至约30ions/厘米2。
可选地，所述第一重掺杂区和所述第二重掺杂区的离子注入浓度为约10ions/厘米2至约15ions/厘米2；所述第一重掺杂区和所述第二重掺杂区的长度分别为约2微米至约5微米。
本公开第三方面的实施例还提供了一种显示装置，该显示装置具体可以包括上述本公开实施例提供的阵列基板。
从以上所述可以看出，本公开提供的阵列基板及其制作方法、显示装置，通过在阵列基板的基板之上，依次设置有源层、栅绝缘层以及栅电极层，所述有源层在水平方向上依次设置有第一重掺杂区、第一低掺杂区、第一非掺杂区、第二低掺杂区、第二非掺杂区、第三低掺杂区、第二重掺杂区。从而可在确保开口率的前提下，有效降低低温多晶硅薄膜晶体管的热量产生以及有效抑制多晶硅薄膜晶体管的漏电流。
附图说明
图1为本公开实施例提供的阵列基板的结构示意图；
图2为本公开实施例提供的阵列基板的结构示意图；
图3为本公开实施例提供的阵列基板的结构示意图；
图4为本公开实施例提供的阵列基板制作方法流程示意图；
图5为本公开实施例提供的阵列基板制作方法流程示意图；
图6为本公开实施例提供的阵列基板制作方法实现过程中阵列基板状态示意图；
图7为本公开实施例提供的阵列基板制作方法实现过程中阵列基板状态示意图；
图8为本公开实施例提供的阵列基板制作方法实现过程中阵列基板状态 示意图；
图9为本公开实施例提供的阵列基板制作方法实现过程中阵列基板状态示意图；
图10为本公开实施例提供的阵列基板制作方法实现过程中阵列基板状态示意图；
图11为本公开实施例提供的阵列基板制作方法流程示意图；
图12为本公开实施例提供的阵列基板制作方法实现过程中阵列基板状态示意图；
图13为本公开实施例提供的阵列基板制作方法实现过程中阵列基板状态示意图；
图14为本公开实施例提供的阵列基板制作方法实现过程中阵列基板状态示意图；
图15为本公开实施例提供的阵列基板制作方法实现过程中阵列基板状态示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开第一方面的实施例提供了一种阵列基板，如图1所示，该阵列基板具体可以包括：
依次设置在基板1的有源层、栅绝缘层3以及栅电极层4，其中有源层 在水平方向上依次设置有第一重掺杂区21、第一低掺杂区22、第一非掺杂区23、第二低掺杂区24、第二非掺杂区25、第三低掺杂区26、第二重掺杂区27。
本公开实施例所提供的阵列基板，通过在薄膜晶体管沟通区域的中间以及两侧预设位置处，设置多个具有高阻值的低掺杂区，从而可降低电子在电场作用下的加速距离，从而降低了电子的动能以及碰撞电离子产生的热载流子的几率，可有效降低低温多晶硅薄膜晶体管的热量产生以及有效抑制漏电流。
本公开实施例中，如图1所示，第二低掺杂区24具体可设置于所述有源层在水平方向的中间位置，这样，当电子在两个非掺杂区传输过程中，必然会经过第二低掺杂区24，从而可以降低电子传输的速度以及动能，以实现降低热量以及抑制漏电流的目的。而在本公开其他实施例中，第二低掺杂区24也可以设置于靠近第一低掺杂区22或第三低掺杂区26的预设位置处。
本公开实施例中，可基于阵列基板沟道区域电场强度，或者薄膜晶体管(TFT)(例如低温多晶硅薄膜晶体管LTPS TFT)的开态电流(Ion)或关态电流(Ioff)等特性要求，对低掺杂区的长度进行控制，从而可在满足薄膜晶体管沟道区域特性需求的前提下，实现开口率的提升。
本公开实施例中，还可通过对离子注入种类和浓度的调节，从而实现对低掺杂区长度的控制。
本公开实施例所提供的阵列基板中的沟道区域结构既可以为NMOS结构，也可以为PMOS结构等，为了便于说明，后续描述时，以采用NMOS为例，对本公开实施例所提供的阵列基板结构进行详细说明。
本公开实施例所提供的阵列基板，具体可为单栅型阵列基板，也可以为双栅型阵列基板。
当本公开实施例所提供的阵列基板为单栅型阵列基板时，如图1或2所示，栅电极层4的图案(即栅极)在阵列基板上的投影区域，可覆盖第一低掺杂区22、第一非掺杂区23、第二低掺杂区24、第二非掺杂区25、第三低掺杂区26在阵列基板上的投影区域，从而在实现低漏电流的同时，具有图形面积小的特性，有利于提升产品的设计度，实现更高的分辨率(PPI)。
当本公开实施例所提供的阵列基板为双栅型阵列基板时，如图3所示，栅电极层4的图案具体可以包括第一栅电极41(即第一栅极)的图案和第二栅电极42(即第二栅极)的图案。
并且，第一栅电极41的图案在阵列基板上的投影区域，可以覆盖第一非掺杂区23在阵列基板上的投影区域；第二栅电极42的图案在阵列基板上的投影区域，可以覆盖第二非掺杂区25在阵列基板上的投影区域。由于本公开实施例中，三个低掺杂区分别位于两个非掺杂区的两边和中间，因此，利用栅电极层4的图案遮挡非掺杂区的结构设置，有利于在制作过程中，精确控制低掺杂区的位置的长度。
在本公开一个具体实施例中，如图2或3所示，本公开实施例所提供的阵列基板具体还可以包括：
设置于基板1与有源层之间的第一绝缘层5。
第一绝缘层5的设置可以起到隔离基板1与有源层的目的。
在本公开一个具体实施例中，如图2或3所示，本公开实施例所提供的阵列基板具体还可以包括：
设置于栅绝缘层3以及栅电极层4之上的第二绝缘层6；和
设置于第二绝缘层6之上的源漏电极层，源漏电极层中具体包括源电极线71(即源极)和漏电极线72(即漏极)，其中，源电极线71经由贯穿第二绝缘层6和栅绝缘层3中的第一过孔61与第一重掺杂区21电连接，漏电极线72经由贯穿第二绝缘层6和栅绝缘层3的第二过孔62与第二重掺杂区27电连接。本公开实施例中，源电极线71和漏电极线72的设置位置可互换。
在本公开一个具体实施例中，如图2或3所示，本公开实施例所提供的阵列基板具体还可以包括：
设置于源漏电极层之上的钝化层8，钝化层8中设置有第三过孔81；和
设置于钝化层8之上的像素电极层9，像素电极层9经由设置于钝化层8中的第三过孔81与漏电极线72电连接。
在另一具体实施例中，本公开实施例所提供的阵列基板，如图2或3所示，具体还可以包括：
设置于钝化层8和像素电极层9之上的保护层10；和
设置于保护层10之上的公共电极层11。
本公开实施例中，低掺杂区(包括第一低掺杂区22、第二低掺杂区24和第三低掺杂区26)的长度具体可分别为约1微米至约3微米，例如约1.5微米；而第一低掺杂区22、第二低掺杂区24和第三低掺杂区26的离子注入浓度具体可为约5ions/厘米2至约30ions/厘米2，例如约10ions/厘米2。
而本公开实施例中，第一重掺杂区21和第二重掺杂区27的离子注入浓 度具体可为约10ions/厘米2至约15ions/厘米2范围，属于重掺杂范畴，其长度具体分别可为约2微米至约5微米。
为了制作本公开实施例所提供的阵列基板，本公开第二方面的实施例还提供了一种制作阵列基板的方法，如图4所示，该方法具体可以包括：
在基板1之上，依次形成有源层、栅绝缘层3以及栅电极层4的图案，其中有源层在水平方向上依次设置有第一重掺杂区21、第一低掺杂区22、第一非掺杂区23、第二低掺杂区24、第二非掺杂区25、第三低掺杂区26、第二重掺杂区27。
在一具体实施例中，本公开实施例所提供的制作阵列基板的方法具体还可以包括：
在基板1之上制作第一绝缘层5的图案。
在一具体实施例中，本公开实施例所提供的制作阵列基板的方法具体还可以包括：
在栅绝缘层3以及栅电极层4之上形成第二绝缘层6的图案；
在第二绝缘层6和栅绝缘层3中形成第一过孔61和第二过孔62，第一过孔61位于第一重掺杂区21之上，第二过孔62位于第二重掺杂区27之上；
在第二绝缘层6之上形成源漏电极层，源漏电极层中包括源电极线71和漏电极线72，其中，源电极线71经由第一过孔61与第一重掺杂区21电连接，漏电极线72经由第二过孔62与第二重掺杂区27电连接；
在源漏电极层之上形成钝化层8的图案，钝化层8中包括第三过孔81；
在钝化层8之上形成像素电极层9的图案，像素电极层9经由第三过孔81与漏电极线72电连接。
在另一具体实施例中，本公开实施例所提供的制作阵列基板的方法具体还可以包括：
在钝化层8和像素电极层9之上形成保护层10的图案；
在保护层10之上形成公共电极层11的图案。
由于本公开实施例所提供的阵列基板具体可为单栅型阵列基板或者双栅型阵列基板，因此，下面以制作单栅型和双栅型阵列基板为例，对本公开实施例提供的制作阵列基板的方法进行详细的说明。
当阵列基板为单栅型阵列基板时，如图5所示，该方法具体可以包括：
步骤51，在基板1之上制作第一绝缘层5图案。
本公开实施例中所涉及的第一绝缘层5和第二绝缘层6，通常采用的材 料为SiNx/SiO2薄膜组合或者SiO2薄膜，并在沉积完成后进行高温处理脱氢，以不影响形成在其上的有源层的半导体特性。
步骤52，在第一绝缘层5上沉积非晶硅薄膜，在非晶硅薄膜晶化后，通过构图工艺，形成有源层的硅岛2。
具体的，可在第一绝缘层5上沉积非晶硅膜层，经过激光退火晶化后，形成多晶硅膜层，对多晶硅膜层进行构图工艺(包括光刻胶的涂覆、曝光和显影，以及刻蚀工艺)形成有源层的硅岛2。
此步骤后的阵列基板状态示意图具体可如附图6所示。
步骤53，在硅岛2上涂覆光刻胶(PR)，通过构图工艺，在光刻胶中形成多个缺口，所述多个缺口位于所述有源层中第一低掺杂区22、第二低掺杂区24、第三低掺杂区26所在位置处的上方。
步骤54，分别通过多个缺口，向硅岛2中第一低掺杂区22、第二低掺杂区24、第三低掺杂区26所在位置处进行离子注入，形成有源层中的第一低掺杂区22、第二低掺杂区24、第三低掺杂区26。
本公开实施例中，低掺杂区(包括第一低掺杂区22、第二低掺杂区24和第三低掺杂区26)的长度具体可分别为约1微米至约3微米，例如约1.5微米。而低掺杂区离子注入浓度具体可为约5ions/厘米2至约30ions/厘米2，例如约10ions/厘米2。
本公开实施例所涉及的离子具体可为磷烷(PH3)离子等。
由于本公开实施例中，低掺杂区和非掺杂区间隔设置，且非掺杂区无需进行离子注入即非掺杂区的材质即为硅岛2的材质，因此，当第一低掺杂区22、第二低掺杂区24、第三低掺杂区26制作完成后，第一非掺杂区23和第二非掺杂区25也同步完成。
此步骤后的阵列基板状态示意图具体可如图7所示。
步骤55，在硅岛2之上依次沉积栅绝缘层3薄膜和栅极层5薄膜，通过构图工艺，形成栅绝缘层3的图案和栅电极层4的图案。
其中，栅电极层4的图案在阵列基板上的投影区域，覆盖于有源层中第一低掺杂区22、第一非掺杂区23、第二低掺杂区24、第二非掺杂区25、第三低掺杂区26在阵列基板上的投影区域。
具体的，此步骤可采用常规的构图工艺，通过涂胶、曝光、显影、刻蚀、剥离等工艺形成栅绝缘层3和栅电极层4的图案。
此步骤后的阵列基板状态示意图具体可如图8所示。
步骤56，向硅岛2中第一重掺杂区21和第二重掺杂区27所在位置处进行离子注入，形成有源层中的第一重掺杂区21和第二重掺杂区27。
本公开实施例中，重掺杂区的离子注入浓度具体可为约10ions/厘米2至约15ions/厘米2范围，属于重掺杂范畴。而重掺杂区的长度可与现有技术相同。
此步骤后的阵列基板状态示意图具体可如图9所示。
步骤57，依次形成第二绝缘层6、源漏电极层、钝化层8、像素电极层9图案。
具体的，此步骤中具体可以包括：
在栅绝缘层3以及栅电极层4之上形成第二绝缘层6的图案；
在第二绝缘层6和栅绝缘层3中形成第一过孔61和第二过孔62，第一过孔61位于第一重掺杂区21之上，第二过孔62位于第二重掺杂区27之上；
在第二绝缘层6之上形成源漏电极层，源漏电极层中包括源电极线71和漏电极线72，其中，源电极线71经由第一过孔61与第一重掺杂区21电连接，漏电极线72经由第二过孔62与第二重掺杂区27电连接，此时，阵列基板状态示意图可如图10所示(俯视图)；
在源漏电极层之上形成钝化层8的图案，钝化层8中包括第三过孔81；
在钝化层8之上形成像素电极层9的图案，像素电极层9经由第三过孔81与漏电极线72电连接。
本公开实施例中，可采用常规构图工艺完成步骤57中各图层的制作。
步骤58，形成保护层10和公共电极层11的图案。
此步骤具体可以包括：
在钝化层8和像素电极层9之上形成保护层10的图案；
在保护层10之上形成公共电极层11的图案。
本公开实施例中，可采用常规构图工艺完成步骤58中各图层的制作。
通过上述制作工艺的实现，即可制作本公开实施例所提供的单栅型阵列基板，该阵列基板具体的结构示意图可如图2所示。
当本公开实施例提供的阵列基板为双栅型阵列基板时，如图11所示，该方法具体可以包括：
步骤111，在基板1之上制作第一绝缘层5的图案。
此步骤的实现过程可与上述步骤51相同。
步骤112，在第一绝缘层5上沉积非晶硅薄膜，在非晶硅薄膜晶化后， 通过构图工艺，形成有源层的硅岛2。
此步骤的实现过程可与上述步骤52相同。
此步骤后的阵列基板状态示意图可如图6所示。
步骤113，在硅岛2上涂覆光刻胶，通过构图工艺，刻蚀掉硅岛2中第一重掺杂区21和第二重掺杂区27所在位置处上方的光刻胶。
步骤114，对硅岛2中第一重掺杂区21和第二重掺杂区27所在位置处进行离子注入，形成有源层中的第一重掺杂区21和第二重掺杂区27。
此步骤中，具体可向第一重掺杂区21和第二重掺杂区27所在位置处的硅岛2注入磷烷(PH3)离子，从而形成第一重掺杂区21(N+SI)和第二重掺杂区27(N+SI)。
此步骤后的阵列基板状态示意图具体可如图12所示。
步骤115，在硅岛2之上依次沉积栅绝缘层3薄膜和栅电极层4薄膜，通过构图工艺，形成栅绝缘层3的图案和栅电极层4的图案。
栅电极层4的图案包括第一栅电极41的图案和第二栅电极42的图案，其中，第一栅电极41的图案在阵列基板上的投影区域，可以覆盖第一非掺杂区23在阵列基板上的投影区域；第二栅电极42的图案在阵列基板上的投影区域，可以覆盖第二非掺杂区25在阵列基板上的投影区域。
由于本公开实施例中，三个低掺杂区分别位于两个非掺杂区的两边和中间，因此，利用栅电极图案遮挡非掺杂区的结构设置，有利于后续制作过程中，精确控制低掺杂区的位置和宽度。
具体的，此步骤可采用常规的构图工艺，通过涂胶、曝光、显影、刻蚀、剥离等工艺形成栅绝缘层3和栅电极层4的图案。
此步骤中所涉及的刻蚀工艺具体可采用干法刻蚀工艺进行。在光刻胶材料选择上可以使用高分辨率光刻胶，在掩膜图形选择上。可以使用相位掩膜技术或者机翼图案掩膜(Wing Pattern Mask)技术，也可以上述掩膜技术的综合使用，从而可以精确控制栅极层4的图案的位置和宽度，从而有利于精确控制低掺杂区的位置和宽度。
此步骤后的阵列基板状态示意图具体可如图13所示。
步骤116，向硅岛2中第一低掺杂区22、第二低掺杂区24、第三低掺杂区26所在位置处进行离子注入，形成有源层中的第一低掺杂区22、第二低掺杂区24、第三低掺杂区26。
由于第一栅电极41的图案位于第一非掺杂区23上方且覆盖第一非掺杂 区23，而第二栅电极42的图案位于第二非掺杂区25上方且覆盖第二非掺杂区25，因此，此步骤中可以利用已经制作完成的栅电极层4的图案为基准，从第一栅电极41的图案和第二栅电极42的图案两侧以及中间位置，向硅岛2中注入离子，从而形成有源层中的第一低掺杂区22、第二低掺杂区24、第三低掺杂区26。
此步骤后的阵列基板状态示意图具体可如图14所示。
步骤117，依次形成第二绝缘层6、源漏电极层、钝化层8、像素电极层9的图案。
此步骤可与步骤57相同或类似，不过在第二绝缘层6之上形成源电极线71和漏电极线72之后，阵列基板状态示意图可如图15所示(俯视图)。
步骤118，形成保护层10和公共电极层11的图案。
此步骤具体可以包括：
在钝化层8和像素电极层9之上形成保护层10的图案；
在保护层10之上形成公共电极层11的图案。
本公开实施例中，可采用常规构图工艺完成步骤118中各图层的制作。
通过上述制作工艺的实现，即可制作本公开实施例所提供的双栅型阵列基板，该阵列基板具体的结构示意图可如图3所示。
在本公开一具体实施例中，在步骤52与步骤53之间，或者步骤112和113之间，具体还可以包括阵列基板沟道区(即薄膜晶体管TFT)阈值电压(Vth)掺杂(Vth Doping)处理，即通过向已经形成的有源层硅岛2注入相应类型和数量等级浓度的离子，以实现对阵列基板沟道区阈值电压设置调整的目的。
本公开第三方面的实施例还提供了一种显示装置，该显示制作具体可包括上述本公开实施例所提供的阵列基板。
该显示装置具体可以为液晶面板、液晶电视、液晶显示器、OLED面板、OLED显示器、等离子显示器或电子纸等显示装置。
从以上所述可以看出，本公开提供的阵列基板及其制作方法、显示装置，通过在阵列基板的基板之上，依次设置有源层、栅绝缘层以及栅电极层，所述有源层在水平方向上依次设置有第一重掺杂区、第一低掺杂区、第一非掺杂区、第二低掺杂区、第二非掺杂区、第三低掺杂区、第二重掺杂区。从而可在确保开口率的前提下，有效降低低温多晶硅薄膜晶体管的热量产生以及有效抑制多晶硅薄膜晶体管的漏电流。
以上所述仅是本公开的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种阵列基板，包括：
    依次设置在基板上的有源层、栅绝缘层以及栅电极层，其中所述有源层在水平方向上依次设置有第一重掺杂区、第一低掺杂区、第一非掺杂区、第二低掺杂区、第二非掺杂区、第三低掺杂区、第二重掺杂区。
  2. 如权利要求1所述的阵列基板，其中所述第二低掺杂区设置于所述有源层水平方向上的中间位置。
  3. 如权利要求1或2所述的阵列基板，其中所述栅电极层的图案在所述阵列基板上的投影区域，覆盖于所述第一低掺杂区、所述第一非掺杂区、所述第二低掺杂区、所述第二非掺杂区、所述第三低掺杂区在所述阵列基板上的投影区域。
  4. 如权利要求1-3任一项所述的阵列基板，其中所述栅电极层的图案包括第一栅电极的图案和第二栅电极的图案，其中
    所述第一栅电极的图案在所述阵列基板上的投影区域，覆盖所述第一非掺杂区在所述阵列基板上的投影区域；
    所述第二栅电极的图案在所述阵列基板上的投影区域，覆盖所述第二非掺杂区在所述阵列基板上的投影区域。
  5. 如权利要求1-4任一项所述的阵列基板，还包括：
    设置于所述基板与所述有源层之间的第一绝缘层。
  6. 如权利要求1-5任一项所述的阵列基板，还包括：
    设置于所述栅绝缘层以及所述栅电极层之上的第二绝缘层；
    设置于所述第二绝缘层之上的源漏电极层，所述源漏电极层中包括源电极线和漏电极线，其中所述源电极线经由贯穿所述第二绝缘层和所述栅绝缘层中的第一过孔与所述第一重掺杂区电连接，所述漏电极线经由贯穿所述第二绝缘层和所述栅绝缘层的第二过孔与所述第二重掺杂区电连接；
    设置于所述源漏电极层之上的钝化层；和
    设置于所述钝化层之上的像素电极层，所述像素电极层经由设置于所述钝化层中的第三过孔与所述漏电极线电连接。
  7. 如权利要求6所述的阵列基板，还包括：
    设置于所述钝化层和所述像素电极层之上的保护层；和
    设置于所述保护层之上的公共电极层。
  8. 如权利要求1至7任一项所述的阵列基板，其中所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区的长度分别为约1微米至约3微米；所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区的离子注入浓度为约5ions/厘米2至约30ions/厘米2。
  9. 如权利要求1至8任一项所述的阵列基板，其中所述第一重掺杂区和所述第二重掺杂区的离子注入浓度为约10ions/厘米2至约15ions/厘米2；所述第一重掺杂区和所述第二重掺杂区的长度分别为约2微米至约5微米。
  10. 一种制作阵列基板的方法，包括以下步骤：
    在基板上依次形成有源层、栅绝缘层以及栅电极层的图案，其中所述有源层在水平方向上依次设置有第一重掺杂区、第一低掺杂区、第一非掺杂区、第二低掺杂区、第二非掺杂区、第三低掺杂区、第二重掺杂区。
  11. 如权利要求10所述的方法，其中所述第二低掺杂区形成于所述有源层水平方向上的中间位置。
  12. 如权利要求10或11所述的方法，其中所述在基板之上依次形成有源层、栅绝缘层以及栅电极层的图案的步骤包括：
    在所述基板上沉积非晶硅薄膜，在所述非晶硅薄膜晶化后，通过构图工艺，形成所述有源层的硅岛；
    在所述硅岛上涂覆光刻胶，通过构图工艺，在所述光刻胶中形成多个缺口，所述多个缺口位于所述硅岛中所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区所在位置处的上方；
    经由所述多个缺口，向所述硅岛中所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区所在位置进行离子注入，形成所述有源层中的所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区；
    在所述硅岛之上依次沉积栅绝缘层薄膜和栅极层薄膜，通过构图工艺，形成所述栅绝缘层的图案和所述栅电极层的图案，所述栅电极层的图案在所述阵列基板上的投影区域，覆盖于所述有源层中所述第一低掺杂区、所述第一非掺杂区、所述第二低掺杂区、所述第二非掺杂区、所述第三低掺杂区在所述阵列基板上的投影区域；和
    向所述硅岛中所述第一重掺杂区和所述第二重掺杂区所在位置处进行离子注入，形成所述有源层中的所述第一重掺杂区和所述第二重掺杂区。
  13. 如权利要求10或11所述的方法，其中所述在基板之上依次形成有源层、栅绝缘层以及栅电极层的图案的步骤还包括：
    在所述基板上沉积非晶硅薄膜，在所述非晶硅薄膜晶化后，通过构图工艺，形成所述有源层的硅岛；
    在所述硅岛上涂覆光刻胶，通过构图工艺，刻蚀掉所述硅岛中所述第一重掺杂区和所述第二重掺杂区所在位置处上方的所述光刻胶；
    对所述硅岛中所述第一重掺杂区和所述第二重掺杂区所在位置处进行离子注入，形成所述有源层中的所述第一重掺杂区和所述第二重掺杂区；
    在所述硅岛之上依次沉积栅绝缘层薄膜和栅极层薄膜，通过构图工艺，形成所述栅绝缘层的图案和所述栅电极层的图案，所述栅电极层的图案包括第一栅电极的图案和第二栅电极的图案，所述第一栅电极的图案在所述阵列基板上的投影区域，覆盖所述有源层中所述第一非掺杂区在所述阵列基板上的投影区域，所述第二栅电极的图案在所述阵列基板上的投影区域，覆盖所述有源层中所述第二非掺杂区在所述阵列基板上的投影区域；和
    透过所述栅绝缘层的图案，向所述硅岛中所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区所在位置处进行离子注入，形成所述有源层中的所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区。
  14. 如权利要求12或13所述的方法，其中在所述硅岛上涂覆所述光刻胶之前，所述在基板之上依次形成有源层、栅绝缘层以及栅电极层的图案的步骤还包括：
    对所述硅岛进行离子注入。
  15. 如权利要求10-13任一项所述的方法，其中在所述在基板之上依次形成有源层、栅绝缘层以及栅电极层的图案的步骤之前，所述方法还包括：
    在所述基板之上形成第一绝缘层的图案，所述有源层的图案设置于所述第一绝缘层之上。
  16. 如权利要求10-15任一项所述的方法，还包括：
    在所述栅绝缘层以及所述栅电极层之上形成第二绝缘层的图案；
    在所述第二绝缘层和所述栅绝缘层中形成第一过孔和第二过孔，所述第一过孔位于所述第一重掺杂区之上，所述第二过孔位于所述第二重掺杂区之上；
    在所述第二绝缘层之上形成源漏电极层，所述源漏电极层中包括源电极线和漏电极线，其中所述源电极线经由所述第一过孔与所述第一重掺杂区电连接，所述漏电极线经由所述第二过孔与所述第二重掺杂区电连接；
    在所述源漏电极层之上形成钝化层的图案，所述钝化层的图案中包括第 三过孔；和
    在所述钝化层之上形成像素电极层的图案，所述像素电极层经由所述第三过孔与漏电极线电连接。
  17. 如权利要求10-16所述的方法，还包括：
    在所述钝化层和所述像素电极层之上形成保护层的图案；和
    在所述保护层之上形成公共电极层的图案。
  18. 如权利要求10至17任一项所述的方法，其中所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区的长度分别为约1微米至约3微米；所述第一低掺杂区、所述第二低掺杂区和所述第三低掺杂区的离子注入浓度为约5ions/厘米2至约30ions/厘米2。
  19. 如权利要求10至18任一项所述的方法，其中所述第一重掺杂区和所述第二重掺杂区的离子注入浓度为约10ions/厘米2至约15ions/厘米2；所述第一重掺杂区和所述第二重掺杂区的长度分别为约2微米至约5微米。
  20. 一种显示装置，包括如权利要求1-9任一项所述的阵列基板。
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