[go: up one dir, main page]

DE3483134D1 - Dynamische halbleiterspeicheranordnung mit geteilten speicherzellenbloecken. - Google Patents

Dynamische halbleiterspeicheranordnung mit geteilten speicherzellenbloecken.

Info

Publication number
DE3483134D1
DE3483134D1 DE8484308140T DE3483134T DE3483134D1 DE 3483134 D1 DE3483134 D1 DE 3483134D1 DE 8484308140 T DE8484308140 T DE 8484308140T DE 3483134 T DE3483134 T DE 3483134T DE 3483134 D1 DE3483134 D1 DE 3483134D1
Authority
DE
Germany
Prior art keywords
cell blocks
dynamic semiconductor
memory cell
divided
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484308140T
Other languages
English (en)
Inventor
Yoshihiro Takemae
Kimiaki Sato
Masao Nakano
Tomio Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3483134D1 publication Critical patent/DE3483134D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G06F11/167—Error detection by comparing the memory output
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
DE8484308140T 1983-11-25 1984-11-23 Dynamische halbleiterspeicheranordnung mit geteilten speicherzellenbloecken. Expired - Lifetime DE3483134D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58220553A JPS60115099A (ja) 1983-11-25 1983-11-25 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3483134D1 true DE3483134D1 (de) 1990-10-11

Family

ID=16752792

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484308140T Expired - Lifetime DE3483134D1 (de) 1983-11-25 1984-11-23 Dynamische halbleiterspeicheranordnung mit geteilten speicherzellenbloecken.

Country Status (5)

Country Link
US (1) US4744061A (de)
EP (1) EP0143624B1 (de)
JP (1) JPS60115099A (de)
KR (1) KR900006159B1 (de)
DE (1) DE3483134D1 (de)

Families Citing this family (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868823B1 (en) * 1984-08-31 1999-07-06 Texas Instruments Inc High speed concurrent testing of dynamic read/write memory array
EP0186040B1 (de) * 1984-12-28 1990-03-21 Siemens Aktiengesellschaft Integrierter Halbleiterspeicher
EP0193210A3 (de) * 1985-02-28 1988-12-14 Nec Corporation Halbleiterspeichergerät mit einer eingebauten Prüfschaltung
ATE53261T1 (de) * 1985-03-26 1990-06-15 Siemens Ag Verfahren zum betreiben eines halbleiterspeichers mit integrierter paralleltestmoeglichkeit und auswerteschaltung zur durchfuehrung des verfahrens.
JPS62170094A (ja) * 1986-01-21 1987-07-27 Mitsubishi Electric Corp 半導体記憶回路
US5293598A (en) * 1986-07-30 1994-03-08 Mitsubishi Denki Kabushiki Kaisha Random access memory with a plurality of amplifier groups
JPS6337894A (ja) * 1986-07-30 1988-02-18 Mitsubishi Electric Corp ランダムアクセスメモリ
DE3751002T2 (de) * 1986-10-20 1995-10-05 Nippon Telegraph & Telephone Halbleiterspeicher.
JPH0828115B2 (ja) * 1986-11-10 1996-03-21 日本電気株式会社 半導体メモリ装置
JP2523586B2 (ja) * 1987-02-27 1996-08-14 株式会社日立製作所 半導体記憶装置
JP2609211B2 (ja) * 1987-03-16 1997-05-14 シーメンス・アクチエンゲゼルシヤフト メモリセルの検査回路装置および方法
JPS63244400A (ja) * 1987-03-16 1988-10-11 シーメンス・アクチエンゲゼルシヤフト メモリセルの検査回路装置および方法
US5249159A (en) * 1987-05-27 1993-09-28 Hitachi, Ltd. Semiconductor memory
US5175839A (en) * 1987-12-24 1992-12-29 Fujitsu Limited Storage control system in a computer system for double-writing
US5153509A (en) * 1988-05-17 1992-10-06 Zilog, Inc. System for testing internal nodes in receive and transmit FIFO's
NL8801835A (nl) * 1988-07-20 1990-02-16 Philips Nv Werkwijze en inrichting voor het testen van meervoudige voedingsverbindingen van een geintegreerde schakeling op een printpaneel.
DE58909568D1 (de) * 1988-08-02 1996-02-22 Siemens Ag Verfahren zur Fehlersicherung in Speichersystemen von Datenverarbeitungsanlagen, insbesondere Fernsprechvermittlungsanlagen
JPH02177200A (ja) * 1988-12-28 1990-07-10 Sharp Corp 半導体記憶装置のテスト装置
KR910005306B1 (ko) * 1988-12-31 1991-07-24 삼성전자 주식회사 고밀도 메모리의 테스트를 위한 병렬리드회로
EP0455653B1 (de) * 1989-01-26 1993-05-05 Siemens Aktiengesellschaft Integrierter halbleiterspeicher
DE3920871A1 (de) * 1989-06-26 1991-01-03 Siemens Ag Integrierter halbleiterspeicher
US5128944A (en) * 1989-05-26 1992-07-07 Texas Instruments Incorporated Apparatus and method for providing notification of bit-cell failure in a redundant-bit-cell memory
KR920001082B1 (ko) * 1989-06-13 1992-02-01 삼성전자 주식회사 반도체 메모리장치에 있어서 메모리 테스트용 멀티바이트 광역 병렬 라이트회로
JPH0357015A (ja) * 1989-07-25 1991-03-12 Nec Corp 電子ディスクサブシステム
JP2717712B2 (ja) * 1989-08-18 1998-02-25 三菱電機株式会社 半導体記憶装置
EP0418521A3 (en) * 1989-09-20 1992-07-15 International Business Machines Corporation Testable latch self checker
KR920007909B1 (ko) * 1989-11-18 1992-09-19 삼성전자 주식회사 램 테스트시 고속 기록방법
KR930008417B1 (ko) * 1990-06-18 1993-08-31 삼성전자 주식회사 반도체 메모리 장치의 다중 비트 병렬 테스트방법
JPH04212799A (ja) * 1990-01-31 1992-08-04 Nec Ic Microcomput Syst Ltd テスト回路内蔵半導体メモリ
US5675544A (en) * 1990-06-25 1997-10-07 Texas Instruments Incorporated Method and apparatus for parallel testing of memory circuits
US5200963A (en) * 1990-06-26 1993-04-06 The United States Of America As Represented By The Administrator, National Aeronautics And Space Administration Self-checking on-line testable static ram
US5265100A (en) * 1990-07-13 1993-11-23 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with improved test mode
JPH04192624A (ja) * 1990-11-22 1992-07-10 Matsushita Electric Ind Co Ltd アナログ信号処理装置を駆動する駆動回路に用いる計数回路
JP2957284B2 (ja) * 1990-12-22 1999-10-04 富士通株式会社 半導体回路
WO1992013281A1 (en) * 1991-01-22 1992-08-06 Vlsi Technology, Inc. Method to reduce test vectors/test time in devices using equivalent blocks
US5555249A (en) * 1991-09-18 1996-09-10 Ncr Corporation Non-destructive memory testing in computers
US5850509A (en) * 1991-11-13 1998-12-15 Intel Corporation Circuitry for propagating test mode signals associated with a memory array
KR950001293B1 (ko) * 1992-04-22 1995-02-15 삼성전자주식회사 반도체 메모리칩의 병렬테스트 회로
JPH0684396A (ja) * 1992-04-27 1994-03-25 Nec Corp 半導体記憶装置
JP3251637B2 (ja) * 1992-05-06 2002-01-28 株式会社東芝 半導体記憶装置
JPH06242181A (ja) * 1992-11-23 1994-09-02 Texas Instr Inc <Ti> 集積回路の試験装置及び方法
JP3293935B2 (ja) * 1993-03-12 2002-06-17 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
JPH06275693A (ja) * 1993-03-20 1994-09-30 Hitachi Ltd ダイナミック型ｒａｍ
DE69426845T2 (de) * 1993-06-30 2001-09-13 Stmicroelectronics, Inc. Verfahren und Einrichtung zur Parallelprüfung von Speichern
KR0141432B1 (ko) * 1993-10-01 1998-07-15 기다오까 다까시 반도체 기억장치
US5533196A (en) * 1994-01-31 1996-07-02 Intel Corporation Method and apparatus for testing for a sufficient write voltage level during power up of a SRAM array
US5630063A (en) * 1994-04-28 1997-05-13 Rockwell International Corporation Data distribution system for multi-processor memories using simultaneous data transfer without processor intervention
US5648730A (en) * 1994-11-30 1997-07-15 Texas Instruments Incorporated Large integrated circuit with modular probe structures
US5533194A (en) * 1994-12-28 1996-07-02 International Business Machines Corporation Hardware-assisted high speed memory test apparatus and method
US5671392A (en) * 1995-04-11 1997-09-23 United Memories, Inc. Memory device circuit and method for concurrently addressing columns of multiple banks of multi-bank memory array
KR0158112B1 (ko) * 1995-04-25 1999-02-01 김광호 다수개의 뱅크들을 가지는 반도체 메모리 장치
KR100206701B1 (ko) * 1996-05-16 1999-07-01 윤종용 반도체 메모리 장치의 멀티비트 테스트 회로 및 그 테스트 방법
US5920573A (en) * 1996-07-22 1999-07-06 Texas Istruments Incorporated Method and apparatus for reducing area and pin count required in design for test of wide data path memories
US5883844A (en) * 1997-05-23 1999-03-16 Stmicroelectronics, Inc. Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof
WO1998054727A2 (en) * 1997-05-30 1998-12-03 Micron Technology, Inc. 256 Meg DYNAMIC RANDOM ACCESS MEMORY
US6009026A (en) * 1997-07-28 1999-12-28 International Business Machines Corporation Compressed input/output test mode
DE19741426C1 (de) * 1997-09-19 1999-01-21 Siemens Ag Schaltungsanordnung zur Datenspeicherung
US5959911A (en) * 1997-09-29 1999-09-28 Siemens Aktiengesellschaft Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices
USRE40172E1 (en) * 1998-05-25 2008-03-25 Hynix Semiconductor, Inc. Multi-bank testing apparatus for a synchronous dram
US6141286A (en) * 1998-08-21 2000-10-31 Micron Technology, Inc. Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines
JP2001167005A (ja) 1999-12-08 2001-06-22 Nec Corp メモリ診断方法とメモリ診断回路および半導体記憶装置
US6724665B2 (en) * 2001-08-31 2004-04-20 Matrix Semiconductor, Inc. Memory device and method for selectable sub-array activation
US6735546B2 (en) 2001-08-31 2004-05-11 Matrix Semiconductor, Inc. Memory device and method for temperature-based control over write and/or read operations
DE10234648A1 (de) * 2002-07-29 2004-02-12 Infineon Technologies Ag Halbleiterwafer mit elektrisch verbundenen Kontakt- und Prüfflächen
KR100451466B1 (ko) * 2002-10-31 2004-10-08 주식회사 하이닉스반도체 테스트 성능이 개선된 반도체 메모리 장치
US6954394B2 (en) * 2002-11-27 2005-10-11 Matrix Semiconductor, Inc. Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions
US7057958B2 (en) * 2003-09-30 2006-06-06 Sandisk Corporation Method and system for temperature compensation for memory cells with temperature-dependent behavior
JP2006120250A (ja) 2004-10-21 2006-05-11 Fujitsu Ltd 半導体装置およびその試験方法
US7218570B2 (en) * 2004-12-17 2007-05-15 Sandisk 3D Llc Apparatus and method for memory operations using address-dependent conditions
US7283414B1 (en) 2006-05-24 2007-10-16 Sandisk 3D Llc Method for improving the precision of a temperature-sensor circuit
US7630259B1 (en) * 2007-12-18 2009-12-08 Lattice Semiconductor Corporation Programmable logic device with built in self test

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit
JPS53120234A (en) * 1977-03-30 1978-10-20 Toshiba Corp Semiconductor memory
JPS5651093A (en) * 1979-09-28 1981-05-08 Nec Corp Semiconductor storage device
JPS573298A (en) * 1980-06-06 1982-01-08 Nec Corp Memory integrated circuit
JPS57105897A (en) * 1980-12-23 1982-07-01 Fujitsu Ltd Semiconductor storage device
JPS57176587A (en) * 1981-04-24 1982-10-29 Hitachi Ltd Semiconductor ram device
US4541090A (en) * 1981-06-09 1985-09-10 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device
JPS5813718A (ja) * 1981-07-16 1983-01-26 Teijin Ltd ポリエステル繊維
JPS5891600A (ja) * 1982-11-19 1983-05-31 Hitachi Ltd メモリ回路

Also Published As

Publication number Publication date
US4744061A (en) 1988-05-10
EP0143624A3 (en) 1987-10-14
JPH0463480B2 (de) 1992-10-09
KR850003615A (ko) 1985-06-20
EP0143624B1 (de) 1990-09-05
JPS60115099A (ja) 1985-06-21
EP0143624A2 (de) 1985-06-05
KR900006159B1 (en) 1990-08-24

Similar Documents

Publication Publication Date Title
DE3483134D1 (de) Dynamische halbleiterspeicheranordnung mit geteilten speicherzellenbloecken.
DE3585711D1 (de) Halbleiterspeicheranordnung.
DE3381545D1 (de) Halbleiterspeicheranordnung.
DE3485174D1 (de) Halbleiterspeicheranordnung.
DE3382212D1 (de) Halbleiterspeicher.
DE3485555D1 (de) Halbleiterspeicher mit mehrfachniveauspeicherstruktur.
DE3485625D1 (de) Halbleiterspeicheranordnung.
DE3581282D1 (de) Inhaltsadressierte halbleiterspeichermatrizen.
DE3583091D1 (de) Halbleiterspeicheranordnung.
DE3577944D1 (de) Halbleiterspeicheranordnung.
DE3582415D1 (de) Halbleiterspeicher mit in bloecken unterteilten bitleitungen.
DE3671124D1 (de) Halbleiterspeicherzelle.
DE3484180D1 (de) Halbleiterspeicheranordnung.
DE3582376D1 (de) Halbleiterspeicheranordnung.
DE3586377D1 (de) Halbleiterspeicheranordnung.
DE3481355D1 (de) Halbleiterspeicheranordnung.
DE3576236D1 (de) Halbleiterspeicheranordnung.
DE3577367D1 (de) Halbleiterspeicheranordnung.
DE3575225D1 (de) Halbleiterspeicheranordnung.
DE3586556D1 (de) Halbleiterspeicheranordnung.
DE3580993D1 (de) Halbleiterspeicheranordnung.
DE3576754D1 (de) Halbleiterspeicheranordnung.
DE3486094D1 (de) Halbleiterspeicheranordnung.
DE3484630D1 (de) Halbleiterspeicheranordnung.
DE3586675D1 (de) Halbleiterspeicheranordnung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition