DE3582415D1 - Halbleiterspeicher mit in bloecken unterteilten bitleitungen. - Google Patents
Halbleiterspeicher mit in bloecken unterteilten bitleitungen.Info
- Publication number
- DE3582415D1 DE3582415D1 DE8585402247T DE3582415T DE3582415D1 DE 3582415 D1 DE3582415 D1 DE 3582415D1 DE 8585402247 T DE8585402247 T DE 8585402247T DE 3582415 T DE3582415 T DE 3582415T DE 3582415 D1 DE3582415 D1 DE 3582415D1
- Authority
- DE
- Germany
- Prior art keywords
- blocks
- semiconductor memory
- bit lines
- lines divided
- divided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24580384A JPH0652635B2 (ja) | 1984-11-20 | 1984-11-20 | 半導体記憶装置 |
JP59245801A JPS61123093A (ja) | 1984-11-20 | 1984-11-20 | 半導体記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3582415D1 true DE3582415D1 (de) | 1991-05-08 |
Family
ID=26537410
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585402247T Expired - Lifetime DE3582415D1 (de) | 1984-11-20 | 1985-11-20 | Halbleiterspeicher mit in bloecken unterteilten bitleitungen. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4730280A (de) |
EP (1) | EP0185572B1 (de) |
KR (1) | KR900005667B1 (de) |
DE (1) | DE3582415D1 (de) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4731747A (en) * | 1986-04-14 | 1988-03-15 | American Telephone And Telegraph Company, At&T Bell Laboratories | Highly parallel computation network with normalized speed of response |
US5132930A (en) * | 1986-07-31 | 1992-07-21 | Mitsubishi Denki Kabushiki Kaisha | CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines |
EP0523756A3 (en) * | 1986-08-15 | 1993-06-09 | Nec Corporation | Static random access memory having bi-cmos construction |
JPH07118193B2 (ja) * | 1986-09-18 | 1995-12-18 | 富士通株式会社 | 半導体記憶装置 |
EP0271718B1 (de) * | 1986-11-18 | 1992-03-04 | Siemens Aktiengesellschaft | Digitalverstärkeranordnung in integrierten Schaltungen |
KR890002812B1 (ko) * | 1986-11-28 | 1989-07-31 | 삼성전자 주식회사 | 씨모오스 디램에서 레이아웃이 최적화된 감지증폭기 |
JPS63149900A (ja) * | 1986-12-15 | 1988-06-22 | Toshiba Corp | 半導体メモリ |
JPH0799627B2 (ja) * | 1987-01-23 | 1995-10-25 | 松下電器産業株式会社 | 半導体メモリの書き込み読み出し回路 |
JPH07107797B2 (ja) * | 1987-02-10 | 1995-11-15 | 三菱電機株式会社 | ダイナミツクランダムアクセスメモリ |
US4980863A (en) * | 1987-03-31 | 1990-12-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device having switching circuit for coupling together two pairs of bit lines |
US4807195A (en) * | 1987-05-18 | 1989-02-21 | International Business Machines Corporation | Apparatus and method for providing a dual sense amplifier with divided bit line isolation |
JP2828630B2 (ja) * | 1987-08-06 | 1998-11-25 | 三菱電機株式会社 | 半導体装置 |
JPH07105137B2 (ja) * | 1987-11-17 | 1995-11-13 | 日本電気株式会社 | 半導体メモリ |
KR890010917A (ko) * | 1987-12-28 | 1989-08-11 | 다니이 아끼오 | 낮은 첨두전류로 작동하는 반도체 메모리 |
JPH0235765A (ja) * | 1988-07-26 | 1990-02-06 | Nec Corp | 半導体集積回路装置 |
DE3937068C2 (de) * | 1988-11-07 | 1994-10-06 | Toshiba Kawasaki Kk | Dynamische Halbleiterspeicheranordnung |
JPH07105140B2 (ja) * | 1988-12-16 | 1995-11-13 | 日本電気株式会社 | 半導体メモリ |
US5293563A (en) * | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
JPH03176891A (ja) * | 1989-12-04 | 1991-07-31 | Nec Corp | 半導体記憶装置 |
US4972374A (en) * | 1989-12-27 | 1990-11-20 | Motorola, Inc. | Output amplifying stage with power saving feature |
US5226014A (en) * | 1990-12-24 | 1993-07-06 | Ncr Corporation | Low power pseudo-static ROM |
JP3533227B2 (ja) * | 1992-09-10 | 2004-05-31 | 株式会社日立製作所 | 半導体記憶装置 |
US5515315A (en) * | 1993-12-24 | 1996-05-07 | Sony Corporation | Dynamic random access memory |
US5666320A (en) * | 1995-12-20 | 1997-09-09 | International Business Machines Corporation | Storage system |
US6552932B1 (en) * | 2001-09-21 | 2003-04-22 | Sandisk Corporation | Segmented metal bitlines |
KR100564607B1 (ko) * | 2004-01-29 | 2006-03-28 | 삼성전자주식회사 | 태퍼드 lio 센스 앰프를 사용하는 반도체 메모리 장치 |
TWI493568B (zh) * | 2013-08-19 | 2015-07-21 | Ind Tech Res Inst | 記憶體裝置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2647394C2 (de) * | 1976-10-20 | 1978-11-16 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | MOS-Halbleiterspeicherbaustein |
US4286178A (en) * | 1978-06-12 | 1981-08-25 | Texas Instruments Incorporated | Sense amplifier with dual parallel driver transistors in MOS random access memory |
JPS573290A (en) * | 1980-01-31 | 1982-01-08 | Nec Corp | Semiconductor storing circuit |
US4287576A (en) * | 1980-03-26 | 1981-09-01 | International Business Machines Corporation | Sense amplifying system for memories with small cells |
JPS57198592A (en) * | 1981-05-29 | 1982-12-06 | Hitachi Ltd | Semiconductor memory device |
EP0101884A3 (de) * | 1982-07-21 | 1987-09-02 | Hitachi, Ltd. | Monolithischer Halbleiterspeicher |
JPH0670878B2 (ja) * | 1982-11-30 | 1994-09-07 | 富士通株式会社 | 半導体記憶装置 |
US4542483A (en) * | 1983-12-02 | 1985-09-17 | At&T Bell Laboratories | Dual stage sense amplifier for dynamic random access memory |
-
1985
- 1985-11-18 KR KR1019850008611A patent/KR900005667B1/ko not_active IP Right Cessation
- 1985-11-18 US US06/798,783 patent/US4730280A/en not_active Expired - Lifetime
- 1985-11-20 DE DE8585402247T patent/DE3582415D1/de not_active Expired - Lifetime
- 1985-11-20 EP EP85402247A patent/EP0185572B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0185572B1 (de) | 1991-04-03 |
EP0185572A3 (en) | 1988-04-20 |
KR860004409A (ko) | 1986-06-20 |
US4730280A (en) | 1988-03-08 |
KR900005667B1 (ko) | 1990-08-03 |
EP0185572A2 (de) | 1986-06-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |