DE3577944D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number: DE3577944D1
Authority: DE; Germany
Prior art keywords: semiconductor memory; memory arrangement; arrangement; semiconductor; memory
Prior art date: 1984-02-21
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE8585101887T

Other languages

English (en)

Inventor

Hiroshi C Patent Divi Iwahashi

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Toshiba Corp

Original Assignee

Toshiba Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1984-02-21

Filing date

1985-02-21

Publication date

1990-06-28

1985-02-21 Application filed by Toshiba Corp filed Critical Toshiba Corp

1990-06-28 Application granted granted Critical

1990-06-28 Publication of DE3577944D1 publication Critical patent/DE3577944D1/de

2005-02-22 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

DE8585101887T 1984-02-21 1985-02-21 Halbleiterspeicheranordnung. Expired - Lifetime DE3577944D1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP59030692A JPS60175293A (ja)	1984-02-21	1984-02-21	半導体メモリ

Publications (1)

Publication Number	Publication Date
DE3577944D1 true DE3577944D1 (de)	1990-06-28

Family

ID=12310728

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8585101887T Expired - Lifetime DE3577944D1 (de)	1984-02-21	1985-02-21	Halbleiterspeicheranordnung.

Country Status (4)

Country	Link
US (1)	US4715017A (de)
EP (1)	EP0152954B1 (de)
JP (1)	JPS60175293A (de)
DE (1)	DE3577944D1 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4905189B1 (en) *	1985-12-18	1993-06-01		System for reading and writing information
DE3778920D1 (de) *	1986-01-20	1992-06-17	Nec Corp	Mikrorechner mit betriebsarten fuer hohe und fuer geringe taktrate.
JPS639096A (ja) *	1986-06-30	1988-01-14	Toshiba Corp	半導体メモリ
JPH0831275B2 (ja) *	1986-09-09	1996-03-27	日本電気株式会社	メモリ回路
JPS63200391A (ja) *	1987-02-16	1988-08-18	Toshiba Corp	スタテイツク型半導体メモリ
JPH0766675B2 (ja) *	1987-07-14	1995-07-19	株式会社東芝	プログラマブルｒｏｍ
US4807189A (en) *	1987-08-05	1989-02-21	Texas Instruments Incorporated	Read/write memory having a multiple column select mode
JPH088304B2 (ja) *	1987-08-19	1996-01-29	富士通株式会社	半導体集積回路装置及びその設計方法
DE3928902C2 (de) *	1988-08-31	1996-01-25	Mitsubishi Electric Corp	Halbleiterspeicher und Verfahren zum Betreiben desselben und Verwendung desselben in einem Video-RAM
US4939692A (en) *	1988-09-15	1990-07-03	Intel Corporation	Read-only memory for microprocessor systems having shared address/data lines
JPH02172097A (ja) *	1988-12-23	1990-07-03	Nec Corp	メモリ
US5257235A (en) *	1989-04-25	1993-10-26	Kabushiki Kaisha Toshiba	Semiconductor memory device having serial access mode
US5546592A (en) *	1989-06-26	1996-08-13	Ncr Corporation	System and method for incrementing memory addresses in a computer system
GB2244157A (en) *	1990-05-15	1991-11-20	Sun Microsystems Inc	Apparatus for row caching in random access memory
US5285421A (en) *	1990-07-25	1994-02-08	Advanced Micro Devices	Scheme for eliminating page boundary limitation on initial access of a serial contiguous access memory
US5799186A (en) *	1990-12-20	1998-08-25	Eastman Kodak Company	Method and apparatus for programming a peripheral processor with a serial output memory device
JP2977296B2 (ja) *	1991-02-19	1999-11-15	沖電気工業株式会社	半導体メモリ装置
US5430859A (en) *	1991-07-26	1995-07-04	Sundisk Corporation	Solid state memory system including plural memory chips and a serialized bus
US5325338A (en) *	1991-09-04	1994-06-28	Advanced Micro Devices, Inc.	Dual port memory, such as used in color lookup tables for video systems
JP2696026B2 (ja) *	1991-11-21	1998-01-14	株式会社東芝	半導体記憶装置
JPH05217365A (ja) *	1992-02-03	1993-08-27	Mitsubishi Electric Corp	半導体記憶装置
US5319597A (en) *	1992-06-02	1994-06-07	Texas Instruments Incorporated	FIFO memory and line buffer
FR2696023A1 (fr) *	1992-09-18	1994-03-25	Devaux Fabrice	Mémoire à accès rapide.
US6091639A (en)	1993-08-27	2000-07-18	Kabushiki Kaisha Toshiba	Non-volatile semiconductor memory device and data programming method
US5592435A (en) *	1994-06-03	1997-01-07	Intel Corporation	Pipelined read architecture for memory
US5890192A (en)	1996-11-05	1999-03-30	Sandisk Corporation	Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM
DE60035630T2 (de) *	1999-02-11	2008-02-07	International Business Machines Corporation	Hierarchische Vorausladung in Halbleiterspeicheranordnungen
KR100824779B1 (ko) *	2007-01-11	2008-04-24	삼성전자주식회사	반도체 메모리 장치의 데이터 출력 경로 및 데이터 출력방법
JP2008204623A (ja) *	2008-04-07	2008-09-04	Renesas Technology Corp	不揮発性メモリ装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS5394140A (en) *	1977-01-28	1978-08-17	Hitachi Ltd	Memory integrated circuit
US4106109A (en) *	1977-02-01	1978-08-08	Ncr Corporation	Random access memory system providing high-speed digital data output
JPS6036592B2 (ja) *	1979-06-13	1985-08-21	株式会社日立製作所	文字図形表示装置
GB2084361B (en) *	1980-09-19	1984-11-21	Sony Corp	Random access memory arrangements

1984
- 1984-02-21 JP JP59030692A patent/JPS60175293A/ja active Pending
1985
- 1985-02-20 US US06/703,435 patent/US4715017A/en not_active Expired - Lifetime
- 1985-02-21 DE DE8585101887T patent/DE3577944D1/de not_active Expired - Lifetime
- 1985-02-21 EP EP85101887A patent/EP0152954B1/de not_active Expired

Also Published As

Publication number	Publication date
EP0152954A2 (de)	1985-08-28
EP0152954B1 (de)	1990-05-23
US4715017A (en)	1987-12-22
JPS60175293A (ja)	1985-09-09
EP0152954A3 (en)	1986-10-08

Publication	Publication Date	Title
DE3585711D1 (de)	1992-04-30	Halbleiterspeicheranordnung.
DE3583091D1 (de)	1991-07-11	Halbleiterspeicheranordnung.
DE3577944D1 (de)	1990-06-28	Halbleiterspeicheranordnung.
DE3481957D1 (de)	1990-05-17	Halbleiteranordnung.
DE3686994D1 (de)	1992-11-26	Halbleiterspeicher.
DE3687322D1 (de)	1993-02-04	Halbleiterspeicheranordnung.
DE3485174D1 (de)	1991-11-21	Halbleiterspeicheranordnung.
DE3582376D1 (de)	1991-05-08	Halbleiterspeicheranordnung.
DE3485625D1 (de)	1992-05-07	Halbleiterspeicheranordnung.
DE3586377D1 (de)	1992-08-27	Halbleiterspeicheranordnung.
DE3576236D1 (de)	1990-04-05	Halbleiterspeicheranordnung.
DE3484180D1 (de)	1991-04-04	Halbleiterspeicheranordnung.
DE3582653D1 (de)	1991-05-29	Halbleiteranordnung.
DE3577367D1 (de)	1990-05-31	Halbleiterspeicheranordnung.
DE3481355D1 (de)	1990-03-15	Halbleiterspeicheranordnung.
DE3680562D1 (de)	1991-09-05	Halbleiterspeicheranordnung.
DE3675445D1 (de)	1990-12-13	Halbleiterspeicheranordnung.
DE3575225D1 (de)	1990-02-08	Halbleiterspeicheranordnung.
DE3580993D1 (de)	1991-02-07	Halbleiterspeicheranordnung.
DE3586556D1 (de)	1992-10-01	Halbleiterspeicheranordnung.
DE3576754D1 (de)	1990-04-26	Halbleiterspeicheranordnung.
DE3578254D1 (de)	1990-07-19	Halbleiterspeicheranordnung.
DE3586675D1 (de)	1992-10-29	Halbleiterspeicheranordnung.
DE3582960D1 (de)	1991-07-04	Halbleiterspeicheranordnung.
DE3486094D1 (de)	1993-04-15	Halbleiterspeicheranordnung.

Legal Events

Date	Code	Title	Description
1991-06-20	8364	No opposition during term of opposition
1999-03-11	8339	Ceased/non-payment of the annual fee