KR930008417B1 - 반도체 메모리 장치의 다중 비트 병렬 테스트방법 - Google Patents
반도체 메모리 장치의 다중 비트 병렬 테스트방법 Download PDFInfo
- Publication number
- KR930008417B1 KR930008417B1 KR1019900008924A KR900008924A KR930008417B1 KR 930008417 B1 KR930008417 B1 KR 930008417B1 KR 1019900008924 A KR1019900008924 A KR 1019900008924A KR 900008924 A KR900008924 A KR 900008924A KR 930008417 B1 KR930008417 B1 KR 930008417B1
- Authority
- KR
- South Korea
- Prior art keywords
- data
- pairs
- pair
- comparator
- input
- Prior art date
Links
- 238000010998 test method Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000012360 testing method Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 8
- 238000012546 transfer Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 235000014121 butter Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
Claims (4)
- 데이타출력버퍼와 소정갯수의 데이타버스쌍 및 메모리셀군을 구비하는 반도체메모리장치의 다중비트병렬테으스트방법에 있어서, 상기 메로리셀군으로부터 공급되는 데이터쌍을 감지하는 데이터감지부와, 상기 데이터감지부와 상기 소정갯수의 데이터버스쌍들의 사이에 연결된 구동부와, 상기 데이터감지부와 하나의 데이터버스쌍사이에 연결되어 상기 데이터 감지부로부터 출력되는 데이터쌍들의 일군을 입력하여 상기 하나의 데이터버스쌍으로 단일의 데이터쌍을 출력하는 하나의 제 1 비교기와, 상기 데이타감지부와 다른하나의 데이터쌍 사이에 연결되어 데이터감지부로부터 출력되는 데이터쌍들의 타군을 입력하는 상기 다른하나의 데이터쌍으로 단일의 데이터쌍을 출력하는 다른하나의 제 1 비교기와, 상기 데이터버스쌍들에 입력이 연결되고 상기 데이타출력버퍼에 출력이 연결되어 상기 데이타버스쌍들에 있는 소정갯수의 데이터쌍을 입력하여 단일의 데이터쌍을 출력하는 제 2 비교기와, 상기 데이터버스쌍들에 입력이 연결되어 상기 데이터출력버퍼에 출력이 연결되어 상기 데이터버스쌍들에 있는 소정갯수의 데이터쌍을 입력하여 단일의 데이터쌍을 출력하는 데이터선택회로를 구비하여, 상기 데이터감지부가 상기 메모리셀군으로부터 공급되는 복수개의 데이터쌍을 노멀모드에서는 상기 구동부를 통하여 상기 데이터버스쌍들로 보내고 테스트모드에서는 상기 제 1 비교기로 보냄을 특징으로 하는 반도체메모리장치의 다중비트병렬테스트방법.
- 제 1 항에 있어서, 상기 제 1 및 제 2 비교기가 노멀모드에서는 동작하지 않음을 특징으로 하는 반도체메모리장치의 다중비트병렬테스트방법.
- 제 1 항 또는 제 2 항에 있어서, 상기 제 1 비교기가 입력단을 소정레벨로 프리차아지하는 회로를 구비하여, 노멀모드에서 상기 피리차아지회로에 의해 입력이 프리차아지됨을 특징으로 하는 반도체메모리장치의 다중비트병렬테스트방법.
- 제 1 항 또는 제 2 항에 있어서, 상기 제 2 비교기가 출력단에 스위칭회로를 구비하여, 상기 스위칭회로가 노멀모드에서 턴오프됨을 특징으로 하는 반도체 메모리 장치의 다중비트병렬 테스트방법.
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900008924A KR930008417B1 (ko) | 1990-06-18 | 1990-06-18 | 반도체 메모리 장치의 다중 비트 병렬 테스트방법 |
FR9009152A FR2663450B1 (fr) | 1990-06-18 | 1990-07-18 | Procede de test en parallele de bits multiples dans un dispositif memoire a semiconducteur. |
DE4023015A DE4023015C1 (ko) | 1990-06-18 | 1990-07-19 | |
US07/559,697 US5077689A (en) | 1990-01-18 | 1990-07-30 | Method for multi-bit parallel test in semiconductor memory device |
CN90106619A CN1025077C (zh) | 1990-06-18 | 1990-07-31 | 半导体存储器件及其多位并行测试方法 |
GB9016763A GB2245393B (en) | 1990-06-18 | 1990-07-31 | Multi-bit parallel testing |
IT48190A IT1241525B (it) | 1990-06-18 | 1990-07-31 | "metodo per collaudo in parallelo su piu' bit in un dispositivo di memoria a semiconduttori". |
JP02201562A JP3025519B2 (ja) | 1990-06-18 | 1990-07-31 | 半導体記憶素子におけるマルチビツトパラレルテストの方法及びその半導体記憶素子 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900008924A KR930008417B1 (ko) | 1990-06-18 | 1990-06-18 | 반도체 메모리 장치의 다중 비트 병렬 테스트방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920001552A KR920001552A (ko) | 1992-01-30 |
KR930008417B1 true KR930008417B1 (ko) | 1993-08-31 |
Family
ID=19300202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900008924A KR930008417B1 (ko) | 1990-01-18 | 1990-06-18 | 반도체 메모리 장치의 다중 비트 병렬 테스트방법 |
Country Status (8)
Country | Link |
---|---|
US (1) | US5077689A (ko) |
JP (1) | JP3025519B2 (ko) |
KR (1) | KR930008417B1 (ko) |
CN (1) | CN1025077C (ko) |
DE (1) | DE4023015C1 (ko) |
FR (1) | FR2663450B1 (ko) |
GB (1) | GB2245393B (ko) |
IT (1) | IT1241525B (ko) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5675544A (en) * | 1990-06-25 | 1997-10-07 | Texas Instruments Incorporated | Method and apparatus for parallel testing of memory circuits |
KR950001293B1 (ko) * | 1992-04-22 | 1995-02-15 | 삼성전자주식회사 | 반도체 메모리칩의 병렬테스트 회로 |
JPH06295599A (ja) * | 1993-04-09 | 1994-10-21 | Nec Corp | 半導体記憶装置 |
KR960008824B1 (en) * | 1993-11-17 | 1996-07-05 | Samsung Electronics Co Ltd | Multi bit test circuit and method of semiconductor memory device |
KR0137846B1 (ko) * | 1994-03-24 | 1998-06-15 | 문정환 | 반도체 기억장치의 멀티비트 테스트회로 |
KR0172533B1 (ko) * | 1995-10-18 | 1999-03-30 | 김주용 | 플래쉬 메모리 장치 |
US5592425A (en) * | 1995-12-20 | 1997-01-07 | Intel Corporation | Method and apparatus for testing a memory where data is passed through the memory for comparison with data read from the memory |
US5905744A (en) * | 1997-09-30 | 1999-05-18 | Lsi Logic Corporation | Test mode for multifunction PCI device |
JP3322303B2 (ja) * | 1998-10-28 | 2002-09-09 | 日本電気株式会社 | 半導体記憶装置 |
KR100339502B1 (ko) | 1999-06-02 | 2002-05-31 | 윤종용 | 다수개의 데이터 라인을 구분되게 테스트하는 통합 데이터 라인 테스트 회로 및 이를 이용하는 테스트 방법 |
KR100295691B1 (ko) * | 1999-06-04 | 2001-07-12 | 김영환 | 디램의 오픈 테스트용 테스트모드회로 |
JP3484388B2 (ja) * | 2000-02-08 | 2004-01-06 | 日本電気株式会社 | 半導体記憶装置 |
KR100346447B1 (ko) * | 2000-06-30 | 2002-07-27 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 병렬 테스트 장치 |
KR100546308B1 (ko) * | 2002-12-13 | 2006-01-26 | 삼성전자주식회사 | 데이터 독출 능력이 향상된 반도체 메모리 장치. |
KR100699827B1 (ko) * | 2004-03-23 | 2007-03-27 | 삼성전자주식회사 | 메모리 모듈 |
US7480195B2 (en) * | 2005-05-11 | 2009-01-20 | Micron Technology, Inc. | Internal data comparison for memory testing |
KR100809070B1 (ko) * | 2006-06-08 | 2008-03-03 | 삼성전자주식회사 | 반도체 메모리 장치의 병렬 비트 테스트 회로 및 그 방법 |
RU2498854C2 (ru) | 2008-07-02 | 2013-11-20 | Бюлер Аг | Способ получения муки из зерна, вальцовая мельница, применение вальцовой мельницы, зигзагообразная просеивающая машина, применение зигзагообразной просеивающей машины |
CN101770967A (zh) * | 2009-01-03 | 2010-07-07 | 上海芯豪微电子有限公司 | 一种共用基底集成电路测试方法、装置和系统 |
KR20150033374A (ko) * | 2013-09-24 | 2015-04-01 | 에스케이하이닉스 주식회사 | 반도체 시스템 및 반도체 장치 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60115099A (ja) * | 1983-11-25 | 1985-06-21 | Fujitsu Ltd | 半導体記憶装置 |
US4686456A (en) * | 1985-06-18 | 1987-08-11 | Kabushiki Kaisha Toshiba | Memory test circuit |
JP2523586B2 (ja) * | 1987-02-27 | 1996-08-14 | 株式会社日立製作所 | 半導体記憶装置 |
JPH01286200A (ja) * | 1988-05-12 | 1989-11-17 | Fujitsu Ltd | 半導体メモリ装置 |
JPH0713858B2 (ja) * | 1988-08-30 | 1995-02-15 | 三菱電機株式会社 | 半導体記憶装置 |
KR910005306B1 (ko) * | 1988-12-31 | 1991-07-24 | 삼성전자 주식회사 | 고밀도 메모리의 테스트를 위한 병렬리드회로 |
-
1990
- 1990-06-18 KR KR1019900008924A patent/KR930008417B1/ko not_active IP Right Cessation
- 1990-07-18 FR FR9009152A patent/FR2663450B1/fr not_active Expired - Fee Related
- 1990-07-19 DE DE4023015A patent/DE4023015C1/de not_active Expired - Lifetime
- 1990-07-30 US US07/559,697 patent/US5077689A/en not_active Expired - Lifetime
- 1990-07-31 IT IT48190A patent/IT1241525B/it active IP Right Grant
- 1990-07-31 JP JP02201562A patent/JP3025519B2/ja not_active Expired - Lifetime
- 1990-07-31 CN CN90106619A patent/CN1025077C/zh not_active Expired - Fee Related
- 1990-07-31 GB GB9016763A patent/GB2245393B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR920001552A (ko) | 1992-01-30 |
GB2245393A (en) | 1992-01-02 |
GB2245393B (en) | 1994-02-23 |
IT1241525B (it) | 1994-01-17 |
CN1025077C (zh) | 1994-06-15 |
IT9048190A1 (it) | 1992-01-31 |
FR2663450B1 (fr) | 1993-10-15 |
GB9016763D0 (en) | 1990-09-12 |
US5077689A (en) | 1991-12-31 |
JPH0448500A (ja) | 1992-02-18 |
FR2663450A1 (fr) | 1991-12-20 |
CN1057720A (zh) | 1992-01-08 |
JP3025519B2 (ja) | 2000-03-27 |
DE4023015C1 (ko) | 1991-12-19 |
IT9048190A0 (it) | 1990-07-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR930008417B1 (ko) | 반도체 메모리 장치의 다중 비트 병렬 테스트방법 | |
US4893278A (en) | Semiconductor memory device including precharge/equalization circuitry for the complementary data lines | |
NL192155C (nl) | Datatransmissieketen. | |
US6661714B2 (en) | Integrated circuit memory devices having sense amplifiers therein that receive nominal and boosted supply voltages when active and methods of operating same | |
JPH0456398B2 (ko) | ||
KR100520179B1 (ko) | 반도체 메모리 장치의 입출력 구조 | |
US6847569B2 (en) | Differential current sense amplifier | |
EP0440206A2 (en) | Semiconductor memory having built-in test circuit | |
EP0521594A2 (en) | Semiconductor memory device | |
US5682110A (en) | Low capacitance bus driver | |
KR930008311B1 (ko) | 센스 앰프의 출력 제어회로 | |
US5455795A (en) | Semiconductor memory device | |
US4730133A (en) | Decoder circuit of a semiconductor memory device | |
US4634900A (en) | Sense amplifier | |
KR950010567B1 (ko) | 반도체장치의 출력단회로 | |
KR0155986B1 (ko) | 반도체 기억장치 | |
US5982692A (en) | Bit line boost amplifier | |
EP0397986B1 (en) | A non-address transition detection memory with improved access time | |
US6011739A (en) | Semiconductor memory | |
US6166964A (en) | Semiconductor memory and method of controlling data therefrom | |
EP0393027B1 (en) | Sense amplifier | |
US6445604B2 (en) | Channel driving circuit of virtual channel DRAM | |
US6252819B1 (en) | Reduced line select decoder for a memory array | |
JP3237234B2 (ja) | センスアンプ回路 | |
KR970004056B1 (ko) | 반도체 소자의 데이타 출력방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19900618 |
|
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19900618 Comment text: Request for Examination of Application |
|
PG1501 | Laying open of application | ||
G160 | Decision to publish patent application | ||
PG1605 | Publication of application before grant of patent |
Comment text: Decision on Publication of Application Patent event code: PG16051S01I Patent event date: 19930806 |
|
E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19931201 |
|
GRNT | Written decision to grant | ||
PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19940110 Patent event code: PR07011E01D |
|
PR1002 | Payment of registration fee |
Payment date: 19940110 End annual number: 3 Start annual number: 1 |
|
PR1001 | Payment of annual fee |
Payment date: 19960730 Start annual number: 4 End annual number: 4 |
|
PR1001 | Payment of annual fee |
Payment date: 19970731 Start annual number: 5 End annual number: 5 |
|
PR1001 | Payment of annual fee |
Payment date: 19980721 Start annual number: 6 End annual number: 6 |
|
PR1001 | Payment of annual fee |
Payment date: 19990721 Start annual number: 7 End annual number: 7 |
|
PR1001 | Payment of annual fee |
Payment date: 20000714 Start annual number: 8 End annual number: 8 |
|
PR1001 | Payment of annual fee |
Payment date: 20010706 Start annual number: 9 End annual number: 9 |
|
PR1001 | Payment of annual fee |
Payment date: 20020708 Start annual number: 10 End annual number: 10 |
|
PR1001 | Payment of annual fee |
Payment date: 20030707 Start annual number: 11 End annual number: 11 |
|
PR1001 | Payment of annual fee |
Payment date: 20040329 Start annual number: 12 End annual number: 12 |
|
PR1001 | Payment of annual fee |
Payment date: 20050708 Start annual number: 13 End annual number: 13 |
|
PR1001 | Payment of annual fee |
Payment date: 20060728 Start annual number: 14 End annual number: 14 |
|
PR1001 | Payment of annual fee |
Payment date: 20070801 Start annual number: 15 End annual number: 15 |
|
PR1001 | Payment of annual fee |
Payment date: 20080729 Start annual number: 16 End annual number: 16 |
|
FPAY | Annual fee payment |
Payment date: 20090814 Year of fee payment: 17 |
|
PR1001 | Payment of annual fee |
Payment date: 20090814 Start annual number: 17 End annual number: 17 |
|
EXPY | Expiration of term | ||
PC1801 | Expiration of term |