KR101187403B1 - 반도체장치 제조방법 - Google Patents
반도체장치 제조방법 Download PDFInfo
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- KR101187403B1 KR101187403B1 KR1020117022507A KR20117022507A KR101187403B1 KR 101187403 B1 KR101187403 B1 KR 101187403B1 KR 1020117022507 A KR1020117022507 A KR 1020117022507A KR 20117022507 A KR20117022507 A KR 20117022507A KR 101187403 B1 KR101187403 B1 KR 101187403B1
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Abstract
Description
도 2는 본 발명에 따른 라미네이팅 시스템을 설명하는 도면.
도 3은 본 발명에 따른 라미네이팅 시스템을 설명하는 도면.
도 4는 본 발명에 따른 라미네이팅 시스템을 설명하는 도면.
도 5(A) 및 도 5(B)는 IC 칩의 제조방법을 설명하는 도면.
도 6(A) 및 도 6(B)는 IC 칩의 제조방법을 설명하는 도면.
도 7(A) 및 도 7(B)는 IC 칩의 제조방법을 설명하는 도면.
도 8은 IC 칩의 제조방법을 설명하는 도면.
도 9는 IC 칩을 설명하는 도면.
도 10(A)~도 10(E)는 IC 칩의 사용 형태에 대하여 설명하는 도면.
도 11(A) 및 도 11(B)는 IC 칩의 사용 형태에 대하여 설명하는 도면.
도 12(A) 및 도 12(B)는 본 발명에 따른 롤을 설명하는 도면.
도 13은 본 발명에 따른 IC 칩을 설명하는 도면.
Claims (15)
- 제1 기판 위에 집적회로를 형성하고; 상기 집적회로 각각은 트랜지스터를 포함하고,
상기 집적회로가 개재되도록 상기 제1 기판을 제2 기판에 접착하고;
상기 제1 기판으로부터 상기 집적회로를 박리하고;
상기 집적회로가 상기 제2 기판과 제3 기판 사이에 봉지되도록 상기 제2 기판을 상기 제3 기판에 접착하고;
상기 제2 기판과 상기 제3 기판을 레이저로 복수의 칩으로 절단하는 공정을 포함하고,
상기 복수의 칩 각각은 상기 제2 기판의 일부와, 상기 제3 기판의 일부와, 상기 제2 기판의 일부와 상기 제3 기판의 일부 사이에 개재된 상기 집적회로의 적어도 하나를 포함하고,
상기 제2 기판의 상기 일부는 상기 집적회로의 상기 적어도 하나의 외측 영역에서 상기 제3 기판의 상기 일부와 접하는, 반도체장치 제조방법.
- 제1 기판 위에 집적회로를 형성하고; 상기 집적회로 각각은 트랜지스터와 안테나를 포함하고,
상기 집적회로가 개재되도록 상기 제1 기판을 제2 기판에 접착하고;
상기 제1 기판으로부터 상기 집적회로를 박리하고;
상기 집적회로가 상기 제2 기판과 제3 기판 사이에 봉지되도록 상기 제2 기판을 상기 제3 기판에 접착하고;
상기 제2 기판과 상기 제3 기판을 레이저로 복수의 칩으로 절단하는 공정을 포함하고,
상기 복수의 칩 각각은 상기 제2 기판의 일부와, 상기 제3 기판의 일부와, 상기 제2 기판의 일부와 상기 제3 기판의 일부 사이에 개재된 상기 집적회로의 적어도 하나를 포함하고,
상기 제2 기판의 상기 일부는 상기 집적회로의 상기 적어도 하나의 외측 영역에서 상기 제3 기판의 상기 일부와 접하는, 반도체장치 제조방법.
- 제 1 항 또는 제 2 항에 있어서,
상기 제2 기판과 상기 제3 기판 각각은 라미네이트 필름 또는 섬유질 재료로 된 종이를 구비하는, 반도체장치 제조방법.
- 제 1 항 또는 제 2 항에 있어서,
상기 제2 기판과 상기 제3 기판 각각은 폴리프로필렌, 폴리에스터, 비닐, 폴리비닐 플루오라이드, 폴리비닐 클로라이드, 폴리에틸렌, 에틸렌 비닐 아세테이트로 이루어진 그룹으로부터 선택된 적어도 하나를 포함하는, 반도체장치 제조방법.
- 제 1 항 또는 제 2 항에 있어서,
상기 제2 기판의 한쪽 면과 상기 제3 기판의 한쪽 면 중 적어도 하나는 접착제가 코팅된, 반도체장치 제조방법.
- 제 1 항 또는 제 2 항에 있어서,
상기 집적회로가 제1 롤러와 제2 롤러 사이를 통과할 때, 가압 처리와 가열 처리 중 적어도 하나를 행하여 상기 제2 기판과 상기 제3 기판 사이에 상기 집적회로가 봉지되는, 반도체장치 제조방법.
- 제 1 항 또는 제 2 항에 있어서,
상기 복수의 칩 각각은 비접촉으로 데이터 교신을 할 수 있는, 반도체장치 제조방법.
- 제 1 항 또는 제 2 항에 있어서,
상기 제2 기판과 상기 제3 기판은 상기 제2 기판을 상기 제3 기판에 접착하는 공정에 의해 상기 집적회로 각각의 외측 영역에서 서로 접하여 있는, 반도체장치 제조방법.
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JP2004094492A (ja) | 2002-08-30 | 2004-03-25 | Konica Minolta Holdings Inc | Icカード |
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Publication number | Publication date |
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JP2006019717A (ja) | 2006-01-19 |
CN101789378A (zh) | 2010-07-28 |
CN101789378B (zh) | 2012-07-04 |
KR101175277B1 (ko) | 2012-08-21 |
EP1774595A1 (en) | 2007-04-18 |
US20140220745A1 (en) | 2014-08-07 |
US8698156B2 (en) | 2014-04-15 |
KR20090027772A (ko) | 2009-03-17 |
EP1774595A4 (en) | 2011-05-18 |
KR101020661B1 (ko) | 2011-03-09 |
WO2005119781A1 (en) | 2005-12-15 |
KR20120030577A (ko) | 2012-03-28 |
CN1993829B (zh) | 2010-06-02 |
KR20110122204A (ko) | 2011-11-09 |
US20090212297A1 (en) | 2009-08-27 |
CN101527270B (zh) | 2012-07-04 |
US8123896B2 (en) | 2012-02-28 |
US20080044940A1 (en) | 2008-02-21 |
KR20070028477A (ko) | 2007-03-12 |
CN101527270A (zh) | 2009-09-09 |
CN1993829A (zh) | 2007-07-04 |
KR20090009996A (ko) | 2009-01-23 |
JP4579057B2 (ja) | 2010-11-10 |
US9536755B2 (en) | 2017-01-03 |
KR101226260B1 (ko) | 2013-01-28 |
KR100970194B1 (ko) | 2010-07-14 |
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