JP3910598B2 - 樹脂封止型半導体装置およびその製造方法 - Google Patents
樹脂封止型半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP3910598B2 JP3910598B2 JP2004060943A JP2004060943A JP3910598B2 JP 3910598 B2 JP3910598 B2 JP 3910598B2 JP 2004060943 A JP2004060943 A JP 2004060943A JP 2004060943 A JP2004060943 A JP 2004060943A JP 3910598 B2 JP3910598 B2 JP 3910598B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor element
- terminal
- connection pad
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 256
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 229920005989 resin Polymers 0.000 claims description 59
- 239000011347 resin Substances 0.000 claims description 59
- 238000007789 sealing Methods 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 43
- 238000000227 grinding Methods 0.000 description 15
- 238000007747 plating Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000004382 potting Methods 0.000 description 5
- 238000007639 printing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 239000010730 cutting oil Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
- H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05664—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/16257—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/16258—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01037—Rubidium [Rb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本発明の第3の構成の樹脂封止型半導体装置は、表面の周辺に沿って形成された第1の接続パッドと前記第1の接続パッドよりも内方に形成された第2の接続パッドとを有する半導体素子と、前記半導体素子の周囲に、先端側部分が前記半導体素子と重なるように形成され、末端側部分の上面に凸部を有するリードと、前記半導体素子の前記第1の接続パッドと前記リードの前記先端側部分とを接続する第1のバンプと、前記半導体素子の下方であって、前記リードより内方に形成された端子と、前記半導体素子の前記第2の接続パッドと前記端子とを接続する第2のバンプと、前記リードの下面と前記リードの前記凸部の上面と前記端子の下面とを露出するように、前記半導体素子の表面と前記リードと前記第1のバンプと前記端子と前記第2のバンプとを封止した封止樹脂とを備え、前記リードは、前記先端側部分の上面に、内部に尖状凸部が形成された凹部を有し、前記尖状凸部と前記第1のバンプとが接合している。
本発明の樹脂封止型半導体装置の第3の製造方法は、表面の周辺に沿って形成された第1の接続パッドと前記第1の接続パッドよりも内方に形成された第2の接続パッドとを有する半導体素子を準備する工程と、リードと前記リードの末端が接続されたリードフレーム枠からなり、前記リードの末端側部分の上面に凸部を有し、前記リードの前記先端側部分の上面に、内部に尖状凸部が形成された凹部を有するリードフレームを準備する工程と、前記リードフレームに囲まれた領域内の前記リードより内方側に、端子を形成する工程と、前記半導体素子の前記第1の接続パッドと前記リードの先端側部分の前記尖状凸部とを第1のバンプを介して接続する工程と、前記半導体素子の前記第2の接続パッドと前記端子とを第2のバンプを介して接続する工程と、前記リードの下面と前記リードの前記凸部の上面と前記端子の下面とを露出するように、前記半導体素子の表面と前記リードと前記第1のバンプと前記端子と前記第2のバンプとを樹脂封止する工程とを備える。
図1は、実施の形態1における樹脂封止型半導体装置を示し、(a)はその平面図、(b)は裏面図、(c)は(a)におけるA−A断面図である。
図7は、実施の形態2における樹脂封止型半導体装置を示し、(a)はその平面図、(b)は(a)のD−D断面図、(c)は裏面図である。図8は、図7の樹脂封止型半導体装置の製造工程を示す図である。
図11は、実施の形態4における樹脂封止型半導体装置を示し、(a)はその平面図、(b)は裏面図、(c)は(a)のF−F断面図である。この樹脂封止型半導体装置は、基本的には図1に示したものと同様の構造を有する。本実施の形態の特徴は、インナーリード6の内側領域に配置された2個の端子36間に、高誘電率樹脂37が挟み込まれていることである。
図13は、実施の形態4における樹脂封止型半導体装置を示し、(a)はその平面図、(b)は裏面図、(c)は(a)のG−G断面図である。この樹脂封止型半導体装置は、基本的には図1に示したものと同様の構造を有する。本実施の形態の特徴は、インナーリード6の内側領域に配置された2個の端子42が、コイル43の始点、終点になっていることである。
図17は、実施の形態5における樹脂封止型半導体装置を示し、(a)は断面図、(b)は平面図である。(a)の断面図は、(b)のH−H断面を示す。本実施の形態の特徴は、図5に示した構造の半導体装置における周縁に配置された第2外部端子部7の上面に、更に第3半導体素子48を接着剤49により接着して積層し、更に第2外部端子部7の外側に端子(インナーリードポスト)50を配置したことである。第3半導体素子48と端子50は、金属細線54で電気的に接続されている。
1a、39、45 リードフレーム保持シート
2 第1半導体素子
3 バンプ
4、30、55、60 封止樹脂
5、18 第1外部端子部
6、16a〜16c、53、58 インナーリード部
7、17、28 第2外部端子部
8、36、42 電気的導通用の端子
9a、9b、46a、46b 樹脂封止金型
10、47 封止用シート
12、13 位置決め穴
14 樹脂封止領域
15 素子搭載領域
19a〜19b 凸部
19c 凹部
21 第2半導体素子
33、34、35 半導体装置
37 高誘電率樹脂
40 ペースト
41 ディスペンサー
43 コイル
48 第3半導体素子
49 接着剤
50 端子
51、57 ダイパッド
52 半導体素子
54、59 金属細線
Claims (8)
- 表面の周辺に沿って形成された第1の接続パッドと前記第1の接続パッドよりも内方に形成された第2の接続パッドとを有する半導体素子と、
前記半導体素子の周囲に、先端側部分が前記半導体素子と重なるように形成され、末端側部分の上面に凸部を有するリードと、
前記半導体素子の前記第1の接続パッドと前記リードの前記先端側部分とを接続する第1のバンプと、
前記半導体素子の下方であって、前記リードより内方に形成された端子と、
前記半導体素子の前記第2の接続パッドと前記端子とを接続する第2のバンプと、
前記リードの下面と前記リードの前記凸部の上面と前記端子の下面とを露出するように、前記半導体素子の表面と前記リードと前記第1のバンプと前記端子と前記第2のバンプとを封止した封止樹脂とを備え、
前記端子は2個配置され、前記端子の一方が渦巻き状コイルの始点、他方が終点を形成している樹脂封止型半導体装置。 - 表面の周辺に沿って形成された第1の接続パッドと前記第1の接続パッドよりも内方に形成された第2の接続パッドとを有する半導体素子と、
前記半導体素子の周囲に、先端側部分が前記半導体素子と重なるように形成され、末端側部分の上面に凸部を有するリードと、
前記半導体素子の前記第1の接続パッドと前記リードの前記先端側部分とを接続する第1のバンプと、
前記半導体素子の下方であって、前記リードより内方に形成された端子と、
前記半導体素子の前記第2の接続パッドと前記端子とを接続する第2のバンプと、
前記リードの下面と前記リードの前記凸部の上面と前記端子の下面とを露出するように、前記半導体素子の表面と前記リードと前記第1のバンプと前記端子と前記第2のバンプとを封止した封止樹脂とを備え、
前記リードは、前記先端側部分の上面に突出部を有し、前記突出部と前記第1のバンプとが接合している樹脂封止型半導体装置。 - 前記突出部の上端面は、凹形状である請求項2に記載の樹脂封止型半導体装置。
- 表面の周辺に沿って形成された第1の接続パッドと前記第1の接続パッドよりも内方に形成された第2の接続パッドとを有する半導体素子と、
前記半導体素子の周囲に、先端側部分が前記半導体素子と重なるように形成され、末端側部分の上面に凸部を有するリードと、
前記半導体素子の前記第1の接続パッドと前記リードの前記先端側部分とを接続する第1のバンプと、
前記半導体素子の下方であって、前記リードより内方に形成された端子と、
前記半導体素子の前記第2の接続パッドと前記端子とを接続する第2のバンプと、
前記リードの下面と前記リードの前記凸部の上面と前記端子の下面とを露出するように、前記半導体素子の表面と前記リードと前記第1のバンプと前記端子と前記第2のバンプとを封止した封止樹脂とを備え、
前記リードは、前記先端側部分の上面に、内部に尖状凸部が形成された凹部を有し、前記尖状凸部と前記第1のバンプとが接合している樹脂封止型半導体装置。 - 表面の周辺に沿って形成された第1の接続パッドと前記第1の接続パッドよりも内方に形成された第2の接続パッドとを有する半導体素子を準備する工程と、
リードと前記リードの末端が接続されたリードフレーム枠からなり、前記リードの末端側部分の上面に凸部を有するリードフレームを準備する工程と、
前記リードフレームに囲まれた領域内の前記リードより内方側に、端子を2個形成し、前記端子の一方を渦巻き状コイルの始点、他方を終点として形成する工程と、
前記半導体素子の前記第1の接続パッドと前記リードの先端側部分とを第1のバンプを介して接続する工程と、
前記半導体素子の前記第2の接続パッドと前記端子とを第2のバンプを介して接続する工程と、
前記リードの下面と前記リードの前記凸部の上面と前記端子の下面とを露出するように、前記半導体素子の表面と前記リードと前記第1のバンプと前記端子と前記第2のバンプとを樹脂封止する工程と
を備えた樹脂封止型半導体装置の製造方法。 - 表面の周辺に沿って形成された第1の接続パッドと前記第1の接続パッドよりも内方に形成された第2の接続パッドとを有する半導体素子を準備する工程と、
リードと前記リードの末端が接続されたリードフレーム枠からなり、前記リードの末端側部分の上面に凸部を有し、前記リードの前記先端側部分の上面に突出部を有するリードフレームを準備する工程と、
前記リードフレームに囲まれた領域内の前記リードより内方側に、端子を形成する工程と、
前記半導体素子の前記第1の接続パッドと前記リードの先端側部分の前記突出部とを第1のバンプを介して接続する工程と、
前記半導体素子の前記第2の接続パッドと前記端子とを第2のバンプを介して接続する工程と、
前記リードの下面と前記リードの前記凸部の上面と前記端子の下面とを露出するように、前記半導体素子の表面と前記リードと前記第1のバンプと前記端子と前記第2のバンプとを樹脂封止する工程と
を備えた樹脂封止型半導体装置の製造方法。 - 前記突出部の上端面を凹形状に形成する工程を備えた請求項6に記載の樹脂封止型半導体装置の製造方法。
- 表面の周辺に沿って形成された第1の接続パッドと前記第1の接続パッドよりも内方に形成された第2の接続パッドとを有する半導体素子を準備する工程と、
リードと前記リードの末端が接続されたリードフレーム枠からなり、前記リードの末端側部分の上面に凸部を有し、前記リードの前記先端側部分の上面に、内部に尖状凸部が形成された凹部を有するリードフレームを準備する工程と、
前記リードフレームに囲まれた領域内の前記リードより内方側に、端子を形成する工程と、
前記半導体素子の前記第1の接続パッドと前記リードの先端側部分の前記尖状凸部とを第1のバンプを介して接続する工程と、
前記半導体素子の前記第2の接続パッドと前記端子とを第2のバンプを介して接続する工程と、
前記リードの下面と前記リードの前記凸部の上面と前記端子の下面とを露出するように、前記半導体素子の表面と前記リードと前記第1のバンプと前記端子と前記第2のバンプとを樹脂封止する工程と
を備えた樹脂封止型半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004060943A JP3910598B2 (ja) | 2004-03-04 | 2004-03-04 | 樹脂封止型半導体装置およびその製造方法 |
TW094105705A TW200531249A (en) | 2004-03-04 | 2005-02-25 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
US11/071,343 US7495319B2 (en) | 2004-03-04 | 2005-03-03 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
CN2005100529995A CN1665023A (zh) | 2004-03-04 | 2005-03-04 | 树脂密封半导体器件和引线框架、及其制造方法 |
US12/355,075 US20090130801A1 (en) | 2004-03-04 | 2009-01-16 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004060943A JP3910598B2 (ja) | 2004-03-04 | 2004-03-04 | 樹脂封止型半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005252018A JP2005252018A (ja) | 2005-09-15 |
JP3910598B2 true JP3910598B2 (ja) | 2007-04-25 |
Family
ID=34909218
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004060943A Expired - Fee Related JP3910598B2 (ja) | 2004-03-04 | 2004-03-04 | 樹脂封止型半導体装置およびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7495319B2 (ja) |
JP (1) | JP3910598B2 (ja) |
CN (1) | CN1665023A (ja) |
TW (1) | TW200531249A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI690046B (zh) * | 2017-11-28 | 2020-04-01 | 日商青井電子股份有限公司 | 半導體裝置及其製造方法 |
Families Citing this family (95)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
DE112006001810T5 (de) | 2005-06-24 | 2008-08-21 | Metaram Inc., San Jose | Integrierte Speicherkern - und Speicherschnittstellenschaltung |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8796830B1 (en) * | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
DE112006004263B4 (de) | 2005-09-02 | 2015-05-13 | Google, Inc. | Speicherbaustein |
CN100395888C (zh) * | 2005-09-30 | 2008-06-18 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
US7361531B2 (en) * | 2005-11-01 | 2008-04-22 | Allegro Microsystems, Inc. | Methods and apparatus for Flip-Chip-On-Lead semiconductor package |
US20070132075A1 (en) * | 2005-12-12 | 2007-06-14 | Mutsumi Masumoto | Structure and method for thin single or multichip semiconductor QFN packages |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US7990727B1 (en) * | 2006-04-03 | 2011-08-02 | Aprolase Development Co., Llc | Ball grid array stack |
US8492906B2 (en) | 2006-04-28 | 2013-07-23 | Utac Thai Limited | Lead frame ball grid array with traces under die |
US8310060B1 (en) | 2006-04-28 | 2012-11-13 | Utac Thai Limited | Lead frame land grid array |
US8487451B2 (en) | 2006-04-28 | 2013-07-16 | Utac Thai Limited | Lead frame land grid array with routing connector trace under unit |
JP4882562B2 (ja) * | 2006-07-13 | 2012-02-22 | パナソニック株式会社 | 熱伝導基板とその製造方法及び電源ユニット及び電子機器 |
US7667308B2 (en) | 2006-07-24 | 2010-02-23 | Stats Chippac, Ltd. | Leaded stacked packages having integrated upper lead |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US9082607B1 (en) | 2006-12-14 | 2015-07-14 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US9761435B1 (en) | 2006-12-14 | 2017-09-12 | Utac Thai Limited | Flip chip cavity package |
US20080157302A1 (en) * | 2006-12-27 | 2008-07-03 | Lee Seungju | Stacked-package quad flat null lead package |
KR100893939B1 (ko) * | 2007-02-16 | 2009-04-21 | 삼성전자주식회사 | 본딩 패드 구조체를 갖는 전자 장치 및 그 제조방법 |
JP2008235401A (ja) | 2007-03-19 | 2008-10-02 | Spansion Llc | 半導体装置及びその製造方法 |
KR100874923B1 (ko) * | 2007-04-02 | 2008-12-19 | 삼성전자주식회사 | 멀티 스택 패키지, 이의 제조 방법 및 이를 제조하기 위한반도체 패키지 금형 |
US8106496B2 (en) * | 2007-06-04 | 2012-01-31 | Stats Chippac, Inc. | Semiconductor packaging system with stacking and method of manufacturing thereof |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US20090115070A1 (en) * | 2007-09-20 | 2009-05-07 | Junji Tanaka | Semiconductor device and method for manufacturing thereof |
JP2009094118A (ja) * | 2007-10-04 | 2009-04-30 | Panasonic Corp | リードフレーム、それを備える電子部品及びその製造方法 |
US7790512B1 (en) | 2007-11-06 | 2010-09-07 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US8063474B2 (en) * | 2008-02-06 | 2011-11-22 | Fairchild Semiconductor Corporation | Embedded die package on package (POP) with pre-molded leadframe |
US9947605B2 (en) | 2008-09-04 | 2018-04-17 | UTAC Headquarters Pte. Ltd. | Flip chip cavity package |
US8288845B2 (en) | 2008-11-14 | 2012-10-16 | Triquint Semiconductor, Inc. | Package including proximately-positioned lead frame |
US20100230792A1 (en) * | 2009-03-12 | 2010-09-16 | Scott Irving | Premolded Substrates with Apertures for Semiconductor Die Packages with Stacked Dice, Said Packages, and Methods of Making the Same |
EP2441007A1 (en) | 2009-06-09 | 2012-04-18 | Google, Inc. | Programming of dimm termination resistance values |
US20100314728A1 (en) * | 2009-06-16 | 2010-12-16 | Tung Lok Li | Ic package having an inductor etched into a leadframe thereof |
US8236607B2 (en) * | 2009-06-19 | 2012-08-07 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof |
US9449900B2 (en) | 2009-07-23 | 2016-09-20 | UTAC Headquarters Pte. Ltd. | Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow |
US9355940B1 (en) | 2009-12-04 | 2016-05-31 | Utac Thai Limited | Auxiliary leadframe member for stabilizing the bond wire process |
US8368189B2 (en) | 2009-12-04 | 2013-02-05 | Utac Thai Limited | Auxiliary leadframe member for stabilizing the bond wire process |
US8575732B2 (en) | 2010-03-11 | 2013-11-05 | Utac Thai Limited | Leadframe based multi terminal IC package |
CN101834163A (zh) * | 2010-04-29 | 2010-09-15 | 南通富士通微电子股份有限公司 | 一种半导体倒装焊封装散热改良结构 |
CN201838585U (zh) * | 2010-06-17 | 2011-05-18 | 国碁电子(中山)有限公司 | 堆叠式芯片封装结构及其基板 |
US9142502B2 (en) | 2011-08-31 | 2015-09-22 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
US8916421B2 (en) * | 2011-08-31 | 2014-12-23 | Freescale Semiconductor, Inc. | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
KR101354894B1 (ko) * | 2011-10-27 | 2014-01-23 | 삼성전기주식회사 | 반도체 패키지, 그 제조방법 및 이를 포함하는 반도체 패키지 모듈 |
US8597983B2 (en) | 2011-11-18 | 2013-12-03 | Freescale Semiconductor, Inc. | Semiconductor device packaging having substrate with pre-encapsulation through via formation |
CN103441115B (zh) * | 2011-11-29 | 2017-04-26 | 矽力杰半导体技术(杭州)有限公司 | 一种引线框架及应用其的芯片倒装封装装置 |
US8643166B2 (en) | 2011-12-15 | 2014-02-04 | Stats Chippac Ltd. | Integrated circuit packaging system with leads and method of manufacturing thereof |
US8629539B2 (en) | 2012-01-16 | 2014-01-14 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US9494660B2 (en) | 2012-03-20 | 2016-11-15 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US9029198B2 (en) | 2012-05-10 | 2015-05-12 | Utac Thai Limited | Methods of manufacturing semiconductor devices including terminals with internal routing interconnections |
US9449905B2 (en) | 2012-05-10 | 2016-09-20 | Utac Thai Limited | Plated terminals with routing interconnections semiconductor device |
US9397031B2 (en) | 2012-06-11 | 2016-07-19 | Utac Thai Limited | Post-mold for semiconductor package having exposed traces |
JP2014143326A (ja) * | 2013-01-24 | 2014-08-07 | Transphorm Japan Inc | 半導体装置、半導体装置の製造方法、リード、及びリードの製造方法 |
US9411025B2 (en) | 2013-04-26 | 2016-08-09 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame and a magnet |
US9082766B2 (en) * | 2013-08-06 | 2015-07-14 | Google Technology Holdings LLC | Method to enhance reliability of through mold via TMVA part on part POP devices |
CN104681504A (zh) * | 2013-11-29 | 2015-06-03 | 意法半导体研发(深圳)有限公司 | 具有第一和第二接触焊盘的电子设备及相关方法 |
CN103730428B (zh) * | 2013-12-05 | 2017-09-08 | 通富微电子股份有限公司 | 封装结构 |
JP6515642B2 (ja) * | 2015-04-02 | 2019-05-22 | スミダコーポレーション株式会社 | コイル部品の製造方法およびコイル部品の製造に用いられる治具 |
US10032645B1 (en) | 2015-11-10 | 2018-07-24 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple molding routing layers and a method of manufacturing the same |
WO2017189367A1 (en) * | 2016-04-29 | 2017-11-02 | Uniqarta, Inc. | Connecting electronic components to substrates |
US10276477B1 (en) | 2016-05-20 | 2019-04-30 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple stacked leadframes and a method of manufacturing the same |
US10199312B1 (en) * | 2017-09-09 | 2019-02-05 | Amkor Technology, Inc. | Method of forming a packaged semiconductor device having enhanced wettable flank and structure |
EP3499552A1 (en) * | 2017-12-14 | 2019-06-19 | Nexperia B.V. | Semiconductor device and method of manufacture |
JP6842433B2 (ja) * | 2018-01-25 | 2021-03-17 | 株式会社加藤電器製作所 | 電子デバイス |
CN108447840B (zh) * | 2018-02-08 | 2020-04-10 | 积高电子(无锡)有限公司 | 一种半导体电阻桥封装结构和工艺 |
JP7051508B2 (ja) | 2018-03-16 | 2022-04-11 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
JP7193284B2 (ja) * | 2018-09-21 | 2022-12-20 | 新光電気工業株式会社 | リードフレーム及びリードフレームの製造方法 |
EP3874595A1 (en) * | 2018-10-30 | 2021-09-08 | Excelitas Canada, Inc. | Low inductance laser driver packaging using lead-frame and thin dielectric layer mask pad definition |
US10991644B2 (en) | 2019-08-22 | 2021-04-27 | Allegro Microsystems, Llc | Integrated circuit package having a low profile |
US11355470B2 (en) * | 2020-02-27 | 2022-06-07 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and methods of manufacturing semiconductor devices |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960005042B1 (ko) * | 1992-11-07 | 1996-04-18 | 금성일렉트론주식회사 | 반도체 펙케지 |
JPH07335804A (ja) * | 1994-06-14 | 1995-12-22 | Dainippon Printing Co Ltd | リードフレーム及びリードフレームの製造方法 |
KR100293815B1 (ko) * | 1998-06-30 | 2001-07-12 | 박종섭 | 스택형 패키지 |
JP3921885B2 (ja) | 1999-08-25 | 2007-05-30 | 松下電器産業株式会社 | 樹脂封止型半導体装置の製造方法 |
JP2001077277A (ja) | 1999-09-03 | 2001-03-23 | Sony Corp | 半導体パッケージおよび半導体パッケージ製造方法 |
US6388336B1 (en) * | 1999-09-15 | 2002-05-14 | Texas Instruments Incorporated | Multichip semiconductor assembly |
JP2001177007A (ja) | 1999-12-21 | 2001-06-29 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP3420153B2 (ja) * | 2000-01-24 | 2003-06-23 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP2001332866A (ja) | 2000-05-24 | 2001-11-30 | Matsushita Electric Ind Co Ltd | 回路基板及びその製造方法 |
JP2002026181A (ja) | 2000-07-05 | 2002-01-25 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置およびその製造方法 |
TW454309B (en) | 2000-07-17 | 2001-09-11 | Orient Semiconductor Elect Ltd | Package structure of CCD image-capturing chip |
TW473965B (en) * | 2000-09-04 | 2002-01-21 | Siliconware Precision Industries Co Ltd | Thin type semiconductor device and the manufacturing method thereof |
US6337510B1 (en) * | 2000-11-17 | 2002-01-08 | Walsin Advanced Electronics Ltd | Stackable QFN semiconductor package |
JP2002170921A (ja) | 2000-12-01 | 2002-06-14 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP3565334B2 (ja) * | 2001-01-25 | 2004-09-15 | シャープ株式会社 | 半導体装置およびそれを用いる液晶モジュール、並びに半導体装置の製造方法 |
US20030038347A1 (en) * | 2001-08-22 | 2003-02-27 | Walton Advanced Electronics Ltd | Stackable-type semiconductor package |
JP2003197822A (ja) | 2001-12-25 | 2003-07-11 | Sony Corp | 配線基板、多層配線基板およびそれらの製造方法 |
JP2003249604A (ja) | 2002-02-25 | 2003-09-05 | Kato Denki Seisakusho:Kk | 樹脂封止半導体装置およびその製造方法、樹脂封止半導体装置に使用されるリードフレーム、ならびに半導体モジュール装置 |
US6812552B2 (en) * | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
TW540123B (en) * | 2002-06-14 | 2003-07-01 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor package with lead frame as chip carrier |
JP3801121B2 (ja) * | 2002-08-30 | 2006-07-26 | 松下電器産業株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP3736516B2 (ja) * | 2002-11-01 | 2006-01-18 | 松下電器産業株式会社 | リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法 |
JP3851607B2 (ja) * | 2002-11-21 | 2006-11-29 | ローム株式会社 | 半導体装置の製造方法 |
US7138707B1 (en) * | 2003-10-21 | 2006-11-21 | Amkor Technology, Inc. | Semiconductor package including leads and conductive posts for providing increased functionality |
-
2004
- 2004-03-04 JP JP2004060943A patent/JP3910598B2/ja not_active Expired - Fee Related
-
2005
- 2005-02-25 TW TW094105705A patent/TW200531249A/zh unknown
- 2005-03-03 US US11/071,343 patent/US7495319B2/en not_active Expired - Lifetime
- 2005-03-04 CN CN2005100529995A patent/CN1665023A/zh active Pending
-
2009
- 2009-01-16 US US12/355,075 patent/US20090130801A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI690046B (zh) * | 2017-11-28 | 2020-04-01 | 日商青井電子股份有限公司 | 半導體裝置及其製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2005252018A (ja) | 2005-09-15 |
US20090130801A1 (en) | 2009-05-21 |
TW200531249A (en) | 2005-09-16 |
CN1665023A (zh) | 2005-09-07 |
US7495319B2 (en) | 2009-02-24 |
US20050194676A1 (en) | 2005-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3910598B2 (ja) | 樹脂封止型半導体装置およびその製造方法 | |
JP5214554B2 (ja) | 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法 | |
US6803254B2 (en) | Wire bonding method for a semiconductor package | |
JP5242644B2 (ja) | 半導体記憶装置 | |
KR101011863B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
JP2011040602A (ja) | 電子装置およびその製造方法 | |
KR101117848B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US20020135049A1 (en) | Electronic package with surface-mountable device built therein | |
JP2005183923A (ja) | 半導体装置およびその製造方法 | |
JP2009044110A (ja) | 半導体装置及びその製造方法 | |
CN101252096A (zh) | 芯片封装结构以及其制作方法 | |
KR20060101385A (ko) | 반도체 장치 및 그 제조 방법 | |
CN112768437B (zh) | 多层堆叠封装结构和多层堆叠封装结构的制备方法 | |
JP2009094434A (ja) | 半導体装置およびその製造方法 | |
US10373930B2 (en) | Package structure and the method to fabricate thereof | |
JP4598316B2 (ja) | 樹脂封止型半導体装置およびその製造方法 | |
TW201733076A (zh) | 半導體裝置及其製造方法 | |
CN108511352A (zh) | 电子封装结构及其制法 | |
JP7467214B2 (ja) | 配線基板、電子装置及び配線基板の製造方法 | |
US11227813B2 (en) | Electronic apparatus | |
WO2007057954A1 (ja) | 半導体装置及びその製造方法 | |
JP2008153699A (ja) | 半導体装置及びその製造方法 | |
JP2003046053A (ja) | 半導体装置およびその製造方法 | |
JP2004165429A (ja) | 半導体装置及びその製造方法、受動素子及びその集積体、並びにリードフレーム | |
JP4740555B2 (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050531 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060516 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060518 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060713 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20061109 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061226 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20070123 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20070124 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100202 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110202 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120202 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130202 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130202 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140202 Year of fee payment: 7 |
|
LAPS | Cancellation because of no payment of annual fees |