JP2014143326A - 半導体装置、半導体装置の製造方法、リード、及びリードの製造方法 - Google Patents
半導体装置、半導体装置の製造方法、リード、及びリードの製造方法 Download PDFInfo
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- JP2014143326A JP2014143326A JP2013011458A JP2013011458A JP2014143326A JP 2014143326 A JP2014143326 A JP 2014143326A JP 2013011458 A JP2013011458 A JP 2013011458A JP 2013011458 A JP2013011458 A JP 2013011458A JP 2014143326 A JP2014143326 A JP 2014143326A
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Abstract
【解決手段】FETチップ10と、FETチップ10の上面11に設けられた複数のパッド12〜16と、複数のパッド12〜16の少なくとも1つのパッド上に複数設けられたバンプ40と、バンプ40によってFETチップ10が接続され、FETチップ10の上面11に沿って延在する第1部分44と、第1部分44のFETチップ10の上面11に沿った面41に接し、FETチップ10の側面13に沿って延在する第2部分46と、を有し、プレス加工又は切削加工により形成されたリード42a〜42cと、FETチップ10とリード42a〜42cとを封止すると共に、FETチップ10の下面15側からリード42a〜42cの第2部分46が露出する封止部48と、を備える半導体装置。
【選択図】図3
Description
(付記1)電界効果トランジスタチップと、前記電界効果トランジスタチップの上面に設けられた複数のパッドと、前記複数のパッドの少なくとも1つのパッド上に複数設けられたバンプと、前記バンプによって前記電界効果トランジスタチップが接続され、前記電界効果トランジスタチップの前記上面に沿って延在する第1部分と、前記第1部分の前記電界効果トランジスタチップの前記上面に沿った面に接し、前記電界効果トランジスタチップの側面に沿って延在する第2部分と、を有し、プレス加工又は切削加工により形成されたリードと、前記電界効果トランジスタチップと前記リードとを封止すると共に、前記電界効果トランジスタチップの下面側から前記リードの前記第2部分が露出する封止部と、を備えることを特徴とする半導体装置。
(付記2)前記リードは、前記第1部分の厚さと前記第2部分の幅とが異なる大きさであることを特徴とする付記1記載の半導体装置。
(付記3)前記電界効果トランジスタチップの前記複数のパッドのうちのソースパッドに接続される前記リードの前記第2部分と、ドレインパッドに接続される前記リードの前記第2部分とは、前記電界効果トランジスタチップを挟む位置で前記封止部から露出することを特徴とする付記1または2記載の半導体装置。
(付記4)前記電界効果トランジスタチップは、高電子移動度トランジスタチップであることを特徴とする付記1から3のいずれか一項記載の半導体装置。
(付記5)前記電界効果トランジスタチップは、GaN系半導体を用いた高電子移動度トランジスタチップであることを特徴とする付記1から4のいずれか一項記載の半導体装置。
(付記6)前記少なくとも1つのパッドに設けられた複数の前記バンプは、前記パッド上で縦横に整列して設けられ、等間隔に配置されていることを特徴とする付記1から5のいずれか一項記載の半導体装置。
(付記7)前記リードは、前記第1部分の前記電界効果トランジスタチップの前記上面に沿った面と反対の面に接し、前記反対の面から離れる方向に向かって延在する第3部分を有し、前記第3部分は前記封止部から露出していることを特徴とする付記1から6のいずれか一項記載の半導体装置。
(付記8)前記第3部分は、前記第2部分に相対する位置の前記第1部分の前記電界効果トランジスタチップの前記上面に沿った面と反対の面に接し、前記第2部分の延長線上を延在していることを特徴とする付記7記載の半導体装置。
(付記9)前記第3部分の幅と前記第1部分の厚さとは異なる大きさであることを特徴とする請求項7または8記載の半導体装置。
(付記10)前記封止部から露出する前記リードの前記第3部分に突起電極が設けられていることを特徴とする付記7から9のいずれか一項記載の半導体装置。
(付記11)前記突起電極の高さは150μm以上であることを特徴とする付記10記載の半導体装置。
(付記12)前記リードの前記第3部分の前記封止部から露出する部分の形状は、矩形状であることを特徴とする付記7から11のいずれか一項記載の半導体装置。
(付記13)前記リードの前記第3部分の前記封止部から露出する部分の形状は、円形状であることを特徴とする付記7から11のいずれか一項記載の半導体装置。
(付記14)付記7から13のいずれか一項記載の半導体装置である第1半導体装置と第2半導体装置とを具備し、前記第1半導体装置の前記リードの前記第3部分又は前記突起電極が、前記第2半導体装置の前記リードの前記第2部分と接続されて、前記第1半導体装置と前記第2半導体装置とが積層されていることを特徴とする半導体装置。
(付記15)ストライプ状の凹部と凸部が形成された金属板を準備する工程と、前記凹部から前記凸部に延在するリードを画定する抜きパターンを、プレス加工又は切削加工によって前記金属板に形成する工程と、前記抜きパターンで画定された前記リードの前記凹部に、電界効果トランジスタチップ上面の複数のパッドに設けられると共に、前記複数のパッドのうちの少なくとも1つのパッド上に複数設けられたバンプを接続する工程と、前記金属板を切断して前記電界効果トランジスタチップを個片化する工程と、個片化した後、前記リードの前記電界効果トランジスタチップ下面に沿った面を露出させるように、前記電界効果トランジスタチップと前記リードとを封止する工程と、を備えることを特徴とする半導体装置の製造方法。
(付記16)前記金属板に縦横に整列した複数の前記抜きパターンを形成し、前記複数の抜きパターンそれぞれで画定された前記リードの凹部に、前記電界効果トランジスタチップ上面の前記パッド上に設けられた前記バンプを接続させ、前記金属板を切断することで、複数の前記電界効果トランジスタチップを一括して個片化することを特徴とする付記15記載の半導体装置の製造方法。
(付記17)前記凹部と前記凸部とが形成された面とは反対の面であって、前記凸部の側端部に相対する部分に突起部が形成された前記金属板を準備することを特徴とする付記15または16記載の半導体装置の製造方法。
(付記18)ストライプ状の凹部と凸部が形成された金属板を準備する工程と、前記凹部から前記凸部に延在するリードを画定する抜きパターンを、プレス加工又は切削加工によって前記金属板に形成する工程と、前記抜きパターンを形成した後、前記金属板を切断する工程と、を供えることを特徴とするリードの製造方法。
(付記19)電界効果トランジスタチップ上面のパッド上に設けられたバンプが接続される部分であって、前記電界効果トランジスタチップの前記上面に沿って延在する第1部分と、前記第1部分の前記電界効果トランジスタチップの前記上面に沿った面に接し、前記電界効果トランジスタチップの側面に沿って延在する第2部分と、前記第1部分の電界効果トランジスタチップの前記上面に沿った面とは反対の面に接し、前記反対の面から離れる方向に向かって延在する第3部分と、を備えることを特徴とするリード。
12 ソースパッド
14 ドレインパッド
16 ゲートパッド
18 領域
20 ソース電極
22 ドレイン電極
24 ゲート電極
26 ソース配線
28 ドレイン配線
30 ゲート配線
40 バンプ
42a〜42c、72a〜72c、82a〜82c リード
44、74 第1部分
46、76 第2部分
48 封止部
50、70 金属板
52 凹部
54 凸部
56 抜きパターン
58 リードフレーム
60 リリースフィルム
64 半田
66 突起部
68 突起電極
78 第3部分
100、200、250、300、400、500 半導体装置
Claims (11)
- 電界効果トランジスタチップと、
前記電界効果トランジスタチップの上面に設けられた複数のパッドと、
前記複数のパッドの少なくとも1つのパッド上に複数設けられたバンプと、
前記バンプによって前記電界効果トランジスタチップが接続され、前記電界効果トランジスタチップの前記上面に沿って延在する第1部分と、前記第1部分の前記電界効果トランジスタチップの前記上面に沿った面に接し、前記電界効果トランジスタチップの側面に沿って延在する第2部分と、を有し、プレス加工又は切削加工により形成されたリードと、
前記電界効果トランジスタチップと前記リードとを封止すると共に、前記電界効果トランジスタチップの下面側から前記リードの前記第2部分が露出する封止部と、を備えることを特徴とする半導体装置。 - 前記リードは、前記第1部分の厚さと前記第2部分の幅とが異なる大きさであることを特徴とする請求項1記載の半導体装置。
- 前記電界効果トランジスタチップの前記複数のパッドのうちのソースパッドに接続される前記リードの前記第2部分と、ドレインパッドに接続される前記リードの前記第2部分とは、前記電界効果トランジスタチップを挟む位置で前記封止部から露出することを特徴とする請求項1または2記載の半導体装置。
- 前記電界効果トランジスタチップは、GaN系半導体を用いた高電子移動度トランジスタチップであることを特徴とする請求項1から3のいずれか一項記載の半導体装置。
- 前記リードは、前記第1部分の前記電界効果トランジスタチップの前記上面に沿った面と反対の面に接し、前記反対の面から離れる方向に向かって延在する第3部分を有し、前記第3部分は、前記封止部から露出していることを特徴とする請求項1から4のいずれか一項記載の半導体装置。
- 前記封止部から露出する前記リードの前記第3部分に突起電極が設けられていることを特徴とする請求項5記載の半導体装置。
- 請求項5または6記載の半導体装置である第1半導体装置と第2半導体装置とを具備し、前記第1半導体装置の前記リードの前記第3部分又は前記突起電極が、前記第2半導体装置の前記リードの前記第2部分と接続されて、前記第1半導体装置と前記第2半導体装置とが積層されていることを特徴とする半導体装置。
- ストライプ状の凹部と凸部が形成された金属板を準備する工程と、
前記凹部から前記凸部に延在するリードを画定する抜きパターンを、プレス加工又は切削加工によって前記金属板に形成する工程と、
前記抜きパターンで画定された前記リードの前記凹部に、電界効果トランジスタチップ上面の複数のパッドに設けられると共に、前記複数のパッドの少なくとも1つのパッド上に複数設けられたバンプを接続する工程と、
前記金属板を切断して前記電界効果トランジスタチップを個片化する工程と、
個片化した後、前記リードの前記電界効果トランジスタチップの下面に沿った面を露出させるように、前記電界効果トランジスタチップと前記リードとを封止する工程と、を備えることを特徴とする半導体装置の製造方法。 - 前記金属板に縦横に整列した複数の前記抜きパターンを形成し、
前記複数の抜きパターンそれぞれで画定された前記リードの凹部に、前記電界効果トランジスタチップ上面の前記パッド上に設けられた前記バンプを接続させ、
前記金属板を切断することで、複数の前記電界効果トランジスタチップを一括して個片化することを特徴とする請求項8記載の半導体装置の製造方法。 - ストライプ状の凹部と凸部が形成された金属板を準備する工程と、
前記凹部から前記凸部に延在するリードを画定する抜きパターンを、プレス加工又は切削加工によって前記金属板に形成する工程と、
前記抜きパターンを形成した後、前記金属板を切断する工程と、を備えることを特徴とするリードの製造方法。 - 電界効果トランジスタ上面のパッド上に設けられたバンプが接続される部分であって、前記電界効果トランジスタチップの前記上面に沿って延在する第1部分と、
前記第1部分の前記電界効果トランジスタチップの前記上面に沿った面に接し、前記電界効果トランジスタチップの側面に沿って延在する第2部分と、
前記第1部分の前記電界効果トランジスタチップの前記上面に沿った面とは反対の面に接し、前記反対の面から離れる方向に向かって延在する第3部分と、を備えることを特徴とするリード。
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JP2017005212A (ja) * | 2015-06-15 | 2017-01-05 | 富士電機株式会社 | パワー半導体回路及びパワー半導体素子の実装方法 |
WO2018056426A1 (ja) * | 2016-09-26 | 2018-03-29 | 株式会社パウデック | 半導体パッケージ、モジュールおよび電気機器 |
JP2018056538A (ja) * | 2016-09-26 | 2018-04-05 | 株式会社パウデック | 半導体パッケージ、モジュールおよび電気機器 |
JP2018093221A (ja) * | 2016-09-26 | 2018-06-14 | 株式会社パウデック | 半導体パッケージ、モジュールおよび電気機器 |
US11270969B2 (en) | 2019-06-04 | 2022-03-08 | Jmj Korea Co., Ltd. | Semiconductor package |
US11676931B2 (en) | 2019-06-04 | 2023-06-13 | Jmj Korea Co., Ltd. | Semiconductor package |
KR20210004066A (ko) * | 2019-07-03 | 2021-01-13 | 제엠제코(주) | 반도체 패키지 |
KR102327950B1 (ko) * | 2019-07-03 | 2021-11-17 | 제엠제코(주) | 반도체 패키지 |
JP2021090070A (ja) * | 2019-08-26 | 2021-06-10 | マクセルホールディングス株式会社 | 半導体装置用基板及び半導体装置 |
JP7412376B2 (ja) | 2019-08-26 | 2024-01-12 | マクセル株式会社 | 半導体装置用基板 |
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US20140203291A1 (en) | 2014-07-24 |
CN103972197A (zh) | 2014-08-06 |
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