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CN117253905A - SiC device with floating island structure and preparation method thereof - Google Patents

SiC device with floating island structure and preparation method thereof Download PDF

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Publication number
CN117253905A
CN117253905A CN202311506101.1A CN202311506101A CN117253905A CN 117253905 A CN117253905 A CN 117253905A CN 202311506101 A CN202311506101 A CN 202311506101A CN 117253905 A CN117253905 A CN 117253905A
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layer
floating island
drift layer
sic device
region
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张婷
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Shenzhen Sirius Semiconductor Co ltd
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Shenzhen Sirius Semiconductor Co ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/035—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon carbide [SiC] technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements

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Abstract

The invention provides a SiC device with a floating island structure and a preparation method thereof, wherein the SiC device comprises: at least one P-type floating island layer; the P-type floating island layer is embedded into the drift layer; the P-type floating island layers are arranged in a stacked mode. The P-type floating island layer protects the grid oxide layer of the JFET region, prevents the grid oxide layer from being broken down in advance, and can also reduce the overlapping area of the grid and the drain electrodeIs beneficial to reducing C gd The invention also provides a polysilicon/silicon carbide heterojunction diode and a Schottky diode which are used for reverse freewheeling, the turn-on voltage of the heterojunction diode and the Schottky diode is lower than that of the body diode, the heterojunction diode and the Schottky diode are easier to conduct when the SiC device is in a reverse state, and the reliability and the reverse performance of the SiC device are improved.

Description

SiC device with floating island structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SiC device with a floating island structure and a preparation method thereof.
Background
The third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. In addition, the silicon carbide device has higher electron saturation rate, small forward on-resistance and lower power loss, is suitable for large-current and large-power application, and reduces the requirement on heat radiation equipment. SiC has unique physical, chemical and electrical properties, and is a semiconductor material with great development potential in the extreme application fields of high temperature, high frequency, high power, radiation resistance and the like. The dielectric breakdown field strength of a power device made of silicon carbide is 10 times that of Si, the band gap is 3 times that of Si, and the impedance of a float layer of the SiC device is lower than that of the Si device, so that high withstand voltage and low impedance can be realized by a MOSFET without conducting conductivity modulation.
A gate oxide is a dielectric layer separating the gate terminal of a MOSFET (metal oxide semiconductor field effect transistor) from the underlying source and drain terminals and the conductive channels connecting the source and drain when the transistor is on. The gate oxide layer is a thin silicon dioxide insulating layer formed by thermally oxidizing the silicon of the channel. The insulating silicon dioxide layer is formed by a self-limiting oxidation process. A conductive gate material is then deposited over the gate oxide to form the transistor. The gate oxide acts as a dielectric layer so the gate can withstand a lateral electric field of up to 5 MV/cm to modulate the conductance of the channel.
The gate oxide layer has three main problems: silicon oxide has many defects in the vicinity of silicon, such as high density electron and hole traps. These traps can introduce fast interface states that cause charge instability under bias and temperature stress. The difference in thermal expansion coefficients between silicon and silicon dioxide creates tensile stress that causes more defects in the oxide layer near the silicon. It is generally believed that regions of oxide layer 100nm thick near silicon are regions with more defects, such as small spots and oxide layer pinholes caused by uneven local growth rates of the oxide layer. The defect of the gate oxide layer causes the voltage resistance of the gate oxide layer to be reduced, and the electric field intensity in the JFET region is far higher than that in other regions, so that breakdown phenomenon is more likely to occur in the gate oxide layer of the JFET region than in other regions, and the SiC device is disabled due to the fact that the gate oxide layer of the JFET region is broken down by a stronger electric field.
Disclosure of Invention
The invention aims to provide a SiC device with a floating island structure and a preparation method thereof, wherein the SiC device protects a grid oxide layer of a JFET region through a P-type floating island layer, prevents the grid oxide layer from being broken down in advance, and the P-type floating island layer can also reduce the overlapping area of a grid and a drain electrode, thereby being beneficial to reducing C gd The invention also provides a polysilicon/silicon carbide heterojunction diode and a Schottky diode which are used for reverse freewheeling, the turn-on voltage of the heterojunction diode and the Schottky diode is lower than that of the body diode, the heterojunction diode and the Schottky diode are easier to conduct when the SiC device is in a reverse state, and the reliability and the reverse performance of the SiC device are improved.
A SiC device having a floating island structure, comprising: at least one P-type floating island layer;
the P-type floating island layer is embedded into the drift layer;
the P-type floating island layers are arranged in a stacked mode.
Preferably, the drift layer includes: a first drift layer and a second drift layer;
the first drift layer is positioned between the substrate and the second drift layer and is adjacent to the substrate and the second drift layer;
the second drift layer is located above the first drift layer.
Preferably, the doping concentration of the first drift layer is smaller than the doping concentration of the second drift layer.
Preferably, the method further comprises: p+ highly doped polysilicon;
the p+ highly doped polysilicon is located between and adjacent to the source and the drift layer.
Preferably, the method further comprises: a schottky metal;
the schottky metal is located between and adjacent to the source and the drift layer.
Preferably, the width of the P-type floating island layer positioned below is smaller than that of the P-type floating island layer positioned above.
Preferably, the doping concentration of the P-type floating island layer is 10 18 cm -3 。
Preferably, the width of the P-type floating island layer is the width of the SiC deviceTo->。
Preferably, the method further comprises: a source, a gate, a drain, a substrate, a p+ region, an n+ region, and a P-body region;
the drain electrode is positioned below the substrate;
the substrate is positioned below the drift layer;
the P-body region and the P+ region are located above the drift layer;
the N+ region is located above the P-body region;
the source electrode is positioned above the N+ region and the P+ region;
the gate is located below the source.
A method for fabricating a SiC device having a floating island structure, comprising:
a drift layer with low doping concentration is extended above the substrate;
a layer of drift layer with high doping concentration is extended above the drift layer with low doping concentration and is subjected to ion implantation to form a P-type floating island layer, a P-body region, a P+ region and an N+ region;
etching the P+ region to form a polysilicon trench;
depositing polysilicon in the polysilicon trench;
depositing a grid electrode and etching the grid electrode to form a Schottky metal groove;
a schottky metal is deposited in the schottky metal trench followed by deposition of a source and drain.
The P-type floating island layer embedded and laminated in the drift layer is used for protecting the grid oxide layer of the JFET region from being broken down in advance,the P-type floating island layer can also reduce the overlapping area of the grid electrode and the drain electrode, and reduce the grid-drain capacitance (C) gd ) The invention also provides two freewheeling heterojunction diodes, namely a Schottky diode positioned below a source electrode in the middle of a grid electrode and a polycrystalline silicon/silicon carbide heterojunction diode positioned below source electrodes on two sides of the grid electrode, wherein the two heterojunction diodes can be conducted when the SiC device is in a reverse state to provide a reverse freewheeling channel.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of the structure of a SiC device of the present invention;
FIG. 2 is a schematic diagram of a process flow for preparing a SiC device according to the present invention;
fig. 3 is a schematic diagram of a process flow structure for preparing a SiC device of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The defect of the gate oxide layer causes the voltage resistance of the gate oxide layer to be reduced, and the electric field intensity in the JFET region is far higher than that in other regions, so that breakdown phenomenon is more likely to occur in the gate oxide layer of the JFET region than in other regions, and the SiC device is disabled due to the fact that the gate oxide layer of the JFET region is broken down by a stronger electric field.
The P-type floating island layer embedded and laminated in the drift layer is used for protecting the grid oxide layer of the JFET region from being broken down in advance, the P-type floating island layer reduces the overlapping area of the grid and the drain electrode, and reduces the grid-drain capacitance (C) gd ) The invention also provides two freewheeling heterojunction diodes, namely a Schottky diode positioned below a source electrode in the middle of a grid electrode and a polycrystalline silicon/silicon carbide heterojunction diode positioned below source electrodes on two sides of the grid electrode, wherein the two heterojunction diodes can be conducted when the SiC device is in a reverse state to provide a reverse freewheeling channel.
Example 1
A SiC device having a floating island structure, referring to fig. 1, comprising: at least one P-type floating island layer 2;
the P-type floating island layer 2 is embedded into the drift layer;
the floating island device (floating junction device) refers to a special power device which is embedded in a drift layer, is not directly connected with an electrode, is a region with a doping type opposite to that of the drift layer, and in the floating island device with the doping type of N-type drift layer, a floating island structure is formed by a P-type doped semiconductor. The SiC device adopts a novel voltage-withstanding structure-floating island structure, and aims to improve the restriction relation between breakdown voltage and specific on-resistance and overcome the defect of high difficulty of a super-junction manufacturing process. By introducing a plurality of floating island structures with opposite doping types into the silicon-based drift layer, the resistivity of the power device is improved and the power loss is reduced under the condition that the breakdown voltage is unchanged. The root cause is that the floating island introduces a new electric field peak in the drift layer, so that the maximum electric field peak in the drift layer is reduced, and the specific on-resistance of the device can be reduced by increasing the doping concentration of the drift layer under the condition of the same breakdown voltage. And the breakdown voltage of the power SiC device having the floating island structure increases with an increase in the number of floating islands.
The P-type floating island layer 2 is arranged in a laminated manner.
According to the invention, the voltage resistance, the gate oxide reliability and the gate drain capacitance of the SiC device are increased by arranging at least one P-type floating island, as an optimal embodiment, four P-type floating islands are arranged, the four P-type floating islands are embedded into two sides of a drift layer, two P-type floating islands are arranged on the left side, two P-type floating islands are also arranged on the right side, a plurality of P-type stacked structures are arranged on one side, the interval of the P-type floating islands is determined by the number and the thickness of the P-type floating islands, and the preparation method of the P-type floating islands comprises the following steps: when the drift layer is extended to a certain thickness, ion implantation is carried out on the upper layer of the drift layer to prepare two P-type floating islands, then a thin drift layer is extended, then ion implantation is carried out in the extended drift layer again to form a second P-type floating island layer 2, then the drift layer is manufactured by extension again above the P-type floating island layer 2, the higher the doping concentration of the P-type floating island layer 2 is, the larger the width is, the stronger the protection effect on the gate oxide layer 9 and the capability of improving the pressure resistance are, but when the P-type floating island layer 2 is manufactured, enough current paths need to be reserved, so that the doping concentration and the width of the P-type floating island layer 2 need to set the upper limit according to the performance of the SiC device.
According to the invention, the P-type floating island layers 2 with the opposite doping types to the drift layer (N-drift layer) are introduced into the drift layer of the device, so that the voltage withstand performance of the SiC device is improved under the condition that the current path of the SiC device is not influenced, the restriction relation between the breakdown voltage and the specific on resistance of the traditional SiC device is effectively improved, the P-type floating island layers 2 can also protect the grid oxide layer 9 of the JFET region, the grid oxide layer 9 is prevented from being broken down in advance, the P-type floating island can reduce the overlapping area of the grid electrode 7 and the drain electrode 12, the grid-drain capacitance is reduced, the switching loss is reduced, and the electrical performance of the SiC device is improved.
Preferably, the drift layer includes: a first drift layer 1 and a second drift layer 3;
the first drift layer 1 is located between the substrate 11 and the second drift layer 3 and is adjacent to the substrate 11 and the second drift layer 3;
the second drift layer 3 is located above the first drift layer 1.
Preferably, the doping concentration of the first drift layer 1 is smaller than the doping concentration of the second drift layer 3.
In order to enable current to normally flow from a SiC device, the doping concentration of the first drift layer 1 is set smaller than that of the second drift layer 3, when the SiC device normally works, current flows from a drain 12 to the first drift layer 1, then flows from the first drift layer 1 to the second drift layer 3 and finally flows to a source 10, and if the doping concentration of the first drift layer 1 is larger than that of the second drift layer 3, current is difficult to flow from the first drift layer 1 to the second drift layer 3, so that the electrical performance of the SiC device is reduced and the normal work of the SiC device is affected.
In comparison with the conventional drift layer with uniform doping concentration, the present invention increases the doping concentration of the second drift layer 3 in order to reduce on-resistance and increase current path, and in the present invention, the area ratio of the first drift layer 1 to the second drift layer 3 is 1:1 to 1.5: and 1, the forward performance of the SiC device is obviously improved.
Preferably, the method further comprises: p+ highly doped polysilicon 4;
the P + highly doped polysilicon 4 is located between the source 10 and the drift layer and adjoins the source 10 and the drift layer.
Polysilicon doping types are classified into P-type and N-type, + is heavily doped (high doping concentration), -is lightly doped (low doping concentration), and P-type is doped with group IIIA elements, such as: boron, aluminum, gallium, indium, thallium. N-type doping with group VA elements such As nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and permangana (Mc).
The P+ high doped polysilicon 4 is P type high doped polysilicon, the invention uses P type polysilicon and N type SiC epitaxial layer to form heterojunction, when the SiC device is in reverse state, the heterojunction is conducted, when the SiC device is in high resistance state, when the SiC device is in reverse conduction, current flows from the source electrode 10 to the P+ high doped polysilicon 4, then flows from the P+ high doped polysilicon 4 to the drift layer, flows from the drift layer to the substrate 11, and finally flows from the substrate 11 to the drain electrode 12. The starting voltage of the heterojunction diode is far lower than that of the body diode of the SiC device, and the reverse performance of the SiC device can be effectively improved.
Preferably, the method further comprises: schottky metal 8;
the schottky metal 8 is located between the source 10 and the drift layer and adjoins the source 10 and the drift layer.
The contact surface of the metal and the semiconductor is classified into two types of schottky contact and ohmic contact. Ohmic contacts are low barrier layers formed when a semiconductor with high doping concentration is contacted with a metal when the semiconductor is high in doping concentration, electrons can pass through the barrier layers by means of tunneling effect, and therefore low-resistance ohmic contacts are formed. The schottky diode is a metal-semiconductor device which is made of noble metal (gold, silver, aluminum, platinum, etc.) as a positive electrode, an N-type semiconductor as a negative electrode, and a rectifying characteristic utilizing a potential barrier formed on a contact surface of the two. Since a large number of electrons exist in the N-type semiconductor and only a very small number of free electrons exist in the noble metal, electrons diffuse from the semiconductor having a high concentration to the metal having a low concentration. Obviously, there are no holes in the metal, i.e. there is no diffusion movement of holes from the metal to the semiconductor. By adjusting the structural parameters, a Schottky barrier is formed between the N-type substrate and the anode metal. When a forward bias voltage is applied to both ends of the schottky barrier (anode metal is connected with the positive electrode of the power supply, and the N-type substrate is connected with the negative electrode of the power supply), the schottky barrier layer becomes narrower and the internal resistance thereof becomes smaller; conversely, if a reverse bias is applied to both ends of the schottky barrier, the schottky barrier layer becomes wider and its internal resistance becomes larger.
The invention uses the Schottky metal 8 and the N-type SiC epitaxial layer to form a heterojunction, the heterojunction is conducted when the SiC device is in a reverse state, the heterojunction is in a high-resistance state when the SiC device is in normal operation, when the SiC device is in reverse conduction, current flows from a source electrode 10 to the Schottky metal 8, then flows from the Schottky metal 8 to a drift layer, flows from the drift layer to a substrate 11, and finally flows from the substrate 11 to a drain electrode 12. The starting voltage of the Schottky diode is far lower than that of the body diode of the SiC device, and the reverse performance of the SiC device can be effectively improved.
Preferably, the width of the P-type floating island layer 2 located below is smaller than the width of the P-type floating island layer 2 located above.
The width of the P-type floating island layer 2 is set according to the electric field intensity distribution of the SiC device, and as a preferred embodiment, the present invention sets the width of the P-type floating island layer 2 located below to be smaller than the width of the P-type floating island layer 2 located above. The electric field lines can be better smoothed, the electric field intensity in the JFET region is reduced, and the gate oxide layer 9 is protected from being broken down in advance.
Preferably, the doping concentration of the P-type floating island layer 2 is 10 18 cm -3 。
The doping concentration of the P-type floating island layer 2 is influenced by the doping concentration of the drift layer, if the doping concentration of the drift layer is higher, the doping concentration of the P-type floating island layer 2 is correspondingly increased, the doping concentration of the P-type floating island layer 2 is also influenced by the thickness of the gate oxide layer 9, if the thickness of the gate oxide layer 9 is thinner, the voltage endurance capability is weaker, the doping concentration of the P-type floating island layer 2 is increased,but the P-type floating island layer 2 has enough current path while the doping concentration is increased, so as a preferred embodiment, the invention sets the doping concentration of the P-type floating island layer 2 to 10 18 cm -3 The grid oxide layer 9 can be better protected, the switching loss can be reduced, and the electrical performance of the SiC device is greatly improved.
Preferably, the width of the P-type floating island layer 2 is the width of the SiC deviceTo->。
The width of the P-type floating island layer 2 is too narrow, which leads to insufficient protection capability of the gate oxide layer 9, so the invention sets the minimum width of the P-type floating island layer 2 as the width of the SiC deviceThe width of the P-type floating island layer 2 if too wide will cause the current path of the SiC device to be narrowed, so the invention sets the maximum width of the P-type floating island layer 2 to +.>。
Preferably, the method further comprises: a source 10, a gate 7, a drain 12, a substrate 11, a p+ region 5, an n+ region 6, and a P-body region 13;
the drain 12 is located under the substrate 11;
drain 12 is the charge sink in the MOSFET, which is connected to the channel and is the charge sink. When the MOSFET is in an on state, a conductive path is formed between the drain 12 and the source 10, and electrons flow from the source 10 into the drain 12, completing the transfer of current. The voltage change of the drain 12 has less influence on the operation state of the MOSFET, and mainly plays a role of current inflow.
The substrate 11 is located below the drift layer;
the electric field distribution of the drift layer plays a key role in the on-characteristics and current control of the MOSFET. When a gate 7 voltage is applied to the MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source 10 and drain 12. When the MOSFET is operated, the current between the source 10 and the drain 12 is mainly transferred through the drift layer. The doping type and concentration of the drift layer determine the conduction type (N-type or P-type) and the magnitude of the current. The structure and characteristics of the drift layer directly affect the current control capability of the MOS transistor. By adjusting the shape, size and doping concentration of the drift layer, accurate control of current can be achieved, so that the requirements of different applications are met.
The P-body region 13 and the p+ region 5 are located above the drift layer;
n+ region 6 is located above P-body region 13;
source 10 is located above n+ region 6 and p+ region 5;
the source 10 is the source of charge in the MOSFET and is the outlet for the charge. When the MOSFET is in an on state, a conductive path is formed between the source 10 and the drain 12, and electrons flow from the source 10 into the drain 12, completing the transfer of current. Meanwhile, the source electrode 10 also plays a role of modulating the gate voltage, and the control of the MOSFET is realized by controlling the change of the voltage of the source electrode 10.
The gate 7 is located below the source 10.
The gate 7 is the control electrode in the MOSFET, and is separated from the channel by an insulating layer, which is a critical part of the MOSFET. The voltage variation of the gate 7 can change the charge density in the channel and thus control the magnitude of the current between the drain 12 and the source 10.
Example 2
A method for fabricating a SiC device having a floating island structure, referring to fig. 2, fig. 3, comprising:
s100, a drift layer with low doping concentration is epitaxially grown above a substrate 11;
the epitaxial process refers to a process of growing a single crystal layer in complete alignment on the substrate 11. Generally, an epitaxial process is a process of growing a layer of crystals on a monocrystalline substrate that have the same lattice orientation as the original substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, and the like. According to the different phases of the growth source, the epitaxial growth modes are divided into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During the implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, and amorphization occurs to form a surface amorphous silicon layer; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The chemical vapor phase epitaxy and Chemical Vapor Deposition (CVD) principles are basically the same, and are all processes for depositing films by utilizing chemical reaction on the surface of a wafer after gas mixing; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S200, a drift layer with high doping concentration is extended above the drift layer with low doping concentration and is subjected to ion implantation to form a P-type floating island layer 2, a P-body region 13, a P+ region 5 and an N+ region 6;
the invention adopts an ion implantation mode to form the P-type floating island layer 2, the P+ region 5 and the N+ region 6. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The "mass" selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocked aperture or "slit" which allows only ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S300, etching the P+ region 5 to form a polysilicon trench;
the invention etches the two sides of the P+ region 5 to form a polysilicon trench. Etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gas and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is an absolute chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor. So that the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S400, depositing polysilicon in the polysilicon trench;
polysilicon deposition forms gate electrodes and local interconnects on the silicide stack on the first layer of polysilicon (Poly 1) and the second layer of polysilicon (Poly 2) forms contact plugs between the source 10/drain 12 and the cell interconnect. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) process by depositing arsenic trioxide (AH) in a reaction chamber (i.e., in a furnace tube) 3 ) Phosphorus trihydride (PH) 3 ) Or diborane (B) 2 H 6 ) The doping gas of the silicon material is directly input into the silicon material gas of silane or DCS, so that the polysilicon doping process of the in-situ low-pressure chemical vapor deposition can be performed. Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rate of both deposition processes is between 100-200 a/min, which is determined primarily by the temperature at which the deposition is performed.
S500, depositing a grid electrode 7 and etching the grid electrode 7 to form a schottky metal 8 groove;
in the embodiment of the invention, the schottky metal 8 trench is etched away from the middle of the gate electrode 7, and then the schottky metal 8 is deposited in the schottky metal 8 trench, the position of the schottky metal 8 trench is not limited, and only the schottky metal 8 is deposited between the source electrode 10 and the drift layer (N-drift layer), so that after the schottky metal 8 is deposited, the current can flow from the source electrode 10 to the schottky metal 8 and then to the drift layer.
S600, depositing the schottky metal 8 in the schottky metal 8 trench and then depositing the source 10 and drain 12.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl into a reaction chamber at 850-1100 DEG C 4 ，H 2 ，CH 4 And forming a coating layer on the surface of the substrate through chemical reaction of the gases.
The P-type floating island layer 2 embedded and laminated in the drift layer is used for protecting the grid oxide layer 9 of the JFET region from being broken down in advance, the P-type floating island layer 2 can also reduce the overlapping area of the grid electrode 7 and the drain electrode 12, and the grid-drain capacitance (C) gd ) The invention also provides two freewheeling heterojunction diodes, namely Schottky diode under the middle source electrode 10 of the grid electrode 7The gate tube and the polysilicon/silicon carbide heterojunction diode positioned below the source electrode 10 at two sides of the gate electrode 7 can be conducted when the SiC device is in a reverse state, and a reverse freewheel channel is provided.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A SiC device having a floating island structure, comprising: at least one P-type floating island layer;
the P-type floating island layer is embedded into the drift layer;
the P-type floating island layers are arranged in a stacked mode.
2. A SiC device having a floating island structure according to claim 1, characterized in that the drift layer comprises: a first drift layer and a second drift layer;
the first drift layer is positioned between the substrate and the second drift layer and is adjacent to the substrate and the second drift layer;
the second drift layer is located above the first drift layer.
3. The SiC device of claim 2 wherein the doping concentration of the first drift layer is less than the doping concentration of the second drift layer.
4. A SiC device having a floating island structure according to claim 1, further comprising: p+ highly doped polysilicon;
the p+ highly doped polysilicon is located between and adjacent to the source and the drift layer.
5. A SiC device having a floating island structure according to claim 1, further comprising: a schottky metal;
the schottky metal is located between and adjacent to the source and the drift layer.
6. The SiC device of claim 1 wherein the width of the underlying P-type floating island layer is less than the width of the overlying P-type floating island layer.
7. The SiC device of claim 1 wherein the P-type floating island layer has a doping concentration of 10 18 cm -3 。
8. The SiC device of claim 1 wherein the P-type floating island layer has a width that is the width of the SiC deviceTo->。
9. A SiC device having a floating island structure according to claim 1, further comprising: a source, a gate, a drain, a substrate, a p+ region, an n+ region, and a P-body region;
the drain electrode is positioned below the substrate;
the substrate is positioned below the drift layer;
the P-body region and the P+ region are located above the drift layer;
the N+ region is located above the P-body region;
the source electrode is positioned above the N+ region and the P+ region;
the gate is located below the source.
10. A method for manufacturing a SiC device having a floating island structure, comprising:
a drift layer with low doping concentration is extended above the substrate;
a layer of drift layer with high doping concentration is extended above the drift layer with low doping concentration and is subjected to ion implantation to form a P-type floating island layer, a P-body region, a P+ region and an N+ region;
etching the P+ region to form a polysilicon trench;
depositing polysilicon in the polysilicon trench;
depositing a grid electrode and etching the grid electrode to form a Schottky metal groove;
and depositing a source electrode and a drain electrode after depositing the Schottky metal in the Schottky metal groove.
CN202311506101.1A 2023-11-13 2023-11-13 SiC device with floating island structure and preparation method thereof Pending CN117253905A (en)

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