CN117238914B - A SiC device with integrated SBD and preparation method thereof - Google Patents
A SiC device with integrated SBD and preparation method thereof Download PDFInfo
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Abstract
本发明提供一种集成SBD的SiC器件及制备方法，该SiC器件包括：集成SBD；所述集成SBD由肖特基金属和漂移层组成；所述肖特基金属位于源极与漂移层之间并与所述源极和所述漂移层邻接；所述漂移层位于衬底上方并与衬底邻接。在源极与漂移层之间集成了肖特基二极管，肖特基二极管的开启电压远低于体二极管，当SiC器件处于反向状态时能够更早于体二极管导通，为反向续流提供导通路径，保护SiC器件不被过大的反向电流损坏，还增加了P型浮岛层用于保护栅极氧化层和降低开关损耗，显著提升了SiC器件的电气性能。
The present invention provides a SiC device with an integrated SBD and a preparation method, the SiC device comprising: an integrated SBD; the integrated SBD is composed of a Schottky metal and a drift layer; the Schottky metal is located between a source and a drift layer and is adjacent to the source and the drift layer; the drift layer is located above a substrate and is adjacent to the substrate. A Schottky diode is integrated between the source and the drift layer, the turn-on voltage of the Schottky diode is much lower than that of the body diode, and when the SiC device is in a reverse state, it can be turned on earlier than the body diode, providing a conduction path for reverse freewheeling, protecting the SiC device from being damaged by excessive reverse current, and adding a P-type floating island layer to protect the gate oxide layer and reduce switching losses, significantly improving the electrical performance of the SiC device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an SBD integrated SiC device and a preparation method thereof.
Background
The third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. In addition, the silicon carbide device has higher electron saturation rate, small forward on-resistance and lower power loss, is suitable for large-current and large-power application, and reduces the requirement on heat radiation equipment. SiC has unique physical, chemical and electrical properties, and is a semiconductor material with great development potential in the extreme application fields of high temperature, high frequency, high power, radiation resistance and the like. The dielectric breakdown field strength of a power device made of silicon carbide is 10 times that of Si, the band gap is 3 times that of Si, and the impedance of a float layer of the SiC device is lower than that of the Si device, so that high withstand voltage and low impedance can be realized by a MOSFET without conducting conductivity modulation.
MOS field effect transistor power devices fabricated using silicon carbide materials can withstand higher voltages and faster switching speeds than Si devices. For conventional Si MOS, the body diode turn-on voltage is only around 0.7V, and is therefore commonly used as a freewheel channel under reverse bias of the MOSFET. However, due to wider forbidden band, the SiC material causes the over-high turn-on voltage (2.7-3.0V) of the body diode of the SiC MOSFET, and the SiC material is difficult to play a role in protecting the MOSFET under reverse bias.
Disclosure of Invention
The invention aims to provide an SBD integrated SiC device and a preparation method thereof, wherein a Schottky diode is integrated between a source electrode and a drift layer, the starting voltage of the Schottky diode is far lower than that of a body diode, the Schottky diode can be conducted earlier than the body diode when the SiC device is in a reverse state, a conduction path is provided for reverse freewheels, the SiC device is protected from being damaged by excessive reverse current, a P-type floating island layer is additionally arranged for protecting a grid oxide layer and reducing switching loss, and the electrical performance of the SiC device is remarkably improved.
An SBD integrated SiC device comprising: integrating SBD;
the integrated SBD consists of a Schottky metal and a drift layer;
the schottky metal is positioned between the source electrode and the drift layer and is adjacent to the source electrode and the drift layer;
the drift layer is located over and adjacent to the substrate.
Preferably, the drift layer includes: a first drift layer and a second drift layer;
the first drift layer is positioned between the substrate and the second drift layer and is adjacent to the substrate and the second drift layer;
the second drift layer is located above the first drift layer.
Preferably, the doping concentration of the first drift layer is smaller than the doping concentration of the second drift layer.
Preferably, the method further comprises: a P-type floating island layer;
the P-type floating island layer is embedded into the drift layer;
The P-type floating island layers are arranged in a stacked mode.
Preferably, the width of the P-type floating island layer positioned below is smaller than that of the P-type floating island layer positioned above.
Preferably, the doping concentration of the first drift layer is 10 16cm-3.
Preferably, the doping concentration of the second drift layer is 10 17cm-3.
Preferably, the doping concentration of the P-type floating island layer is 10 18cm-3.
Preferably, the width of the P-type floating island layer is the width of the SiC deviceTo the point of。
A method of fabricating an SBD integrated SiC device comprising:
A drift layer with low doping concentration is extended above the substrate;
a drift layer with high doping concentration is extended above the drift layer with low doping concentration and is subjected to ion implantation to form a P-type floating island layer, a P-body layer, a P+ region and an N+ region;
Etching the P+ region to form a groove;
depositing a gate and etching the gate to form a trench;
the source and drain are deposited after the schottky metal is deposited in the trench.
According to the invention, the Schottky diode is arranged below the source electrode for reverse freewheeling, when the SiC device works normally, the Schottky diode is in a high-resistance state and is not conducted, when the SiC device is connected with reverse voltage, the Schottky diode is turned on to provide a freewheeling channel, so that current can flow from the source electrode to the Schottky metal, then flow from the Schottky metal to the drift layer, and flow from the drift layer to the substrate and finally flow to the drain electrode.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of the structure of a SiC device of the present invention;
FIG. 2 is a schematic diagram of a process flow for preparing a SiC device according to the present invention;
Fig. 3 is a schematic diagram of a process flow structure for preparing a SiC device of the present invention.
Reference numerals illustrate:
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
MOS field effect transistor power devices fabricated using silicon carbide materials can withstand higher voltages and faster switching speeds than Si devices. For conventional Si MOS, the body diode turn-on voltage is only around 0.7V, and is therefore commonly used as a freewheel channel under reverse bias of the MOSFET. However, due to wider forbidden band, the SiC material causes the over-high turn-on voltage (2.7-3.0V) of the body diode of the SiC MOSFET, and the SiC material is difficult to play a role in protecting the MOSFET under reverse bias.
According to the invention, the Schottky diode is arranged below the source electrode for reverse freewheeling, when the SiC device works normally, the Schottky diode is in a high-resistance state and is not conducted, when the SiC device is connected with reverse voltage, the Schottky diode is turned on to provide a freewheeling channel, so that current can flow from the source electrode to the Schottky metal, then flow from the Schottky metal to the drift layer, and flow from the drift layer to the substrate and finally flow to the drain electrode.
Example 1
An SBD integrated SiC device, referring to fig. 1, comprising: integrating SBD;
The integrated SBD consists of a Schottky metal 4 and a drift layer;
The contact surface of the metal and the semiconductor is classified into two types of schottky contact and ohmic contact. Ohmic contacts are low barrier layers formed when a semiconductor with high doping concentration is contacted with a metal when the semiconductor is high in doping concentration, electrons can pass through the barrier layers by means of tunneling effect, and therefore low-resistance ohmic contacts are formed. The schottky diode is a metal-semiconductor device which is made of noble metal (gold, silver, aluminum, platinum, etc.) as a positive electrode, an N-type semiconductor as a negative electrode, and a rectifying characteristic utilizing a potential barrier formed on a contact surface of the two. Since a large number of electrons exist in the N-type semiconductor and only a very small number of free electrons exist in the noble metal, electrons diffuse from the semiconductor having a high concentration to the metal having a low concentration. Obviously, there are no holes in the metal, i.e. there is no diffusion movement of holes from the metal to the semiconductor. By adjusting the structural parameters, a Schottky barrier is formed between the N-type substrate and the anode metal. When a forward bias voltage is applied to both ends of the schottky barrier (anode metal is connected with the positive electrode of the power supply, and the N-type substrate is connected with the negative electrode of the power supply), the schottky barrier layer becomes narrower and the internal resistance thereof becomes smaller; conversely, if a reverse bias is applied to both ends of the schottky barrier, the schottky barrier layer becomes wider and its internal resistance becomes larger.
The invention uses the Schottky metal 4 and the N-type SiC epitaxial layer to form a heterojunction, the heterojunction is conducted when the SiC device is in a reverse state, the heterojunction is in a high-resistance state when the SiC device is in normal operation, when the SiC device is in reverse conduction, current flows from the source electrode 10 to the Schottky metal 4, then flows from the Schottky metal 4 to the drift layer, flows from the drift layer to the substrate 12, and finally flows from the substrate 12 to the drain electrode 11. The starting voltage of the Schottky diode is far lower than that of the body diode of the SiC device, and the reverse performance of the SiC device can be effectively improved.
The schottky metal 4 is located between the source 10 and the drift layer and adjoins the source 10 and the drift layer;
Schottky diode comprising schottky metal 4 and N-type SiC epitaxial layer is used to provide a reverse freewheeling channel as a preferred embodiment the schottky metal 4 of the present invention is disposed between the source 10 and the drift layer and adjacent to the source 10 and drift layer, and when the source 10 is connected to a high potential (positive) drain 11 and the drain 11 is connected to a low potential (negative), current can flow from the source 10 through the schottky diode and then to the drain 11.
The drift layer is located above the substrate 12 and is contiguous with the substrate 12.
The electric field distribution of the drift layer plays a key role in the on-characteristics and current control of the MOSFET. When a gate voltage is applied to the MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source 10 and the drain 11. When the MOSFET is operated, the current between the source 10 and the drain 11 is mainly transferred through the drift layer. The doping type and concentration of the drift layer determine the conduction type (N-type or P-type) and the magnitude of the current. The structure and characteristics of the drift layer directly affect the current control capability of the MOS transistor. By adjusting the shape, size and doping concentration of the drift layer, accurate control of current can be achieved, so that the requirements of different applications are met.
Preferably, the drift layer includes: a first drift layer 1 and a second drift layer 3;
The first drift layer 1 is located between the substrate 12 and the second drift layer 3 and adjoins the substrate 12 and the second drift layer 3;
The second drift layer 3 is located above the first drift layer 1.
Preferably, the doping concentration of the first drift layer 1 is smaller than the doping concentration of the second drift layer 3.
In order to enable current to normally flow from a SiC device, the doping concentration of the first drift layer 1 is set smaller than that of the second drift layer 3, when the SiC device normally works, current flows from a drain electrode 11 to the first drift layer 1, then flows from the first drift layer 1 to the second drift layer 3 and finally flows to a source electrode 10, and if the doping concentration of the first drift layer 1 is larger than that of the second drift layer 3, current is difficult to flow from the first drift layer 1 to the second drift layer 3, so that the electrical performance of the SiC device is reduced and the normal work of the SiC device is influenced.
Compared with the conventional drift layer with uniform doping concentration, the invention increases the doping concentration of the second drift layer 3, so as to reduce on-resistance and increase current path, and in the invention, the area ratio of the first drift layer 1 to the second drift layer 3 is 1:1 to 1.5:1, if the area ratio of the first drift layer 1 and the second drift layer 3 differs too much, it may cause a shortage of forward withstand voltage capability of the SiC device, and if the second drift layer 3 occupies a relatively small area, the improvement effect on-resistance may be impaired, and as a preferred embodiment, the present invention sets the area ratio of the first drift layer 1 to the second drift layer 3 to 1: and 1, the forward performance of the SiC device is obviously improved.
Preferably, the method further comprises: a P-type floating island layer 2;
the P-type floating island layer 2 is embedded into the drift layer;
The floating island device (floating junction device) refers to a special power device which is embedded in a drift layer, is not directly connected with an electrode, is a region with a doping type opposite to that of the drift layer, and in the floating island device with the doping type of N-type drift layer, a floating island structure is formed by a P-type doped semiconductor. The SiC device adopts a novel voltage-withstanding structure-floating island structure, and aims to improve the restriction relation between breakdown voltage and specific on-resistance and overcome the defect of high difficulty of a super-junction manufacturing process. By introducing a plurality of floating island structures with opposite doping types into the silicon-based drift layer, the resistivity of the power device is improved and the power loss is reduced under the condition that the breakdown voltage is unchanged. The root cause is that the floating island introduces a new electric field peak in the drift layer, so that the maximum electric field peak in the drift layer is reduced, and the specific on-resistance of the device can be reduced by increasing the doping concentration of the drift layer under the condition of the same breakdown voltage. And the breakdown voltage of the power SiC device having the floating island structure increases with an increase in the number of floating islands.
The P-type floating island layer 2 is arranged in a laminated manner.
According to the invention, the voltage resistance, the gate oxide reliability and the gate drain capacitance of the SiC device are increased by arranging at least one P-type floating island, as an optimal embodiment, four P-type floating islands are arranged, the four P-type floating islands are embedded into two sides of a drift layer, two P-type floating islands are arranged on the left side, two P-type floating islands are also arranged on the right side, a plurality of P-type stacked structures are arranged on one side, the interval of the P-type floating islands is determined by the number and the thickness of the P-type floating islands, and the preparation method of the P-type floating islands comprises the following steps: when the drift layer is extended to a certain thickness, ion implantation is carried out on the upper layer of the drift layer to prepare two P-type floating islands, then a thin drift layer is extended, then ion implantation is carried out in the extended drift layer again to form a second P-type floating island layer 2, then the drift layer is manufactured by extension again above the P-type floating island layer 2, the higher the doping concentration of the P-type floating island layer 2 is, the larger the width is, the stronger the protection effect on the gate oxide layer 8 and the capability of improving the pressure resistance are, but when the P-type floating island layer 2 is manufactured, enough current paths need to be reserved, so that the doping concentration and the width of the P-type floating island layer 2 need to set the upper limit according to the performance of the SiC device.
According to the invention, the P-type floating island layers 2 with the opposite doping types to the drift layer (N-drift layer) are introduced into the drift layer of the device, so that the voltage withstand performance of the SiC device is improved under the condition that the current path of the SiC device is not influenced, the restriction relation between the breakdown voltage and the specific on resistance of the traditional SiC device is effectively improved, the P-type floating island layers 2 can also protect the grid oxide layer 8 of the JFET region, the grid oxide layer 8 is prevented from being broken down in advance, the P-type floating island can reduce the overlapping area of the grid electrode 7 and the drain electrode 11, the grid-drain capacitance is reduced, the switching loss is reduced, and the electrical performance of the SiC device is improved.
Preferably, the width of the P-type floating island layer 2 located below is smaller than the width of the P-type floating island layer 2 located above.
The width of the P-type floating island layer 2 is set according to the electric field intensity distribution of the SiC device, and as a preferred embodiment, the present invention sets the width of the P-type floating island layer 2 located below to be smaller than the width of the P-type floating island layer 2 located above. The electric field lines can be better smoothed, the electric field intensity in the JFET region is reduced, and the gate oxide layer 8 is protected from being broken down in advance.
Preferably, the doping concentration of the first drift layer 1 is 10 16cm-3.
Preferably, the doping concentration of the second drift layer 3 is 10 17cm-3.
In the SiC device, an appropriate increase in the doping concentration of the drift layer can reduce the on-resistance, so that the second drift layer 3 is appropriately increased in doping concentration in order to enable the SiC device to operate normally while reducing the on-resistance, so that the on-resistance of the SiC device is significantly reduced, and as a preferred embodiment, the first drift layer 1 is set to 10 16cm-3 and the second drift layer 3 is set to 10 17cm-3.
Preferably, the doping concentration of the P-type floating island layer 2 is 10 18cm-3.
Because the P-type floating island is in charge balance with the drift layer, the doping concentration of the P-type floating island layer 2 is influenced by the doping concentration of the drift layer, in the state that the SiC device is in the opposite direction, the P-type floating island layer 2 and the drift layer are mutually depleted, if the doping concentration of the drift layer is higher, the doping concentration of the P-type floating island layer 2 is correspondingly increased, if the doping concentration of the drift layer is too low, the effect of reducing the on-resistance of the SiC device cannot be achieved, and the doping concentration of the P-type floating island layer 2 is also influenced by the thickness of the gate oxide layer 8, if the thickness of the gate oxide layer 8 is thinner, the doping concentration of the P-type floating island layer 2 is increased, the higher the doping concentration of the P-type floating island layer 2 is, the higher the improvement capability of the electric field line distribution is, and the protection capability of the gate oxide layer 8 is also better, but the P-type floating island layer 2 is provided with enough current paths while the doping concentration is increased, so that as a preferable embodiment, the P-type floating island 2 is set to be 10 18cm-3, the gate oxide layer 8 can be better protected, and the electrical loss of the SiC device can be greatly reduced.
Preferably, the width of the P-type floating island layer 2 is the width of the SiC deviceTo the point of。
The width of the P-type floating island layer 2 also affects the protection capability of the gate oxide layer 8 and the current path, the wider the width of the P-type floating island layer 2 is, the stronger the protection capability of the gate oxide layer 8 is, and the smaller the current path is, and the narrower the width of the P-type floating island layer 2 is, the less the protection capability of the gate oxide layer 8 is, so the invention sets the minimum width of the P-type floating island layer 2 as the width of the SiC deviceThe width of the P-type floating island layer 2 if too wide will cause the current path of the SiC device to be narrowed, so the present invention sets the width of the P-type floating island layer 2 to be at maximum the width of the SiC device. In this interval, the P-type floating island layer 2 can better protect the gate oxide layer 8 while leaving a sufficient current path.
Example 2
A method of fabricating an SBD integrated SiC device, referring to fig. 2,3, comprising:
S100, a drift layer (a first drift layer 1) with low doping concentration is epitaxially grown on the substrate 12;
The epitaxial process refers to a process of growing a fully ordered single crystal layer on the substrate 12. Generally, an epitaxial process is a process of growing a layer of crystals on a monocrystalline substrate that have the same lattice orientation as the original substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, and the like. According to the different phases of the growth source, the epitaxial growth modes are divided into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During ion implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, amorphization occurs, and a surface amorphous silicon layer is formed; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The chemical vapor phase epitaxy and Chemical Vapor Deposition (CVD) principles are basically the same, and are all processes for depositing films by utilizing chemical reaction on the surface of a wafer after gas mixing; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S200, a drift layer with high doping concentration is extended above the drift layer with low doping concentration and is subjected to ion implantation to form a P-type floating island layer 2, a P-body layer 9, a P+ region 5 and an N+ region 6;
The invention adopts an ion implantation mode to form the P-type floating island layer 2, the P+ region 5 and the N+ region 6. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The "mass" selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocked aperture or "slit" which allows only ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S300, etching the P+ region 5 to form a groove;
The invention etches the two sides of the P+ region 5 to form a polysilicon trench. Etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gases and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is an absolute chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor. So that the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S400, depositing a grid electrode 7 and etching the grid electrode 7 to form a groove;
The step of depositing the grid electrode 7 is as follows: the formation of the gate oxide layer 8 and the deposition of polysilicon. The invention adopts wet oxidation or dry oxidation to deposit an oxide layer, and the thermal oxidation process can be divided into dry oxidation and wet oxidation according to different oxidants in oxidation reaction, wherein the former uses pure oxygen to generate a silicon dioxide layer, the speed is low, but the oxide layer is thin and compact, and the latter needs to use oxygen and high-solubility water vapor at the same time, and the invention is characterized by high growth speed, relatively thicker protective layer and lower density. Wet oxidation has two main steps: mass transfer of oxygen in air from the gas phase to the liquid phase; chemical reaction between dissolved oxygen and the substrate. If the mass transfer process affects the overall reaction rate, it can be eliminated by enhancing agitation. In the embodiment of the invention, the rate of forming the oxide layer of the source electrode 10 by wet oxygen oxidation can be controlled by controlling the temperature, the pressure and the concentration of the reaction gas during the wet oxygen oxidation, so that the purpose of controlling the thickness of the oxide layer of the source electrode 10 is achieved.
The dry oxidation adopts a mode of directly reacting high-temperature pure oxygen with the wafer. The dry oxidation uses only pure oxygen (O 2), so the oxide film has a slow growth rate, is mainly used for forming a thin film, and can form an oxide with good conductivity. The dry oxidation has the advantages that no byproduct (H 2) is generated, and the uniformity and density of the oxide film are high.
Polysilicon deposition is to form gate electrodes and local interconnects on the silicide stack on the first layer of polysilicon (Poly 1) and the second layer of polysilicon (Poly 2) forms contact plugs between the source 10/drain 11 and the cell interconnect. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) that can be performed in situ by directly introducing a dopant gas of arsine (AH 3), phosphine (PH 3), or diborane (B 2H6) into the silicon material gas of silane or DCS in a reaction chamber (i.e., in a furnace). Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rate of both deposition processes is between 100-200 a/min, which is determined primarily by the temperature at which the deposition is performed.
S500, depositing the schottky metal 4 in the trench and then depositing the source 10 and drain 11.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl 4,H2,CH4 and other gases into a reaction chamber at 850-1100 ℃ and forming a coating on the surface of a substrate through chemical reaction.
The invention sets up the schottky diode under source 10 for reverse freewheeling, when the SiC device works normally, the schottky diode is in the high-resistance state and is not conducted, when the SiC device connects the reverse voltage, the schottky diode is turned on, offer the freewheeling channel, enable electric current to flow from source 10 to schottky metal 4, then flow from schottky metal 4 to drift layer, flow from drift layer to substrate 12 and finally flow to drain 11, because silicon carbide material forbidden bandwidth, the body diode turn-on voltage is very high, difficult to protect the SiC device in reverse freewheeling, so the invention adopts the schottky diode to protect the SiC device, the turn-on voltage of the schottky diode is far lower than the body diode, can provide sufficient current path when the SiC device reverses, has improved the security and stability of the SiC device.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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