CN117423730A - sJ SiC VDMOS with split gate and preparation method thereof - Google Patents

Abstract

The invention provides an SJ SiC VDMOS with split gates and a preparation method thereof, wherein the SJ SiC VDMOS comprises the following components: a silicon layer and split gates; the silicon layer includes: a first body region, an n+ region, a p+ region, and a first N pillar; the silicon layer is positioned between the silicon carbide layer and the source electrode and the grid electrode oxide layer and is adjacent to the source electrode and the grid electrode oxide layer; the split gate is located on the side of the gate and is covered by the gate oxide layer. According to the invention, the silicon material is deposited above the N column made of the silicon carbide material, so that the channel is prepared in the silicon material, and the channel has higher channel mobility in the silicon material because the channel mobility of silicon is higher than that of silicon carbide, and the SJ SiC VDMOS device also has high breakdown voltage caused by the silicon carbide material, and the split gate structure can reduce the relative area of a gate and a drain electrode, and reduce the gate-drain capacitance, so that the switching frequency of the SJ SiC MOS is improved.

Description

A SJ SiC VDMOS with split gate and preparation method

Technical field

The invention relates to the field of semiconductor technology, and in particular to a SJ SiC VDMOS with a split gate and a preparation method.

Background technique

The third generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturation electron migration rate, stable physical and chemical properties, etc., and can be applied to high temperature, high frequency, high power and extreme environments. Silicon carbide has a larger bandgap and higher critical breakdown field strength. Compared with silicon power devices under the same conditions, the voltage resistance of silicon carbide devices is about 10 times that of silicon materials.

Channel mobility is one of the important parameters of SiC MOSFET. Channel mobility refers to the migration speed of electrons or holes in the channel under the action of an electric field. In MOSFETs, channel mobility determines the efficiency and speed of current transfer. The higher the channel mobility, the faster electrons or holes migrate in the channel, and the better the conductive performance of the device. Factors that affect channel mobility include: the characteristics of silicon carbide materials. Silicon carbide materials have higher electron mobility and saturation drift speed, which makes SiC MOSFET have higher channel mobility. In comparison, traditional silicon-based materials have low mobility, limiting device performance. Channel structure and size Channel structure and size also have an important impact on channel mobility. Shorter channel length and smaller channel width can reduce the scattering of current in the channel, thereby improving channel mobility. Surface state and interface state, surface state and interface state refer to the channel surface and the charge state between the channel and the insulating layer. These charge states affect the migration speed of electrons or holes in the channel, thereby affecting channel mobility. By optimizing materials and processes, the influence of surface states and interface states can be reduced and channel mobility improved.

There are currently several methods for optimizing channel mobility: optimizing materials and selecting silicon carbide materials with higher channel mobility, such as 4H-SiC or 6H-SiC, which can improve device performance. Optimizing the structure and size, by reducing the channel length and channel width, can reduce the scattering of current in the channel and improve channel mobility. Optimize the process. By optimizing the process and reducing the influence of surface states and interface states, the channel mobility can be improved. Lower the temperature. When using SiCMOSFET in a high-temperature environment, you can take heat dissipation measures or lower the operating temperature to reduce the impact of temperature on channel mobility. However, the improvement of channel mobility by the above methods still cannot meet the current industrial production needs.

Contents of the invention

The purpose of the present invention is to provide a SJ SiC VDMOS with a split gate and a preparation method. The SJ SiCVDMOS deposits silicon material above the N pillar made of silicon carbide material, so that the channel is prepared in the silicon material. Due to the silicon channel The mobility is higher than that of silicon carbide, so the channel has a higher channel mobility in silicon materials. SJ SiC VDMOS devices also have high breakdown voltages brought by silicon carbide materials. Setting up a split gate structure can reduce the gate The relative area of the electrode and drain reduces the gate-to-drain capacitance, thereby increasing the switching frequency of SJ SiC MOS.

A SJ SiC VDMOS with a split gate, including: a silicon layer and a split gate;

The silicon layer includes: a first body region, an N+ region, a P+ region and a first N pillar;

The silicon layer is located between the silicon carbide layer and the source and gate oxide layers, and is adjacent to the source and gate oxide layers;

The split gate is located on the side of the gate and is covered by a gate oxide layer.

Preferably, it also includes: an electron tunneling layer;

The electron tunneling layer is located under the silicon layer and adjacent to the silicon layer.

Preferably, the first body region includes a first extension portion located below the source electrode and adjacent to the source electrode, and a second extension portion located below the N+ region and the P+ region and adjacent to the N+ region and the P+ region.

Preferably, it also includes: a silicon carbide layer;

The silicon carbide layer includes: a second body region, a second N pillar and a substrate;

The second body region is located between the first body region and the second N-pillar and adjacent to the first body region and the second N-pillar;

The silicon carbide layer is located between the drain electrode and the silicon layer and adjacent to the silicon layer and the drain electrode.

Preferably, the doping concentration of the electron tunneling layer is 10 ¹⁹ cm ^-3 .

Preferably, the thickness of the first N pillar is equal to the thickness of the silicon layer;

The thickness of the first N pillar is 0.1um.

Preferably, the thickness of the silicon carbide layer is 12um.

Preferably, it also includes: source electrode, drain electrode, gate electrode, substrate, P pillar, N+ region and P+ region;

The drain electrode is located under the substrate;

The substrate is located under the P pillar and the second N pillar;

The source electrode is located above the silicon layer;

The P+ region is located below the source;

The N+ region is located under the gate and source;

The gate electrode is located between the source electrode and the silicon layer.

A method for preparing SJ SiC VDMOS with split gate, including:

Epitaxially grow a silicon carbide layer over the substrate and ion-implant to form a P pillar, a second body region and a second N pillar;

epitaxially growing a silicon layer over the silicon carbide layer;

Implanting ions into the silicon layer forms a first body region, a P+ region and an N+ region;

Deposit source, drain, gate and split gate.

Preferably, the step of epitaxially growing a silicon carbide layer over the substrate and ion implanting to form a P pillar, a second body region and a second N pillar further includes: forming an electron tunneling layer by ion implantation on the silicon carbide layer.

The present invention takes advantage of the fact that silicon material has a higher channel mobility than silicon carbide material, and replaces part of the silicon carbide layer of planar SiCVDMOS with a silicon layer, so that the channel falls into the silicon material, thereby improving the channel mobility of planar SiC VDMOS. Mobility: Since the Si/SiC heterojunction has a high potential barrier, it is difficult for electrons to cross the barrier. Therefore, the present invention adds an electron tunneling layer between the silicon layer and the silicon carbide layer so that electrons can pass through more easily. Si/SiC interface, thereby reducing the heterojunction resistance, increasing the on-current, significantly improving the electrical performance of SJ SiC VDMOS, and also introducing a split gate structure. The split gate can reduce the relative area of the gate and drain, This reduces the capacitance between the gate and drain and increases the switching frequency of SJ SiCMOS.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings needed to describe the embodiments or the prior art. Obviously, for those of ordinary skill in the art, It is said that other drawings can be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic structural diagram of the SJ SiC VDMOS of the present invention;

Figure 2 is a schematic diagram of the SJ SiC VDMOS preparation process method of the present invention;

Figure 3 is a schematic structural diagram of the SJ SiC VDMOS preparation process of the present invention.

Explanation of reference symbols:

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiment of the present invention are only used to explain the relationship between components in a specific posture (as shown in the drawings). Relative positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

In addition, descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor within the protection scope required by the present invention.

There are currently several methods for optimizing silicon carbide-based channel mobility: optimizing materials and selecting silicon carbide materials with higher channel mobility, such as 4H-SiC or 6H-SiC, which can improve device performance. Optimizing the structure and size, by reducing the channel length and channel width, can reduce the scattering of current in the channel and improve channel mobility. Optimize the process. By optimizing the process and reducing the influence of surface states and interface states, the channel mobility can be improved. Lower the temperature. When using SiC MOSFET in a high-temperature environment, you can take heat dissipation measures or lower the operating temperature to reduce the impact of temperature on channel mobility. However, the costs of the above methods are relatively high, and the improvement in channel mobility still cannot meet the current industrial production needs.

The present invention takes advantage of the fact that silicon material has a higher channel mobility than silicon carbide material, and replaces part of the silicon carbide layer of SiC VDMOS with a silicon layer, so that the channel falls into the silicon material, thereby improving the channel migration of SiC VDMOS. Since the Si/SiC heterojunction has a high potential barrier and it is difficult for electrons to cross the barrier, the present invention adds an electron tunneling layer between the silicon layer and the silicon carbide layer so that electrons can more easily pass through the Si /SiC interface, thereby reducing the heterojunction resistance, increasing the on-current, and significantly improving the electrical performance of SiC VDMOS.

A SJ SiC VDMOS with a split gate, including: a silicon layer and a split gate 13;

The silicon layer includes: a first body region 14, an N+ region 6, a P+ region 3 and a first N pillar 10;

MOSFET can be divided into planar gate 5MOSFET and superjunction MOSFET according to the manufacturing process. The disadvantage of planar structure transistors is that if the rated voltage is increased, the drift layer will become thicker, so the on-resistance will increase. The rated voltage of a MOSFET depends on the width of the vertical drift region and the doping parameters. In order to increase the rated voltage level, the width of the drift region is usually increased and the doping concentration is reduced, but this will cause a significant increase in the on-resistance of the MOSFET. In order to solve the problem of increased on-resistance as the rated voltage increases, the super-junction structure MOSFET has a structure in which multiple vertical PN junctions are arranged at the drain 12 and source 9. As a result, low on-resistance is achieved while maintaining high voltage. The existence of super junction greatly breaks through the theoretical limit of silicon, and the higher the rated voltage, the more obvious the decrease in on-resistance.

MOSFETs are usually made of silicon or silicon carbide. Silicon materials have high thermal stability and electrical properties, which make silicon MOSFET devices have high reliability and long-term stability during operation. Silicon MOSFETs are suitable for analog circuits. In various application fields such as digital circuits and mixed signals, the third-generation semiconductor material silicon carbide has a larger band gap and can withstand higher temperatures and higher voltages. It is suitable for high-temperature, high-frequency, high-voltage, and high-power circuits. However, the channel mobility of silicon carbide MOSFET is one order of magnitude lower than that of silicon MOSFET. In order to improve the channel mobility of silicon carbide MOSFET, the present invention adds a silicon layer to the traditional silicon carbide MOSFET and prepares the channel. In the silicon layer, the silicon carbide MOSFET also has the high mobility of the silicon MOSFET, and because part of the material of the first N pillar 10 is silicon carbide, it also has the high breakdown voltage characteristics of the silicon carbide MOSFET.

The silicon layer is located between the silicon carbide layer, the source electrode 9 and the gate oxide layer 4, and is adjacent to the source electrode 9 and the gate oxide layer 4;

Placing the silicon layer between the silicon carbide layer, the source electrode 9 and the gate oxide layer 4 can make the channel completely fall into the silicon layer, thereby improving the channel mobility of SJ SiC VDMOS.

The split gate 13 is located on the side of the gate 5 and is covered by the gate oxide layer 4 .

The split gate 13 is to split the traditional gate into two. The split gate is the split gate 13, and the original gate is the control gate. The split gate 13 will not affect the normal operation of the control gate. , when the SJ SiC VDMOS is turned off in the forward direction, the charges near the gate 5 are evenly distributed, so no concentrated electric field is generated. However, since the JFET area of the device is completely covered by the gate 5, a large amount of charge will be generated between the gate and the drain, which increases the capacitance of the SJ SiC VDMOS, mainly the reverse transfer capacitance. In order to further increase the switching frequency and switching losses, smaller reverse transfer capacitance and gate drain charge are required, because the switching speed is determined by the charging and discharging speed of the gate capacitor. In order to solve the above problems, the present invention uses SJ SiC VDMOS with a planar split gate structure, as shown in Figure 1. When the SJ SiC VDMOS with a planar split-gate structure is turned off in the forward direction, charges are attracted to the negatively biased gates at both ends, and the electric field is concentrated at the bottom terminal of the gate, resulting in a very high concentrated electric field. The gate area above the JFET area of the device is greatly reduced, the charge between the gate and drain is reduced, the switching frequency of the device is increased, and the switching loss is reduced.

Preferably, it also includes: an electron tunneling layer 7;

The electron tunneling layer 7 is located under the silicon layer and adjacent to the silicon layer.

The electron tunneling layer 7 is a heavily doped N-type silicon carbide layer. The doping types of silicon carbide are divided into P-type and N-type. The ion concentration of heavily doped (high doping concentration) is generally above 10 ¹⁸ cm ^-3 , the ion concentration of lightly doped (low doping concentration) is generally less than 10 ¹⁸ cm ^-3 , and P-type doping is group IIIA elements, such as: boron, aluminum, gallium, indium, and thallium. N-type doping is group VA elements such as nitrogen, phosphorus, arsenic, antimony, bismuth and enrium.

In the present invention, the electron tunneling layer 7 is arranged at the interface between the silicon carbide layer and the silicon layer. When the gate voltage is positive, it can attract electrons in the body region of the silicon layer, so that the first body region 14 is close to the gate oxide layer 4 The part becomes an inversion layer, and because the electron tunneling layer 7 is connected to the silicon layer and the silicon carbide layer, electrons can more easily pass through the Si/SiC heterojunction, reducing the resistance of the Si/SiC heterojunction and improving the conductivity. Pass current.

Preferably, the first body region 14 includes a first extension portion located below the source electrode 9 and adjacent to the source electrode 9 and a second extension portion located below the N+ region 6 and the P+ region 3 and adjacent to the N+ region 6 and the P+ region 3 .

The first extending portion and the second extending portion of the first body region 14 are both rectangular. The first extending portion of the first body region 14 is located between the source electrode 9 and the second body region 2 and is in contact with the source electrode 9 and the second body region 2 . The body region 2 is a rectangle adjacent to the first body region 14 and the second extension of the first body region 14 is a rectangle located below the N+ region 6 and the P+ region 3 and adjacent to the N+ region 6 and the P+ region 3 .

The first body region 14 is completely located in the silicon layer and covers the N+ region 6 and the P+ region 3. The N+ region 6 and the P+ region 3 in the silicon layer are respectively adjacent to the source electrode 9. The N+ region 6 and the source electrode 9 form an ohmic The P+ region 3 forms Schottky contact with the source 9. The contact surface between the metal and the semiconductor is divided into two types: Schottky contact and ohmic contact. Ohmic contact is when the doping concentration of the semiconductor is very high. When the semiconductor with high doping concentration comes into contact with the metal, a low barrier layer is formed. The electrons can pass through the barrier through the tunnel effect, thus forming a low resistance ohmic contact. Ohmic contact The characteristic is that the current-voltage characteristics of the contact surface are linear, and the contact resistance is negligible compared to the bulk resistance of the semiconductor. When a current passes through, the voltage drop generated is smaller than the voltage drop on the device.

When SJ SiC VDMOS is operating normally, the gate 5 turns on the inversion layer located in the body region of the silicon layer, and current can flow from the N+ region 6 to the source 9 to form a loop. The N+ region 6 is heavily doped, making it easier to connect with the source 9 To form an ohmic contact, P+ is also heavily doped, making it easier to form Schottky contact with the source 9. As a preferred embodiment, the present invention sets the doping concentration of the N+ region 6 to 10 ²⁰ cm ^-3 and the P+ region The doping concentration of 3 is set to 10 ¹⁹ cm ^-3 .

Preferably, it also includes: a silicon carbide layer;

The silicon carbide layer includes: the second body region 2, the second N pillar 8 and the substrate 11;

In the present invention, the material of the N pillar and part of the body region is silicon carbide, and the material of the substrate 11 is also silicon carbide, because silicon carbide has a wide band gap, high breakdown field strength, high thermal conductivity, and saturated electron mobility rate. High, stable physical and chemical properties and other characteristics, it can be applied to high temperature, high frequency, high power and extreme environments. Silicon carbide has a larger bandgap and higher critical breakdown field strength. Compared with silicon power devices under the same conditions, the voltage resistance of silicon carbide devices is about 10 times that of silicon materials. Therefore, the present invention has high channel mobility and at the same time has various advantages of silicon carbide MOSFET.

The second body region 2 is located between the first body region 14 and the second N-pillar 8 and adjacent to the first body region 14 and the second N-pillar 8;

The body region is made of two materials, one is the first body region 14 made of silicon material, and the other is the second body region 2 made of silicon carbide material. The first body region 14 is completely located in the silicon layer. The second body region 2 is completely located in the silicon carbide layer. During the preparation process of SJSiC VDMOS, the silicon carbide layer and the silicon layer are first epitaxially epitaxially formed on the substrate 11, and then ion implantation is performed to form each region. The second body region 2 and The first body region 14 is formed by ion implantation during fabrication. The role of the second body region 2 is because the first body region 14 located below the N+ region 6 and the P+ region 3 is relatively thin. It will cause leakage of SJ SiCVDMOS, so a second body region 2 is provided below the first body region 14 to prevent leakage of SJ SiC VDMOS and significantly improve the reliability of SJ SiC VDMOS.

The silicon carbide layer is located between the drain electrode 12 and the silicon layer, and is adjacent to the silicon layer and the drain electrode 12 .

In the present invention, SJ SiC VDMOS is mainly made of three materials, namely the substrate 11 made of silicon carbide material and the second N pillar 8, P pillar 1, etc., and the N+ region 6 and P+ region 3 made of silicon material. and the first body region 14, the first N pillar 10, etc., as well as electrodes made of metal. The source electrode 9 is connected to the silicon layer, then the silicon layer is connected to the silicon carbide layer, and the silicon carbide layer is connected to the drain electrode 12. When SJSiC VDMOS operates normally When , the current flows from the drain electrode 12 to the silicon carbide layer, then passes through the heterojunction of silicon and silicon carbide to the silicon layer, and finally flows from the silicon layer to the source electrode 9 .

Preferably, the doping concentration of the electron tunneling layer 7 is 10 ¹⁹ cm ^-3 .

The thickness and doping concentration of the electron tunneling layer 7 affect the resistance of the Si/SiC heterojunction. The greater the thickness of the electron tunneling layer 7, the smaller the resistance of the Si/SiC heterojunction. The thickness of the electron tunneling layer 7 The smaller, the greater the Si/SiC heterojunction resistance, if the thickness of the electron tunneling layer 7 is too large. It will cause the field strength at the position of the electron tunneling layer 7 to be too large, leading to the problem of early breakdown of VDMOS. The greater the doping concentration of the electron tunneling layer 7, the smaller the resistance of the Si/SiC heterojunction. The electron tunneling layer 7 The smaller the doping concentration, the greater the resistance of the Si/SiC heterojunction. If the doping concentration of the electron tunneling layer 7 is too large, it will cause partial leakage at the location of the electron tunneling layer 7, leading to the problem of SJ SiC VDMOS failure. , as a preferred embodiment, the present invention sets the thickness of the electron tunneling layer 7 to 0.07um, and the ion concentration of the electron tunneling layer 7 to 10 ¹⁹ cm ^-3 .

Preferably, the thickness of the first N pillar 10 is equal to the thickness of the silicon layer, and the thickness of the first N pillar 10 is also equal to the thickness of the first body region 14 .

The thickness of the silicon layer should not be too wide. If the thickness of the silicon layer is too wide, it will reduce various aspects of VDMOS performance, such as high temperature characteristics, high frequency characteristics, switching characteristics, conduction loss, etc., especially the voltage resistance performance will decrease significantly, so the silicon layer It is only necessary to ensure that the trench is completely in the silicon layer and the thickness is minimum. As a preferred embodiment, the present invention sets the thickness of the silicon layer to 0.1um, which can minimize the thickness while the trench is completely in the silicon layer.

The thickness of the first N-pillar 10 is 0.1um.

When the SJ SiC VDMOS is in the off state, the body region is in a high resistance state, which can prevent the SJ SiC VDMOS from leaking electricity and the current cannot pass through the MOSFET. When the SJ SiC VDMOS is in the on state, the gate 5 is turned on in the body region. The current channel allows current to flow from drain 12 to source 9. The doping concentration of the body region determines the turn-on voltage of SJ SiC VDMOS. The greater the doping concentration of the body region, the greater the turn-on voltage of SJ SiC VDMOS. The thickness also affects the turn-on voltage of SJ SiCVDMOS. The greater the thickness of the body region, the greater the turn-on voltage of SJ SiC VDMOS. If the doping concentration or thickness of the body region is too small, it will cause leakage of SJ SiC VDMOS. , as a preferred embodiment, the present invention sets the doping concentration of the body region to 10 ¹⁸ cm ^-3 and the thickness of the first body region 14 to 0.1um.

Preferably, the thickness of the silicon carbide layer is 12um.

The thickness of the silicon carbide layer includes the thickness of the second N pillar 8 and the thickness of the substrate 11. The SJ SiC VDMOS epitaxial layer includes a silicon layer and a silicon carbide layer. The thickness of the silicon carbide layer affects the resistance of the SJ SiC VDMOS. Voltage performance and chip area. The thicker the silicon carbide layer, the larger the drift region. The better the voltage resistance performance of SJ SiC VDMOS, but it will increase the chip area, so the thickness of the silicon carbide layer should not be too large. According to SJ For the electrical performance required by SiC VDMOS, as a preferred embodiment, the present invention sets the thickness of the silicon carbide layer to 12um.

Preferably, it also includes: source 9, drain 12, gate 5, substrate 11, P pillar 1, N+ region 6 and P+ region 3;

The drain electrode 12 is located under the substrate 11;

Drain 12 is the charge sink in the MOSFET. It is connected to the channel and is the entrance to the charge. When the MOSFET is in the on state, a conductive path is formed between the drain electrode 12 and the source electrode 9, and electrons flow from the source electrode 9 into the drain electrode 12 to complete the transmission of current. The voltage change of the drain 12 has little impact on the working state of the MOSFET and mainly plays the role of current inflow.

The substrate 11 is located under the P pillar 1 and the second N pillar 8;

The substrate 11 is a material used to support crystal growth in MOSFET, and the substrate 11 plays a role of mechanical support. In the present invention, the substrate 11 is made of silicon carbide material, and its mechanical strength and stability can effectively support various stresses and distortions during crystal growth. This is crucial to ensure uniformity and integrity of crystal growth. In addition, the substrate 11 can prevent impurities and defects during crystal growth, thereby improving the quality of the MOSFET. Secondly, the substrate 11 plays an important role in the electrical performance of the MOSFET. When preparing MOSFET, the electrical properties of the substrate 11 determine the performance and stability of the device. For example, the conductivity of substrate 11 directly affects the efficiency and speed of current transfer. In addition, the electron affinity and bandgap width of the substrate 11 are also crucial for adjusting the threshold voltage and electron mobility of the MOSFET. In addition, the substrate 11 also plays an important role in isolating the insulation layer of the MOSFET. During the MOSFET preparation process, the insulating layer of the substrate 11 is usually composed of silicon dioxide. The quality and characteristics of the insulating layer directly affect the insulation performance of MOSFET, such as electrical insulation and capacitance characteristics. A good insulating layer can effectively isolate different electrodes in the MOSFET structure and reduce leakage current and capacitive coupling effects.

Source 9 is located above the silicon layer;

Source 9 is the charge source in the MOSFET and is the outlet of the charge. When the MOSFET is in the on state, a conductive path is formed between the source electrode 9 and the drain electrode 12, and electrons flow from the source electrode 9 into the drain electrode 12 to complete the transmission of current. At the same time, the source 9 also plays the role of modulating the gate voltage, and controls the MOSFET by controlling changes in the source voltage.

P+ region 3 is located below source 9;

N+ region 6 is located under gate 5 and source 9;

Gate 5 is located between source 9 and the silicon layer.

Gate 5 is the control electrode in the MOSFET. It is separated from the channel by an insulating layer and is a key part of the MOSFET. The voltage change of gate 5 can change the charge density in the channel, thereby controlling the size of the current between drain 12 and source 9 .

Example 2

A method for preparing SJ SiC VDMOS with split gate, refer to Figure 2 and Figure 3, including:

S100, epitaxially grow a silicon carbide layer over the substrate 11 and perform ion implantation to form the P pillar 1, the second body region 2 and the second N pillar 8;

The present invention uses ion implantation to form the P pillar 1, the second body region 2 and the second N pillar 8. Ion implantation is to emit an ion beam in a vacuum towards a solid material. After the ion beam hits the solid material, its speed slowly slows down due to the resistance of the solid material, and finally stays in the solid material. The ions of an element are accelerated into a solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacturing of semiconductor devices, metal surface treatment, and materials science research. If the ions are stopped and retained in the target, the ions will change the elemental composition of the target (if the ions are of a different composition than the target). Ion implantation beamline designs all contain a common set of functional components. The main part of an ion beamline consists of a device called an ion source, which is used to generate ion species. The source is tightly coupled to a bias electrode to extract ions into the beamline, and most commonly to some means of selecting specific ion species for transport into the main accelerator section. Mass selection accompanies the extracted ion beam through the magnetic field region, with its exit path restricted by blocking holes or slits that only allow ions with mass and velocity/charge to continue along the beamline. If the target surface is larger than the ion beam diameter, and the implant dose is evenly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When injected into a semiconductor, each dopant atom can generate charge carriers in the semiconductor after annealing. A hole can be created for P-type dopants and an electron for N-type dopants. Changes the conductivity of the semiconductor near the doped region.

S200, epitaxial silicon layer on top of silicon carbide layer;

The epitaxial process refers to the process of growing a completely ordered single crystal layer on the substrate 11. The epitaxial process is the growth of a crystal layer with the same lattice orientation as the original substrate on the single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxy methods are solid-phase epitaxy and vapor-phase epitaxy.

Solid-phase epitaxy refers to the growth of a single crystal layer on a substrate by a solid source. For example, thermal annealing after ion implantation is actually a solid-phase epitaxy process. During ion implantation processing, the silicon atoms of the silicon wafer are bombarded by high-energy implanted ions, leaving the original crystal lattice position and becoming amorphous, forming a surface amorphous silicon layer. After high-temperature thermal annealing, the amorphous atoms return to the original lattice position. The lattice position is consistent with the atomic orientation within the substrate.

The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. In the embodiment of the present invention, chemical vapor epitaxy (CVE) is used to form the N-drift layer. The principles of chemical vapor epitaxy and chemical vapor deposition (CVD) are basically the same. They are both processes that use gas mixing to react chemically on the surface of the wafer to deposit thin films. The difference is that because chemical vapor epitaxy grows a single crystal layer, it is The impurity content in the equipment and the cleanliness requirements on the silicon wafer surface are both higher. In integrated circuit manufacturing, CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source-drain epitaxial processes. The epitaxial silicon wafer process is to epitaxially extend a layer of single crystal silicon on the surface of the silicon wafer. Compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, thus improving the yield of semiconductor manufacturing. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to device design. For example, it can be used to reduce substrate resistance, enhance substrate isolation, etc. The embedded source-drain epitaxy process refers to the process of epitaxially growing doped silicon germanium or silicon in the source and drain regions of the transistor. The main advantages of introducing the embedded source-drain epitaxial process include: it can grow a pseudocrystalline layer that contains stress due to lattice adaptation, improving channel carrier mobility; it can dope the source and drain in situ, reducing the parasitic resistance of the source-drain junction , Reduce the defects of high-energy ion implantation.

S300, ion implantation is performed in the silicon layer to form the first body region 14, the P+ region 3 and the N+ region 6;

S400, deposit the source electrode 9, the drain electrode 12, the gate electrode 5 and the split gate electrode 13.

Metal electrode deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to the method of chemically depositing coatings on the surface of wafers, generally by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

Both chemical vapor deposition (CVD) and physical vapor deposition (PVD) can be used as technical means to deposit metal electrodes. In embodiments of the present invention, a chemical vapor deposition method is used to deposit metal electrodes. The chemical vapor deposition process is divided into three stages: diffusion of reaction gas to the surface of the substrate, adsorption of the reaction gas on the surface of the substrate, and chemical reaction on the surface of the substrate to form a solid deposition. The substances and the gas phase by-products produced are separated from the surface of the matrix. The most common chemical vapor deposition reactions are: thermal decomposition reactions, chemical synthesis reactions and chemical transport reactions.

The gate electrode is deposited using the polysilicon deposition method. Polysilicon deposition is when silicide is stacked on the first layer of polysilicon (Poly1) to form the gate electrode and local connections. The second layer of polysilicon (Poly2) forms the source 9/drain 12 and unit. Contact plugs between wires. The silicide is stacked on the third layer of polysilicon (Poly3) to form the unit connection. The fourth layer of polysilicon (Poly4) and the fifth layer of polysilicon (Poly5) form the two electrodes of the storage capacitor. Sandwiched between them is a high dielectric coefficient of dielectric. To maintain the desired capacitance value, the size of the capacitor can be reduced by using a high-k dielectric. Polycrystalline silicon deposition is a type of low-pressure chemical vapor deposition (LPCVD), by placing arsenic (AH ₃ ), phosphorus (PH ₃ ) or diborane (B ₂ H ₆ ) in a reaction chamber (i.e., a furnace tube). By directly inputting the doping gas into the silicon material gas of silane or DCS, the polysilicon doping process of on-site low-pressure chemical vapor deposition can be performed. Polysilicon deposition is carried out under low pressure conditions of 0.2-1.0 Torr and deposition temperatures between 600 and 650°C, using pure silane or silane with a purity of 20% to 30% diluted with nitrogen. The deposition rate of both deposition processes is between 100-200Å/min, mainly determined by the temperature during deposition.

Preferably, S100, epitaxially extend a silicon carbide layer over the substrate 11 and ion-implant it to form the P pillar 1, the second body region 2 and the second N-pillar 8, and further include: forming an electron tunneling layer 7 by ion implantation on the silicon carbide layer. .

The electron tunneling layer 7 is formed by ion implantation after the P pillar 1 and the second N pillar 8 are formed. The electron tunneling layer 7 is located on the upper layer of the second N pillar 8. The present invention controls the dose of ion implantation, The doping concentration and thickness of the electron tunneling layer 7 are controlled by the energy, ion concentration and injection times.

The present invention takes advantage of the fact that silicon material has a higher channel mobility than silicon carbide material, and replaces part of the silicon carbide layer of planar SiCVDMOS with a silicon layer, so that the channel falls into the silicon material, thereby improving the channel mobility of planar SiC VDMOS. Mobility, since the Si/SiC heterojunction has a high potential barrier, it is difficult for electrons to cross the barrier, so the present invention adds an electron tunneling layer 7 between the silicon layer and the silicon carbide layer, so that electrons can easily Through the Si/SiC interface, the heterojunction resistance is reduced, the on-current is increased, and the electrical performance of SJ SiC VDMOS is significantly improved. A split gate structure is also introduced. The split gate 13 can reduce the gate electrode 5 and the drain electrode 12 The relative area, thereby reducing the capacitance between gate 5 and drain 12, increases the switching frequency of SJ SiC MOS.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. A SJ SiC VDMOS with a split gate, characterized in that it includes: a silicon layer and a split gate; The silicon layer includes: a first body region, an N+ region, a P+ region and a first N pillar; The silicon layer is located between the silicon carbide layer and the source and gate oxide layers, and is adjacent to the source and gate oxide layers; The split gate is located on the side of the gate and is covered by a gate oxide layer. 2. A SJ SiC VDMOS with split gate according to claim 1, further comprising: an electron tunneling layer; The electron tunneling layer is located under the silicon layer and adjacent to the silicon layer. 3. A SJ SiC VDMOS with a split gate according to claim 1, wherein the first body region includes a first extension portion located below the source electrode and adjacent to the source electrode and located in the N+ region and the P+ region. A second extension below the region and adjacent to the N+ and P+ regions. 4. A SJ SiC VDMOS with split gate according to claim 1, further comprising: a silicon carbide layer; The silicon carbide layer includes: a second body region, a second N pillar and a substrate; The second body region is located between the first body region and the second N-pillar and adjacent to the first body region and the second N-pillar; The silicon carbide layer is located between the drain electrode and the silicon layer and adjacent to the silicon layer and the drain electrode. 5. The SJ SiC VDMOS with split gate according to claim 2, wherein the doping concentration of the electron tunneling layer is 10 ¹⁹ cm ^-3 . 6. A SJ SiC VDMOS with split gate according to claim 1, wherein the thickness of the first N pillar is equal to the thickness of the silicon layer; The thickness of the first N pillar is 0.1um. 7. The SJ SiC VDMOS with split gate according to claim 4, wherein the thickness of the silicon carbide layer is 12um. 8. A SJ SiC VDMOS with a split gate according to claim 1, further comprising: a source, a drain, a gate, a substrate, a P pillar, an N+ region and a P+ region; The drain electrode is located under the substrate; The substrate is located under the P pillar and the second N pillar; The source electrode is located above the silicon layer; The P+ region is located below the source; The N+ region is located under the gate and source; The gate electrode is located between the source electrode and the silicon layer. 9. A method for preparing SJ SiC VDMOS with split gate, characterized by including: Epitaxially grow a silicon carbide layer over the substrate and ion-implant to form a P pillar, a second body region and a second N pillar; epitaxially growing a silicon layer over the silicon carbide layer; Implanting ions into the silicon layer forms a first body region, a P+ region and an N+ region; Deposit source, drain, gate and split gate. 10. A method for preparing SJ SiC VDMOS with split gate according to claim 9, characterized in that the silicon carbide layer is epitaxially grown over the substrate and ion implanted to form a P pillar, a second body region and a second N The column also includes: ion implantation into the upper layer of the silicon carbide layer to form an electron tunneling layer.