CN117423729A - Trench gate VDMOS with heterojunction and preparation method - Google Patents

Abstract

The invention provides a trench gate VDMOS with heterojunction and a preparation method thereof, wherein the VDMOS comprises the following steps: a silicon layer and a trench gate; the silicon layer includes: a body region and an n+ region; the silicon layer is positioned above the drift layer; the silicon layer is adjacent to the drift layer; the trench gate is located in the trench and adjacent to the silicon layer and the drift layer. According to the invention, the silicon material is deposited above the drift layer made of the silicon carbide material, so that the channel is prepared in the silicon material, and the channel has higher channel mobility in the silicon material because the channel mobility of silicon is higher than that of the silicon carbide, and the VDMOS device also has high breakdown voltage brought by the silicon carbide material.

Description

A trench gate VDMOS with heterojunction and preparation method

Technical field

The invention relates to the field of semiconductor technology, and in particular to a trench gate VDMOS with heterojunction and a preparation method.

Background technique

The third generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturation electron migration rate, stable physical and chemical properties, etc., and can be applied to high temperature, high frequency, high power and extreme environments. Silicon carbide has a larger bandgap and higher critical breakdown field strength. Compared with silicon power devices under the same conditions, the voltage resistance of silicon carbide devices is about 10 times that of silicon materials.

Channel mobility is one of the important parameters of SiC MOSFET. Channel mobility refers to the migration speed of electrons or holes in the channel under the action of an electric field. In MOSFETs, channel mobility determines the efficiency and speed of current transfer. The higher the channel mobility, the faster electrons or holes migrate in the channel, and the better the conductive performance of the device. Factors that affect channel mobility include: the characteristics of silicon carbide materials. The channel mobility of silicon carbide-based devices is low, an order of magnitude lower than that of silicon-based devices, which limits the performance of the device. Channel structure and size also have an important impact on channel mobility. Shorter channel length and smaller channel width can reduce the scattering of current in the channel, thereby improving channel mobility. Surface state and interface state, surface state and interface state refer to the channel surface and the charge state between the channel and the insulating layer. These charge states affect the migration speed of electrons or holes in the channel, thereby affecting channel mobility. By optimizing materials and processes, the influence of surface states and interface states can be reduced and channel mobility improved.

There are currently several methods for optimizing silicon carbide-based channel mobility: optimizing materials and selecting silicon carbide materials with higher channel mobility, such as 4H-SiC or 6H-SiC, which can improve device performance. Optimizing the structure and size, by reducing the channel length and channel width, can reduce the scattering of current in the channel and improve channel mobility. Optimize the process. By optimizing the process and reducing the influence of surface states and interface states, the channel mobility can be improved. Lower the temperature. When using SiC MOSFET in a high-temperature environment, you can take heat dissipation measures or lower the operating temperature to reduce the impact of temperature on channel mobility. However, the costs of the above methods are relatively high, and the improvement in channel mobility still cannot meet the current industrial production needs.

Contents of the invention

In order to solve at least one of the technical problems raised above, the purpose of the present invention is to provide a trench gate VDMOS with a heterojunction and a preparation method. The VDMOS deposits silicon material above a drift layer made of silicon carbide material to allow the channel to Prepared in silicon material, since the channel mobility of silicon is higher than that of silicon carbide, the channel has a higher channel mobility in silicon material, and the VDMOS device also has a high breakdown voltage brought by silicon carbide material .

The object of the present invention is achieved by the following technical means:

In a first aspect, the present invention provides a trench gate VDMOS with a heterojunction, including: a silicon layer and a trench gate;

The silicon layer includes: a body region and an N+ region;

The silicon layer is located above the drift layer;

The silicon layer is adjacent to the drift layer;

The trench gate is located in the trench and adjacent to the silicon layer and the drift layer.

Preferably, the thickness of the silicon layer is 1-15um.

Preferably, the body region is located between and adjacent to the drift layer and the N+ region.

Preferably, the thickness of the body region is 1-15um.

Preferably, the doping concentration of the body region is 10 ¹⁷ cm ^-3 .

Preferably, the N+ region is located between the trench gate and the body region and adjacent to the trench gate and the body region.

Preferably, the doping concentration of the N+ region is 10 ¹⁹ cm ^-3 .

Preferably, it also includes: a silicon carbide layer;

The silicon carbide layer includes: a drift layer, a substrate and a P+ region;

The substrate is located above the drain electrode and adjacent to the drain electrode and the drift layer;

The drift layer is located above the substrate and adjacent to the body region;

The P+ regions are located on both sides of the silicon layer.

Preferably, the thickness of the silicon carbide layer is 50-200um.

In a second aspect, the present invention provides a method for preparing a trench gate VDMOS with a heterojunction, including:

Epitaxially growing a silicon carbide layer above the substrate to form a drift layer;

Etching a first trench above the drift layer;

deposit silicon inside the first trench to form a silicon layer;

Etching a via hole on the silicon layer, etching a second trench on the drift layer, the via hole being connected to the second trench;

depositing a gate electrode in the second trench;

Ion implantation is performed on the upper layer of the silicon layer to form a body region and an N+ region;

A P+ region is formed by ion implantation in the upper layer of the drift layer;

Deposit source and drain electrodes.

Compared with the existing technology, the beneficial effects of the present invention are:

The present invention takes advantage of the fact that silicon material has a higher channel mobility than silicon carbide material, and replaces part of the silicon carbide layer of SiC VDMOS with a silicon layer, so that the channel falls into the silicon material, thereby improving the channel migration of SiC VDMOS. Rate.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings needed to describe the embodiments or the prior art. Obviously, for those of ordinary skill in the art, It is said that other drawings can be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic structural diagram of a trench gate VDMOS with a heterojunction provided by an embodiment of the present invention;

Figure 2 is a schematic flow chart of a method for preparing a trench gate VDMOS with heterojunction provided by an embodiment of the present invention;

Figure 3 is a schematic structural diagram A of a method for preparing a trench gate VDMOS with a heterojunction provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram B of a method for preparing a trench gate VDMOS with a heterojunction provided by an embodiment of the present invention.

In the picture: 1-drain, 2-substrate, 3-drift layer, 4-body region, 5-trench gate, 6-P+ region, 7-N+ region.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiment of the present invention are only used to explain the relationship between components in a specific posture (as shown in the drawings). Relative positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

In addition, descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor within the protection scope required by the present invention.

There are currently several methods for optimizing silicon carbide-based channel mobility: optimizing materials and selecting silicon carbide materials with higher channel mobility, such as 4H-SiC or 6H-SiC, which can improve device performance. Optimizing the structure and size, by reducing the channel length and channel width, can reduce the scattering of current in the channel and improve channel mobility. Optimize the process. By optimizing the process and reducing the influence of surface states and interface states, the channel mobility can be improved. Lower the temperature. When using SiC MOSFET in a high-temperature environment, you can take heat dissipation measures or lower the operating temperature to reduce the impact of temperature on channel mobility. However, the costs of the above methods are relatively high, and the improvement in channel mobility still cannot meet the current industrial production needs.

The present invention takes advantage of the fact that silicon material has a higher channel mobility than silicon carbide material, and replaces part of the silicon carbide layer of SiC VDMOS with a silicon layer, so that the channel falls into the silicon material, thereby improving the channel migration of SiC VDMOS. Rate.

Example 1

A trench gate VDMOS with a heterojunction is provided, see Figure 1, including: a silicon layer and a trench gate 5;

The silicon layer includes: body region 4 and N+ region 7;

MOSFETs are usually made of silicon or silicon carbide. Silicon materials have high thermal stability and electrical properties, which make silicon MOSFET devices have high reliability and long-term stability during operation. Silicon MOSFETs are suitable for analog circuits. In various application fields such as digital circuits and mixed signals, the third-generation semiconductor material silicon carbide has a larger band gap and can withstand higher temperatures and higher voltages. It is suitable for high-temperature, high-frequency, high-voltage, and high-power circuits. However, the channel mobility of silicon carbide MOSFET is one order of magnitude lower than that of silicon MOSFET. In order to improve the channel mobility of silicon carbide MOSFET, this embodiment adds a silicon layer to the traditional silicon carbide MOSFET and separates the channel It is prepared in the silicon layer, so that the silicon carbide MOSFET also has the high mobility of the silicon MOSFET, and because part of the material of the drift layer 3 is silicon carbide, it also has the high breakdown voltage characteristics of the silicon carbide MOSFET. In this embodiment, by placing the trench gate 5 in the silicon layer to open the channel in the silicon layer, the interface between silicon and silicon dioxide increases the channel mobility of the silicon carbide MOSFET to a maximum of 1420cm ² /Vs .

The silicon layer is located above the drift layer 3;

In this embodiment, in order to prepare the channel in the silicon layer, the silicon layer is placed above the silicon carbide drift layer 3, and ions are implanted in the silicon layer to form the body region 4 and the N+ region 7, so that the channel is completely Placed in the silicon layer to improve the channel mobility of silicon carbide VDMOS.

The silicon layer is adjacent to the drift layer 3;

When VDMOS works normally, the gate and drain 1 are connected to a positive voltage, and the gate induces an inversion layer in the body region 4. Then the current flows from the drain 1 to the substrate 2, from the substrate 2 to the drift layer 3, and from the drift layer Layer 3 flows to body region 4, from body region 4 to N+ region 7 and then to the source.

The trench gate 5 is located in the trench and adjoins the silicon layer and the drift layer 3 .

In some embodiments, trench gate 5 includes: gate polysilicon and a gate oxide layer;

There are two types of gates for MOSFETs, one is a trench gate and the other is a planar gate. The trench gate has a deep and narrow trench structure, which can increase the effective channel cross-sectional area of the device. , thereby reducing the on-resistance and enabling higher current transmission and power handling capabilities. The channel structure of planar gate process MOSFET is relatively simple and the on-resistance is high. Trench process MOSFET controls the shape and size of the trench. Due to the deep trench structure of the trench process, the surface area of the drain-source region is significantly increased. This makes MOSFET devices better able to withstand high voltages, making them suitable for high-voltage applications such as power switches, motor drives, and power systems. By forming a larger PN junction between the insulating material in the trench and the substrate 2, the flow of reverse leakage current can be effectively prevented. Therefore, trench process MOSFET has better anti-leakage performance under reverse bias.

The trench gate 5 is formed by etching a through hole in the silicon layer and etching a trench on the upper layer of the silicon carbide layer. The etched through hole is connected to the trench, and then a gate oxide layer is deposited on the trench wall and then a polysilicon gate is deposited. The polysilicon gate is covered with a gate oxide layer to form a trench gate 5 . Part of the trench is placed in the silicon layer and part is placed in the silicon carbide layer. The lower part of the gate oxide layer is adjacent to the silicon carbide layer and the upper part is adjacent to the silicon layer.

Preferably, the thickness of the silicon layer is 1-15um.

The thickness of the silicon layer should not be too wide. If the thickness of the silicon layer is too wide, it will reduce various aspects of VDMOS performance, such as high temperature characteristics, high frequency characteristics, switching characteristics, conduction loss, etc., especially leading to a significant decrease in voltage resistance performance. At the same time, the thickness of the silicon layer cannot be too small, and the trench needs to be ensured to fall into it. In this embodiment, the thickness of the silicon layer is set to 1-15um. As a preferred embodiment, the present invention sets the thickness of the silicon layer to 1 μm, which enables the channel to fall into the silicon layer while minimizing the thickness.

Preferably, the body region 4 is located between the drift layer 3 and the N+ region 7 and is adjacent to the drift layer 3 and the N+ region 7 .

Preferably, the thickness of the body region 4 is 1-15um.

Preferably, the doping concentration of the body region 4 is 10 ¹⁷ cm ^-3 .

When the VDMOS is in the off state, the body region 4 presents a high resistance state, which can prevent the VDMOS from leaking current and the current cannot pass through the MOSFET. When the VDMOS is in the on state, the gate opens the current channel in the body region 4, causing the current to It can flow from drain 1 to source. The doping concentration of body region 4 determines the turn-on voltage of VDMOS. The greater the doping concentration of body region 4, the greater the turn-on voltage of VDMOS. The thickness of body region 4 also affects VDMOS. The greater the thickness of body region 4, the greater the turn-on voltage of VDMOS. If the doping concentration or thickness of body region 4 is too small, leakage of VDMOS will occur. In this embodiment, the thickness of the body region 4 is set to 1-15um. As a preferred embodiment, the present invention sets the doping concentration of the body region 4 to 10 ¹⁷ cm ^-3 .

Preferably, the N+ region 7 is located between the trench gate 5 and the body region 4 and adjacent to the trench gate 5 and the body region 4 .

Preferably, the doping concentration of N+ region 7 is 10 ¹⁹ cm ^-3 .

The N+ region 7 is adjacent to the source electrode, and the N+ region 7 forms an ohmic contact with the source electrode. The contact surface between the metal and the semiconductor is divided into two types: Schottky contact and ohmic contact. Ohmic contact is when the doping concentration of the semiconductor is very high. When the semiconductor with high doping concentration comes into contact with the metal, a low barrier layer is formed. Electrons can pass through the barrier through the tunnel effect, thus forming a low resistance ohmic contact. Ohmic contact The characteristic is that the current-voltage characteristics of the contact surface are linear, and the contact resistance is negligible compared to the bulk resistance of the semiconductor. When a current passes through, the voltage drop generated is smaller than the voltage drop on the device.

When VDMOS is operating normally, current can flow from the N+ region 7 to the source to form a loop. The N+ region 7 is heavily doped, making it easier to form ohmic contact with the source. In this embodiment, the doping concentration of N+ region 7 is set to 10 ¹⁹ cm ^-3 .

Preferably, it also includes: a silicon carbide layer;

In this embodiment, the material of the drift layer 3 is silicon carbide, and the material of the substrate 2 is also silicon carbide, because silicon carbide has a wide band gap, high breakdown field strength, high thermal conductivity, and high saturated electron mobility rate. It has stable physical and chemical properties and can be used in high temperature, high frequency, high power and extreme environments. Silicon carbide has a larger bandgap and higher critical breakdown field strength. Compared with silicon power devices under the same conditions, the voltage resistance of silicon carbide devices is about 10 times that of silicon materials. Therefore, this embodiment has high channel mobility and at the same time has various advantages of silicon carbide MOSFET.

The silicon carbide layer includes: drift layer 3, substrate 2 and P+ region 6;

The electric field distribution of the drift layer 3 plays a key role in the conduction characteristics and current control of the MOSFET. When a gate voltage is applied to the MOSFET, the electric field distribution in the drift layer 3 is modulated by the gate voltage, thereby controlling the current flow between the source and drain 1. When the MOSFET is operating, the current between the source and drain 1 is mainly transmitted through the drift layer 3. The doping type and concentration of the drift layer 3 determine the conduction type (N-type or P-type) and magnitude of the current. The structure and characteristics of the drift layer 3 directly affect the current control capability of the MOS tube. By adjusting the shape, size and doping concentration of the drift layer 3, precise control of the current can be achieved to meet the requirements of different applications.

The substrate 2 is located above the drain electrode 1 and adjacent to the drain electrode 1 and the drift layer 3;

Drain 1 is the charge sink in the MOSFET. It is connected to the channel and is the entrance to the charge. When the MOSFET is in the on state, a conductive path is formed between the drain 1 and the source, and electrons flow from the source to the drain 1 to complete the transmission of current. The voltage change of drain 1 has little impact on the working state of the MOSFET, and mainly plays the role of current inflow.

The drift layer 3 is located above the substrate 2 and adjacent to the body region 4;

Substrate 2 is the material used to support crystal growth in MOSFET, and substrate 2 plays a role of mechanical support. In this embodiment, the substrate 2 is made of silicon carbide material, and the mechanical strength and stability of silicon carbide can effectively support various stresses and distortions during crystal growth. The choice of substrate material is crucial, and silicon carbide can ensure the uniformity and integrity of crystal growth. In addition, the substrate 2 can prevent impurities and defects during crystal growth, thereby improving the quality of the MOSFET. Secondly, the substrate 2 plays an important role in the electrical performance of the MOSFET. When preparing MOSFET, the electrical properties of substrate 2 determine the performance and stability of the device. For example, the conductivity of the substrate 2 directly affects the efficiency and speed of current transmission. In addition, the electron affinity and bandgap width of the substrate 2 are also crucial for adjusting the threshold voltage and electron mobility of the MOSFET. In addition, the substrate 2 also plays an important role in isolating the insulating layer of the MOSFET. During the MOSFET preparation process, the insulating layer of the substrate 2 is usually composed of silicon dioxide. The quality and characteristics of the insulating layer directly affect the insulation performance of MOSFET devices, such as electrical insulation and capacitance characteristics. A good insulating layer can effectively isolate different electrodes in the MOSFET structure and reduce leakage current and capacitive coupling effects.

P+ regions 6 are located on both sides of the silicon layer.

Good terminal design can effectively improve the withstand voltage and reliability of the device and reduce the leakage of the device. Terminals can be divided into two major types according to their basic structure, namely extended type and truncated type. The extended terminal mainly reduces or shares the high electric field at the main junction by setting some special structures around the main junction, thereby increasing the breakdown voltage. Extended terminal structures mainly include field plates, field-limited rings, junction terminal extensions, lateral variable doping, RESURF, etc. In the MOSFET structure, the field limiting ring is the most commonly used, mainly because its process is very simple but the effect is very obvious. Field limiting rings can be formed by diffusion together with the main junction, without adding additional process steps and masks. Different numbers of field limiting rings can be used to design for different withstand voltage conditions. Generally speaking, the breakdown voltage increases as the number of rings increases. However, when the number of rings increases to a certain level, the effect of increasing the number of rings on the voltage is less and less obvious, and it will waste chip area.

In this embodiment, the P+ region 6 is an extended field-limited ring structure, and the number of P+ regions 6 and the specific ring width and ring spacing are not limited.

Preferably, the thickness of the silicon carbide layer is 50-200um.

In some embodiments, the silicon carbide layer includes substrate 2 and drift layer 3 . The breakdown voltage of the MOSFET device mainly bears the structure of the substrate 2 and the drift layer 3. Among them, the main influencing factors are its thickness and doping concentration. The critical electric field strength of silicon carbide is 10 times that of silicon. This means that to achieve the same breakdown voltage, the thickness of the drift layer 3 required by silicon carbide devices is much smaller than that of silicon devices. The thinner drift layer 3 of the silicon carbide device will also cause the resistance of the drift layer 3 of the silicon carbide device to decrease. The substrate 2 carries the current and voltage of the MOSFET, and the thickness of the substrate 2 has an important impact on the performance and characteristics of the MOSFET. The thickness of substrate 2 will affect the conductive performance of MOSFET. When substrate 2 is thin, the current density of MOSFET will increase, causing the current to pass through the MOSFET more easily. The thickness of substrate 2 will also affect the voltage characteristics of MOSFET. When When the substrate 2 is thin, the electric field distribution will be more concentrated on the substrate 2, allowing the MOSFET to withstand higher voltages; the thickness of the substrate 2 will also affect the thermal characteristics of the MOSFET. When the substrate 2 is thin, the heat can Dissipates from the MOSFET more easily, thereby improving the thermal stability of the MOSFET. Therefore, a reasonable selection of the thickness of the substrate 2 can optimize the performance and characteristics of the MOSFET and improve the reliability and stability of its application. In embodiments, the thickness of the silicon carbide layer is set to 50-200um. As a preferred embodiment, the present invention sets the thickness of the silicon carbide layer to 100um.

Example 2

A method for preparing trench gate VDMOS with heterojunction is provided, see Figure 2, Figure 3 and Figure 4, including:

S100, epitaxially extend the silicon carbide layer over the substrate 2 to form the drift layer 3;

The epitaxial process refers to the process of growing a completely ordered single crystal layer on the substrate 2. The epitaxial process is the growth of a crystal layer with the same lattice orientation as the original substrate on the single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxy methods are solid-phase epitaxy and vapor-phase epitaxy.

Solid-phase epitaxy refers to the growth of a single crystal layer on the substrate 2 by a solid source. For example, thermal annealing after ion implantation is actually a solid-phase epitaxy process. During ion implantation processing, the silicon atoms of the silicon wafer are bombarded by high-energy implanted ions, leaving the original crystal lattice position and becoming amorphous, forming a surface amorphous silicon layer. After high-temperature thermal annealing, the amorphous atoms return to the original lattice position. The lattice position is consistent with the atomic orientation within the substrate.

The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. The principles of chemical vapor epitaxy and chemical vapor deposition (CVD) are basically the same. They are both processes that use gas mixing to react chemically on the surface of the wafer to deposit thin films. The difference is that because chemical vapor epitaxy grows a single crystal layer, it is The impurity content in the equipment and the cleanliness requirements on the silicon wafer surface are both higher. In integrated circuit manufacturing, CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source-drain epitaxial processes. The epitaxial silicon wafer process is to epitaxially extend a layer of single crystal silicon on the surface of the silicon wafer. Compared with the original substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, thus improving the yield of semiconductor manufacturing. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to device design. For example, it can be used to reduce substrate resistance, enhance substrate isolation, etc. The embedded source-drain epitaxy process refers to the process of epitaxially growing doped silicon germanium or silicon in the source and drain regions of the transistor. The main advantages of introducing the embedded source-drain epitaxial process include: it can grow a pseudocrystalline layer that contains stress due to lattice adaptation, improving channel carrier mobility; it can dope the source and drain in situ, reducing the parasitic resistance of the source-drain junction , Reduce the defects of high-energy ion implantation.

In this embodiment, the substrate 2 and the drift layer 3 are both made of silicon carbide, where the substrate 2 is made of N+ type 4H- silicon carbide and the drift layer 3 is made of N- type silicon carbide.

S200, etching the first trench above the drift layer 3;

S300, deposit silicon inside the first trench to form a silicon layer;

S400, etching a through hole on the silicon layer, etching a second trench on the drift layer 3, and connecting the through hole to the second trench;

In this embodiment, the etched via hole and the trench are connected, that is, after the via hole is etched on the silicon layer, the trench is continued to be etched toward the upper layer of the drift layer 3, and finally the via hole and the trench are connected to form a trench. groove. Etching is the process of selectively removing unwanted materials from the surface of silicon wafers using chemical or physical methods. It is a general term for stripping and removing materials through solutions, reactive ions or other mechanical means. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Thereby, argon ions are radiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they hit the material on the surface. With the wafer vertical or tilted into the ion beam, the etching process is absolutely anisotropic. Selectivity is low as there is no difference between layers. The gases and ground material are removed by a vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched using this method, with very low wear on vertical walls due to vertical radiation.

Plasma etching is a chemical etching process that has the advantage that the wafer surface will not be damaged by accelerated ions. Due to the mobile particles of the etching gas, the etching profile is isotropic, so this method is used to remove the entire film layer (e.g. backside cleaning after thermal oxidation). One type of reactor used for plasma etching is a downstream reactor whereby the plasma is ignited at a high frequency of 2.45 GHz via impact ionization at a location separated from the wafer.

The etch rate depends on the pressure, power of the high frequency generator, process gas, actual gas flow and wafer temperature. Anisotropy increases with increasing high-frequency power, decreasing pressure, and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes, and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed unevenly, resulting in inhomogeneity. If the distance between the electrodes is increased, the etch rate decreases because the plasma is distributed in an enlarged volume. For electrodes, carbon has proven to be the material of choice. Because fluorine and chlorine gases also attack carbon, the electrodes create a uniformly strained plasma so the edges of the wafer are affected in the same way as the center of the wafer. Selectivity and etch rate are highly dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.

S500, depositing a gate electrode in the second trench;

Depositing the gate is divided into two steps, one is the formation of the gate oxide layer, and the other is the deposition of polysilicon. The gate oxide layer is used to isolate the gate electrode and the substrate 2, and plays a role in protecting and controlling the current. The gate oxide layer It is generally prepared by thermal oxidation. The leakage current of a good oxide layer is basically 0 and has a high breakdown electric field strength (breakdown electric field strength is about 10MV/cm). Wet oxygen oxidation is used to generate an oxide layer. Wet oxidation uses gaseous oxygen (usually air) as an oxidant under high temperature (120~320℃) and high pressure (0.5~20MPa) conditions to oxidize organic matter in water into small molecules. Organic or inorganic matter. High temperature can improve the solubility of oxygen in the liquid phase. The purpose of high pressure is to inhibit the evaporation of water to maintain the liquid phase. The water in the liquid phase can serve as a catalyst to allow the oxidation reaction to proceed at a lower temperature.

Polysilicon deposition is when silicide is stacked on the first layer of polysilicon (Poly1) to form the gate electrode and local connections, and the second layer of polysilicon (Poly2) forms the contact plug between the source/drain 1 and the cell connection. The silicide is stacked on the third layer of polysilicon (Poly3) to form the unit connection. The fourth layer of polysilicon (Poly4) and the fifth layer of polysilicon (Poly5) form the two electrodes of the storage capacitor. Sandwiched between them is a high dielectric coefficient of dielectric. To maintain the desired capacitance value, the size of the capacitor can be reduced by using a high-k dielectric. Polycrystalline silicon deposition is a type of low-pressure chemical vapor deposition (LPCVD), by placing arsenic (AH ₃ ), phosphorus (PH ₃ ) or diborane (B ₂ H ₆ ) in a reaction chamber (i.e., a furnace tube). By directly inputting the doping gas into the silicon material gas of silane or DCS, the polysilicon doping process of on-site low-pressure chemical vapor deposition can be performed. Polysilicon deposition is carried out under low pressure conditions of 0.2-1.0 Torr and deposition temperatures between 600 and 650°C, using pure silane or silane with a purity of 20% to 30% diluted with nitrogen. The deposition rate of both deposition processes is between 100-200Å/min, mainly determined by the temperature during deposition.

S600, ion implantation is performed on the upper layer of the silicon layer to form body region 4 and N+ region 7;

In this embodiment, ion implantation is used to form the N+ region 7 on the upper layer of the silicon layer, and the area of the silicon layer that has not been ion implanted forms the body region 4 . Ion implantation is to emit an ion beam in a vacuum towards a solid material. After the ion beam hits the solid material, its speed slowly slows down due to the resistance of the solid material, and finally stays in the solid material. The ions of an element are accelerated into a solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacturing of semiconductor devices, metal surface treatment, and materials science research. If the ions are stopped and retained in the target, the ions will change the elemental composition of the target (if the ions are of a different composition than the target). Ion implantation beamline designs all contain a common set of functional components. The main part of an ion beamline consists of a device called an ion source, which is used to generate ion species. The source is tightly coupled to a bias electrode to extract ions into the beamline, and most commonly to some means of selecting specific ion species for transport into the main accelerator section. Mass selection accompanies the extracted ion beam through the magnetic field region, with its exit path restricted by blocking holes or slits that only allow ions with mass and velocity/charge to continue along the beamline. If the target surface is larger than the ion beam diameter, and the implant dose is evenly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When injected into a semiconductor, each dopant atom can generate charge carriers in the semiconductor after annealing. A hole can be created for P-type dopants and an electron for N-type dopants. Changes the conductivity of the semiconductor near the doped region.

S700, ion implantation is performed on the upper layer of the drift layer 3 to form a P+ region 6;

S800, deposit source and drain 1.

Metal electrode deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to the method of chemically depositing coatings on the surface of wafers, generally by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

Both chemical vapor deposition (CVD) and physical vapor deposition (PVD) can be used as technical means to deposit metal electrodes. In this embodiment, the chemical vapor deposition method is used to deposit the metal electrode. The chemical vapor deposition process is divided into three stages: diffusion of the reaction gas to the surface of the substrate, adsorption of the reaction gas on the surface of the substrate, and chemical reaction on the surface of the substrate to form a solid deposit. And the gas phase by-products produced are separated from the substrate surface. The most common chemical vapor deposition reactions are: thermal decomposition reactions, chemical synthesis reactions and chemical transport reactions.

This embodiment takes advantage of the fact that silicon material has a higher channel mobility than silicon carbide material, and replaces part of the silicon carbide layer of SiC VDMOS with a silicon layer, so that the channel falls into the silicon material, thereby improving the channel mobility of SiC VDMOS. migration rate.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. A trench-gate VDMOS having a heterojunction, comprising: a silicon layer and a trench gate;

the silicon layer includes: a body region and an n+ region;

the silicon layer is positioned above the drift layer;

the silicon layer is adjacent to the drift layer;

the trench gate is located in the trench and adjacent to the silicon layer and the drift layer.

2. A trench-gate VDMOS with heterojunction as claimed in claim 1 characterized in that the thickness of the silicon layer is 1-15um.

3. A trench-gate VDMOS with heterojunction as claimed in claim 1, characterized in that the body region is located between the drift layer and the n+ region and adjoins the drift layer and the n+ region.

4. A trench-gate VDMOS with a heterojunction as claimed in claim 3, characterized in that the thickness of the body region is 1-15um.

5. A trench-gate VDMOS having a heterojunction as claimed in claim 3, characterized in that the doping concentration of the body region is 10 ¹⁷ cm ^-3 。

6. A trench-gate VDMOS having a heterojunction as claimed in claim 1, characterized in that the n+ region is located between and adjoining the trench gate and the body region.

7. The trench-gate VDMOS with heterojunction as claimed in claim 6, wherein the doping concentration of the n+ region is 10 ¹⁹ cm ^-3 。

8. A trench-gate VDMOS having a heterojunction as claimed in claim 1, further comprising: a silicon carbide layer;

the silicon carbide layer includes: a drift layer, a substrate and a P+ region;

the substrate is positioned above the drain electrode and is adjacent to the drain electrode and the drift layer;

the drift layer is positioned above the substrate and is adjacent to the body region;

the P+ region is positioned at two sides of the silicon layer.

9. A trench-gate VDMOS having a heterojunction as claimed in claim 8 wherein the silicon carbide layer has a thickness of 50-200um.

10. The preparation method of the trench gate VDMOS with the heterojunction is characterized by comprising the following steps of:

forming a drift layer on the silicon carbide layer in an epitaxial manner above the substrate;

etching a first trench over the drift layer;

depositing silicon in the first groove to form a silicon layer;

etching a through hole on the silicon layer, and etching a second groove on the drift layer, wherein the through hole is connected with the second groove;

depositing a gate in the second trench;

forming a body region and an N+ region by ion implantation on the upper layer of the silicon layer;

forming a P+ region on the upper layer of the drift layer by ion implantation;

and depositing a source electrode and a drain electrode.