CN117457731B - A SiC vertical IGBT with a P-type space layer under the gate and a preparation method thereof - Google Patents

Abstract

The present invention provides a SiC vertical IGBT with a P-type space layer under the gate and a preparation method. The SiC vertical IGBT includes: a P-type space layer; the P-type space layer is located between the gate, the N+ region and the drift layer and is adjacent to the gate oxide layer, the N+ region and the drift layer. The present invention introduces a P-type space layer under the trench gate. Because the thickness of the P-type space layer is very thin, when the gate is connected to a positive voltage, an inversion layer will be formed in the P-type space layer under a lower gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector. The gate oxide layer has a low mobility and a large resistance at the interface of the silicon carbide. The conductive path short-circuits the interface channel of the gate oxide layer, thereby reducing the on-resistance of the SiC vertical IGBT.

Description

A SiC vertical IGBT with a P-type space layer under the gate and a preparation method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a SiC vertical IGBT having a P-type space layer under a gate and a preparation method thereof.

Background technique

IGBT (Insulated Gate Bipolar Transistor) is the abbreviation of insulated gate bipolar transistor, which is composed of bipolar junction transistor (BJT) and metal oxide field effect transistor (MOSFET). It is a composite fully controlled voltage-driven switching power semiconductor device, a core device for realizing electric energy conversion, and one of the main development directions of MOS-bipolar power devices. IGBT not only has the characteristics of high input impedance and easy gate drive of MOSFET, but also has the advantages of high current density and high power density of bipolar transistor. It has been widely used in high voltage and high current fields such as rail transportation, new energy vehicles, smart grids, wind power generation, as well as low power household appliances such as microwave ovens, washing machines, induction cookers, electronic rectifiers, cameras, etc. The driving method of IGBT is basically the same as that of MOSFET. IGBT is also a three-terminal device with two electrodes on the front, namely the emitter and the gate, and the collector on the back. In the forward working state, the emitter is grounded or connected to a negative voltage, and the collector is connected to a positive voltage. The voltage between the two electrodes Vce>0, so the emitter and collector of IGBT are respectively called cathode and anode. IGBT can control the conduction/switching/blocking state of IGBT by controlling the size of its collector-emitter voltage Vce and gate-emitter voltage Vge. The switching function of IGBT is to form a channel by adding a forward gate voltage, provide base current to the PNP transistor, and turn on the IGBT. Conversely, adding a reverse gate voltage eliminates the channel, and the reverse base current flows, turning off the IGBT.

The maximum voltage of Si IGBT can reach 8.4 kV, which is close to the limit of Si devices, but the frequency and operating temperature also greatly limit the further development of Si IGBT in these fields. As a wide bandgap material, SiC has higher breakdown field strength, higher intrinsic temperature, higher thermal conductivity and higher carrier saturation drift velocity. Therefore, SiC IGBT devices show stronger competitiveness in the fields of high voltage, high temperature and high power. The maximum blocking voltage of SiC IGBT can reach 15kV, and it has less carrier storage effect. Since the atomic surface density per unit area of SiC is higher than that of Si, the density of dangling Si bonds, C bonds and carbon clusters at the interface is higher, more defects will be introduced when forming gate oxide, acting as electron traps, and the SiC/ _SiO2 interface defect problem will lead to reduced device reliability.

Summary of the invention

The purpose of the present invention is to provide a SiC vertical IGBT with a P-type space layer under the gate and a preparation method thereof. The SiC vertical IGBT introduces a P-type space layer under the trench gate. Because the thickness of the P-type space layer is very thin, when the gate is connected to a positive voltage, an inversion layer will be formed in the P-type space layer under a lower gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector. The interface mobility between the gate oxide layer and the silicon carbide is low and the resistance is large. The conductive path short-circuits the interface channel of the gate oxide layer, thereby reducing the on-resistance of the SiC vertical IGBT.

A SiC vertical IGBT having a P-type space layer below a gate comprises: a P-type space layer;

The P-type space layer is located between the gate, the N+ region and the drift layer and is adjacent to the gate oxide layer, the N+ region and the drift layer.

Preferably, the thickness of the P-type space layer is 80-100 nm.

Preferably, the doping concentration of the P-type space layer is 5×10 ¹⁵ to 10 ¹⁶ cm ⁻³ .

Preferably, it also includes: an N-buffer layer;

The N-buffer layer is located between the substrate and the drift layer and is adjacent to the substrate and the drift layer.

Preferably, the doping concentration of the N-buffer layer is 5×10 ¹⁷ to 10 ¹⁸ cm ⁻³ .

Preferably, the width of the P-type space layer is greater than or equal to the sum of the widths of the gate and the N+ region.

Preferably, it also includes: an emitter, a collector, a gate, a substrate, a buffer layer, a drift layer, and a P+ region;

The collector is located below the substrate;

The substrate is located below the buffer layer;

The buffer layer is located below the drift layer;

The drift layer is located below the P+ region;

The P+ region is located below the emitter;

The gate is located below the emitter;

The emitter is located above the N+ region, the P+ region and the gate.

A method for preparing a SiC vertical IGBT having a P-type space layer under a gate comprises:

epitaxially growing a buffer layer and a drift layer on the substrate;

Ion implantation is performed on the upper layer of the drift layer to form a P-type space layer, an N+ region and a P+ region;

Etching the N+ region to form a groove;

depositing a gate in the trench;

Deposit the emitter and collector.

Preferably, the step of implanting ions into the upper layer of the drift layer to form a P-type space layer, an N+ region and a P+ region comprises:

Ion implantation is performed on the upper layer of the drift layer to form a P-type space layer;

Ion implantation is performed on both sides of the P-type space layer to form a P+ region;

Ions are implanted into the upper layer of the P-type space layer to form an N+ region.

Preferably, the step of forming an N+ region by ion implantation on the upper layer of the P-type space layer comprises:

Ion implantation is performed above the P-type space layer with a thickness of 80-100 nm to form an N+ region.

The present invention introduces a P-type space layer under the trench gate. Since the thickness of the P-type space layer is very thin, when the gate is connected to a positive voltage, an inversion layer will be formed in the P-type space layer under a relatively low gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector. The interface mobility between the gate oxide layer and the silicon carbide is low, and the resistance is large. The conductive path short-circuits the interface channel of the gate oxide layer, thereby reducing the on-resistance of the SiC vertical IGBT.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

FIG1 is a schematic diagram of the structure of a SiC vertical IGBT of the present invention;

FIG2 is a schematic diagram of a SiC vertical IGBT preparation process method of the present invention;

FIG. 3 is a schematic structural diagram of the SiC vertical IGBT preparation process of the present invention.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

The maximum voltage of Si IGBT can reach 8.4 kV, which is close to the limit of Si devices, but the frequency and operating temperature also greatly limit the further development of Si IGBT in these fields. As a wide bandgap material, SiC has higher breakdown field strength, higher intrinsic temperature, higher thermal conductivity and higher carrier saturation drift velocity. Therefore, SiC IGBT devices show stronger competitiveness in the fields of high voltage, high temperature and high power. The maximum blocking voltage of SiC IGBT can reach 15kV, and it has less carrier storage effect. Since the atomic surface density per unit area of SiC is higher than that of Si, the density of dangling Si bonds, C bonds and carbon clusters at the interface is higher, more defects will be introduced when forming gate oxide, acting as electron traps, and the SiC/ _SiO2 interface defect problem will lead to reduced device reliability.

The present invention introduces a P-type space layer under the trench gate. Since the thickness of the P-type space layer is very thin, when the gate is connected to a positive voltage, an inversion layer will be formed in the P-type space layer under a relatively low gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector. The interface mobility between the gate oxide layer and the silicon carbide is low, and the resistance is large. The conductive path short-circuits the interface channel of the gate oxide layer, thereby reducing the on-resistance of the SiC vertical IGBT.

Example 1

A SiC vertical IGBT having a P-type space layer below a gate, referring to FIG1 , comprises: a P-type space layer;

The substrate of the PN junction is divided into P type and N type, + is heavily doped (high doping concentration), - is lightly doped (low doping concentration), P type is doped with IIIA group elements, such as boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl). N type is doped with VA group elements, such as nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and magnesium (Mc).

The P-type space layer is located between the gate, the N+ region and the drift layer and is adjacent to the gate oxide layer, the N+ region and the drift layer.

The P-type space layer is a P-type doped semiconductor. The P-type space layer is set between the N+ region and the drift layer. The gate can open the conductive path located in the P-type space layer. When the gate is connected to a positive voltage, the gate can attract the negative charge located in the P-type space layer, thereby forming an inversion layer under the gate. The current can flow from the emitter to the N+ region, then from the N+ region to the P-type space layer, from the P-type space layer to the drift layer, and finally from the drift layer to the collector.

Since the thickness of the P-type space layer is very small, the P-type space layer can form a conductive path from the N+ region to the drift layer under a lower gate voltage, thereby overcoming the problem of low interface mobility between silicon carbide and silicon dioxide, greatly reducing the channel resistance, and significantly improving the electrical performance of the SiC vertical IGBT.

Preferably, the thickness of the P-type space layer is 80-100 nm.

The thickness of the P-type space layer will affect the turn-on voltage of the conductive channel, because the opening of the conductive channel requires the P-type space layer to be completely transformed into an inversion layer in the vertical direction. Therefore, the greater the thickness of the P-type space layer, the more difficult it is to completely sense the P-type space layer as an inversion layer in the vertical direction, and the higher the required gate voltage. Therefore, the thickness of the P-type space layer should not be too thick, otherwise it will make it difficult for the gate to sense the formation of an inversion layer, the turn-on voltage required for the conductive channel will be too high, and the on-resistance will also increase accordingly. The thickness of the P-type space layer should not be too thin. If the thickness of the P-type space layer is too small, electrons will pass through the P-type space layer more easily. Therefore, a too thin P-type space layer will cause leakage of the SiC vertical IGBT and reduce the voltage resistance. As a preferred embodiment, the present invention sets the thickness of the P-type space layer to 100nm, in order to reduce the channel resistance while ensuring that the SiC vertical IGBT has good voltage resistance and stability.

Preferably, the doping concentration of the P-type space layer is 5×10 ¹⁵ to 10 ¹⁶ cm ⁻³ .

The doping concentration of the P-type space layer affects the turn-on voltage of the conductive channel, because most carriers in the P-type semiconductor are holes, and the principle of the gate turning on the conductive channel is to attract electrons in the P-type space layer to form a conductive channel. The higher the doping concentration of the P-type semiconductor, the higher the concentration of holes and the lower the concentration of electrons. It is more difficult for the gate to attract electrons to form a conductive channel, and a higher gate voltage is required to form an inversion layer in the P-type space layer. Therefore, the higher the doping concentration of the P-type space layer, the higher the turn-on voltage of the conductive channel, and the lower the doping concentration of the P-type space layer, the lower the turn-on voltage of the conductive channel. If the doping concentration of the P-type space layer is too low, it will cause leakage of the SiC vertical IGBT and reduce the withstand voltage performance. As a preferred embodiment, the present invention sets the doping concentration of the P-type space layer to 10 ¹⁶ cm ^-3 , in order to reduce the channel resistance while ensuring that the SiC vertical IGBT has good withstand voltage and stability.

Preferably, it also includes: an N-buffer layer;

The N-buffer layer is located between the substrate and the drift layer and is adjacent to the substrate and the drift layer.

The N-buffer layer is a buffer layer, and its main function is to block the expansion of the depletion layer of the SiC vertical IGBT during forward blocking, so that the SiC vertical IGBT can achieve the same forward blocking capability as the non-punch-through IGBT with a smaller drift layer width. While improving the switching speed of the SiC vertical IGBT, it maintains a low on-state voltage drop and has better forward blocking characteristics.

When the gate voltage is greater than the threshold voltage, the SiC vertical IGBT starts to conduct, the gate induces an inversion layer in the P-type space layer, forms a conductive channel in the P-type space layer, and electrons are injected into the drift layer through the conductive channel, while promoting the hole injection in the collector P+ region. Since the drift layer width is very large, most of the holes recombine with the electrons injected from the conductive channel in the drift layer. The remaining holes diffuse from the drift layer to the PN junction formed by the drift layer and the P+ region. Since the PN junction formed by the drift layer and the P+ region is slightly reverse biased, the holes are captured by the electric field and enter the P+ region through the space charge region. Since the drift layer adopts a low doping concentration in order to achieve high blocking voltage capability, the hole concentration under medium current density exceeds the doping concentration of the drift layer. Therefore, the drift layer is in a state of large injection, accompanied by a strong conductivity modulation effect, which enables the SiC vertical IGBT to maintain a good low on-state voltage drop and high current density in the on-state. Therefore, the present invention sets the buffer layer between the drift layer and the substrate, which significantly improves the switching speed of the SiC vertical IGBT.

Preferably, the doping concentration of the N-buffer layer is 5×10 ¹⁷ to 10 ¹⁸ cm ⁻³ .

In a punch-through IGBT, a highly doped buffer layer needs to be provided between the substrate and the drift layer to increase the switching speed of the IGBT and maintain a low on-state voltage drop. If the doping concentration of the N-buffer layer is too low, the expansion of the depletion layer cannot be blocked. If the doping concentration of the N-buffer layer is too high, it cannot be depleted. As a preferred embodiment, the present invention sets the doping concentration of the N-buffer layer to 10 ¹⁸ cm ^-3 .

Preferably, the width of the P-type space layer is greater than or equal to the sum of the widths of the gate and the N+ region.

The minimum width of the P-type space layer is the sum of the width of the gate and the width of the N+ region. If the width of the P-type space layer is smaller than the sum of the width of the gate and the width of the N+ region, it will cause partial leakage of the SiC vertical IGBT. If the P-type space layer does not fully extend to the bottom of the N+ region, the N+ region that forms an ohmic contact with the emitter will partially leak, and part of the current will flow directly to the N column and then to the drain, causing leakage of the SiC vertical IGBT and circuit damage, thereby reducing the safety and reliability of the SiC vertical IGBT.

Preferably, it also includes: an emitter, a collector, a gate, a substrate, a buffer layer, a drift layer, and a P+ region;

The collector is located below the substrate;

The collector is used to collect and output electrons, converting the electron flow into current output.

The substrate is located below the buffer layer;

The substrate is a material used to support crystal growth in the IGBT, and the substrate plays a role of mechanical support. In the present invention, the substrate is made of silicon carbide material, and its mechanical strength and stability can effectively support various stresses and distortions during the crystal growth process. This is crucial to ensure the uniformity and integrity of crystal growth. In addition, the substrate can also prevent impurities and defects during the crystal growth process, thereby improving the quality of the IGBT. Secondly, the substrate plays an important role in the electrical properties of the IGBT. When preparing the IGBT, the electrical properties of the substrate determine the performance and stability of the device. For example, the conductivity of the substrate directly affects the efficiency and speed of current transmission. In addition, the electron affinity and bandgap width of the substrate are also crucial for adjusting the threshold voltage and electron mobility of the IGBT. In addition, the substrate also plays an important role in isolating the insulating layer of the IGBT. In the process of preparing the IGBT, the insulating layer of the substrate is usually composed of silicon dioxide. The quality and characteristics of the insulating layer directly affect the insulation properties of the IGBT, such as electrical insulation and capacitance characteristics. A good insulating layer can effectively isolate different electrodes in the IGBT structure and reduce leakage current and capacitive coupling effects.

The buffer layer is located below the drift layer;

The P-type substrate, as the collector region of the SiC vertical IGBT, has a high concentration and is difficult to thin. In order to reduce the injection efficiency of hole carriers on the collector side, an N+ buffer layer is usually epitaxially grown between the drift layer and the substrate to block some hole injection. In the blocking state, the buffer layer also plays the role of cutting off the electric field in the drift region.

The drift layer is located below the P+ region;

The electric field distribution in the drift layer plays a key role in the conduction characteristics and current control of the IGBT. When the gate voltage is applied to the IGBT, the electric field distribution in the drift layer is modulated by the gate voltage, thereby controlling the current flow between the source and the drain. When the IGBT is working, the current between the source and the drain is mainly transmitted through the drift layer. The doping type and concentration of the drift layer determine the conduction type (N-type or P-type) and size of the current. The structure and characteristics of the drift layer directly affect the current control capability of the IGBT. By adjusting the shape, size and doping concentration of the drift layer, precise control of the current can be achieved to meet the requirements of different applications.

The P+ region is located below the emitter;

The gate is located below the emitter;

The gate is the control electrode in the IGBT. It is separated from the channel by an insulating layer and is a key part of the IGBT. The voltage change of the gate can change the charge density in the channel, thereby controlling the current between the emitter and the collector.

The emitter is located above the N+ region, P+ region and the gate.

The emitter is used to supply electrons and control the current.

Example 2

A method for preparing a SiC vertical IGBT having a P-type space layer under a gate, referring to FIG. 2 and FIG. 3, comprises:

S100, epitaxially growing a buffer layer and a drift layer on the substrate;

Epitaxial process refers to the process of growing a completely ordered single crystal layer on a substrate. The epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial process is widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxial methods are solid phase epitaxy and vapor phase epitaxy.

Solid phase epitaxy refers to the growth of a single crystal layer on a substrate using a solid source. For example, thermal annealing after ion implantation is actually a solid phase epitaxy process. During ion implantation, the silicon atoms of the silicon wafer are bombarded by high-energy implanted ions, leaving their original lattice positions and becoming amorphous, forming a surface amorphous silicon layer. After high-temperature thermal annealing, the amorphous atoms return to their lattice positions and remain consistent with the atomic crystal orientation inside the substrate.

The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. In the embodiment of the present invention, chemical vapor epitaxy (CVE) is used to form the N-drift layer. The principles of chemical vapor epitaxy and chemical vapor deposition (CVD) are basically the same. Both are processes for depositing thin films by chemically reacting on the surface of the wafer after gas mixing; the difference is that because chemical vapor epitaxy grows a single crystal layer, the requirements for the impurity content in the equipment and the cleanliness of the silicon wafer surface are higher. In integrated circuit manufacturing, CVE can also be used for epitaxial silicon wafer process. The epitaxial silicon wafer process is to epitaxially grow a layer of single crystal silicon on the surface of the silicon wafer. Compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, thereby improving the yield of semiconductor manufacturing. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as reducing substrate resistance and enhancing substrate isolation.

S200, ion implantation is performed on the upper layer of the drift layer to form a P-type space layer, an N+ region and a P+ region;

The present invention adopts ion implantation to form a P-type space layer, an N+ region and a P+ region on the upper layer of the drift layer. Ion implantation is to launch an ion beam in a vacuum toward a solid material. After the ion beam hits the solid material, it is resisted by the solid material and its speed is slowly reduced, and finally stays in the solid material. The ions of an element are accelerated into a solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacture of semiconductor devices, metal surface treatment and material science research. If the ions stop and remain in the target, the ions will change the elemental composition of the target (if the ions are different from the composition of the target). The ion implantation beam line design contains a common functional component group. The main part of the ion beam line includes a device called an ion source for generating ion species. The source is closely coupled with a bias electrode to extract ions into the beam line, and most commonly is coupled with a certain way of selecting specific ion species for transmission to the main accelerator part. Mass selection accompanies the extracted ion beam through a magnetic field region with its exit path restricted by blocking holes or slits that allow only ions with the mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter, and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the surface to be implanted is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each dopant atom can create a charge carrier in the semiconductor after annealing. It can create a hole for a P-type dopant and an electron for an N-type dopant. This changes the conductivity of the semiconductor near the doped area.

S300, etching the N+ region to form a groove;

Etching is the process of selectively removing unwanted materials from the surface of silicon wafers by chemical or physical methods. It is a general term for stripping and removing materials by solutions, reactive ions or other mechanical methods. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Hereby, argon ions are irradiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they impact the material on the surface. The wafer is fed vertically or tilted into the ion beam and the etching process is absolutely anisotropic. The selectivity is low, since there is no differentiation of the individual layers. The gases and the ablated material are evacuated by the vacuum pump, however, since the reaction products are not gaseous, particles can be deposited on the wafer or on the chamber walls. All materials can be etched with this method and due to the vertical irradiation, the wear on the vertical walls is low.

Plasma etching is a chemical etching process with the advantage that the wafer surface is not damaged by accelerated ions. Due to the mobile particles of the etching gas, the etching profile is isotropic, so this method is used to remove entire film layers (such as backside cleaning after thermal oxidation). One type of reactor used for plasma etching is a downstream reactor, whereby the plasma is ignited at a high frequency of 2.45 GHz by impact ionization, the location of which is separated from the wafer.

The etching rate depends on the pressure, the power of the HF generator, the process gas, the actual gas flow rate and the wafer temperature. Anisotropy increases with increasing HF power, decreasing pressure and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed inhomogeneously, which leads to inhomogeneities. If the distance of the electrodes is increased, the etching rate decreases because the plasma is distributed in an enlarged volume. For the electrodes, carbon has proven to be the material of choice. Since fluorine and chlorine also attack carbon, the electrodes produce a uniform strained plasma, so the wafer edge is affected in the same way as the wafer center. Selectivity and etching rate depend largely on the process gas. For silicon and silicon compounds, fluorine and chlorine are mainly used.

S400, depositing a gate in the trench;

The gate electrode is deposited by polysilicon deposition. Polysilicon deposition is to form a gate electrode and local wiring on the first layer of polysilicon (Poly1) stacked with silicide, and the second layer of polysilicon (Poly2) forms a contact plug between the source/drain and the unit wiring. The silicide is stacked on the third layer of polysilicon (Poly3) to form the unit wiring, and the fourth layer of polysilicon (Poly4) and the fifth layer of polysilicon (Poly5) form the two electrodes of the storage capacitor, sandwiched between which is a high-dielectric dielectric. In order to maintain the required capacitance value, the size of the capacitor can be reduced by using a high-dielectric dielectric. Polysilicon deposition is a low-pressure chemical vapor deposition (LPCVD). By directly inputting the doping gas of arsenic (AH ₃ ), phosphine (PH ₃ ) or diborane (B ₂ H ₆ ) into the silicon material gas of silane or DCS in the reaction chamber (i.e., the furnace tube), the polysilicon doping process of on-site low-pressure chemical vapor deposition can be carried out. Polysilicon deposition is carried out at low pressure conditions of 0.2-1.0 Torr and deposition temperatures between 600 and 650°C, using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rates of both deposition processes are between 100-200Å/min, mainly determined by the temperature during deposition.

S500, depositing the emitter and collector.

Metal electrode deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to a method of depositing a coating on a wafer surface by chemical means, generally by applying energy to a mixed gas. Assuming that a substance (A) is deposited on the surface of a wafer, two gases (B and C) that can generate substance (A) are first input into the deposition equipment, and then energy is applied to the gases to cause a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputtering, arc plasma coating, ion coating and molecular beam epitaxy. The corresponding vacuum coating equipment includes vacuum evaporation coating machine, vacuum sputtering coating machine and vacuum ion coating machine.

Chemical vapor deposition (CVD) and physical vapor deposition (PVD) can both be used as technical means for depositing metal electrodes. In the embodiment of the present invention, the metal electrode is deposited by chemical vapor deposition, and the chemical vapor deposition process is divided into three stages: diffusion of the reaction gas to the substrate surface, adsorption of the reaction gas on the substrate surface, chemical reaction on the substrate surface to form solid deposits, and separation of the generated gas phase byproducts from the substrate surface. The most common chemical vapor deposition reactions are: thermal decomposition reaction, chemical synthesis reaction, and chemical transport reaction.

Preferably, S200, forming a P-type space layer, an N+ region and a P+ region by ion implantation in the upper layer of the drift layer includes:

S210, ion implantation is performed on the upper layer of the drift layer to form a P-type space layer;

S220, ion implantation is performed on both sides of the P-type space layer to form a P+ region;

S230, ion implantation is performed on the upper layer of the P-type space layer to form an N+ region.

On the upper layer of the drift layer, ion implantation is performed according to the pre-set positions and doping concentrations of the P-type space layer, N+ region, and P+ region. First, a P-type space layer with a thickness of 80-100nm is deposited on the upper layer of the drift layer. Then, pentavalent ion implantation is continued on both sides of the P-type space layer to form a P+ region of a P-type semiconductor with a higher doping concentration. Then, trivalent ion implantation is performed above the P-type space layer to convert the N column with a low doping concentration into an N+ region with a high doping concentration, completing the preparation of the semiconductor structure.

Preferably, S230, forming an N+ region by ion implantation on the upper layer of the P-type space layer includes:

Ion implantation is performed above the P-type space layer with a thickness of 80-100 nm to form an N+ region.

When performing ion implantation above the P-type space layer to form an N+ region, it is necessary to ensure that the thickness of the P-type space layer is not less than 80nm. In order to more easily control the thickness of the P-type space layer, the present invention first implants all the N columns into the P-type space layer, and then performs ion implantation on the upper layer of the P-type space layer with a thickness of 80-100nm to form an N+ region, that is, retaining the bottom P-type space layer with a thickness of 80-100nm, and partially implanting ions in the upper layer to form an N+ region.

The present invention introduces a P-type space layer under the trench gate. Since the thickness of the P-type space layer is very thin, when the gate is connected to a positive voltage, an inversion layer will be formed in the P-type space layer under a relatively low gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector. The interface mobility between the gate oxide layer and the silicon carbide is low, and the resistance is large. The conductive path short-circuits the interface channel of the gate oxide layer, thereby reducing the on-resistance of the SiC vertical IGBT.

The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims (6)

1. A SiC vertical IGBT having a P-type space layer under a gate, characterized in that it comprises: a P-type space layer, an emitter, a gate, a P+ region, an N+ region and a drift layer; The P-type space layer is located between the gate, the N+ region and the drift layer and is adjacent to the gate oxide layer, the N+ region and the drift layer; The P-type space layer is adjacent to the bottom surface of the gate; The thickness of the P-type space layer is 80-100 nm; The doping concentration of the P-type space layer is 5×10 ¹⁵ to 10 ¹⁶ cm ^-3 ; The width of the P-type space layer is greater than or equal to the sum of the widths of the gate and the N+ region; The emitter is located above the N+ region, the gate and the P+ region, and is adjacent to the P+ region, the N+ region and the gate; The gate is located below the emitter; The P+ region is located below the emitter and is adjacent to the N+ region; The N+ region is located below the emitter and on both sides of the gate; The thickness of the N+ region is equal to the thickness of the gate trench; The thickness of the P+ region is greater than the thickness of the gate trench; Also includes: N-buffer layer; The N-buffer layer is located between the substrate and the drift layer and is adjacent to the substrate and the drift layer. 2 . The SiC vertical IGBT having a P-type space layer under the gate according to claim 1 , wherein the doping concentration of the N-buffer layer is 5×10 ¹⁷ to 10 ¹⁸ cm ⁻³ . 3. The SiC vertical IGBT with a P-type space layer under the gate according to claim 1, characterized in that it also includes: a collector, a substrate, and a buffer layer; The collector is located below the substrate; The substrate is located below the buffer layer; The buffer layer is located below the drift layer. 4. A method for preparing a SiC vertical IGBT having a P-type space layer under a gate, the method being applied to preparing a SiC vertical IGBT having a P-type space layer under a gate as claimed in any one of claims 1 to 3, characterized in that it comprises: epitaxially growing a buffer layer and a drift layer on the substrate; Implanting ions on the upper layer of the drift layer to form a P-type space layer, an N+ region and a P+ region; Etching the N+ region to form a groove; depositing a gate in the trench; Deposit the emitter and collector. 5. The method for preparing a SiC vertical IGBT having a P-type space layer under the gate according to claim 4, characterized in that the step of implanting ions on the upper layer of the drift layer to form the P-type space layer, the N+ region and the P+ region comprises: Ion implantation is performed on the upper layer of the drift layer to form a P-type space layer; Ion implantation is performed on both sides of the P-type space layer to form a P+ region; Ions are implanted into the upper layer of the P-type space layer to form an N+ region. 6. The method for preparing a SiC vertical IGBT having a P-type space layer below the gate according to claim 5, characterized in that the step of forming an N+ region by ion implantation on the upper layer of the P-type space layer comprises: Ion implantation is performed above the P-type space layer with a thickness of 80-100 nm to form an N+ region.