CN117410322B - Groove type super junction silicon MOSFET and preparation method - Google Patents

Abstract

The invention discloses a groove type super junction silicon MOSFET and a preparation method thereof, wherein the MOSFET comprises the following components: trench gate, P-pillar and N-pillar; the trench gate comprises a first extension part and a second extension part; the first extension part is positioned between and adjacent to the Pwell layers; the second extension part is positioned between and adjacent to the Pwell layer, the first extension part, the P column and the N column; the first end of the first extension part is connected with the second extension part; the first extension part and the second extension part form an inverted T shape; the P column is positioned among the Pwell layer, the second extension part, the N column and the substrate; the P column is adjacent to the Pwell layer, the N column and the substrate; the N column is positioned between the second extension part, the P column and the substrate; the N pillars are adjacent to the substrate. According to the invention, the trench is extended on the basis of the traditional vertical trench, so that the length of the grid electrode positioned in the trench is increased, the channel length of the super-junction silicon MOSFET is increased due to the increase of the length of the grid electrode, and the thermal stability of the super-junction silicon MOSFET device is improved.

Description

A trench type super junction silicon MOSFET and preparation method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a trench type super junction silicon MOSFET and a preparation method thereof.

Background technique

Trench MOSFET devices are a new type of vertical MOSFET device, which is optimized and developed based on the traditional planar MOSFET structure. Compared with planar MOSFET devices, trench MOSFET devices construct the bottom trench structure through the body region, and the channel formed is located between the source region and the drift region, eliminating the JFET region and the JFET resistance; at the same time, the trench gate structure of trench MOSFET devices makes the cell spacing smaller than that of planar MOSFET devices, and more cells can be connected in parallel in design, further reducing the total resistance. Therefore, trench MOSFET devices can obtain smaller on-resistance.

In the transfer characteristic curve, when the threshold voltage does not change with temperature under a certain gate-source voltage, this point is called point A. When the actual gate-source voltage is less than the gate-source voltage at point A, the threshold voltage of the trench superjunction silicon MOSFET is negatively correlated with temperature, that is, the higher the temperature, the lower the threshold voltage of the superjunction silicon MOSFET. The wider and shallower the conductive channel of the superjunction silicon MOSFET is, the greater the channel current generated; the increase in channel current will cause the MOSFET device to heat up, and the increase in temperature will cause the threshold voltage to decrease, and the output current of the superjunction silicon MOSFET will increase, thus forming a positive feedback, causing the superjunction silicon MOSFET device to fail thermally.

Summary of the invention

In order to solve at least one of the technical problems mentioned above, an object of the present invention is to provide a trench type super junction silicon MOSFET and a preparation method to solve the thermal instability problem of trench type super junction silicon MOSFET.

The purpose of the present invention is achieved by the following technical means:

In a first aspect, the present invention provides a trench type super junction silicon MOSFET, comprising: a trench gate, a P column and an N column;

The trench gate includes a first extension portion and a second extension portion;

The first extension portion is located between the Pwell layers and is adjacent to the Pwell layers;

The second extension portion is located between the Pwell layer, the first extension portion, the P column and the N column and is adjacent to the Pwell layer, the P column and the N column;

The first end of the first extension portion is connected to the second extension portion;

The first extension portion and the second extension portion form an inverted T shape;

The P column is located between the Pwell layer, the second extension, the N column and the substrate;

The P column is adjacent to the Pwell layer, the N column and the substrate;

The N column is located between the second extension, the P column and the substrate;

The N column is adjacent to the substrate.

Preferably, the trench gate further includes a third extension portion;

The third extension portion is located above the Pwell layer and the first extension portion and is adjacent to the Pwell layer;

The third extension portion is connected to the second end of the first extension portion;

The first extension portion, the second extension portion and the third extension portion form an I-shape.

Preferably, the length of the second extension portion is 300-600 nm.

Preferably, the thickness of the second extension portion is 300 nm.

Preferably, the length of the third extension portion is 300-600 nm.

Preferably, the thickness of the third extension portion is 300 nm.

Preferably, the width of the P column is 3.5um;

The width of the N column is 3.5 um.

Preferably, the doping concentration of the P column is 6×10 ¹⁵ cm ^-3 ;

The doping concentration of the N column is 6×10 ¹⁵ cm ⁻³ .

Preferably, it also includes: a drain, a substrate, a Pwell layer, a P+ layer, an N+ layer and a source;

The drain is located below the substrate;

The substrate is located below the P column and the N column;

The Pwell layer is located above the P column;

The P+ layer and the N+ layer are located above the Pwell layer;

The source is located above the N+ layer.

In a second aspect, the present invention provides a method for preparing a trench super junction silicon MOSFET, comprising:

Epitaxially forming a P column and an N column on the substrate;

Depositing a first oxide layer and a polycrystalline material above the P column and the N column;

etching the first oxide layer and the polycrystalline material;

Depositing a second oxide layer on the top and sidewall of the polycrystalline material to form a second extension;

Extending the P column to a height of a second extension portion;

depositing an active layer over the P column and the second extension;

Etching the active layer above the second oxide layer to form a groove;

Ion implantation is performed on the active layer at both sides of the groove to form a Pwell layer;

Depositing a third oxide layer above the Pwell layer and on the sidewalls of the trench;

etching the second oxide layer and the third oxide layer;

Depositing the polycrystalline material along the third oxide layer to form a first extension and a third extension;

Ion implantation is performed on the upper layer of the Pwell layer to form an N+ layer and a P+ layer;

Depositing a fourth oxide layer over the third extension, the N+ layer and the P+ layer;

The fourth oxide layer is etched above the N+ layer to form a contact hole.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention extends the trench on the basis of the traditional vertical trench, so that the length of the gate located in the trench is increased. The increase in the gate length will increase the channel length of the super junction silicon MOSFET. The increase in the channel length will reduce the gate-source voltage corresponding to point A, reduce the range of negative feedback, and increase the temperature. The threshold voltage increases, thereby reducing the channel current and improving the thermal stability of the super junction silicon MOSFET device.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

FIG1 is a schematic diagram of the structure of a trench super junction silicon MOSFET provided by an embodiment of the present invention;

FIG2 is a schematic flow chart of a method for preparing a trench super junction silicon MOSFET according to an embodiment of the present invention;

FIG3 is a schematic structural diagram A of a method for preparing a trench super junction silicon MOSFET provided by an embodiment of the present invention;

FIG4 is a schematic structural diagram B of a method for preparing a trench super junction silicon MOSFET provided by an embodiment of the present invention;

FIG5 is a structural schematic diagram C of a method for preparing a trench super junction silicon MOSFET provided in an embodiment of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

The term "and/or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

In addition, in order to better illustrate the present invention, numerous specific details are provided in the following specific embodiments. It should be understood by those skilled in the art that the present invention can be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

In the transfer characteristic curve, when the threshold voltage does not change with temperature under a certain gate-source voltage, this point is called point A. When the actual gate-source voltage is less than the gate-source voltage at point A, the threshold voltage of the superjunction silicon MOSFET is negatively correlated with temperature, that is, the higher the temperature, the lower the threshold voltage of the superjunction silicon MOSFET. The wider and shallower the conductive channel of the superjunction silicon MOSFET is, the greater the channel current generated; the increase in channel current will cause the MOSFET device to heat up, and the increase in temperature will cause the threshold voltage to decrease, and the output current of the superjunction silicon MOSFET will increase, thus forming a positive feedback, causing the superjunction silicon MOSFET device to fail thermally.

The present invention extends the trench on the basis of the traditional vertical trench, so that the length of the gate located in the trench is increased. The increase in the gate length will increase the channel length of the super junction silicon MOSFET. The increase in the channel length will reduce the gate-source voltage corresponding to point A, reduce the range of negative feedback, and increase the temperature. The threshold voltage increases, thereby reducing the channel current and improving the thermal stability of the super junction silicon MOSFET device.

Example 1

A trench type super junction silicon MOSFET is provided, referring to FIG1 , comprising: a trench gate, a P column and an N column;

The trench gate includes a first extension portion and a second extension portion;

The first extension portion is located between the Pwell layers and adjacent to the Pwell layers;

The second extension portion is located between the Pwell layer, the first extension portion, the P column and the N column and is adjacent to the Pwell layer, the P column and the N column;

The first end of the first extension portion is connected to the second extension portion;

The first extension portion and the second extension portion form an inverted T shape;

The channel is a thin semiconductor layer between the source and drain in MOSFET. Applying an external electric field to MOSFET is a common method to open the channel. When voltage is applied to the MOSFET gate, an inversion layer is formed in the MOSFET along the direction of the electric field, in which current flows and is controlled by the gate. Thermal failure refers to the phenomenon that MOSFET performance degrades or completely fails in a high temperature environment. The channel current is negatively correlated with the length of the channel. Excessive channel current will cause the MOSFET device to heat up and the temperature will rise, causing the MOSFET device to fail thermally.

In this embodiment, the first extension portion is a vertical portion in the middle of the trench gate, and the second extension portion is a horizontal portion at the bottom of the trench gate. The second extension portion is obtained by extending the bottom of the first extension portion on the basis of the first extension portion. The inverted T-shaped trench gate formed by the first extension portion and the second extension portion has a longer gate length than the vertical trench gate, so that the trench length of the super junction silicon MOSFET is increased, thereby improving the thermal stability of the super junction silicon MOSFET device.

The P column is located between the Pwell layer, the second extension, the N column and the substrate;

The P column is adjacent to the Pwell layer, the N column, and the substrate;

The N column is located between the second extension, the P column and the substrate;

The N column is adjacent to the substrate.

For MOSFET devices with traditional structures, the reverse withstand voltage mainly relies on a single N-type doped drift region. Starting from the PN junction surface, the electric field gradually decreases. In order to increase the breakdown voltage, it is necessary to increase the thickness of the drift region or reduce the doping concentration of the drift region, but such conditions lead to an increase in on-resistance. The superjunction structure is proposed to solve the problem of silicon limit. The superjunction structure can introduce an additional electric field in the body of the device, greatly reducing the on-resistance of the device under the same breakdown voltage. Compared with the traditional structure, the superjunction structure greatly reduces the energy loss and achieves more efficient energy use efficiency. The biggest feature of the superjunction structure is that the original single doped N-type drift region is transformed into a doped N-type drift region and a P-type drift region. During the reverse withstand voltage, the two charges compensate each other laterally, and the longitudinal electric field becomes very uniform, thereby increasing the breakdown voltage of the device. In addition, the doping concentration of the drift region of the superjunction structure is higher than that of the drift region of the traditional structure, which reduces the on-resistance of the MOSFET device while increasing the breakdown voltage.

In order to ensure that the high-voltage power MOSFET has sufficient breakdown voltage, the most direct way to reduce the on-resistance is to separate the reverse blocking voltage from the on-resistance function and design them in different areas. In this embodiment, the N column is sandwiched between the P columns on both sides. When the trench MOSFET device is turned off, two reverse-biased PN junctions are formed, namely the P column and the N column and the P-well and the N column. The P-well cannot form an inversion layer to generate a conductive channel. The P column and the N column form a reverse bias, the PN junction depletion layer increases, and a lateral electric field is established; the PN junction formed by the P-well and the N column is also reverse biased, generating a wide depletion layer and establishing a vertical electric field. The entire area of the N column is basically turned into a depletion layer with a very high longitudinal blocking voltage. When the trench MOSFET device is turned on, the electric field of the gate and the source inverts the P-well to generate an N-type conductive channel. The electrons in the source region enter the N column through the conductive channel, neutralize the holes in the N column, and thus restore the doping concentration of the N column, so that the conductive channel is formed. The doping concentration of the N column increases, and it has a lower resistivity, thereby reducing the on-resistance.

Preferably, the trench gate further comprises a third extension portion;

The third extension portion is located above the Pwell layer and the first extension portion and is adjacent to the Pwell layer;

The third extension portion is connected to the second end of the first extension portion;

The first extension portion, the second extension portion and the third extension portion form an I-shape.

There are certain limitations in extending the bottom of the first extension portion to obtain the second extension portion to increase the length of the trench gate. The second extension portion occupies the space in the horizontal direction of the N-drift layer. In the actual manufacturing process, the length of the second extension portion is too long, which will increase the area of the super junction silicon MOSFET device. In some embodiments, the third extension portion is the horizontal portion at the top of the trench gate. The second extension portion and the third extension portion are obtained by extending the bottom and top of the first extension portion respectively on the basis of the first extension portion. The I-shaped trench gate composed of the first extension portion, the second extension portion and the third extension portion has a longer gate length than the vertical trench gate, so that the trench length of the super junction silicon MOSFET is increased, and the thermal stability of the super junction silicon MOSFET device is improved.

Preferably, the length of the second extension portion is 300-600 nm.

The gate is used as a control element of the MOSFET to control the opening and closing of the channel, and the length of the channel depends on the length of the gate. The increase in the channel length can reduce the channel current, thereby reducing the heating temperature of the MOSFET and improving the thermal stability of the MOSFET device. However, if the length of the groove is too long, the on-resistance of the MOSFET will increase, reducing the working efficiency and power handling capacity of the MOSFET; if the length of the groove is too long, the switching speed of the MOSFET will be reduced, reducing the response speed of the MOSFET; if the length of the groove is too long, the leakage current of the MOSFET will be increased, and the energy consumption of the MOSFET will be increased. When designing a MOSFET, it is necessary to weigh the choice of the channel length to balance the performance and stability of the MOSFET. In this embodiment, the length of the second extension portion is set to 300-600nm. As a preferred embodiment, the present invention sets the length of the second extension portion to 500nm. It should be noted that the length of the second extension portion refers to its length in the horizontal direction.

Preferably, the thickness of the second extension portion is 300 nm.

The thickness of the gate affects the performance of the MOSFET device. A larger gate thickness can provide a larger current path, improve the switching speed of the MOSFET device, and is not easily affected by charge accumulation and heat accumulation, thereby improving the reliability of the MOSFET device; however, a larger gate thickness will result in greater power and heat generation, increasing the power consumption of the MOSFET device. When designing a MOSFET, it is necessary to select a suitable gate thickness to ensure that the MOSFET device operates stably and reliably. In this embodiment, the thickness of the second extension portion is set to 300nm, and the thickness of the third extension portion is set to 300nm.

Preferably, the length of the third extension portion is 300-600 nm.

There are certain limitations in extending the bottom of the first extension portion to obtain the second extension portion to increase the length of the trench gate. The second extension portion occupies the space in the horizontal direction of the N-drift layer. In the actual manufacturing process, the excessive length of the second extension portion will increase the area of the super junction silicon MOSFET device. The third extension portion is obtained by extending the top of the first extension portion, and the second extension portion and the third extension portion jointly increase the length of the gate. In some embodiments, the length of the third extension portion is set to 300-600nm. As a preferred embodiment, the present invention sets the length of the second extension portion to 300nm and the length of the third extension portion to 300nm. It should be noted that the length of the third extension portion refers to its length in the horizontal direction.

Preferably, the thickness of the third extension portion is 300 nm.

The thickness of the gate affects the performance of the MOSFET device. A larger gate thickness can provide a larger current path, increase the switching speed of the MOSFET device, and is not easily affected by charge accumulation and heat accumulation, thereby improving the reliability of the MOSFET device; however, a larger gate thickness will result in greater power and heat generation, increasing the power consumption of the MOSFET device. When designing a MOSFET, it is necessary to select a suitable gate thickness to ensure that the MOSFET device operates stably and reliably. In some embodiments, the thickness of the third extension portion is set to 300nm.

Preferably, the width of the P column is 3.5um;

The width of the N column is 3.5um.

When the width of the P column and the N column is properly controlled, the N column can be completely depleted, so that there is no free charge in the N column, and the lateral electric field in the middle is very high. Only when the external voltage is greater than the internal lateral electric field can this area be broken down. The width of the P column and the N column is set to a larger width. When the trench MOSFET is in the off state, the depletion layer formed between the P column and the N column is relatively thin, and the N column cannot be completely depleted. The breakdown voltage of the trench MOSFET is reduced compared with the breakdown voltage of the MOSFET with the N column completely depleted; when the trench MOSFET is in the on state, the doping concentration of the N column is low, and the resistivity is high, resulting in an increase in the on-resistance of the trench MOSFET. The width of the P column and the N column is set to a smaller width, which can reduce the on-resistance of the trench MOSFET, but the problem of reducing the breakdown voltage also needs to be considered. In this embodiment, the width of the P column is set to 3.5um, and the width of the N column is set to 3.5um.

Preferably, the doping concentration of the P column is 6×10 ¹⁵ cm ^-3 ;

The doping concentration of the N column is 6×10 ¹⁵ cm ^-3 .

Complete depletion of the N column can also be achieved by adjusting the doping concentration of the P column and the N column. When the doping concentration of the P column and the N column is properly controlled, the N column can also be completely depleted, so that there is no free charge in the N column, and the lateral electric field in the middle is very high. Only when the external voltage is greater than the internal lateral electric field can this area be broken down. The doping concentration of the P column and the N column is set at a lower concentration. When the trench MOSFET is in the off state, the depletion layer formed between the P column and the N column is relatively thin, and the N column cannot be completely depleted. The breakdown voltage of the trench MOSFET is lower than the breakdown voltage of the MOSFET with the N column completely depleted; when the trench MOSFET is in the on state, the doping concentration of the N column is low and has a high resistivity, resulting in an increase in the on-resistance of the trench MOSFET. The doping concentration of the P column and the N column is set at a higher concentration, which can reduce the on-resistance of the trench MOSFET device, but it is also necessary to consider the reduction of the breakdown voltage and the high cost. In this embodiment, the doping concentration of the P column is set to 6×10 ¹⁵ cm ^-3 , and the doping concentration of the N column is set to 6×10 ¹⁵ cm ^-3 .

Preferably, it also includes: a drain, a substrate, a Pwell layer, a P+ layer, an N+ layer and a source;

The drain is located below the substrate;

The substrate is located below the P column and the N column;

The Pwell layer is located above the P column;

The P+ layer and N+ layer are located above the Pwell layer;

The source is located above the N+ layer.

Example 2

A method for preparing a trench super junction silicon MOSFET is provided, referring to FIGS. 2 , 3 , 4 and 5 , comprising:

S100, epitaxially forming a P column and an N column on the substrate;

Epitaxial process refers to the process of growing a completely ordered single crystal layer on a substrate. The epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial process is widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxial methods are solid phase epitaxy and vapor phase epitaxy.

Solid phase epitaxy refers to the growth of a single crystal layer on a substrate using a solid source. For example, thermal annealing after ion implantation is actually a solid phase epitaxy process. During ion implantation, the silicon atoms of the silicon wafer are bombarded by high-energy implanted ions, leaving their original lattice positions and becoming amorphous, forming a surface amorphous silicon layer. After high-temperature thermal annealing, the amorphous atoms return to their lattice positions and remain consistent with the atomic crystal orientation inside the substrate.

The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. The principles of chemical vapor epitaxy and chemical vapor deposition (CVD) are basically the same. Both are processes that use gas mixtures to react chemically on the surface of the wafer to deposit thin films. The difference is that because chemical vapor epitaxy grows a single crystal layer, it has higher requirements for the impurity content in the equipment and the cleanliness of the silicon wafer surface. In integrated circuit manufacturing, CVE can also be used for epitaxial silicon wafer processes and MOS transistor embedded source and drain epitaxial processes. The epitaxial silicon wafer process is to grow a layer of single crystal silicon on the surface of the silicon wafer. Compared with the original substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, thereby improving the yield of semiconductor manufacturing. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as reducing substrate resistance and enhancing substrate isolation. The embedded source and drain epitaxial process refers to the process of epitaxially growing doped germanium silicon or silicon in the source and drain regions of the transistor. The main advantages of introducing the embedded source-drain epitaxial process include: it is possible to grow a pseudocrystalline layer containing stress due to lattice adaptation, thereby improving the channel carrier mobility; it is possible to in-situ dope the source and drain, reduce the parasitic resistance of the source-drain junction, and reduce the defects of high-energy ion implantation.

S200, depositing a first oxide layer and a polycrystalline material above the P column and the N column;

S300, etching the first oxide layer and the polycrystalline material;

Etching is the process of selectively removing unwanted materials from the surface of silicon wafers by chemical or physical methods. It is a general term for stripping and removing materials by solutions, reactive ions or other mechanical methods. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Hereby, argon ions are irradiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they impact the material on the surface. The wafer is fed vertically or tilted into the ion beam and the etching process is absolutely anisotropic. The selectivity is low, since there is no differentiation of the individual layers. The gases and the ablated material are evacuated by the vacuum pump, however, since the reaction products are not gaseous, particles can be deposited on the wafer or on the chamber walls. All materials can be etched with this method and due to the vertical irradiation, the wear on the vertical walls is low.

Plasma etching is a chemical etching process with the advantage that the wafer surface is not damaged by accelerated ions. Due to the mobile particles of the etching gas, the etching profile is isotropic, so this method is used to remove entire film layers (such as backside cleaning after thermal oxidation). One type of reactor used for plasma etching is a downstream reactor, whereby the plasma is ignited at a high frequency of 2.45 GHz by impact ionization, the location of which is separated from the wafer.

The etching rate depends on the pressure, the power of the HF generator, the process gas, the actual gas flow rate and the wafer temperature. Anisotropy increases with increasing HF power, decreasing pressure and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed inhomogeneously, which leads to inhomogeneities. If the distance of the electrodes is increased, the etching rate decreases because the plasma is distributed in an enlarged volume. For the electrodes, carbon has proven to be the material of choice. Since fluorine and chlorine also attack carbon, the electrodes produce a uniform strained plasma, so the wafer edge is affected in the same way as the wafer center. Selectivity and etching rate depend largely on the process gas. For silicon and silicon compounds, fluorine and chlorine are mainly used.

S400, depositing a second oxide layer on the top and sidewalls of the polycrystalline material to form a second extension;

S500, epitaxially extending the P column to a height of the second extension portion;

S600 , depositing an active layer above the P column and the second extension;

S700, etching the active layer above the second oxide layer to form a groove;

S800, ion implantation is performed on the active layer at both sides of the trench to form a Pwell layer;

Ion implantation is the process of firing an ion beam in a vacuum at a solid material. After the ion beam hits the solid material, it is resisted by the solid material and its speed is slowly reduced, and finally stops in the solid material. The ions of one element are accelerated into the solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacture of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions will change the elemental composition of the target (if the ions are of a different composition than the target). Ion implantation beamline designs all contain a common set of functional components. The main part of the ion beamline includes a device called an ion source for generating ion species. The source is tightly coupled to bias electrodes to extract ions into the beamline, and most commonly is coupled to some way of selecting specific ion species for transmission into the main accelerator section. Mass selection accompanies the extracted ion beam through a magnetic field region, and its exit path is limited by blocking holes or slits that only allow ions with mass and speed/charge to continue along the beamline. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the surface to be implanted is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each dopant atom can create a charge carrier in the semiconductor after annealing. It can create a hole for a P-type dopant and an electron for an N-type dopant. This changes the conductivity of the semiconductor near the doped area.

S900, depositing a third oxide layer on the Pwell layer and on the sidewalls of the trench;

S1000, etching the second oxide layer and the third oxide layer;

The gate oxide layer is a key part in the structure of semiconductor devices. Its growth process refers to the process of depositing the oxide layer on the substrate. The formation principle of the gate oxide layer mainly involves two processes, namely oxidation reaction and diffusion reaction. In the oxidation reaction, oxygen and silicon atoms on the surface of the substrate react chemically to generate silicon dioxide. During the diffusion process, oxygen diffuses downward through the already generated silicon dioxide, continuously increasing the thickness of the oxide layer. In the integrated circuit manufacturing process, the methods for forming the gate oxide layer mainly include thermal oxidation and chemical vapor deposition. The thermal oxidation method is to place the substrate in a high-temperature oxygen environment and grow the oxide layer through a thermal oxidation reaction. The chemical vapor deposition method is a method of heating and decomposing chemical gases in the gas phase to generate silicon dioxide deposited on the substrate. The oxidation process refers to the process of forming silicon dioxide on the surface of the substrate by thermal oxidation. The oxidation process is divided into two types: dry oxygen oxidation and wet oxygen oxidation. Dry oxygen oxidation uses dry pure oxygen as the oxidation atmosphere, and directly reacts chemically with silicon at a high temperature of about 1000 degrees Celsius. The rate of dry oxygen oxidation is lower than that of wet oxygen oxidation. Usually, dry oxygen oxidation takes up to 2 hours, while wet oxygen oxidation takes about 12 minutes. However, the quality of the oxide film is higher than that of wet oxygen oxidation, so the growth of thinner shielding oxide layers, substrate oxide layers, and gate oxide layers is generally done with dry oxygen oxidation. Wet oxygen oxidation replaces oxygen with water, and water decomposes into HO at high temperatures. The diffusion rate of HO in silicon dioxide is higher than that of dry oxygen oxidation. Wet oxygen oxidation is used to grow thicker oxide layers such as shielding oxide layers, full-surface and full-area covering oxide layers, and LOCOS oxide layers. In the wet oxygen oxidation method, oxygen first passes through deionized water at 95-98 degrees Celsius, and brings water vapor into the oxidation furnace together. Oxygen and water vapor react with silicon at the same time. The quality of the silicon dioxide film generated by this oxidation method is slightly worse than that of the dry oxidation method, but it is much better than the effect of water vapor oxidation, and the growth rate is faster. Therefore, when the required oxide layer thickness is very thick and the electrical properties of the oxide layer are not required to be high, this method is often used for production capacity considerations. There are two main types of thermal oxidation equipment: horizontal and vertical. Wafers with a size of less than 6 inches use a horizontal oxidation furnace, and wafers with a size of more than 8 inches use a vertical oxidation furnace. The oxidation furnace tube and the wafer boat are made of quartz material. During the oxidation process, impurity contamination and metal contamination must be prevented. In order to reduce human factors, most modern manufacturing uses automated control.

In this embodiment, the deposited first oxide layer, second oxide layer and third oxide layer together constitute a gate oxide layer.

S1100, depositing a polycrystalline material along the third oxide layer to form a first extension portion and a third extension portion;

Chemical vapor deposition is a commonly used method for preparing polysilicon. Chemical vapor deposition decomposes silicon source gas into silicon atoms under high temperature conditions and deposits them on the surface of the substrate to form a polysilicon film. In chemical vapor deposition, the deposition process is achieved by controlling parameters such as gas flow, temperature and pressure. First, the prepared silicon source gas is introduced into the reaction chamber through the gas inlet and mixed with an inert carrier gas such as hydrogen. Then, the reaction is heated to reach an appropriate temperature, usually between 600-700 degrees Celsius. Under high temperature conditions, the silicon source gas will decompose to generate silicon atoms and deposit on the surface of the substrate. The deposition rate and film quality can be controlled by adjusting parameters such as reaction temperature, gas flow and pressure.

In this embodiment, the trench gate is formed by depositing a polycrystalline material on the first oxide layer, the second oxide layer and the third oxide layer.

S1200, ion implantation is performed on the upper layer of the Pwell layer to form an N+ layer and a P+ layer;

S1300, depositing a fourth oxide layer on the third extension portion, the N+ layer and the P+ layer;

S1400, etching the fourth oxide layer above the N+ layer to form a contact hole.

In this embodiment, the trench is extended on the basis of the traditional vertical trench, so that the length of the gate located in the trench is increased. The increase in the gate length will increase the channel length of the super junction silicon MOSFET. The increase in the channel length will reduce the gate-source voltage corresponding to point A and reduce the range of negative feedback. The increase in temperature will bring about an increase in the threshold voltage, thereby reducing the channel current and improving the thermal stability of the super junction silicon MOSFET device.

The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims (5)

1. A trench superjunction silicon MOSFET comprising: trench gate, P-pillar and N-pillar;

The trench gate includes a first extension and a second extension;

The first extension is positioned between and adjacent to the Pwell layers;

The depth of the first extension is the same as the depth of the Pwell layer;

the second extension is located between and adjacent to the Pwell layer, the first extension, the P-pillar, and the N-pillar;

The first end of the first extension part is connected with the second extension part;

the first extension part and the second extension part form an inverted T shape;

The P column is positioned among the Pwell layer, the second extension part, the N column and the substrate;

the P-pillars are adjacent to the Pwell layer, the N-pillars, and the substrate;

the N column is positioned among the second extension part, the P column and the substrate;

the N column is adjacent to the substrate;

the trench gate further includes a third extension;

the third extension is positioned above the Pwell layer and the first extension and is adjacent to the Pwell layer;

the third extension part is connected with the second end of the first extension part;

the first extension part, the second extension part and the third extension part form an I shape;

The length of the second extension part is 300-600nm;

The thickness of the second extension part is 300nm;

the length of the third extension part is 300-600nm;

The thickness of the third extension is 300nm.

2. The trench super junction silicon MOSFET of claim 1, wherein said P-pillar has a width of 3.5um;

the width of the N column is 3.5um.

3. The trench super-junction silicon MOSFET of claim 1, wherein said P-pillar has a doping concentration of 6 x 10 ¹⁵cm^-3;

the doping concentration of the N column is 6×10 ¹⁵cm^-3.

4. The trench super-junction silicon MOSFET of claim 1, further comprising: a drain, a substrate, a Pwell layer, a p+ layer, an n+ layer, and a source;

The drain electrode is positioned below the substrate;

the substrate is positioned below the P column and the N column;

The Pwell layer is positioned above the P column;

the P+ layer and the N+ layer are positioned above the Pwell layer;

the source is located above the n+ layer.

5. A method for preparing a trench super-junction silicon MOSFET, applied to a trench super-junction silicon MOSFET as set forth in any one of claims 1 to 4, comprising:

epitaxially forming a P column and an N column above the substrate;

Depositing a first oxide layer and a polycrystalline material over the P and N pillars;

Etching the first oxide layer and the polycrystalline material;

depositing a second oxide layer over and on the side walls of the polycrystalline material to form second extension portions;

Extending the P column to the height of the second extension part;

depositing an active layer over the P-pillars and the second extension;

etching the active layer above the second oxide layer to form a trench;

Ion implantation is carried out on the active layer at two sides of the groove to form a Pwell layer;

Depositing a third oxide layer over the Pwell layer and on the sidewalls of the trench;

etching the second oxide layer and the third oxide layer;

depositing the polycrystalline material along the third oxide layer to form a first extension and a third extension;

forming an N+ layer and a P+ layer by ion implantation on the upper layer of the Pwell layer;

Depositing a fourth oxide layer over the third extension, the n+ layer, and the p+ layer;

and etching the fourth oxide layer above the N+ layer to form a contact hole.