CN117558762B - A trench MOSFET and its preparation method - Google Patents

Abstract

The present invention discloses a trench MOSFET and a preparation method thereof, wherein the MOSFET comprises: a trench; the length of the trench along a first direction is greater than a first threshold; the trench comprises: a filling layer; the filling layer fills the interior of the trench; the filling layer forms a PN junction with a substrate. The present invention forms a channel by designing a new gate structure to replace the traditional trench gate, changes the length of the channel from the original fixed length to the length of the entire drift layer, opens a channel along the drift layer, reduces the resistance of the drift layer, and thus reduces the on-resistance of the MOSFET.

Description

A trench MOSFET and its preparation method

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a trench MOSFET and a preparation method thereof.

Background technique

Trench MOSFET devices are a new type of vertical MOSFET device, which is optimized and developed based on the traditional planar MOSFET structure. Compared with planar MOSFET devices, trench MOSFET devices construct the bottom trench structure through the body region, and the channel formed is located between the source region and the drift region, eliminating the JFET region and the JFET resistance; at the same time, the trench gate structure of trench MOSFET devices makes the cell spacing smaller than that of planar MOSFET devices, and more cells can be connected in parallel in design, further reducing the total resistance. Therefore, trench MOSFET devices can obtain smaller on-resistance.

The on-resistance of MOSFET will affect the operation of MOSFET. The on-resistance of traditional MOSFET is divided into 8 parts, namely source contact resistance, source region resistance, channel resistance, accumulation resistance, JFET resistance, drift region resistance, substrate resistance and drain contact resistance. The trench gate junction of trench MOSFET passes through the bottom of the P-well layer, eliminating the JFET region and JFET resistance. Therefore, the on-resistance of trench MOSFET becomes 7 parts, namely source contact resistance, source region resistance, channel resistance, accumulation resistance, drift region resistance, substrate resistance and drain contact resistance, among which the drift region resistance and substrate resistance occupy a large proportion.

The bottom of the trench of the traditional trench MOSFET is located on the upper layer of the drift layer, and the open conductive channel is located between the N+ region and the drift layer. The current path flows from the drain through the substrate into the drift layer, then flows into the N+ region through the conductive channel and finally reaches the source. The current path needs to pass through the high-resistance drift layer, resulting in a large on-resistance of the MOSFET device. Directly adjusting the MOSFET drift layer to reduce the drift region resistance will result in insufficient withstand voltage of the MOSFET device.

Summary of the invention

In order to solve at least one of the above-mentioned technical problems, an object of the present invention is to provide a trench MOSFET and a preparation method thereof.

The purpose of the present invention is achieved by the following technical means:

In a first aspect, the present invention provides a trench MOSFET, comprising: a trench;

The length of the groove along the first direction is greater than a first threshold;

The groove comprises: a filling layer;

The filling layer fills the interior of the groove;

The filling layer forms a PN junction with the substrate.

Preferably, the filling layer comprises: a first P+ layer and a first P- layer;

The first P+ layer is located below the gate and adjacent to the gate;

The first P- layer is located below the first P+ layer and is adjacent to the first P+ layer.

Preferably, the filling layer further comprises: an N+ layer, a second P- layer and a second P+ layer;

The N+ layer is located below the first P- layer and is adjacent to the first P- layer;

The second P- layer is located below the N+ layer and is adjacent to the N+ layer;

The second P+ layer is located between the second P- layer and the substrate and is adjacent to the second P- layer and the substrate.

Preferably, the width of the groove is 0.6 um.

Preferably, the thickness of the first P+ layer is 1 um;

The thickness of the first P-layer is 7 um.

Preferably, the doping concentration of the first P+ layer is 1×10 ¹⁹ cm ^-3 ;

The doping concentration of the first P-layer is 8×10 ¹⁷ cm ⁻³ .

Preferably, the thickness of the N+ layer is 1 um;

The thickness of the second P-layer is 0.5um;

The thickness of the second P+ layer is 0.5 um.

Preferably, the doping concentration of the N+ layer is 1×10 ¹⁹ cm ^-3 ;

The doping concentration of the second P-layer is 8×10 ¹⁷ cm ^-3 ;

The doping concentration of the second P+ layer is 1×10 ¹⁹ cm ⁻³ .

Preferably, it also includes a substrate, a drift layer, a P-well layer, an N+ region, a P+ region, a source, a gate and a drain;

The substrate is located above the drain and adjacent to the drain;

The drift layer is located above the substrate and adjacent to the substrate;

The P-well layer is located above the drift layer and is adjacent to the drift layer;

The N+ region and the P+ region are located above the P-well layer, and the N+ region is adjacent to the P-well layer and the P+ region;

The source is located above the N+ region and the P+ region and is adjacent to the N+ region and the P+ region.

In a second aspect, the present invention provides a method for preparing a trench MOSFET, comprising:

epitaxially forming a drift layer on the substrate;

etching the drift layer to form a groove;

forming a gate oxide layer on the sidewalls of the trench;

Filling the groove to form a filling layer;

Ion implantation is performed above the drift layer to form a P-well layer, an N+ region and a P+ region;

Deposit source and gate.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention forms a channel by designing a new gate structure to replace the traditional trench gate, changes the length of the channel from the original fixed length to the length of the entire drift layer, opens a channel along the drift layer, reduces the resistance of the drift layer, and thus reduces the on-resistance of the MOSFET.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

FIG1 is a schematic diagram of the structure of a trench MOSFET provided by an embodiment of the present invention;

FIG2 is a schematic diagram of a process for preparing a trench MOSFET according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a method for preparing a trench MOSFET provided in an embodiment of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

The term "and/or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

In addition, in order to better illustrate the present invention, numerous specific details are provided in the specific embodiments below. It should be understood by those skilled in the art that the present invention can be implemented without certain specific details. In some embodiments, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

The on-resistance of MOSFET will affect the operation of MOSFET. The on-resistance of traditional MOSFET is divided into 8 parts, namely source contact resistance, source region resistance, channel resistance, accumulation resistance, JFET resistance, drift region resistance, substrate resistance and drain contact resistance. The trench gate junction of trench MOSFET passes through the bottom of the P-well layer, eliminating the JFET region and JFET resistance. Therefore, the on-resistance of trench MOSFET becomes 7 parts, namely source contact resistance, source region resistance, channel resistance, accumulation resistance, drift region resistance, substrate resistance and drain contact resistance, among which the drift region resistance and substrate resistance occupy a large proportion.

The bottom of the trench of the traditional trench MOSFET is located on the upper layer of the drift layer, and the opened conductive channel is located between the N+ region and the drift layer. The current path flows from the drain through the substrate into the drift layer, then flows into the N+ region through the conductive channel and finally reaches the source. The current path needs to pass through the high-resistance drift layer, resulting in a large on-resistance of the MOSFET device. Directly adjusting the MOSFET drift layer to reduce the resistance of the drift region will lead to insufficient withstand voltage of the MOSFET device. The present invention forms a channel by designing a new gate structure to replace the traditional trench gate, and changes the length of the channel from the original fixed length to the length of the entire drift layer. A channel is opened along the drift layer, which reduces the resistance of the drift layer, thereby reducing the on-resistance of the MOSFET.

Example 1

A trench MOSFET is provided, as shown in FIG1 , comprising: a trench;

The length of the groove along the first direction is greater than a first threshold;

The trench includes: a filling layer;

The fill layer fills the interior of the trench;

The filling layer forms a PN junction with the substrate.

Trench MOSFET is a common field effect transistor. The basic structure of trench MOSFET includes source, drain, gate and channel. Among them, the channel between the source and drain is the channel for current flow, and the gate is the switch that controls the current in the channel. The source metal and gate metal of the trench MOSFET are located above the silicon wafer, the lower part of the silicon wafer is the substrate, and the drain is located below the silicon wafer and contacts the substrate. Trench MOSFET is also called surface effect transistor, which buries the gate in the substrate to form a vertical channel, although its process is complex and the unit consistency is worse than the planar structure. However, the trench structure can increase the unit density, there is no JFET effect, the parasitic capacitance is smaller, the switching speed is fast, and the switching loss is very low; moreover, by selecting the appropriate channel crystal plane and optimizing the design structure, the best channel mobility can be achieved, and the on-resistance can be significantly reduced.

The trench refers to the channel area. The trench MOSFET can change the performance and characteristics of the transistor by adjusting the size of the trench. In order to form a vertical channel structure, the trench MOSFET opens a trench in the drift layer, makes an oxide layer on the surface of the trench, and fills the trench with polysilicon to form a gate. This structure buries the gate in the substrate to form a vertical channel. The current path flows vertically from the lower substrate drain through the drift layer, channel and source region, and the channel and current directions are parallel.

In this embodiment, a new type of gate structure is designed to replace the traditional trench gate to form a channel, and the length of the channel is changed from the original fixed length to the length of the entire drift layer. A channel is opened along the drift layer, which reduces the resistance of the drift layer, thereby reducing the on-resistance of the MOSFET. Specifically, the groove is embedded in the drift layer, and the length along the first direction is greater than the first threshold. It should be noted that the first direction is the direction describing the depth of the groove. For a vertically arranged groove, the first direction is the direction perpendicular to the placement direction of the drift layer. The first direction can be the direction from the top etching of the groove to the bottom of the groove, or the direction from the bottom of the groove to the top etching of the groove. The first threshold is 10um. In this embodiment, the length of the groove along the first direction is increased to greater than 10um. By changing the length of the channel to the length of the entire drift layer and opening the channel along the drift layer, the resistance of the drift layer is reduced, thereby reducing the on-resistance of the MOSFET.

In some embodiments, as shown in FIG1 , the filling layer includes: a first P+ layer and a first P- layer;

The first P+ layer is located below the gate and adjacent to the gate;

The first P- layer is located below the first P+ layer and is adjacent to the first P+ layer.

The channel is a thin semiconductor layer between the source and drain in a MOSFET. Applying an external electric field to a MOSFET is a common method for turning on the channel. When a voltage is applied to the MOSFET gate, an inversion layer is formed in the MOSFET along the direction of the electric field, in which current flows and is controlled by the gate.

In this embodiment, the first P+ layer is located at the top layer of the filling layer, and the first P+ layer is arranged corresponding to the P-well layer, and is used to open an N-type channel on the side of the P-well layer adjacent to the groove. In addition to opening a channel in the P-type lightly doped P-well layer, it is also necessary to open a channel in the N-type lightly doped drift layer. Compared with the P-type lightly doped P-well layer, the N-type lightly doped drift layer is easier to open an N-type channel. The first P-layer is arranged corresponding to the drift layer, and is used to open an N-type channel on the side of the drift layer adjacent to the groove. Because the first P-layer is located below the first P+ layer and adjacent to the first P+ layer, the channel opened by the first P-layer in the drift layer is connected to the channel opened by the first P+ layer in the P-well layer, forming a whole channel from the drain to the substrate and then to the N+ region. This embodiment forms a channel by designing a new gate structure to replace the traditional trench gate, changes the length of the channel from the original fixed length to the length of the entire drift layer, opens a channel along the drift layer, reduces the resistance of the drift layer, and thus reduces the on-resistance of the MOSFET.

In some embodiments, as shown in FIG1 , the filling layer further includes: an N+ layer, a second P- layer, and a second P+ layer;

The N+ layer is located below the first P- layer and is adjacent to the first P- layer;

The second P- layer is located below the N+ layer and adjacent to the N+ layer;

The second P+ layer is located between the second P- layer and the substrate and is adjacent to the second P- layer and the substrate.

The positive end of the external voltage is added to the drain of the MOSFET, and a low-doped N- region is added between the highly doped substrate N+ and the channel of the P-well layer. Because N- and N+ are of the same semiconductor type, the current conduction loop is not affected, and the current can flow directly from N+ to N-; although N- is low-doped, its resistivity is lower than the channel. In this way, by adjusting its doping concentration and width, a higher reverse voltage can be obtained, while controlling its on-resistance within the designed range. This structure can flow a large current and is applied to power circuits. Therefore, for the trench MOSFET with an N-type drift layer, the doping type of the substrate is N+ type. The N-type substrate forms a forward diode with the first P- layer and the first P+ layer in the filling layer, so the drain and gate are turned on.

In this embodiment, the N+ layer is located below the first P-layer and is adjacent to the first P-layer; the second P-layer is located below the N+ layer and is adjacent to the N+ layer; the second P+ layer is located between the second P-layer and the substrate and is adjacent to the second P-layer and the substrate. The N+ layer, the second P-layer, and the second P+ layer arranged from top to bottom form a reverse diode structure with the substrate, preventing the drain and the gate from being directly connected.

In some embodiments, the width of the trench is 0.6 um.

The formation of the gate structure of the MOSFET device is a very critical process, which includes the thermal growth of the thinnest gate oxide layer and the etching of the polysilicon gate. The polysilicon gate is a gate structure made of polysilicon material. Due to the characteristics of silicon material, the polysilicon gate has high conductivity and low resistance, and is commonly used in MOSFET devices. In addition, the polysilicon gate also has good heat resistance and low leakage current. The polysilicon gate can control the conduction and cutoff of the MOSFET device by changing the gate voltage, which plays a role in controlling the current. The size of the polysilicon gate directly affects the electrical performance of the MOSFET device. The reduction of the gate can reduce the impedance and energy consumption, but it will also increase the non-ideality of thermal noise and channel current. The small gate is also a huge challenge to the manufacturing process. In this embodiment, the width of the groove is set to 0.6um.

In some embodiments, the thickness of the first P+ layer is 1 um;

The thickness of the first P-layer is 7 um.

The drift layer is formed by epitaxy of the substrate. Epitaxy refers to the process of growing a new single crystal on a single crystal substrate that has been carefully processed by cutting, grinding, polishing, etc. The new single crystal can be the same material as the substrate or a different material. Since the new single crystal layer grows along the substrate crystal phase, it is called an epitaxial layer. The thickness of the epitaxial layer is usually several microns. The thickness of the first P+ layer and the thickness of the first P- layer need to be set corresponding to the thickness of the P-well layer and the drift layer, respectively. In this embodiment, the thickness of the first P+ layer is set to 1um, and the thickness of the first P- layer is set to 7um.

In some embodiments, the doping concentration of the first P+ layer is 1×10 ¹⁹ cm ⁻³ ;

The doping concentration of the first P-layer is 8×10 ¹⁷ cm ⁻³ .

The first P+ layer is arranged corresponding to the P-well layer, and is used to open the N-type channel on the side of the P-well layer adjacent to the trench. Compared with the P-well layer lightly doped with P type, the drift layer lightly doped with N type is easier to open the N-type channel. The first P- layer is arranged corresponding to the drift layer, and is used to open the N-type channel on the side of the drift layer adjacent to the trench. The doping concentration of the first P+ layer and the first P- layer will affect the threshold voltage of the trench MOSFET device. In this embodiment, the doping concentration of the first P+ layer is set to 1×10 ¹⁹ cm ^-3 ; the doping concentration of the first P- layer is set to 8×10 ¹⁷ cm ^-3 .

In some embodiments, the thickness of the N+ layer is 1 um;

The thickness of the second P-layer is 0.5um;

The thickness of the second P+ layer is 0.5 um.

The change in the thickness of the N+ layer, the second P- layer, and the second P+ layer will affect the capacitance characteristics of the trench MOSFET. When the thickness of the N+ layer, the second P- layer, and the second P+ layer is large, the capacitance between the drain and the gate is large, and the gate's ability to control the drain current is weak; when the thickness of the N+ layer, the second P- layer, and the second P+ layer is small, the trench MOSFET will face the risk of breakdown. In this embodiment, the thickness of the N+ layer is set to 1um, the thickness of the second P- layer is set to 0.5um, and the thickness of the second P+ layer is set to 0.5um.

In some embodiments, the doping concentration of the N+ layer is 1×10 ¹⁹ cm ⁻³ ;

The doping concentration of the second P-layer is 8×10 ¹⁷ cm ^-3 ;

The doping concentration of the second P+ layer is 1×10 ¹⁹ cm ⁻³ .

In this embodiment, the doping concentration of the N+ layer is set to 1×10 ¹⁹ cm ⁻³ ; the doping concentration of the second P− layer is set to 8×10 ¹⁷ cm ⁻³ ; and the doping concentration of the second P+ layer is set to 1×10 ¹⁹ cm ⁻³ .

In some embodiments, as shown in FIG. 1 , it further includes a substrate, a drift layer, a P-well layer, an N+ region, a P+ region, a source, a gate, and a drain;

The substrate is located above the drain and adjacent to the drain;

The drift layer is located above the substrate and adjacent to the substrate;

The P-well layer is located above the drift layer and is adjacent to the drift layer;

The N+ region and the P+ region are located above the P-well layer, and the N+ region is adjacent to the P-well layer and the P+ region;

The source is located above the N+ region and the P+ region and is adjacent to the N+ region and the P+ region.

Example 2

A method for preparing a trench MOSFET is provided, as shown in FIG2 and FIG3, comprising:

S100, epitaxially forming a drift layer on the substrate;

Epitaxial process refers to the process of growing a completely ordered single crystal layer on a substrate. Generally speaking, the epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial process is widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source and drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, etc. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxial methods are solid phase epitaxy and vapor phase epitaxy.

Solid phase epitaxy refers to the process of epitaxial recrystallization of the amorphous layer on a semiconductor single crystal at a temperature lower than the melting point or eutectic point of the material. The recrystallization process without epitaxy does not belong to solid phase epitaxy. There are two main growth modes of solid phase epitaxy: one is that the amorphous layer is directly in contact with the single crystal substrate for epitaxial growth; the other is to sandwich a layer of metal or carbide between the amorphous layer and the single crystal silicon substrate for solid phase epitaxy. Metals and carbides act as transport media. There are many methods to form polycrystalline or amorphous films. One is the direct ion implantation method, which can implant germanium ions in large doses on a silicon single crystal substrate to form a GeSi amorphous thin layer, anneal and grow again at 475-575℃ to obtain a strained alloy layer. The other is to deposit thin films, such as evaporation or sputtering. Compared with general epitaxial methods, the solid phase epitaxial substrate temperature is low and the impurity diffusion is small, which is conducive to the manufacture of epitaxial layers with sudden doping interfaces.

In the gas phase state, semiconductor materials are deposited on a single crystal wafer so that a single crystal layer with the required thickness and resistivity is grown along the crystal axis of the single crystal wafer. This process is called vapor phase epitaxy. Its characteristics are: high epitaxial growth temperature and long growth time, so thicker epitaxial layers can be produced; the concentration and conductivity type of impurities can be arbitrarily changed during the epitaxial process. Commonly used vapor phase epitaxial processes in industrial production include: silicon tetrachloride (germanium) epitaxy, silicon (germanium) ane epitaxy, trichlorosilane and dichlorodihydrogen silicon (dichlorodihydrogen silicon has the advantages of low deposition temperature, fast deposition speed, uniform deposition film formation, etc.) epitaxy, etc. Common concepts and principles of silicon vapor phase epitaxy: Use silicon gaseous compounds (such as: SiCl ₄ , SiH ₄ ) to react chemically with hydrogen on the surface of the heated silicon substrate or undergo thermal decomposition itself, reduce to silicon, and deposit on the surface of the silicon substrate in the form of single crystals. The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. Vapor phase epitaxy of semiconductors is a process in which gaseous compounds of silicon react with hydrogen on the surface of a heated substrate or thermally decompose and reduce to silicon, and are deposited on the surface of the substrate in the form of a single crystal. Specifically, it includes: the reactant molecules are transferred from the gas phase to the surface of the growth layer by diffusion; the reactant molecules are adsorbed by the growth layer; the adsorbed reactant molecules complete chemical reactions on the surface of the growth layer to produce semiconductors and other by-products; the by-product molecules are decomposed from the surface and discharged from the reaction chamber with the gas flow; the atoms generated by the reaction form a lattice, or are added to the lattice lattice to form a single crystal epitaxial layer.

The epitaxial system includes: gas distribution and control system, heating and temperature measurement device, reaction chamber, and waste gas treatment device. The process includes: substrate and base treatment: substrate treatment is mainly to remove the oxide layer and dust particles on the surface of the substrate wafer, rinse and dry it, and put it into the graphite base. For the used graphite base, it should be HCl etched in advance to remove the silicon left on it from the previous epitaxy. Dopant preparation: dopants have gas sources, such as phosphine PH ₃ , borane B ₂ H ₆ , etc.; liquid sources such as POCI ₃ , BBr ₃ , etc. Different devices have different requirements for the resistivity and conductivity type of the epitaxial layer, and the amount of doping source must be accurately controlled according to the resistivity. Epitaxial growth: The main procedures are: furnace loading - ventilation, first nitrogen and then hydrogen - heating - substrate heat treatment or HCl polishing - epitaxial growth - hydrogen flushing - cooling - nitrogen flushing. When the base temperature drops below 300℃, the furnace is opened to take out the wafer. The quality requirements of vapor phase epitaxy are that the quality of the epitaxial layer should meet the following requirements: complete crystal structure, accurate and uniform resistivity, uniform and within the range of epitaxial layer thickness, smooth surface, no oxidation and white fog, less surface defects (pyramids, papillae, star-shaped defects, etc.) and internal defects (dislocations, stacking faults, slip lines, etc.). The epitaxial quality inspection includes: resistivity, impurity concentration distribution, epitaxial layer thickness, minority carrier lifetime and mobility, interlayer dislocation and stacking fault density, surface defects, etc. The usual inspection items in production are defect density, resistivity and epitaxial layer thickness. The epitaxial layer thickness measurement methods include stacking fault method, grinding angle or rolling groove dyeing method, direct reading method, infrared interferometry method, etc. The resistivity measurement methods include four-probe method, three-probe method, capacitance-voltage method, and extended resistance method. For epitaxial layers with higher resistivity or thinner thickness, capacitance-voltage method and extended resistance method are often used.

S200, etching the drift layer to form a groove;

Etching is the process of selectively removing unwanted materials from the surface of silicon wafers by chemical or physical methods. It is a general term for stripping and removing materials by solutions, reactive ions or other mechanical methods. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Hereby, argon ions are irradiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they impact the material on the surface. The wafer is fed vertically or tilted into the ion beam and the etching process is absolutely anisotropic. The selectivity is low, since there is no differentiation of the individual layers. The gases and the abraded material are evacuated by the vacuum pump, however, since the reaction products are not gaseous, particles can be deposited on the wafer or on the chamber walls. All materials can be etched with this method and due to the vertical irradiation, the wear on the vertical walls is low.

Plasma etching is a chemical etching process with the advantage that the wafer surface is not damaged by accelerated ions. Due to the mobile particles of the etching gas, the etching profile is isotropic, so this method is used to remove entire film layers (such as backside cleaning after thermal oxidation). One type of reactor used for plasma etching is a downstream reactor, whereby the plasma is ignited at a high frequency of 2.45 GHz by impact ionization, the location of which is separated from the wafer.

The etching rate depends on the pressure, the power of the HF generator, the process gas, the actual gas flow rate and the wafer temperature. Anisotropy increases with increasing HF power, decreasing pressure and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed inhomogeneously, which leads to inhomogeneities. If the distance of the electrodes is increased, the etching rate decreases because the plasma is distributed in an enlarged volume. For the electrodes, carbon has proven to be the material of choice. Since fluorine and chlorine also attack carbon, the electrodes produce a uniform strained plasma, so the wafer edge is affected in the same way as the wafer center. Selectivity and etching rate depend largely on the process gas. For silicon and silicon compounds, fluorine and chlorine are mainly used.

S300, forming a gate oxide layer on the sidewall of the trench;

The oxidation process is to generate a protective film on the silicon wafer. During the semiconductor manufacturing process, the oxide film formed by the oxidation process is stable and can prevent other substances from penetrating. The oxide film can also be used to prevent the flow of current between circuits. MOSFET isolates the gate from the current channel through the oxide film. This oxide film is called the gate oxide layer. The oxidation process can be divided into wet oxidation and dry oxidation. Wet oxidation is to generate an oxide film by reacting with high-temperature water vapor. Although the oxide film grows quickly, the overall uniformity and density of the oxide layer are low, and byproducts such as hydrogen are produced during the oxidation process. Dry oxidation is to generate an oxide film by directly reacting with high-temperature pure oxygen. Compared with water molecules, oxygen molecules penetrate into the interior of the wafer relatively slowly. Therefore, compared with wet oxidation, the oxide film growth rate of dry oxidation is slower, but dry oxidation does not produce byproducts, and the uniformity and density of the oxide film are higher.

Different crystal planes have different atomic densities, resulting in different etching rates. Some etchants etch a certain crystal plane much faster than other crystal planes, which is called anisotropic etching. The energy applied to the plasma by the dry etching method using plasma causes the outermost electrons of the source gas in a neutral state to be stripped off, thereby converting them into cations. Cations are anisotropic and suitable for etching in a certain direction. For the silicon dioxide of the gate oxide layer, chlorine-based plasma with polysilicon etching selectivity is used to remove silicon. For the bottom insulating layer, a carbon-fluorine-based plasma source gas with stronger etching selectivity and effectiveness is used to etch the silicon dioxide film.

In this embodiment, thermal oxide is formed on the wall surface of the trench by dry oxidation, and then a gate oxide layer is formed on the side wall by anisotropic etching.

S400, filling the groove to form a filling layer;

Polysilicon deposition is to form gate electrodes and local connections on the first layer of polysilicon (Poly1) stacked with silicide, and the second layer of polysilicon (Poly2) forms the contact plug between the source/drain 1 and the unit connection. The silicide is stacked on the third layer of polysilicon (Poly3) to form the unit connection, and the fourth layer of polysilicon (Poly4) and the fifth layer of polysilicon (Poly5) form the two electrodes of the storage capacitor, sandwiched between which is a high-dielectric dielectric. In order to maintain the required capacitance value, the size of the capacitor can be reduced by using a high-dielectric dielectric. Polysilicon deposition is a low-pressure chemical vapor deposition (LPCVD). By directly inputting the doping gas of arsenic (AH ₃ ), phosphine (PH ₃ ) or diborane (B ₂ H ₆ ) into the silicon material gas of silane or DCS in the reaction chamber (i.e., the furnace tube), the polysilicon doping process of on-site low-pressure chemical vapor deposition can be carried out. Polysilicon deposition is carried out at low pressure conditions of 0.2-1.0 Torr and deposition temperatures between 600 and 650°C, using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rates for both deposition processes are between 100-200Å/min, mainly determined by the temperature during deposition.

In the present embodiment, the filling layer is formed by depositing a second P+ layer, a second P− layer, an N+ layer, a first P− layer, and a first P+ layer in the trench.

S500, ion implantation is performed on the drift layer to form a P-well layer, an N+ region and a P+ region;

Doping is a process of adding a certain amount of impurities to semiconductor materials in order to change the electrical properties of semiconductor materials. The main methods of doping are diffusion and ion implantation. Diffusion is to place the semiconductor wafer into a precisely controlled high-temperature quartz tube furnace and pass through a mixed gas with the impurities to be diffused. The number of impurity atoms diffused into the semiconductor is related to the impurity partial pressure of the mixed gas. For the diffusion of silicon, the commonly used temperature range is generally 800 degrees Celsius to 1200 degrees Celsius. Boron is the most commonly used P-type impurity, and arsenic and phosphorus are the most commonly used N-type impurities. Ion implantation is to dope charged ions with a certain energy into silicon. The implantation energy is between 1keV and 1MeV, and the corresponding average ion distribution depth ranges from 10nm to 10um. Compared with the diffusion process, the advantage of ion implantation is that the amount of impurity doping can be more accurately controlled and good repeatability can be maintained. At the same time, the processing temperature of ion implantation is lower than that of diffusion.

In this embodiment, the P-well layer, the N+ region and the P+ region are formed by ion implantation.

S600, depositing a source electrode and a gate electrode.

The metal electrode deposition process is divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to a method of depositing a coating on the surface of a wafer by chemical methods, generally by applying energy to a mixed gas. Assuming that a substance (A) is deposited on the surface of a wafer, two gases (B and C) that can generate substance (A) are first input into the deposition equipment, and then energy is applied to the gas to cause a chemical reaction between gas B and C. PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy. The corresponding vacuum coating equipment includes vacuum evaporation coating machine, vacuum sputtering coating machine and vacuum ion coating machine.

This embodiment forms a channel by designing a new gate structure to replace the traditional trench gate, changes the length of the channel from the original fixed length to the length of the entire drift layer, opens a channel along the drift layer, reduces the resistance of the drift layer, and thus reduces the on-resistance of the MOSFET.

The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims (8)

1. A trench MOSFET, comprising: a trench, a source and a gate; The length of the groove along the first direction is greater than a first threshold; The source electrode is located above the N+ region and the P+ region and is adjacent to the N+ region and the P+ region; The gate is located above the trench and adjacent to the trench; The bottom of the source electrode and the bottom of the gate electrode are located in the same plane; The groove comprises: a filling layer; The filling layer fills the interior of the groove; The filling layer forms a PN junction with the substrate; The first threshold is the distance between the bottom of the drift layer and the source; The filling layer includes: a first P+ layer and a first P- layer; The first P+ layer is located below the gate and adjacent to the gate; The first P- layer is located below the first P+ layer and is adjacent to the first P+ layer; The first P+ layer is arranged corresponding to the P-well layer, and is used to open an N-type channel on a side of the P-well layer adjacent to the groove; The bottom of the first P-layer is arranged corresponding to the drift layer, and is used to open an N-type channel on a side of the drift layer adjacent to the trench; The filling layer further includes: an N+ layer, a second P- layer and a second P+ layer; The N+ layer is located below the first P- layer and is adjacent to the first P- layer; The second P- layer is located below the N+ layer and is adjacent to the N+ layer; The second P+ layer is located below the second P- layer and above the substrate, and is adjacent to the second P- layer and the substrate. 2 . The trench MOSFET according to claim 1 , wherein the width of the trench is 0.6 microns. 3. The trench MOSFET according to claim 1, wherein the thickness of the first P+ layer is 1 micron; The thickness of the first P-layer is 7 microns. 4. The trench MOSFET according to claim 1, wherein the doping concentration of the first P+ layer is 1×10 ¹⁹ cm ^-3 ; The doping concentration of the first P-layer is 8×10 ¹⁷ cm ⁻³ . 5. The trench MOSFET according to claim 1, wherein the thickness of the N+ layer is 1 micron; The thickness of the second P-layer is 0.5 micrometer; The thickness of the second P+ layer is 0.5 micrometers. 6. The trench MOSFET according to claim 1, wherein the doping concentration of the N+ layer is 1×10 ¹⁹ cm ^-3 ; The doping concentration of the second P-layer is 8×10 ¹⁷ cm ^-3 ; The doping concentration of the second P+ layer is 1×10 ¹⁹ cm ⁻³ . 7. A trench MOSFET according to claim 1, characterized in that it further comprises a substrate, a drift layer, a P-well layer, an N+ region, a P+ region and a drain; The substrate is located above the drain and adjacent to the drain; The drift layer is located above the substrate and adjacent to the substrate; The P-well layer is located above the drift layer and is adjacent to the drift layer; The N+ region and the P+ region are located above the P-well layer, and the N+ region is adjacent to the P-well layer and the P+ region. 8. A method for preparing a trench MOSFET, applied to a trench MOSFET according to any one of claims 1 to 7, characterized in that it comprises: epitaxially forming a drift layer on the substrate; etching the drift layer to form a groove; forming a gate oxide layer on the sidewalls of the trench; Filling the groove to form a filling layer; Ion implantation is performed above the drift layer to form a P-well layer, an N+ region and a P+ region; Deposit source and gate.