CN117238964A - A superjunction SiC MOS with a homojunction freewheeling channel and its preparation method - Google Patents

Abstract

The invention provides a superjunction SiC MOS with a homojunction freewheeling channel and a preparation method. The superjunction SiC MOS includes: an N-base layer, a P pillar and a first N+ layer; the N-base layer is in contact with In the gate oxide layer; the first N+ layer is located in the area surrounded by the P-body layer and the N-base layer. The P-pillar is located between the P-body layer and the substrate, and is adjacent to the N-drift layer, the P-body layer and the substrate. The present invention sets a reverse freewheeling channel below the gate trench. When the SiC MOS is in the reverse state, the current flows from the source to the first N+ layer, then from the first N+ layer to the N-base layer, and from the N- The base layer flows to the N‑drift layer and finally to the drain, forming a reverse freewheeling circuit. Compared with the body diode of SiC MOS, this reverse freewheeling circuit has a lower turn-on voltage, which can save chip area and reduce production costs. Improve the safety and stability of SiC MOS.

Description

A superjunction SiC MOS with a homojunction freewheeling channel and its preparation method

Technical field

The invention relates to the field of semiconductor technology, and in particular to a superjunction SiCMOS with a homojunction freewheeling channel and a preparation method.

Background technique

The third generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturation electron migration rate, stable physical and chemical properties, etc., and can be applied to high temperature, high frequency, high power and extreme environments. Silicon carbide has a larger bandgap and higher critical breakdown field strength. Compared with silicon power devices under the same conditions, the voltage resistance of silicon carbide devices is about 10 times that of silicon materials. In addition, silicon carbide devices have high electron saturation rate, small forward conduction resistance, and low power loss. They are suitable for high-current and high-power applications and reduce the requirements for heat dissipation equipment. SiC power devices have a series of advantages such as high input impedance, fast switching speed, high operating frequency and high voltage resistance, and have been widely used in switching regulated power supplies, high frequencies and power amplifiers.

As a switching device, a reverse freewheeling diode is often required in the circuit due to oscillation or voltage spikes to avoid device degradation. There are currently several ways to use freewheeling diodes: parallel diodes in the circuit, but this will cause the circuit to increase the switching capacitance and gate charge degradation, increasing the energy loss of the entire circuit; while the device is packaged, Freewheeling diodes and MOSFETs are made into a set of facilities, but this reduces the area usage of the chip. At the same time, due to the integration of multiple systems, additional current leakage of the device is caused, reducing the reliability of the device, etc. It uses the parasitic body diode of the switching element as the freewheeling diode when the reverse voltage occurs. However, for traditional SiCMOSFET, the use of body diode will bring some characteristics: First, the threshold voltage of SiC MOSFET's own body diode is relatively high. High, about 3V, which increases the extra energy consumption of the circuit and decreases the energy utilization rate; secondly, the conduction of the body diode will lead to bipolar degradation of the device. This is due to the recombination of electron-hole pairs that will cause internal degradation of the SiC material. The number of defects increases and the doping region drifts, which leads to an increase in leakage currents of various types of permanent MOSFETs, eventually causing permanent damage and failure. In order to reduce the size of transistor devices, reduce on-resistance, reduce dynamic losses, improve energy-saving characteristics, and improve the cost performance of transistors, a new structure of SiC MOSFET is currently needed to increase the switching frequency of the circuit and reduce switching losses in the circuit.

Contents of the invention

The purpose of the present invention is to provide a superjunction SiC MOS with a homojunction freewheeling channel and a preparation method. The superjunction SiC MOS is provided with a reverse freewheeling channel below the gate trench. When the SiC MOS is in reverse state, the current flows from the source to the first N+ layer, then from the first N+ layer to the N-base layer, from the N-base layer to the N-drift layer and finally to the drain, forming a reverse freewheeling loop. Compared with the body diode of SiC MOS, the freewheeling circuit has a lower turn-on voltage, which can save chip area, reduce production costs, and improve the safety and stability of SiC MOS.

A superjunction SiC MOS with a homojunction freewheeling channel, including: an N-base layer, a P pillar and a first N+ layer;

The N-base layer is in contact with the gate oxide layer;

The first N+ layer is located in the area surrounded by the P-body layer and the N-base layer.

The P pillar is located between the P-body layer and the substrate, and is adjacent to the N-drift layer, the P-body layer and the substrate.

Preferably, the P-body layer includes: a first extension located between the source and the N-drift layer and a second extension located between the N-drift layer, the N+ layer and the N-base layer. department;

The first extension is adjacent to the source and the N-drift layer;

The second extension is adjacent to the N-drift layer, the N+ layer and the N-base layer.

Preferably, the thickness of the N-base layer is 80-100 nm.

Preferably, the thickness of the oxide layer located on the right side of the gate is smaller than that of the oxide layer located below the gate.

Preferably, the thickness of the oxide layer located on the right side of the gate is 40-50 nm.

Preferably, the thickness of the oxide layer under the gate is 160-200 nm.

Preferably, the doping concentration of the N-base layer is smaller than the doping concentration of the N-drift layer.

Preferably, the doping concentration of the P pillar is 2×10 ¹⁶ -6×10 ¹⁶ cm ^-3 .

Preferably, it also includes: a source electrode, a drain electrode, a gate electrode, a substrate, a P-well layer, a second N+ layer and a P+ layer;

The drain electrode is located under the substrate;

The substrate is located below the N-drift layer and the P-pillar;

The N-drift layer is located below the P-well layer and the P-body;

The P-well layer is located below the second N+ layer and the P+ layer;

The second N+ layer and the P+ layer are located under the source electrode;

The gate is located above the first N+ layer and the N-base layer;

The source is located above the P-body layer, the first N+ layer, the second N+ layer and the P+ layer.

A method for preparing superjunction SiC MOS with a homojunction freewheeling channel, including:

Epitaxial P-pillars and N-drift layers above the substrate;

Etch trenches on the N-drift layer;

Ion implantation is performed on the upper layer of the N-drift layer to form a P-body layer, a first N+ layer, an N-base layer, a second N+ layer, a P+ layer and a P-well layer;

Depositing polysilicon and oxide layers in trenches to form gates;

etching the polysilicon;

Deposit source and drain electrodes.

The present invention sets a reverse freewheeling loop composed of the source, the first N+ layer, the N-base layer and the N-drift layer below the gate. When the superjunction SiC MOS is connected to a reverse current, due to the N-base to The potential barrier of the N-drift layer is lower than that of the PN junction, so the turn-on voltage of the reverse freewheeling path is lower than that of the body diode. The current flowing from the source to the drain can pass through the reverse freewheeling path preferentially, which can be suppressed to a certain extent. Turning on the body diode can reduce switching losses. Compared with the existing technology of integrating SiC MOSFET and SBD or JFET in anti-parallel to achieve reverse freewheeling, the process flow is very simple and the chip area is very small. Small, and the reliability and stability of SiC MOS are also higher.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those of ordinary skill in the art, It is said that other drawings can be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic structural diagram of the superjunction SiC MOS of the present invention;

Figure 2 is a schematic diagram of the superjunction SiC MOS preparation process method of the present invention;

Figure 3 is a schematic structural diagram of the preparation process of superjunction SiC MOS according to the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiment of the present invention are only used to explain the relationship between components in a specific posture (as shown in the drawings). Relative positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

In addition, descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor within the protection scope required by the present invention.

In the prior art, the body diode of the MOSFET or an external parallel diode is usually used to realize the reverse freewheeling of the MOSFET. The body diode of MOSFET is also called a parasitic diode. The body diode can play a role in reverse protection and freewheeling when driving large currents and inductive loads. Generally, the forward voltage drop is around 2.7-3V because of the existence of the body diode. , MOSFET cannot simply see the role of a switch in the circuit. For example, in a charging circuit, after charging is completed and the power supply is removed, the battery will supply power to the outside in reverse, causing serious heat under high current conditions and causing a waste of energy. , making the entire circuit energy inefficient.

The freewheeling diode is a special type of diode, which is composed of a PN junction diode. Its main function is to play the role of freewheeling in the circuit, which can effectively prevent the flow of reverse current and protect the stability and safety of the circuit. The working principle of the freewheeling diode is to combine the forward conduction characteristics of the PN junction diode and the negative resistance characteristics of the MOSFET to prevent reverse current. When the MOSFET works in the first quadrant, the PN diode is reverse-biased and cut off; when the MOSFET works in the third quadrant, the PN diode has an appropriate voltage drop (Si MOSFET VF=0.7V-1V, SiC MOSFET VF=2.7V-3.0V) The lower opening plays the role of continuous flow. The reverse leakage current of the freewheeling diode is very small, which can effectively protect the stability and safety of the circuit. Secondly, its on-resistance is very small, which can reduce the power consumption and heat loss of the circuit. In addition, its response speed is very fast, which can prevent the flow of reverse current in an instant, protect the components of the circuit from damage, and improve the stability and safety of the circuit. However, the chip area formed by anti-parallel integration of SiC MOS and freewheeling diodes is large and cannot meet current industrial needs.

The present invention sets a reverse freewheeling loop composed of the source, the first N+ layer, the N-base layer and the N-drift layer below the gate. When the superjunction SiC MOS is connected to a reverse current, due to the N-base to The potential barrier of the N-drift layer is lower than that of the PN junction, so the turn-on voltage of the reverse freewheeling path is lower than that of the body diode. The current flowing from the source to the drain can pass through the reverse freewheeling path preferentially, which can be suppressed to a certain extent. Turning on the body diode can reduce switching losses. Compared with the existing technology of integrating SiC MOSFET and SBD or JFET in anti-parallel to achieve reverse freewheeling, the process flow is very simple and the chip area is very small. Small, and the reliability and stability of SiC MOS are also higher.

Example 1

A superjunction SiC MOS with a homojunction freewheeling channel, referring to Figure 1, including: N-base layer, P-pillar and first N+ layer;

The N-base layer is in contact with the gate oxide layer;

The first N+ layer is located in the area surrounded by the P-body layer and the N-base layer.

The P pillar is located between the P-body layer and the substrate, and is adjacent to the N-drift layer, the P-body layer and the substrate.

MOSFET can be divided into planar gate MOSFET and superjunction MOSFET according to the manufacturing process. The disadvantage of planar structure transistor is that if the rated voltage is increased, the drift layer will become thicker, so the on-resistance will increase. The rated voltage of a MOSFET depends on the width of the vertical drift region and the doping parameters. In order to increase the rated voltage level, the width of the drift region is usually increased and the doping concentration is reduced, but this will cause a significant increase in the on-resistance of the MOSFET. In order to solve the problem of increased on-resistance as the rated voltage increases, the super-junction structure MOSFET has a structure in which multiple vertical PN junctions are arranged at the D and S terminals. The result is a low on-resistance while maintaining high voltage. The existence of super junction greatly breaks through the theoretical limit of silicon, and the higher the rated voltage, the more obvious the decrease in on-resistance.

The heterojunction of semiconductors is a special PN junction, which is formed by depositing more than two layers of different semiconductor material films on the same base. These materials have different energy band gaps. They can be compounds such as gallium arsenide. , or it can be a semiconductor alloy such as silicon-germanium. A heterojunction is an interface region formed by the contact of two different semiconductors. According to the different conductivity types of the two materials, heterojunctions can be divided into homojunctions (P-p junction or N-n junction) and heterogeneous heterojunctions (P-n or p-N). Multi-layer heterojunctions are called heterostructures. Usually the conditions for forming a heterojunction are that the two semiconductors have similar crystal structures, similar atomic spacing and thermal expansion coefficients. Heterojunctions can be manufactured using technologies such as interface alloys, epitaxial growth, and vacuum deposition. Heterojunction often has excellent optoelectronic properties that cannot be achieved by the respective PN junctions of two semiconductors, making it suitable for making ultra-high-speed switching devices, solar cells, and semiconductor lasers.

The potential barrier that the homojunction composed of N-drift layer and N-base layer needs to overcome is much lower than that of the heterojunction composed of P-type semiconductor and N-type semiconductor (body diode). , the freewheeling channel proposed by the present invention has a lower opening voltage and smaller switching loss than the traditional freewheeling channel.

When the MOSFET is in the off state, a reverse current will be generated in the tube due to the reverse voltage. This reverse current is called the reverse recovery current of the MOSFET. The reverse recovery current of the MOSFET has an important impact on the working performance and reliability of the MOSFET. The reverse recovery current of the MOSFET is related to the structural parameters, operating temperature, external voltage and other factors of the MOSFET. When the MOSFET works in a circuit with a higher frequency, if the reverse recovery performance is insufficient, the MOSFET can easily be damaged. , only by improving the reverse recovery speed of MOSFET can it adapt to high-frequency circuits.

MOSFET inevitably has switching losses during the switching process, and switching losses include conduction losses and cut-off losses. Conduction loss refers to the power loss generated when the power tube goes from cutoff to conduction. Cut-off loss refers to the power loss caused by the power tube from conduction to cut-off. Switching losses include turn-on losses and turn-off losses. When a non-ideal switch tube is turned on, the voltage of the switch tube does not drop to zero immediately, but has a falling time. At the same time, its current does not rise to the load current immediately, but also has a Rise Time. During this period of time, the current and voltage of the switch tube have an overlap area, which will cause loss. This loss is the turn-on loss. Switching loss refers to the need to charge and discharge parasitic capacitors when switching large MOSFETs in switching power supplies, which will also cause losses.

In order to increase the switching rate of the MOSFET and reduce the switching loss of the MOSFET, the present invention sets a reverse freewheeling circuit composed of the source, the first N+ layer, the N-base layer and the N-drift layer below the gate. When the SiC MOS is connected During reverse current flow, since the potential barrier from the N-base to the N-drift layer is lower than that of the PN junction, the turn-on voltage of the reverse freewheeling path is lower than that of the body diode. The current flowing from the source to the drain can continue from the reverse direction preferentially. The passage of the flow path can suppress the turning on of the body diode to a certain extent, which can reduce switching losses. Compared with the existing technology of integrating SiC MOSFET and SBD or JFET in anti-parallel to play a reverse freewheeling effect, The process flow is very simple, the chip area is small, and the reliability and stability of SiC MOS are also higher, and it can also protect the circuit and extend the service life of the circuit.

Preferably, the P-body layer includes: a first extension portion located between the source and the N-drift layer and a second extension portion located between the N-drift layer, the N+ layer, and the N-base layer;

The first extension is adjacent to the source electrode and the N-drift layer;

The second extension is adjacent to the N-drift layer, the N+ layer and the N-base layer.

The first function of the P-body layer is to control the turn-off of the reverse freewheeling channel. When the SiC MOS is in the off state, the P-body layer can deplete the N-base layer, thus turning off the first N+ layer. The current channel to the N-base layer protects the SiC MOS from being broken down by large current.

The second function of the P-body layer is to protect the gate oxide layer at the bottom corner of the gate trench. After the gate oxide layer is oxidized and formed, due to the technical limitations of the existing process, the gate oxide layer will inevitably appear. Defects, such as small spots and pinholes in the oxide layer caused by uneven local growth rates of the oxide layer. Especially at the corners at the bottom of the trench, defects in the oxide layer are more likely to appear. Defects in the gate oxide layer cause electric field lines to be concentrated at the corners at the bottom of the trench gate. Therefore, the electric field intensity at the corners at the bottom of the trench is much greater than other locations in the trench. At the corners at the bottom of the gate trench The problem of gate oxide layer breakdown is most likely to occur at this location. Therefore, the present invention provides a P-body layer under the gate oxide layer, which can reduce the problem of concentrated electric field distribution at the bottom corner of the gate trench and improve the reliability of the gate oxide layer.

Preferably, the thickness of the N-base layer is 80-100 nm.

In order to ensure that the N-base layer can be completely depleted by the P-body layer in the off state, if the thickness of the N-base layer is too large, the N-base layer cannot be depleted by the P-body layer, which will cause SiC MOS has a large area of leakage, resulting in SiC MOS loss. If the thickness of the N-base layer is too small, it will be exhausted by the P-body layer prematurely and cannot provide a large enough freewheeling circuit. Therefore, the N-base layer The minimum thickness cannot be less than 80nm, and the maximum thickness cannot exceed 100nm. As a preferred embodiment, in the present invention, the thickness of the N-base layer is 90nm, which ensures that the N-base layer can be P- The body layer is completely depleted, while ensuring sufficient reverse recovery current for SiC MOS, improving the reliability and reverse recovery performance of SiC MOS.

Preferably, the thickness of the oxide layer located on the right side of the gate is smaller than that of the oxide layer located below the gate.

Preferably, the thickness of the oxide layer located on the right side of the gate is 40-50nm.

Preferably, the thickness of the oxide layer located under the gate is 160-200 nm.

The thickness of the oxide layer to the right of the gate is the thickness of the oxide layer below the gate. For example, when the SiCMOS withstand voltage is 1200V, the thickness of the gate oxide layer on the right side of the trench is 40nm, and the thickness of the gate oxide layer at the bottom of the trench is 200nm, because the thinner the oxide layer on the right side of the gate, The easier it is to induce an inversion layer in the P-well layer. When SiCMOS is operating normally, current can flow from the drain to the substrate, from the substrate to the P-well layer, and then from the P-well layer to the second N+ The layer finally flows to the source. A thin gate oxide layer can increase the current density of SiC MOS, but a too thin gate oxide layer has insufficient voltage resistance, so the thickness of the oxide layer on the right side of the gate cannot be less than 40nm.

Due to the technical limitations of the existing process after the gate oxide layer is oxidized and formed, defects in the gate oxide layer are inevitably caused, such as small spots and oxide layer pinholes caused by uneven local growth rates of the oxide layer. Especially at the corners at the bottom of the trench, defects in the oxide layer are more likely to appear. Defects in the gate oxide layer cause electric field lines to be concentrated at the corners at the bottom of the trench gate. Therefore, the electric field intensity at the corners at the bottom of the trench is much greater than other locations in the trench. At the corners at the bottom of the gate trench The problem of gate oxide layer breakdown is most likely to occur at the gate, so the thickness of the oxide layer under the gate should be greater than the thickness of the oxide layer on the right side of the gate. This can ensure that there is no breakdown problem in the gate oxide layer and improve SiC MOS devices. reliability and circuit safety.

Preferably, the doping concentration of the N-base layer is smaller than the doping concentration of the N-drift layer.

The concentration of the N-base layer is 10 ¹⁶ cm ^-3 .

The substrate of PN junction is divided into P type and N type. + is heavily doped (high doping concentration), - is lightly doped (low doping concentration), and P type is doped with IIIA group elements, such as boron and aluminum. , gallium, indium, thallium. N-type doped VA group elements, such as nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and enrium (Mc). The doping concentration of heavily doped is above 10 ¹⁸ cm ^-3 , and the doping concentration of lightly doped is below that of heavily doped, because only when the doping concentration of N-base layer is slightly lower than that of N-drift layer , the current can flow from the N-base layer to the N-drift layer. The N-base layer is lightly doped. In the embodiment of the present invention, due to the use of a superjunction structure, the doping concentration of the N-drift layer is higher than that of the planar structure. The doping ^{concentration} of ^the N-drift layer in the The impurity concentration is 10 ¹⁶ cm ^-3 .

Preferably, the doping concentration of the P pillar is 2×10 ¹⁶ -6×10 ¹⁶ cm ^-3 .

The P-pillar is lightly doped. If the doping concentration of the P-pillar is too low or too low, the charge in the SiC MOS will not be balanced and the electrical performance of the SiC MOS will be affected. Therefore, the doping concentration of the P-pillar is based on N-drift. The doping concentration of the layer is set. As a preferred embodiment, the present invention sets the doping concentration of the P pillar to 2×10 ¹⁶ -6×10 ¹⁶ cm ^-3 .

Preferably, it also includes: source (S), drain (D), gate (G), substrate (N-sub), P-well layer, second N+ layer and P+ layer;

The drain is located beneath the substrate;

The drain is the charge sink in the MOSFET. It is connected to the channel and is the entrance to the charge. When the MOSFET is in the on state, a conductive path is formed between the drain and source, and electrons flow from the source to the drain to complete the transmission of current. The voltage change of the drain has little impact on the working state of the MOSFET, and mainly plays the role of current inflow.

The substrate is located under the N-drift layer (drift layer) and P-pillar;

The electric field distribution of the N-drift layer plays a key role in the conduction characteristics and current control of MOSFET. When a gate voltage is applied to a MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source and drain. When the MOSFET is working, the current between the source and the drain is mainly transmitted through the N-drift layer. The doping type and concentration of the N-drift layer determines the conduction type (N-type or P-type) and size of the current. The structure and characteristics of the N-drift layer directly affect the current control capability of the MOS tube. By adjusting the shape, size and doping concentration of the N-drift layer, precise control of the current can be achieved to meet the requirements of different applications.

The N-drift layer is located below the P-well layer and P-body;

The P-well layer is located below the second N+ layer and P+ layer;

The second N+ layer and P+ layer are located under the source;

The gate is located above the first N+ layer and N-base layer;

The gate is the control electrode in the MOSFET. It is separated from the channel by an insulating layer and is a key part of the MOSFET. Changes in gate voltage can change the charge density in the channel, thereby controlling the amount of current between the drain and source.

The source is located above the P-body layer, the first N+ layer, the second N+ layer, and the P+ layer.

The source is the source of charge in the MOSFET and is the outlet of the charge. When the MOSFET is in the on state, a conductive path is formed between the source and drain, and electrons flow from the source to the drain to complete the transmission of current. At the same time, the source also plays the role of modulating the gate voltage. By controlling the change of the source voltage, the MOSFET is controlled.

Example 2

A method for preparing superjunction SiC MOS with a homojunction freewheeling channel, refer to Figures 2 and 3, including:

S100, epitaxially P-pillar and N-drift layer above the substrate;

The epitaxial process refers to the process of growing a fully ordered single crystal layer on a substrate. Generally speaking, the epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source-drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, etc. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxy methods are solid-phase epitaxy and vapor-phase epitaxy.

Solid-phase epitaxy refers to the growth of a single crystal layer on a substrate by a solid source. For example, thermal annealing after ion implantation is actually a solid-phase epitaxy process. During the ion implantation process, the silicon atoms of the silicon wafer are bombarded by high-energy implanted ions, leaving the original lattice position and becoming amorphous, forming a surface amorphous silicon layer; after high-temperature thermal annealing, the amorphous atoms return to the original lattice position. to the crystal lattice position and consistent with the atomic orientation within the substrate.

The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. In the embodiment of the present invention, chemical vapor epitaxy (CVE) is used to form the N-drift layer. The principles of chemical vapor epitaxy and chemical vapor deposition (CVD) are basically the same. They are both processes that use gas mixture to react chemically on the surface of the wafer to deposit thin films. The difference is that because chemical vapor epitaxy grows a single crystal layer, it requires a lot of equipment. The impurity content in the silicon wafer and the cleanliness requirements on the silicon wafer surface are both higher. In integrated circuit manufacturing, CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source-drain epitaxial processes. The epitaxial silicon wafer process is to epitaxially extend a layer of single crystal silicon on the surface of the silicon wafer. Compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, thus improving the yield of semiconductor manufacturing. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to device design. For example, it can be used to reduce substrate resistance, enhance substrate isolation, etc. The embedded source-drain epitaxy process refers to the process of epitaxially growing doped silicon germanium or silicon in the source and drain regions of the transistor. The main advantages of introducing the embedded source-drain epitaxy process include: it can grow a pseudocrystalline layer that contains stress due to lattice adaptation, improving channel carrier mobility; it can dope the source and drain in situ, reducing the parasitic resistance of the source-drain junction , Reduce the defects of high-energy ion implantation.

S200, etching trenches on the N-drift layer;

In the present invention, trenches are formed by etching the upper layer of the N-drift layer. Etching is the process of selectively removing unwanted materials from the surface of silicon wafers using chemical or physical methods. It is a general term for stripping and removing materials through solutions, reactive ions or other mechanical means. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Thereby, argon ions are radiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they hit the material on the surface. With the wafer vertical or tilted into the ion beam, the etching process is absolutely anisotropic. Selectivity is low as there is no difference between layers. The gases and ground material are removed by a vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched using this method, with very low wear on vertical walls due to vertical radiation.

Plasma etching is an absolute chemical etching process. The advantage is that the wafer surface will not be damaged by accelerated ions. Due to the movable particles of the etching gas, the etching profile is isotropic, so this method is used to remove the entire film layer (such as backside cleaning after thermal oxidation). One type of reactor used for plasma etching is the downstream reactor. Thus, plasma is ignited at a high frequency of 2.45GHz through impact ionization, and the location of impact ionization is separated from the wafer.

The etch rate depends on the pressure, power of the high frequency generator, process gas, actual gas flow and wafer temperature. Anisotropy increases with increasing high-frequency power, decreasing pressure, and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes, and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed unevenly, resulting in inhomogeneity. If the distance between the electrodes is increased, the etch rate decreases because the plasma is distributed in an enlarged volume. For electrodes, carbon has proven to be the material of choice. Because fluorine and chlorine gases also attack carbon, the electrodes create a uniformly strained plasma so the edges of the wafer are affected in the same way as the center of the wafer. Selectivity and etch rate are highly dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.

S300, ion implantation is performed on the upper layer of the N-drift layer to form a P-body layer, a first N+ layer, an N-base layer, a second N+ layer, a P+ layer and a P-well layer;

The present invention uses ion implantation to form a P-body layer, a first N+ layer, an N-base layer, a second N+ layer, a P+ layer and a P-well layer on the upper layer of the N-drift layer. Ion implantation is to emit an ion beam in a vacuum towards a solid material. After the ion beam hits the solid material, its speed slowly slows down due to the resistance of the solid material, and finally stays in the solid material. The ions of an element are accelerated into a solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacturing of semiconductor devices, metal surface treatment, and materials science research. If the ions are stopped and remain in the target, the ions will change the elemental composition of the target (if the ions are of a different composition than the target). Ion implantation beamline designs all contain a common set of functional components. The main part of an ion beamline consists of a device called an ion source, which is used to generate ion species. The source is tightly coupled to a bias electrode to extract ions into the beamline, and most commonly to some means of selecting specific ion species for transport into the main accelerator section. The "mass" selection accompanies the extracted ion beam through the magnetic field region, with its exit path restricted by blocking holes or "slits" that only allow ions with mass and velocity/charge to continue along the beamline. If the target surface is larger than the ion beam diameter, and the implant dose is evenly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When injected into a semiconductor, each dopant atom can generate charge carriers in the semiconductor after annealing. A hole can be created for P-type dopants and an electron for N-type dopants. Changes the conductivity of the semiconductor near the doped region.

S400, deposit polysilicon and oxide layer in the trench to form the gate;

The gate electrode is deposited using the polysilicon deposition method. Polysilicon deposition is when silicide is stacked on the first layer of polysilicon (Poly1) to form the gate electrode and local connections, and the second layer of polysilicon (Poly2) forms the source/drain and cell connections. contact plug. The silicide is stacked on the third layer of polysilicon (Poly3) to form the unit connection. The fourth layer of polysilicon (Poly4) and the fifth layer of polysilicon (Poly5) form the two electrodes of the storage capacitor. Sandwiched between them is a high dielectric coefficient of dielectric. To maintain the desired capacitance value, the size of the capacitor can be reduced by using a high-k dielectric. Polysilicon deposition is a type of low-pressure chemical vapor deposition (LPCVD) by placing arsenic (AH ₃ ), phosphorus (PH ₃ ), or diborane (B ₂ H ₆ ) in a reaction chamber (i.e., a furnace tube). By directly inputting the doping gas into the silicon material gas of silane or DCS, the polysilicon doping process of on-site low-pressure chemical vapor deposition can be performed. Polysilicon deposition is carried out under low pressure conditions of 0.2-1.0 Torr and deposition temperatures between 600 and 650°C, using pure silane or silane with a purity of 20% to 30% diluted with nitrogen. The deposition rates for both deposition processes are is mainly determined by the temperature during deposition.

S500, etched polysilicon;

Polysilicon gate MOSFET requires polysilicon etching to form the gate pattern. MOSFETs with high-k and metal gates require polysilicon etching. In order to protect the gate oxide layer from damage, the etching of the silicon gate is usually divided into several steps: main etching, landing etching and over-etching. The main etch usually has a relatively high etch rate but a relatively small selection of silicon oxide. The main etching can basically determine the cross-sectional profile and critical dimensions of the silicon gate. Landing etching usually has a relatively high selectivity ratio for the gate oxide layer to ensure that the gate oxide layer is not damaged. Once the gate oxide is reached, it must be converted to an over-etch step with a higher selectivity for silicon oxide to ensure that the remaining silicon is removed without damaging the gate oxide. Cl ₂ , HBr, HCl are the main gases for silicon gate etching.

The polysilicon gate etching process must have a high selectivity to the underlying gate oxide layer and have very good uniformity and repeatability. A high degree of anisotropy is also required because the polysilicon gate acts as a barrier during source/drain implantation. Sloping sidewalls cause doping of the underlying portion of the polysilicon gate structure.

Polycrystalline silicon etching is divided into three steps. The first step is pre-etching, which is used to remove the natural oxide layer, hard masking layer (such as SiON) and surface contaminants to obtain uniform etching (this reduces the risk of microorganisms during etching). Surface defects caused by contaminants in the masking layer). Next is the main etching to the end. This step is used to etch away most of the polysilicon film without damaging the gate oxide layer and to obtain an ideal anisotropic sidewall profile. The final step is overetching, which removes etching residues and remaining polysilicon and ensures high selectivity to the gate oxide layer. This step should avoid the formation of microgrooves in the gate oxide around the polysilicon.

S600, deposit source and drain electrodes.

Metal electrode deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to the method of chemically depositing coatings on the surface of wafers, generally by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

Both chemical vapor deposition (CVD) and physical vapor deposition (PVD) can be used as technical means to deposit metal electrodes. In embodiments of the present invention, a chemical vapor deposition method is used to deposit metal electrodes. The chemical vapor deposition process is divided into three stages: diffusion of reaction gas to the surface of the substrate, adsorption of the reaction gas on the surface of the substrate, and chemical reaction on the surface of the substrate to form a solid deposition. The substances and the gas phase by-products produced are separated from the surface of the matrix. The most common chemical vapor deposition reactions are: thermal decomposition reactions, chemical synthesis reactions and chemical transport reactions. Usually, to deposit TiC or TiN, gases such as TiCl ₄ , H ₂ , and CH ₄ are introduced into a reaction chamber at 850 to 1100°C. After chemical reaction, a coating is formed on the surface of the substrate.

The present invention sets a reverse freewheeling loop composed of the source, the first N+ layer, the N-base layer and the N-drift layer below the gate. When the superjunction SiC MOS is connected to a reverse current, due to the N-base to The potential barrier of the N-drift layer is lower than that of the PN junction, so the turn-on voltage of the reverse freewheeling path is lower than that of the body diode. The current flowing from the source to the drain can pass through the reverse freewheeling path preferentially, which can be suppressed to a certain extent. Turning on the body diode can reduce switching losses. Compared with the existing technology of integrating SiC MOSFET and SBD or JFET in anti-parallel to achieve reverse freewheeling, the process flow is very simple and the chip area is very small. Small, and the reliability and stability of SiC MOS are also higher.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. A superjunction SiC MOS with a homojunction freewheeling channel, characterized in that it includes: an N-base layer, a P pillar and a first N+ layer; The N-base layer is in contact with the gate oxide layer; The first N+ layer is located in the area surrounded by the P-body layer and the N-base layer. The P pillar is located between the P-body layer and the substrate, and is adjacent to the N-drift layer, the P-body layer and the substrate. 2. A superjunction SiC MOS with a homojunction freewheeling channel according to claim 1, characterized in that the P-body layer includes: a first layer located between the source and the N-drift layer. The extension part and the second extension part located between the N-drift layer and the N+ layer and the N-base layer; The first extension is adjacent to the source and the N-drift layer; The second extension is adjacent to the N-drift layer, the N+ layer and the N-base layer. 3. A superjunction SiC MOS with a homojunction freewheeling channel according to claim 1, characterized in that the thickness of the N-base layer is 80-100 nm. 4. A superjunction SiC MOS with a homojunction freewheeling channel according to claim 1, characterized in that the thickness of the oxide layer located on the right side of the gate is smaller than the thickness of the oxide layer located below the gate. 5. A superjunction SiC MOS with a homojunction freewheeling channel according to claim 4, characterized in that the thickness of the oxide layer located on the right side of the gate is 40-50 nm. 6. A superjunction SiC MOS with a homojunction freewheeling channel according to claim 4, wherein the thickness of the oxide layer located below the gate is 160-200 nm. 7. A superjunction SiC MOS with a homojunction freewheeling channel according to claim 1, characterized in that the doping concentration of the N-base layer is smaller than the doping concentration of the N-drift layer. 8. A superjunction SiC MOS with a homojunction freewheeling channel according to claim 1, characterized in that the doping concentration of the P pillar is 2×10 ¹⁶ -6×10 ¹⁶ cm ^-3 . 9. A superjunction SiC MOS with a homojunction freewheeling channel according to claim 1, further comprising: a source, a drain, a gate, a substrate, a P-well layer, a third Two N+ layers and P+ layers; The drain electrode is located under the substrate; The substrate is located below the N-drift layer and the P-pillar; The N-drift layer is located below the P-well layer and the P-body; The P-well layer is located below the second N+ layer and the P+ layer; The second N+ layer and the P+ layer are located under the source electrode; The gate is located above the first N+ layer and the N-base layer; The source is located above the P-body layer, the first N+ layer, the second N+ layer and the P+ layer. 10. A method for preparing superjunction SiC MOS with a homojunction freewheeling channel, which is characterized by including: Epitaxial P-pillars and N-drift layers above the substrate; Etch trenches on the N-drift layer; Ion implantation is performed on the upper layer of the N-drift layer to form a P-body layer, a first N+ layer, an N-base layer, a second N+ layer, a P+ layer and a P-well layer; Depositing polysilicon and oxide layers in trenches to form gates; etching the polysilicon; Deposit source and drain electrodes.