CN117334748B - Source electrode trench integrated SBD and HK medium SiC UMOS and preparation method - Google Patents

Abstract

The present invention provides a source trench integrated SBD and HK dielectric SiC UMOS and a preparation method, the SiC UMOS comprising: a HK dielectric layer and a Schottky metal; the HK dielectric layer is located between the source trench and the substrate, and is adjacent to the substrate and the N-drift layer; the Schottky metal is located between the N-drift layer and the source, and is used to provide a conductive channel from the source to the drain. The present invention connects the Schottky diode in reverse parallel to the two side walls at the bottom of the source trench, the turn-on voltage of the Schottky diode is much smaller than the body diode, and the Schottky diode can be turned on at a lower voltage drop when the SiC UMOS is in a reverse state, and plays a reverse freewheeling role without increasing the chip area, and an HK dielectric layer is arranged below the source trench to avoid leakage at the bottom of the trench, and can also improve the electric field distribution, prevent the electric field line from being concentrated and damaging the SiC UMOS, and significantly improve the electrical performance of the SiC UMOS.

Description

A source trench integrated SBD and HK dielectric SiC UMOS and preparation method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a source trench integrated SBD and HK dielectric SiC UMOS and a preparation method thereof.

Background technique

The third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturated electron migration rate, stable physical and chemical properties, etc., and can be used in high temperature, high frequency, high power and extreme environment. Silicon carbide has a larger band gap and a higher critical breakdown field strength. Compared with silicon power devices under the same conditions, the voltage resistance of silicon carbide devices is about 10 times that of silicon materials. In addition, silicon carbide devices have a high electron saturation rate, low forward on-resistance, and low power loss, which are suitable for high current and high power applications, reducing the requirements for heat dissipation equipment. Compared with other third-generation semiconductors (such as GaN), silicon carbide can be more conveniently formed into silicon dioxide through thermal oxidation. SiC has unique physical, chemical and electrical properties, and is a semiconductor material with great development potential in extreme application fields such as high temperature, high frequency, high power and radiation resistance. SiC power devices have a series of advantages such as high input impedance, fast switching speed, high operating frequency and high voltage resistance, and have been widely used in switching power supplies, high frequency and power amplifiers.

MOS field effect transistor power devices made of silicon carbide materials can withstand higher voltages and faster switching speeds than Si devices. For conventional Si MOS, its body diode turn-on voltage is only about 0.7V, so it is often used as a freewheeling channel under reverse bias of MOSFET. However, the SiC material has a wider bandgap, and the SiC MOSFET body diode turn-on voltage is too high (2.7-3.0V), which makes it difficult to play the role of freewheeling protection MOSFET under reverse bias. In the prior art, SiC MOSFET usually enhances the device's freewheeling capability by using an anti-parallel Schottky diode or a JFET short-circuited body diode, but both methods will take up additional area, increasing the chip area, or by splitting the gate to control the freewheeling channel to open when the SiC MOS is reversed, but it will lead to problems such as reduced gate reliability, complex process, high production cost, and low current density.

Summary of the invention

The purpose of the present invention is to provide a source trench integrated SBD and HK dielectric SiC UMOS and a preparation method. The SiCUMOS connects a Schottky diode in anti-parallel to both side walls of the bottom of a source trench. The turn-on voltage of the Schottky diode is much smaller than that of the body diode. When the SiC UMOS is in a reverse state, the Schottky diode can be turned on at a lower voltage drop, and plays a reverse freewheeling role without increasing the chip area. In addition, an HK dielectric layer is arranged under the source trench to avoid leakage at the bottom of the trench, and the electric field distribution can be improved to prevent the concentrated electric field lines from damaging the SiC UMOS, thereby significantly improving the electrical performance of the SiC UMOS.

A source trench integrated SBD and HK dielectric SiC UMOS, comprising: an HK dielectric layer and a Schottky metal;

The HK dielectric layer is located between the source trench and the substrate, and is adjacent to the substrate and the N-drift layer;

The Schottky metal is located between the N-drift layer and the source electrode, and is used to provide a conductive channel from the source electrode to the drain electrode.

Preferably, the Schottky metal is adjacent to the N-drift layer and the source electrode.

Preferably, it further comprises: a CSL layer;

The CSL layer is located between the P-well layer and the N-drift layer;

The CSL layer is adjacent to the Schottky metal, the P-well layer, and the N-drift layer.

Preferably, the dielectric constant of the HK dielectric layer is 100-300.

Preferably, the doping concentration of the CSL layer is 10 ¹⁶ cm ^-3 to 8×10 ¹⁶ cm ^-3 .

Preferably, the width of the HK dielectric layer is 0.1-0.2 um greater than the width of the source trench.

Preferably, the thickness of the CSL layer is 0.4-0.6 um.

Preferably, it also includes: a source, a drain, a gate, a substrate, an N-drift layer, a P-well layer, a P+ region and an N+ region;

The drain is located below the substrate;

The substrate is located below the HK dielectric layer and the N-drift layer;

The N-drift layer is located below the P-well layer;

The P-well layer is located below the N+ region;

The N+ region is located below the source;

The P+ region is located below the source and is adjacent to the N+ region, the P-well layer and the N-drift layer;

The source is located above the gate, the N+ region and the P+ region;

The gate is located at both sides of the N+ region, the N-drift layer and the P+ region.

A method for preparing a source trench integrated SBD and HK dielectric SiC UMOS, comprising:

Epitaxially forming a HK dielectric layer, an N-drift layer, a P-well layer and an N+ region on the substrate;

Implanting ions into the N+ region and the P-well layer to form a P+ region;

Etching the N+ region, the P-well layer and both sides of the N-drift layer, etching through holes on the P+ region and the N-drift layer, etching trenches on the upper layer of the HK dielectric layer, wherein the trenches are connected to the through holes;

Depositing gates on both sides of the N+ region, the P-well layer and the N-drift layer, and depositing an ILD layer on the N+ region, the P+ region and the N-drift layer;

Deposit Schottky metal, source and drain.

Preferably, the epitaxially forming a HK dielectric layer, an N-drift layer, a P-well layer and an N+ region on the substrate further comprises:

Before forming the P-well layer and the N+ region, a CSL layer is epitaxially formed on the N-drift layer and the HK dielectric layer.

The present invention opens a source trench in the P+ region toward the N-drift layer, the source trench replaces part of the P+ region and the N-drift layer, and Schottky metal is deposited on the two side walls of the bottom of the source trench. Compared with the anti-parallel Schottky diode on the device surface in the prior art, the chip area is smaller, and the reverse current of the Schottky metals on both sides of the source is larger than that of the Schottky metal on one side of the source. Since the electric field strength under the source trench is large, the present invention arranges an HK dielectric layer under the source trench to shield the channel between the source and the drain and reduce leakage. The HK dielectric layer can improve the electric field distribution in the N-drift layer, alleviate the electric field spike under the source trench, prevent the SiC UMOS from being broken down prematurely, and significantly improve the reliability of the SiC UMOS.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

FIG1 is a schematic diagram of the SiC UMOS structure of the present invention;

FIG2 is a schematic diagram of a SiC UMOS preparation process of the present invention;

FIG. 3 is a schematic structural diagram of the SiC UMOS preparation process of the present invention.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

MOS field effect transistor power devices made of silicon carbide materials can withstand higher voltages and faster switching speeds than Si devices. For conventional Si MOS, its body diode turn-on voltage is only about 0.7V, so it is often used as a freewheeling channel under reverse bias of MOSFET. However, SiC material has a wider bandgap, and the SiC UMOSFET body diode turn-on voltage is too high (2.7-3.0V), which makes it difficult to play the role of freewheeling protection MOSFET under reverse bias. In the prior art, SiCUMOSFET usually enhances the device's freewheeling capability by anti-parallel Schottky diodes or JFET short-circuit body diodes, but both methods will take up additional area, increasing the chip area, or by splitting the gate to control the freewheeling channel to open when the SiC UMOS is reversed, but it will lead to problems such as reduced gate reliability, complex process, high production cost, and low current density.

The present invention opens a source trench in the P+ region toward the N-drift layer, the source trench replaces part of the P+ region and the N-drift layer, and Schottky metal is deposited on the two side walls of the bottom of the source trench. Compared with the anti-parallel Schottky diode on the device surface in the prior art, the chip area is smaller, and the reverse current of the Schottky metals on both sides of the source is larger than that of the Schottky metal on one side of the source. Since the electric field strength under the source trench is large, the present invention arranges an HK dielectric layer under the source trench to shield the channel between the source and the drain and reduce leakage. The HK dielectric layer can improve the electric field distribution in the N-drift layer, alleviate the electric field spike under the source trench, prevent the SiC UMOS from being broken down prematurely, and significantly improve the reliability of the SiC UMOS.

Example 1

A source trench integrated SBD and HK dielectric SiC UMOS, referring to FIG1 , comprises: a HK dielectric layer (High-k) and a Schottky metal (Schottky);

The HK dielectric layer is located between the source trench and the substrate, and is adjacent to the substrate and the N-drift layer;

The material of the HK dielectric layer is a high-K dielectric, where K is a dielectric constant. The high-K dielectric has a large barrier height when in contact with the semiconductor and has good insulation properties, and can be regarded as an insulating layer. In the selection of high-K materials, the present invention selects materials with good thermal stability. When the SiC UMOS works normally, it will emit heat. Good thermal stability can ensure the normal working performance of the SiC UMOS; it has a high lattice matching degree with silicon carbide. If the lattice matching degree between crystals is not high, it will cause lattice distortion and structural disorder. A high lattice matching degree will also improve the interface quality, and the electrical performance of the SiC UMOS will also be improved accordingly. Nitrides and metal oxides are generally selected as the materials for the HK dielectric layer.

The Schottky metal is located between the N-drift layer (drift layer) and the source (S) to provide a conductive path from the source to the drain.

The contact surface between metal and semiconductor is divided into two types: Schottky contact and Ohmic contact. Ohmic contact is when the semiconductor doping concentration is very high. When the semiconductor with high doping concentration contacts with metal, a low barrier layer is formed. Electrons can pass through the barrier by tunneling effect, thus forming an Ohmic contact with low resistance. For example, the N+ region and the source electrode form an Ohmic contact. The characteristics of Ohmic contact are that the current-voltage characteristic of the contact surface is linear, and the contact resistance is negligible relative to the bulk resistance of the semiconductor. When current passes through, the voltage drop generated is smaller than the voltage drop on the device.

Schottky contact is also made by using the contact characteristics of metal-semiconductor (MS). Since the current transport of metal-semiconductor contact mainly relies on majority carriers (electrons), its electron mobility is high, and Schottky junction can be precisely manufactured and processed on a sub-micron scale, so that Schottky barrier diodes can be used in submillimeter wave and terahertz wave bands. Schottky diodes are metal-semiconductor devices made by using precious metals (gold, silver, aluminum, platinum, etc.) as positive electrodes and N-type semiconductors as negative electrodes, and using the potential barrier formed on the contact surface of the two to have the rectification characteristics. Because there are a large number of electrons in N-type semiconductors and only a very small number of free electrons in precious metals, electrons diffuse from semiconductors with high concentrations to metals with low concentrations. There are no holes in metals, so there is no diffusion movement of holes from metals to semiconductors. As electrons continue to diffuse from semiconductors to metals, the electron concentration on the semiconductor surface gradually decreases, and the surface electrical neutrality is destroyed, so a potential barrier is formed, and its electric field direction is semiconductor → metal. However, under the action of this electric field, electrons in the metal will also drift from metal → semiconductor, thereby weakening the electric field formed by the diffusion movement. When a space charge region of a certain width is established, the electron drift motion caused by the electric field and the electron diffusion motion caused by different concentrations reach a relative balance, and a Schottky barrier is formed. The internal circuit structure of a typical Schottky rectifier is based on an N-type semiconductor as a substrate, and an N-epitaxial layer with arsenic as a dopant is formed on it. The anode is made of materials such as molybdenum or aluminum to form a barrier layer. Silicon dioxide (SiO ₂ ) is used to eliminate the electric field in the edge area and improve the withstand voltage of the tube. The N-type substrate has a very small on-state resistance, and an N+ cathode layer is formed under the substrate, which serves to reduce the contact resistance of the cathode. By adjusting the structural parameters, a Schottky barrier is formed between the N-type substrate and the anode metal. When a forward bias is applied to both ends of the Schottky barrier (the anode metal is connected to the positive pole of the power supply, and the N-type substrate is connected to the negative pole of the power supply), the Schottky barrier layer becomes narrower and its internal resistance becomes smaller; conversely, if a reverse bias is applied to both ends of the Schottky barrier, the Schottky barrier layer becomes wider and its internal resistance becomes larger.

The work function of metal is Wm= _E0 - _EFm , and the work function of semiconductor is Ws= _E0 - _EFs . _E0 is the vacuum energy level, that is, the energy of a static electron in a vacuum, and the work function W is the difference between the vacuum energy level _E0 and the Fermi level _EF . _EFm is the Fermi level of metal, and _EFs is the Fermi level of semiconductor, indicating the minimum energy required for an electron with energy at the Fermi level to escape from the material into the vacuum. The size of the work function indicates the strength of the material's ability to bind electrons. When the work function of the metal is greater than the work function of the N-type semiconductor, in the case of metal-semiconductor contact, a very high electron potential barrier, namely the Schottky barrier, is formed on the metal side. Only electrons with energy higher than the barrier can flow from the metal to the semiconductor. Ideally, the height of the barrier on the metal side does not change with the bias voltage. Therefore, when a reverse bias is applied to the metal side, a large interface resistance will be generated. When a positive bias is applied to the metal side, the electrons flowing from the semiconductor to the metal will have a very small on-resistance after overcoming the built-in potential. This metal-semiconductor contact with different positive and negative characteristics is called a Schottky contact. When the work function of the metal is less than the work function of the N-type semiconductor, an ohmic contact is formed. If the metal is in contact with a P-type semiconductor, an ohmic contact is formed when the work function of the metal is greater than the work function of the P-type semiconductor, and a Schottky contact is formed when the work function of the metal is less than the work function of the P-type semiconductor.

In the embodiment of the present invention, the Schottky metal uses a metal with a high work function such as titanium (Ti), nickel (Ni), chromium (Cr), gold (Au), etc. to form a Schottky contact with an N-type silicon carbide semiconductor.

Preferably, the Schottky metal is adjacent to the N-drift layer and the source.

The Schottky metal is located between the N-drift layer and the source and is adjacent to the N-drift layer and the source. When the SiC UMOS is in the reverse state, the current flows from the source to the Schottky metal, from the Schottky metal to the N-drift layer, from the N-drift layer to the substrate, and from the substrate to the drain. The Schottky metal provides a channel for the current to flow from the source to the drain. The turn-on voltage of the Schottky diode composed of the Schottky metal and the N-drift layer is much smaller than the turn-on voltage of the SiC UMOS body diode. It can be turned on in advance when the SiC UMOS is reversed to play a freewheeling role.

Preferably, it further comprises: a CSL layer;

The CSL layer is located between the P-well layer and the N-drift layer;

The CSL layer is adjacent to the Schottky metal, the P-well layer, and the N-drift layer.

As a material layer of SiC UMOSFET, CSL layer (current spreading layer) is usually used to control carrier injection in semiconductor devices and improve device performance. In semiconductor devices, carrier injection refers to the process of injecting electrons or holes into semiconductor materials to generate current. However, this injection process may cause certain adverse effects, such as thermal effects, carrier capture and material damage. These effects will reduce the performance and life of the device. In order to solve these problems, the present invention introduces a CSL layer (current spreading layer), which can effectively limit carrier injection and diffusion while maintaining low resistance and high transparency. And because the doping concentration of the CSL layer is greater than the doping concentration of the N-drift layer, the higher the doping concentration of the N-type semiconductor, the smaller the work function, which enables SiC UMOSFET to better form Schottky contact with the metal and improve the performance of the device. It can also reduce the leakage current of SiC UMOSFET and improve the reliability of SiC UMOSFET. The production of the CSL layer (current spreading layer), that is, before the P-body layer is injected, a certain depth of N-type doping greater than the epitaxial layer concentration is performed to achieve the effect of increasing the current path and reducing the on-resistance.

In the present invention, the CSL layer can be used to replace part of the top N-drift layer and be adjacent to the Schottky metal. When the SiC UMOS is in a reverse state, the current flows from the source to the Schottky metal, from the Schottky metal to the N-drift layer, from the N-drift layer to the substrate, and from the substrate to the drain. The Schottky metal provides a channel for the current to flow from the source to the drain. The turn-on voltage of the Schottky diode formed by the Schottky metal and the N-drift layer is much lower than the turn-on voltage of the SiC UMOS body diode. When the SiC UMOS is reversed, it can be turned on in advance to play a freewheeling role.

Preferably, the dielectric constant of the HK dielectric layer is 100-300.

K represents a coefficient of insulation capability characteristics. The larger the value of K, the better the insulation performance of the material. In order to prevent leakage at the bottom of the source trench, the HK dielectric layer should use a material with a larger dielectric constant K to ensure the insulation performance at the bottom of the source trench. As a preferred embodiment, the present invention uses _TiO2 , _SrTiO3 , etc. as the material of the HK dielectric layer.

Preferably, the doping concentration of the CSL layer is 10 ¹⁶ cm ^-3 to 8×10 ¹⁶ cm ^-3 .

The doping concentration of the CSL layer affects the on-resistance of the SiC UMOS and the turn-on voltage of the Schottky diode. The higher the doping concentration of the CSL layer, the smaller the on-resistance of the SiC UMOS and the turn-on voltage of the Schottky diode. If the doping concentration of the CSL layer is too high, then when the SiC UMOS works normally, the Schottky metal part will also leak electricity, causing the SiC UMOS to fail. As a preferred embodiment, the present invention sets the doping concentration of the CSL layer to 10 ¹⁶ cm ^-3 , thereby reducing the on-resistance of the SiC UMOS and ensuring the normal working performance of the SiC UMOS.

Preferably, the width of the HK dielectric layer is 0.1-0.2 um greater than the width of the source trench.

The width of the HK dielectric layer must be larger than the width of the source to ensure the insulation performance at the bottom of the source trench, so that only the Schottky metal on the side wall of the bottom of the source trench can form a Schottky contact with the N-type semiconductor. At the same time, the electric field strength at the bottom of the source trench is large, and the HK dielectric layer can protect the bottom of the source trench from being broken down prematurely. As a preferred embodiment, the present invention sets the width of the HK dielectric layer to be 0.1um larger than the width of the source trench.

Preferably, the thickness of the CSL layer is 0.4-0.6 um.

The thickness of the CSL layer is equal to the width of the contact between the Schottky metal and the walls on both sides of the bottom of the source groove. The Schottky metal contacts the wall of the bottom of the source groove, and the Schottky metal adjacent to both sides of the bottom wall and the CSL layer together constitute a Schottky diode. The greater the thickness of the CSL layer, the greater the saturation current of the Schottky diode. If the thickness of the CSL layer is too large, it will cause leakage of the Schottky diode. If the thickness of the CSL layer is too small, the reverse freewheeling capability of the Schottky diode will be weak, which is insufficient to meet the requirements of SiC UMOS. As a preferred embodiment, the present invention sets the thickness of the CSL layer to 0.5um, so the height of the Schottky metal adjacent to the walls on both sides of the bottom of the source groove is also 0.5um, and the Schottky metal adjacent to the bottom surface of the source groove is adjacent to the P+ shielding layer. The Schottky metals of various parts are deposited adjacent to each other at the bottom of the source groove.

Preferably, it also includes: a source, a drain, a gate (G), a substrate (N-sub), an N-drift layer, a P-well layer (body region), a P+ region and an N+ region;

The drain is located below the substrate;

The drain is the charge sink in the MOSFET. It is connected to the channel and is the entrance of the charge. When the MOSFET is in the on state, a conductive path is formed between the drain and the source, and electrons flow from the source to the drain to complete the current transmission. The voltage change of the drain has little effect on the working state of the MOSFET, and mainly plays the role of current inflow.

The substrate is located below the HK dielectric layer and the N-drift layer;

The electric field distribution of the N-drift layer plays a key role in the conduction characteristics and current control of the MOSFET. When the gate voltage is applied to the MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the current flow between the source and the drain. When the MOSFET is working, the current between the source and the drain is mainly transmitted through the N-drift layer. The doping type and concentration of the N-drift layer determine the conduction type (N-type or P-type) and size of the current. The structure and characteristics of the N-drift layer directly affect the current control capability of the MOS tube. By adjusting the shape, size and doping concentration of the N-drift layer, precise control of the current can be achieved to meet the requirements of different applications.

The N-drift layer is located below the P-well layer;

The P-well layer is located below the N+ region;

The N+ region is located below the source;

The P+ region is located below the source and is adjacent to the N+ region, the P-well layer, and the N-drift layer;

The source is located above the gate, N+ region, and P+ region;

The source is the charge source in MOSFET and the charge outlet. When MOSFET is in the on state, a conductive path is formed between the source and the drain, and electrons flow from the source to the drain to complete the current transmission. At the same time, the source also plays the role of modulating the gate voltage, and the control of MOSFET is achieved by controlling the change of the source voltage.

The gate is located on both sides of the N+ region, the N-drift layer and the P+ region.

The gate is the control electrode in MOSFET, which is separated from the channel by an insulating layer and is the key part of MOSFET. The voltage change of the gate can change the charge density in the channel, thereby controlling the current between the drain and the source.

Example 2

A method for preparing a source trench integrated SBD and HK dielectric SiC UMOS, referring to FIG2 and FIG3, comprises:

S100, epitaxially forming a HK dielectric layer, an N-drift layer, a P-well layer and an N+ region on the substrate;

Epitaxial process refers to the process of growing a completely ordered single crystal layer on a substrate. The epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial process is widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxial methods are solid phase epitaxy and vapor phase epitaxy.

Solid phase epitaxy refers to the growth of a single crystal layer on a substrate using a solid source. For example, thermal annealing after ion implantation is actually a solid phase epitaxy process. During ion implantation, the silicon atoms of the silicon wafer are bombarded by high-energy implanted ions, leaving their original lattice positions and becoming amorphous, forming a surface amorphous silicon layer. After high-temperature thermal annealing, the amorphous atoms return to their lattice positions and remain consistent with the atomic crystal orientation inside the substrate.

The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. In the embodiment of the present invention, chemical vapor epitaxy (CVE) is used to form the N-drift layer. The principles of chemical vapor epitaxy and chemical vapor deposition (CVD) are basically the same. Both are processes for depositing thin films by chemically reacting on the surface of the wafer after gas mixing; the difference is that because chemical vapor epitaxy grows a single crystal layer, the requirements for the impurity content in the equipment and the cleanliness of the silicon wafer surface are higher. In integrated circuit manufacturing, CVE can also be used for epitaxial silicon wafer process and MOS transistor embedded source and drain epitaxial process. The epitaxial silicon wafer process is to epitaxially grow a layer of single crystal silicon on the surface of the silicon wafer. Compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, thereby improving the yield of semiconductor manufacturing. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as reducing substrate resistance and enhancing substrate isolation. The embedded source-drain epitaxy process refers to the process of epitaxially growing doped germanium silicon or silicon in the source-drain region of the transistor. The main advantages of introducing the embedded source-drain epitaxy process include: growing a pseudocrystalline layer containing stress due to lattice adaptation, improving channel carrier mobility; in-situ doping of the source and drain can reduce the parasitic resistance of the source-drain junction and reduce the defects of high-energy ion implantation.

S200, ion implantation is performed in the N+ region and the P-well layer to form a P+ region;

The present invention uses ion implantation to form a P+ region in the N+ region and the P-well layer. Ion implantation is to launch an ion beam in a vacuum toward a solid material. After the ion beam hits the solid material, it is resisted by the solid material and its speed is slowly reduced, and finally stays in the solid material. The ions of an element are accelerated into a solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacture of semiconductor devices, metal surface treatment, and material science research. If the ions stop and remain in the target, the ions will change the elemental composition of the target (if the ions are different from the composition of the target). The ion implantation beam line design contains a common functional component group. The main part of the ion beam line includes a device called an ion source for generating ion species. The source is closely coupled to the bias electrode to extract ions into the beam line, and most commonly is coupled to a certain way of selecting specific ion species for transmission into the main accelerator part. Mass selection is accompanied by the extracted ion beam passing through the magnetic field region, and its exit path is limited by blocking holes or slits, which only allow ions with mass and speed/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the surface to be implanted is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each dopant atom can create a charge carrier in the semiconductor after annealing. It can create a hole for a P-type dopant and an electron for an N-type dopant. This changes the conductivity of the semiconductor near the doped area.

S300, etching the N+ region, the P-well layer and both sides of the N-drift layer, etching through holes on the P+ region and the N-drift layer, etching trenches on the upper layer of the HK dielectric layer, and connecting the trenches with the through holes;

Etching is the process of selectively removing unwanted materials from the surface of silicon wafers by chemical or physical methods. It is a general term for stripping and removing materials by solutions, reactive ions or other mechanical methods. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Hereby, argon ions are irradiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they impact the material on the surface. The wafer is fed vertically or tilted into the ion beam and the etching process is absolutely anisotropic. The selectivity is low, since there is no differentiation of the individual layers. The gases and the ablated material are evacuated by the vacuum pump, however, since the reaction products are not gaseous, particles can be deposited on the wafer or on the chamber walls. All materials can be etched with this method and due to the vertical irradiation, the wear on the vertical walls is low.

Plasma etching is a chemical etching process with the advantage that the wafer surface is not damaged by accelerated ions. Due to the mobile particles of the etching gas, the etching profile is isotropic, so this method is used to remove entire film layers (such as backside cleaning after thermal oxidation). One type of reactor used for plasma etching is a downstream reactor, whereby the plasma is ignited at a high frequency of 2.45 GHz by impact ionization, the location of which is separated from the wafer.

The etching rate depends on the pressure, the power of the HF generator, the process gas, the actual gas flow rate and the wafer temperature. Anisotropy increases with increasing HF power, decreasing pressure and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed inhomogeneously, which leads to inhomogeneities. If the distance of the electrodes is increased, the etching rate decreases because the plasma is distributed in an enlarged volume. For the electrodes, carbon has proven to be the material of choice. Since fluorine and chlorine also attack carbon, the electrodes produce a uniform strained plasma, so the wafer edge is affected in the same way as the wafer center. Selectivity and etching rate depend largely on the process gas. For silicon and silicon compounds, fluorine and chlorine are mainly used.

S400, depositing gates on both sides of the N+ region, the P-well layer, and the N-drift layer, and depositing an ILD layer on the N+ region, the P+ region, and the N-drift layer;

The material of the ILD layer is generally _SiO2 or SiN. The purpose of depositing the ILD layer is to play an insulating role, block moisture, and protect the internal structure of the chip. The ILD layer includes multiple layers of film, and the thickness of each layer is different.

Polysilicon deposition is carried out using low pressure chemical vapor deposition (LPCVD) at low pressure conditions of 0.2-1.0 Torr and deposition temperatures between 600 and 650°C, using pure silane or silane diluted with nitrogen with a purity of 20% to 30%. The deposition rates of both deposition processes are between 100-200Å/min, which is mainly determined by the temperature during deposition. The resistivity of polysilicon depends on the temperature during deposition, the dopant concentration and the annealing temperature, and the annealing temperature will affect the grain size. Increasing the deposition temperature will cause the resistivity to decrease, increasing the dopant concentration will reduce the resistivity, and a higher annealing temperature will form larger grains and cause the resistivity to decrease accordingly. The larger the grain size of polysilicon, the more difficult its etching process is, because the large grain size will cause a rough polycrystalline sidewall, so polysilicon deposition must be carried out at a low temperature to obtain a smaller grain size, and after polysilicon etching and photoresist stripping, a high temperature annealing will form a larger grain size and a lower resistivity.

S500, depositing Schottky metal at the bottom of the trench;

In the chip manufacturing process, contact hole etching is a very important process step. In this step, contact holes are etched in the interlayer dielectric (ILD) layer, and then metal is filled in the contact holes to achieve the connection between the bottom device and the metal wire. The Schottky metal is deposited by chemical vapor deposition.

S500, depositing Schottky metal, source and drain.

Metal electrode deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to a method of depositing a coating on a wafer surface by chemical means, generally by applying energy to a mixed gas. Assuming that a substance (A) is deposited on the surface of a wafer, two gases (B and C) that can generate substance (A) are first input into the deposition equipment, and then energy is applied to the gases to cause a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputtering, arc plasma coating, ion coating and molecular beam epitaxy. The corresponding vacuum coating equipment includes vacuum evaporation coating machine, vacuum sputtering coating machine and vacuum ion coating machine.

Chemical vapor deposition (CVD) and physical vapor deposition (PVD) can both be used as technical means for depositing metal electrodes. In the embodiment of the present invention, the metal electrode is deposited by chemical vapor deposition, and the chemical vapor deposition process is divided into three stages: diffusion of the reaction gas to the substrate surface, adsorption of the reaction gas on the substrate surface, chemical reaction on the substrate surface to form solid deposits, and separation of the generated gas phase byproducts from the substrate surface.

Preferably, epitaxially forming a HK dielectric layer, an N-drift layer, a P-well layer and an N+ region on the substrate further comprises:

Before forming the P-well layer and the N+ region, a CSL layer is epitaxially formed over the N-drift layer and the P column.

After the N-drift layer and the HK dielectric layer are formed, a CSL layer is first epitaxially grown on the N-drift layer and the HK dielectric layer. The CSL layer is an N-type semiconductor with a doping concentration greater than that of the N-drift layer. Then the P-well layer is epitaxially grown. After the P-well layer is epitaxially grown, the N+ layer is epitaxially grown.

The present invention opens a source trench in the P+ region toward the N-drift layer, the source trench replaces part of the P+ region and the N-drift layer, and Schottky metal is deposited on the two side walls of the bottom of the source trench. Compared with the anti-parallel Schottky diode on the device surface in the prior art, the chip area is smaller, and the reverse current of the Schottky metals on both sides of the source is larger than that of the Schottky metal on one side of the source. Since the electric field strength under the source trench is large, the present invention arranges an HK dielectric layer under the source trench to shield the channel between the source and the drain and reduce leakage. The HK dielectric layer can improve the electric field distribution in the N-drift layer, alleviate the electric field spike under the source trench, prevent the SiC UMOS from being broken down prematurely, and significantly improve the reliability of the SiC UMOS.

The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims (3)

1. The source electrode trench integrated SBD and HK medium SiC UMOS is characterized by comprising: HK dielectric layer and schottky metal;

the HK dielectric layer is positioned between the source electrode groove and the substrate and is adjacent to the substrate and the N-drift layer;

the Schottky metal is positioned between the N-drift layer and the source electrode and is used for providing a conductive channel from the source electrode to the drain electrode;

the Schottky metal is located below the P+ region and is adjacent to the N-drift layer and the source electrode;

further comprises: a CSL layer;

the CSL layer is positioned between the P-well layer and the N-drift layer;

the CSL layer is adjacent to the Schottky metal, the P-well layer and the N-drift layer;

the dielectric constant of the HK dielectric layer is 100-300;

the doping concentration of the CSL layer is 10 ¹⁶ cm ^-3 Up to 8X 10 ¹⁶ cm ^-3 ；

The width of the HK dielectric layer is 0.1-0.2um larger than that of the source electrode groove, so that the insulation performance of the bottom of the source electrode groove is ensured, only the Schottky metal on the side wall of the bottom of the source electrode groove can form Schottky contact with the N-type semiconductor, meanwhile, the electric field intensity of the bottom of the source electrode groove is large, and the bottom of the source electrode groove can be protected from being broken down in advance by the HK dielectric layer;

the thickness of the CSL layer is 0.4-0.6um;

further comprises: the device comprises a source electrode, a drain electrode, a grid electrode, a substrate, an N-drift layer, a P-well layer, a P+ region and an N+ region;

the drain electrode is positioned below the substrate;

the substrate is positioned below the HK dielectric layer and the N-drift layer;

the N-drift layer is positioned below the P-well layer;

the P-well layer is positioned below the N+ region;

the N+ region is located below the source electrode;

the P+ region is positioned below the source electrode and is adjacent to the N+ region, the P-well layer and the N-drift layer;

the source electrode is positioned above the grid electrode, the N+ region and the P+ region;

the grid electrode is positioned at two sides of the N+ region, the N-drift layer and the P+ region.

2. The method for preparing the source trench integrated SBD and HK dielectric SiC UMOS of claim 1, comprising:

forming an HK dielectric layer, an N-drift layer, a P-well layer and an N+ region by epitaxy above a substrate;

ion implantation is carried out in the N+ region and the P-well layer to form a P+ region;

etching two sides of the N+ region, the P-well layer and the N-drift layer, etching through holes on the P+ region and the N-drift layer, etching grooves on the upper layer of the HK dielectric layer, and connecting the grooves with the through holes;

depositing grid electrodes on two sides of the N+ region, the P-well layer and the N-drift layer, and depositing an ILD layer above the N+ region, the P+ region and the N-drift layer;

depositing schottky metal, source and drain.

3. The method for preparing the source trench integrated SBD and HK dielectric SiC UMOS according to claim 2, wherein epitaxially forming an HK dielectric layer, an N-drift layer, a P-well layer, and an n+ region over the substrate further comprises:

and before forming the P-well layer and the N+ region, epitaxially forming a CSL layer above the N-drift layer and the HK dielectric layer.