CN117238914A - SiC device integrated with SBD and preparation method - Google Patents

Abstract

The invention provides an SBD-integrated SiC device and a preparation method. The SiC device includes: an integrated SBD; the integrated SBD is composed of a Schottky metal and a drift layer; the Schottky metal is located between the source and the drift layer. and adjacent to the source electrode and the drift layer; the drift layer is located above the substrate and adjacent to the substrate. A Schottky diode is integrated between the source and the drift layer. The turn-on voltage of the Schottky diode is much lower than that of the body diode. When the SiC device is in the reverse state, it can conduct earlier than the body diode, which is reverse freewheeling. It provides a conduction path to protect SiC devices from being damaged by excessive reverse current. It also adds a P-type floating island layer to protect the gate oxide layer and reduce switching losses, which significantly improves the electrical performance of SiC devices.

Description

A SiC device integrated with SBD and its preparation method

Technical field

The invention relates to the field of semiconductor technology, and in particular to a SiC device integrating SBD and a preparation method.

Background technique

The third generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturation electron migration rate, stable physical and chemical properties, etc., and can be applied to high temperature, high frequency, high power and extreme environments. Silicon carbide has a larger bandgap and higher critical breakdown field strength. Compared with silicon power devices under the same conditions, the voltage resistance of silicon carbide devices is about 10 times that of silicon materials. In addition, silicon carbide devices have high electron saturation rate, small forward conduction resistance, and low power loss. They are suitable for high-current and high-power applications and reduce the requirements for heat dissipation equipment. SiC has unique physical, chemical and electrical properties and is a semiconductor material with great development potential in extreme application fields such as high temperature, high frequency, high power and radiation resistance. The insulation breakdown field strength of power devices made of silicon carbide is 10 times that of Si, and the band gap is 3 times that of Si. Moreover, the impedance of the floating layer of SiC devices is lower than that of Si devices. It can be implemented with MOSFET without conductivity modulation. High withstand voltage and low impedance.

MOS field effect transistor power devices made of silicon carbide materials can withstand higher voltages and faster switching speeds than Si devices. For conventional Si MOS, its body diode turn-on voltage is only about 0.7V, so it is often used as a freewheeling channel under reverse bias of MOSFET. However, due to the wider band gap of SiC material, the turn-on voltage of the body diode of SiC MOSFET is too high (2.7-3.0V), making it difficult to play the role of freewheeling protection MOSFET under reverse bias.

Contents of the invention

The purpose of the present invention is to provide an SBD-integrated SiC device and a preparation method. The SiC device integrates a Schottky diode between the source and the drift layer. The turn-on voltage of the Schottky diode is much lower than that of the body diode. When the SiC device When the device is in the reverse state, it can conduct earlier than the body diode, providing a conduction path for reverse freewheeling and protecting the SiC device from being damaged by excessive reverse current. A P-type floating island layer is also added to protect the gate. The anodized layer and reduced switching losses significantly improve the electrical performance of SiC devices.

A SiC device with integrated SBD, including: integrated SBD;

The integrated SBD is composed of Schottky metal and drift layer;

The Schottky metal is located between the source electrode and the drift layer and adjacent to the source electrode and the drift layer;

The drift layer is located above and adjacent to the substrate.

Preferably, the drift layer includes: a first drift layer and a second drift layer;

The first drift layer is located between the substrate and the second drift layer and adjacent to the substrate and the second drift layer;

The second drift layer is located above the first drift layer.

Preferably, the doping concentration of the first drift layer is smaller than the doping concentration of the second drift layer.

Preferably, it also includes: P-type floating island layer;

The P-type floating island layer is embedded in the drift layer;

The P-type floating islands are arranged in layers.

Preferably, the width of the P-type floating island layer located below is smaller than the width of the P-type floating island layer located above.

Preferably, the doping concentration of the first drift layer is 10 ¹⁶ cm ^-3 .

Preferably, the doping concentration of the second drift layer is 10 ¹⁷ cm ^-3 .

Preferably, the doping concentration of the P-type floating island layer is 10 ¹⁸ cm ^-3 .

Preferably, the width of the P-type floating island layer is the width of the SiC device. to/> .

A method for preparing SBD-integrated SiC devices, including:

Epitaxially layer a drift layer with a low doping concentration above the substrate;

A high-doping concentration drift layer is epitaxially grown on the low-doping concentration drift layer and ion-implanted to form a P-type floating island layer, a P-body layer, a P+ region, and an N+ region;

Etch the P+ region to form a trench;

depositing a gate electrode and etching the gate electrode to form a trench;

The source and drain are deposited after Schottky metal is deposited in the trench.

In the present invention, a Schottky diode is provided below the source for reverse freewheeling. When the SiC device is operating normally, the Schottky diode is in a high-resistance state and does not conduct. When the SiC device is connected to a reverse voltage, the Schottky diode Turn on, providing a freewheeling channel so that current can flow from the source to the Schottky metal, then from the Schottky metal to the drift layer, from the drift layer to the substrate and finally to the drain. Due to the forbidden bandwidth of the silicon carbide material, the body diode is turned on The voltage is very high, and it is difficult to protect the SiC device during reverse freewheeling. Therefore, the present invention uses a Schottky diode to protect the SiC device. The turn-on voltage of the Schottky diode is much lower than that of the body diode, and it can provide sufficient power when the SiC device reverses direction. current path, improving the safety and stability of SiC devices.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those of ordinary skill in the art, It is said that other drawings can be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic structural diagram of the SiC device of the present invention;

Figure 2 is a schematic diagram of the SiC device preparation process method of the present invention;

Figure 3 is a schematic structural diagram of the SiC device preparation process of the present invention.

Explanation of reference symbols:

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiment of the present invention are only used to explain the relationship between components in a specific posture (as shown in the drawings). Relative positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

In addition, descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor within the protection scope required by the present invention.

MOS field effect transistor power devices made of silicon carbide materials can withstand higher voltages and faster switching speeds than Si devices. For conventional Si MOS, its body diode turn-on voltage is only about 0.7V, so it is often used as a freewheeling channel under reverse bias of MOSFET. However, due to the wider band gap of SiC material, the turn-on voltage of the body diode of SiC MOSFET is too high (2.7-3.0V), making it difficult to play the role of freewheeling protection MOSFET under reverse bias.

In the present invention, a Schottky diode is provided below the source for reverse freewheeling. When the SiC device is operating normally, the Schottky diode is in a high-resistance state and does not conduct. When the SiC device is connected to a reverse voltage, the Schottky diode Turn on, providing a freewheeling channel so that current can flow from the source to the Schottky metal, then from the Schottky metal to the drift layer, from the drift layer to the substrate and finally to the drain. Due to the forbidden bandwidth of the silicon carbide material, the body diode is turned on The voltage is very high, and it is difficult to protect the SiC device during reverse freewheeling. Therefore, the present invention uses a Schottky diode to protect the SiC device. The turn-on voltage of the Schottky diode is much lower than that of the body diode, and it can provide sufficient power when the SiC device reverses direction. current path, improving the safety and stability of SiC devices.

Example 1

A SiC device with integrated SBD, refer to Figure 1, including: integrated SBD;

The integrated SBD consists of Schottky metal 4 and drift layer;

The contact surface between metal and semiconductor is divided into two types: Schottky contact and Ohmic contact. Ohmic contact is when the doping concentration of the semiconductor is very high. When the semiconductor with high doping concentration comes into contact with the metal, a low barrier layer is formed. The electrons can pass through the barrier through the tunnel effect, thus forming a low resistance ohmic contact. Ohmic contact The characteristic is that the current-voltage characteristics of the contact surface are linear, and the contact resistance is negligible compared to the bulk resistance of the semiconductor. When a current passes through, the voltage drop generated is smaller than the voltage drop on the device. Schottky diode is a metal-semiconductor device made of noble metal (gold, silver, aluminum, platinum, etc.) as the positive electrode and an N-type semiconductor as the negative electrode. The potential barrier formed on the contact surface of the two has rectifying characteristics. Because there are a large number of electrons in N-type semiconductors and only a very small amount of free electrons in noble metals, electrons diffuse from the semiconductor with high concentration to the metal with low concentration. Obviously, there are no holes in the metal, and there is no diffusion movement of holes from the metal to the semiconductor. By adjusting the structural parameters, a Schottky barrier is formed between the N-type substrate and the anode metal. When a forward bias is applied to both ends of the Schottky barrier (the anode metal is connected to the positive electrode of the power supply, and the N-type substrate is connected to the negative electrode of the power supply), the Schottky barrier layer becomes narrower and its internal resistance becomes smaller; conversely, if When reverse bias is applied to both ends of the Schottky barrier, the Schottky barrier layer becomes wider and its internal resistance becomes larger.

The present invention uses Schottky metal 4 and the N-type SiC epitaxial layer to form a heterojunction, which conducts when the SiC device is in the reverse state and is in a high resistance state when the SiC device operates normally. When the SiC device conducts in the reverse state, The current flows from the source electrode 10 to the Schottky metal 4 , then flows from the Schottky metal 4 to the drift layer, flows from the drift layer to the substrate 12 , and finally flows from the substrate 12 to the drain electrode 11 . The turn-on voltage of the Schottky diode is much lower than the turn-on voltage of the body diode of the SiC device, which can effectively improve the reverse performance of the SiC device.

Schottky metal 4 is located between the source electrode 10 and the drift layer and adjacent to the source electrode 10 and the drift layer;

The Schottky diode composed of Schottky metal 4 and N-type SiC epitaxial layer is used to provide a reverse freewheeling channel. As a preferred embodiment, the Schottky metal 4 of the present invention is disposed between the source electrode 10 and the drift layer. and adjacent to the source electrode 10 and the drift layer. When the source electrode 10 is connected to a high potential (positive electricity) and the drain electrode 11 is connected to a low potential (negative electricity), current can flow from the source electrode 10 through the Schottky diode and then to the drain electrode 11 .

The drift layer is located above and adjacent to substrate 12 .

The electric field distribution of the drift layer plays a key role in the conduction characteristics and current control of MOSFET. When a gate voltage is applied to the MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source 10 and the drain 11 . When the MOSFET is operating, the current between the source 10 and the drain 11 is mainly transmitted through the drift layer. The doping type and concentration of the drift layer determine the conduction type (N-type or P-type) and magnitude of the current. The structure and characteristics of the drift layer directly affect the current control capability of the MOS tube. By adjusting the shape, size and doping concentration of the drift layer, precise control of the current can be achieved to meet the requirements of different applications.

Preferably, the drift layer includes: a first drift layer 1 and a second drift layer 3;

The first drift layer 1 is located between the substrate 12 and the second drift layer 3 and adjacent to the substrate 12 and the second drift layer 3;

The second drift layer 3 is located above the first drift layer 1 .

Preferably, the doping concentration of the first drift layer 1 is smaller than the doping concentration of the second drift layer 3 .

The present invention sets up two drift layers with different doping concentrations. The lower layer is the first drift layer 1 and the upper layer is the second drift layer 3. In order to allow the current to flow normally from the SiC device, the doping layer of the first drift layer 1 is The impurity concentration is set to be smaller than the doping concentration of the second drift layer 3. When the SiC device operates normally, the current flows from the drain 11 to the first drift layer 1, then from the first drift layer 1 to the second drift layer 3 and finally to the source. 10. If the doping concentration of the first drift layer 1 is greater than the doping concentration of the second drift layer 3, then it will be difficult for the current to flow from the first drift layer 1 to the second drift layer 3, resulting in a reduction in the electrical performance of the SiC device and affecting the SiC device. The device is functioning normally.

Compared with the conventional drift layer with uniform doping concentration, the present invention increases the doping concentration of the second drift layer 3 in order to reduce the on-resistance and increase the current path. In the present invention, the first drift layer 1 The area ratio to the second drift layer 3 is 1:1 to 1.5:1. If the area ratio of the first drift layer 1 and the second drift layer 3 is too different, it will lead to insufficient forward voltage withstand capability of the SiC device. If the proportion of the second drift layer 3 is small, the improvement effect on the on-resistance will be weakened. As a preferred embodiment, the present invention sets the area ratio of the first drift layer 1 to the second drift layer 3 to 1:1, significantly improving the forward performance of SiC devices.

Preferably, it also includes: P-type floating island layer 2;

P-type floating island layer 2 is embedded in the drift layer;

Floating island device (floating junction device) refers to a special power device. It is embedded in the drift layer and is not directly connected to the electrode. It is a region with the opposite doping type to that of the drift layer. The doping type in the drift layer is In N-type floating island devices, the floating island structure is composed of P-type doped semiconductors. SiC devices adopt a new voltage-resistant structure - the floating island structure, with the purpose of improving the relationship between breakdown voltage and specific on-resistance and overcoming the difficulty of the super-junction manufacturing process. By introducing multiple floating island structures of opposite doping types into the silicon-based drift layer, the resistivity of the power device is increased while the breakdown voltage remains unchanged, and the power loss is reduced. The fundamental reason is that the floating island introduces a new electric field peak into the drift layer, which reduces the maximum electric field peak in the drift layer. Therefore, under the same breakdown voltage, the device ratio can also be reduced by increasing the doping concentration of the drift layer. On-resistance. And the breakdown voltage of power SiC devices with floating island structure will increase as the number of floating islands increases.

The P-type floating island layers 2 are stacked.

The present invention increases the withstand voltage performance, gate oxide reliability and reduces gate leakage capacitance of SiC devices by setting at least one P-type floating island. As a preferred embodiment, the present invention sets four P-type floating islands, four P-type The floating islands are embedded on both sides of the drift layer. There are two P-type floating islands on the left and two P-type floating islands on the right. Multiple P-type floating islands on one side are stacked. The intervals between the P-type floating islands are separated by P-type floating islands. The number and thickness of the islands are determined by the preparation method of P-type floating islands: when the drift layer is epitaxially extended to a certain thickness, ion implantation is performed on the upper layer of the drift layer to prepare two P-type floating islands, and then a thin drift layer is epitaxially formed. Then, ions are implanted again in the epitaxial drift layer to form the second P-type floating island layer 2, and then epitaxy is performed again on top of the P-type floating island layer 2 to complete the production of the drift layer. The doping concentration of the P-type floating island layer 2 The higher the height and the width, the stronger the protective effect on the gate oxide layer 8 and the ability to improve the voltage resistance performance. However, when making the P-type floating island layer 2, care must be taken to leave sufficient current paths, so the P-type The doping concentration and width of the floating island layer 2 should be set to an upper limit based on the performance of the SiC device.

The present invention improves the withstand voltage of the SiC device without affecting the current path of the SiC device itself by introducing a plurality of P-type floating island layers 2 with the opposite doping type to the drift layer (N-drift layer) in the device drift layer. performance, effectively improving the relationship between the breakdown voltage and specific on-resistance of traditional SiC devices, and the P-type floating island layer 2 can also protect the gate oxide layer 8 in the JFET area and prevent the gate oxide layer 8 from premature breakdown. Moreover, the P-type floating island can reduce the overlapping area of the gate 7 and the drain 11, reduce the gate-drain capacitance, reduce switching losses, and improve the electrical performance of the SiC device.

Preferably, the width of the P-type floating island layer 2 located below is smaller than the width of the P-type floating island layer 2 located above.

The width of the P-type floating island layer 2 is set according to the electric field intensity distribution of the SiC device. As a preferred embodiment, the present invention sets the width of the lower P-type floating island layer 2 to be smaller than the upper P-type floating island. The width of layer 2. It can better smooth the electric field lines, reduce the electric field intensity in the JFET area, and protect the gate oxide layer 8 from premature breakdown.

Preferably, the doping concentration of the first drift layer 1 is 10 ¹⁶ cm ^-3 .

Preferably, the doping concentration of the second drift layer 3 is 10 ¹⁷ cm ^-3 .

In SiC devices, appropriately increasing the doping concentration of the drift layer can reduce the on-resistance. In order to reduce the on-resistance while enabling the SiC device to operate normally, the present invention increases the doping concentration of the second drift layer 3. Appropriately increase, so that the on-resistance of the SiC device is significantly reduced. As a preferred embodiment, the present invention sets the doping concentration of the first drift layer 1 to 10 ¹⁶ cm ^-3 and the doping concentration of the second drift layer 3. is 10 ¹⁷ cm ^-3 .

Preferably, the doping concentration of the P-type floating island layer 2 is 10 ¹⁸ cm ^-3 .

Because the P-type floating island needs to be charge-balanced with the drift layer, the doping concentration of the P-type floating island layer 2 is affected by the doping concentration of the drift layer. When the SiC device is in the reverse state, the P-type floating island layer 2 and the drift layer mutual depletion. If the doping concentration of the drift layer is high, the doping concentration of the P-type floating island layer 2 will also increase accordingly. If the concentration of the drift layer is too low, it will not be able to reduce the on-resistance of the SiC device. Moreover, the doping concentration of the P-type floating island layer 2 is also affected by the thickness of the gate oxide layer 8. If the thickness of the gate oxide layer 8 is thin and the withstand voltage capability is weak, then the doping concentration of the P-type floating island layer 2 needs to be The higher the doping concentration of the P-type floating island layer 2, the stronger the ability to improve the electric field line distribution and the better the protection ability of the gate oxide layer 8. However, the doping concentration of the P-type floating island layer 2 is While increasing, sufficient current paths must be left, so as a preferred embodiment, the present invention sets the doping concentration of the P-type floating island layer 2 to 10 ¹⁸ cm ^-3 , which can better protect the gate oxide layer 8. It can also reduce switching losses and greatly improve the electrical performance of SiC devices.

Preferably, the width of the P-type floating island layer 2 is the width of the SiC device. to/> .

The width of the P-type floating island layer 2 will also affect the protection ability of the gate oxide layer 8 and the impact on the current path. The wider the width of the P-type floating island layer 2, the protective ability of the gate oxide layer 8 will become worse. Strong will cause the current path to become smaller. If the width of the P-type floating island layer 2 is too narrow, it will lead to insufficient protection of the gate oxide layer 8. Therefore, the present invention sets the minimum width of the P-type floating island layer 2 to SiC device width , if the width of the P-type floating island layer 2 is too wide, the current path of the SiC device will be narrowed, so the present invention sets the maximum width of the P-type floating island layer 2 to the width of the SiC device/> . Within this interval, the P-type floating island layer 2 can better protect the gate oxide layer 8 while leaving a sufficient current path.

Example 2

A method for preparing SBD-integrated SiC devices, refer to Figures 2 and 3, including:

S100, epitaxially extend a low doping concentration drift layer (first drift layer 1) over the substrate 12;

The epitaxial process refers to the process of growing a completely ordered single crystal layer on the substrate 12 . Generally speaking, the epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source-drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, etc. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxy methods are solid-phase epitaxy and vapor-phase epitaxy.

Solid-phase epitaxy refers to the growth of a single crystal layer on a substrate by a solid source. For example, thermal annealing after ion implantation is actually a solid-phase epitaxy process. During ion implantation processing, the silicon atoms of the silicon wafer are bombarded by high-energy implanted ions, leaving the original crystal lattice position and becoming amorphous, forming a surface amorphous silicon layer. After high-temperature thermal annealing, the amorphous atoms return to the original lattice position. The lattice position is consistent with the atomic orientation within the substrate.

The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. In the embodiment of the present invention, chemical vapor epitaxy (CVE) is used to form the N-drift layer. The principles of chemical vapor epitaxy and chemical vapor deposition (CVD) are basically the same. They are both processes that use gas mixture to react chemically on the surface of the wafer to deposit thin films. The difference is that because chemical vapor epitaxy grows a single crystal layer, it requires a lot of equipment. The impurity content in the silicon wafer and the cleanliness requirements on the silicon wafer surface are both higher. In integrated circuit manufacturing, CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source-drain epitaxial processes. The epitaxial silicon wafer process is to epitaxially extend a layer of single crystal silicon on the surface of the silicon wafer. Compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, thus improving the yield of semiconductor manufacturing. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to device design. For example, it can be used to reduce substrate resistance, enhance substrate isolation, etc. The embedded source-drain epitaxy process refers to the process of epitaxially growing doped silicon germanium or silicon in the source and drain regions of the transistor. The main advantages of introducing the embedded source-drain epitaxial process include: it can grow a pseudocrystalline layer that contains stress due to lattice adaptation, improving channel carrier mobility; it can dope the source and drain in situ, reducing the parasitic resistance of the source-drain junction , Reduce the defects of high-energy ion implantation.

S200, epitaxially extend a high-doping concentration drift layer on top of the low-doping concentration drift layer and ion-implant to form the P-type floating island layer 2, P-body layer 9, P+ region 5, and N+ region 6;

The present invention uses ion implantation to form the P-type floating island layer 2, P+ region 5 and N+ region 6. Ion implantation is to emit an ion beam in a vacuum towards a solid material. After the ion beam hits the solid material, its speed slowly slows down due to the resistance of the solid material, and finally stays in the solid material. The ions of an element are accelerated into a solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacturing of semiconductor devices, metal surface treatment, and materials science research. If the ions are stopped and retained in the target, the ions will change the elemental composition of the target (if the ions are of a different composition than the target). Ion implantation beamline designs all contain a common set of functional components. The main part of an ion beamline consists of a device called an ion source, which is used to generate ion species. The source is tightly coupled to a bias electrode to extract ions into the beamline, and most commonly to some means of selecting specific ion species for transport into the main accelerator section. The "mass" selection accompanies the extracted ion beam through the magnetic field region, with its exit path restricted by blocking holes or "slits" that only allow ions with mass and velocity/charge to continue along the beamline. If the target surface is larger than the ion beam diameter, and the implant dose is evenly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When injected into a semiconductor, each dopant atom can generate charge carriers in the semiconductor after annealing. A hole can be created for P-type dopants and an electron for N-type dopants. Changes the conductivity of the semiconductor near the doped region.

S300, etching the P+ region 5 to form a trench;

In the present invention, both sides of the P+ region 5 are etched to form polysilicon trenches. Etching is the process of selectively removing unwanted materials from the surface of silicon wafers using chemical or physical methods. It is a general term for stripping and removing materials through solutions, reactive ions or other mechanical means. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Thereby, argon ions are radiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they hit the material on the surface. With the wafer vertical or tilted into the ion beam, the etching process is absolutely anisotropic. Selectivity is low as there is no difference between layers. The gases and ground material are removed by a vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched using this method, with very low wear on vertical walls due to vertical radiation.

Plasma etching is an absolute chemical etching process. The advantage is that the wafer surface will not be damaged by accelerated ions. Due to the mobile particles of the etching gas, the etching profile is isotropic, so this method is used to remove the entire film layer (e.g. backside cleaning after thermal oxidation). One type of reactor used for plasma etching is the downstream reactor. Thus, plasma is ignited at a high frequency of 2.45GHz through impact ionization, and the location of impact ionization is separated from the wafer.

The etch rate depends on the pressure, power of the high frequency generator, process gas, actual gas flow and wafer temperature. Anisotropy increases with increasing high-frequency power, decreasing pressure, and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes, and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed unevenly, resulting in inhomogeneity. If the distance between the electrodes is increased, the etch rate decreases because the plasma is distributed in an enlarged volume. For electrodes, carbon has proven to be the material of choice. Because fluorine and chlorine gases also attack carbon, the electrodes create a uniformly strained plasma so the edges of the wafer are affected in the same way as the center of the wafer. Selectivity and etch rate are highly dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.

S400, deposit the gate electrode 7 and etch the gate electrode 7 to form a trench;

The steps of depositing the gate electrode 7 are: the formation of the gate oxide layer 8 and the deposition of polysilicon. The present invention uses wet oxidation or dry oxidation to deposit the oxide layer. According to the different oxidants in the oxidation reaction, the thermal oxidation process can be divided into dry oxidation and wet oxidation. The former uses pure oxygen to produce a silicon dioxide layer and is slow. However, the oxide layer is thin and dense, and the latter requires the use of both oxygen and highly soluble water vapor. It is characterized by a fast growth rate but a relatively thick protective layer and low density. Wet oxidation has two main steps: the mass transfer process of oxygen in the air from the gas phase to the liquid phase; and the chemical reaction between dissolved oxygen and the substrate. If the mass transfer process affects the overall reaction rate, it can be eliminated by strengthening stirring. In embodiments of the present invention, the temperature, pressure, and concentration of the reaction gas during wet oxygen oxidation can be controlled to control the rate at which the oxide layer of the source electrode 10 is formed by wet oxygen oxidation, thereby achieving the purpose of controlling the thickness of the oxide layer of the source electrode 10 .

Dry oxidation uses high-temperature pure oxygen to directly react with the wafer. Dry oxidation only uses pure oxygen (O ₂ ), so the growth rate of the oxide film is slow. It is mainly used to form thin films and can form oxides with good conductivity. The advantage of dry oxidation is that no by-product (H ₂ ) is produced, and the uniformity and density of the oxide film are high.

Polysilicon deposition is when silicide is stacked on the first layer of polysilicon (Poly1) to form gate electrodes and local connections, and the second layer of polysilicon (Poly2) forms contact plugs between source 10/drain 11 and cell connections. The silicide is stacked on the third layer of polysilicon (Poly3) to form the unit connection. The fourth layer of polysilicon (Poly4) and the fifth layer of polysilicon (Poly5) form the two electrodes of the storage capacitor. Sandwiched between them is a high dielectric coefficient of dielectric. To maintain the desired capacitance value, the size of the capacitor can be reduced by using a high-k dielectric. Polycrystalline silicon deposition is a type of low-pressure chemical vapor deposition (LPCVD), by placing arsenic (AH ₃ ), phosphorus (PH ₃ ) or diborane (B ₂ H ₆ ) in a reaction chamber (i.e., a furnace tube). By directly inputting the doping gas into the silicon material gas of silane or DCS, the polysilicon doping process of on-site low-pressure chemical vapor deposition can be carried out. Polysilicon deposition is carried out under low pressure conditions of 0.2-1.0 Torr and deposition temperatures between 600 and 650°C, using pure silane or silane with a purity of 20% to 30% after dilution with nitrogen. The deposition rate of both deposition processes is between 100-200Å/min, mainly determined by the temperature during deposition.

S500, after depositing the Schottky metal 4 in the trench, the source electrode 10 and the drain electrode 11 are deposited.

Metal electrode deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to the method of chemically depositing coatings on the surface of wafers, generally by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

Both chemical vapor deposition (CVD) and physical vapor deposition (PVD) can be used as technical means to deposit metal electrodes. In embodiments of the present invention, a chemical vapor deposition method is used to deposit metal electrodes. The chemical vapor deposition process is divided into three stages: diffusion of reaction gas to the surface of the substrate, adsorption of the reaction gas on the surface of the substrate, and chemical reaction on the surface of the substrate to form a solid deposition. The substances and the gas phase by-products produced are separated from the surface of the matrix. The most common chemical vapor deposition reactions are: thermal decomposition reactions, chemical synthesis reactions and chemical transport reactions. Usually, to deposit TiC or TiN, gases such as TiCl ₄ , H ₂ , and CH ₄ are introduced into a reaction chamber at 850 to 1100°C. After chemical reaction, a coating is formed on the surface of the substrate.

The present invention sets a Schottky diode under the source 10 for reverse freewheeling. When the SiC device is operating normally, the Schottky diode is in a high resistance state and does not conduct. When the SiC device is connected to a reverse voltage, the Schottky diode The diode is turned on, providing a freewheeling channel so that the current can flow from the source 10 to the Schottky metal 4, then from the Schottky metal 4 to the drift layer, from the drift layer to the substrate 12 and finally to the drain 11. Due to the silicon carbide material The forbidden bandwidth and the body diode turn-on voltage are very high, making it difficult to protect the SiC device during reverse freewheeling. Therefore, the present invention uses a Schottky diode to protect the SiC device. The turn-on voltage of the Schottky diode is much lower than that of the body diode. When the SiC device reverses the flow, It can provide sufficient current path to improve the safety and stability of SiC devices.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. A SiC device with integrated SBD, characterized by comprising: integrated SBD; The integrated SBD is composed of Schottky metal and drift layer; The Schottky metal is located between the source electrode and the drift layer and adjacent to the source electrode and the drift layer; The drift layer is located above and adjacent to the substrate. 2. An SBD-integrated SiC device according to claim 1, wherein the drift layer includes: a first drift layer and a second drift layer; The first drift layer is located between the substrate and the second drift layer and adjacent to the substrate and the second drift layer; The second drift layer is located above the first drift layer. 3. An SBD-integrated SiC device according to claim 2, wherein the doping concentration of the first drift layer is smaller than the doping concentration of the second drift layer. 4. An SBD-integrated SiC device according to claim 1, further comprising: a P-type floating island layer; The P-type floating island layer is embedded in the drift layer; The P-type floating islands are arranged in layers. 5. An SBD-integrated SiC device according to claim 4, wherein the width of the P-type floating island layer located below is smaller than the width of the P-type floating island layer located above. 6. An SBD-integrated SiC device according to claim 3, wherein the doping concentration of the first drift layer is 10 ¹⁶ cm ^-3 . 7. An SBD-integrated SiC device according to claim 3, wherein the doping concentration of the second drift layer is 10 ¹⁷ cm ^-3 . 8. An SBD-integrated SiC device according to claim 4, wherein the doping concentration of the P-type floating island layer is 10 ¹⁸ cm ^-3 . 9. An SBD-integrated SiC device according to claim 4, characterized in that the width of the P-type floating island layer is 10 times the width of the SiC device. to/> . 10. A method for preparing an SBD-integrated SiC device, characterized by comprising: Epitaxially layer a drift layer with a low doping concentration above the substrate; Epitaxially layer a high-doping-concentration drift layer above the low-doping-concentration drift layer and ion-implant it to form a P-type floating island layer, a P-body layer, a P+ region, and an N+ region; Etch the P+ region to form a trench; depositing a gate electrode and etching the gate electrode to form a trench; The source and drain are deposited after Schottky metal is deposited in the trench.