CN116845092A - SiC power semiconductor device integrated with Schottky diode - Google Patents

Abstract

The invention relates to a SiC power semiconductor device integrating a Schottky diode and belongs to the technical field of power semiconductor devices. Among them, the first type of conductive channel and the second type of conductive channel are both in ohmic contact with the front first electrode metal above the SiC substrate, so that the first type of conductive channel and the second type of conductive channel can be used to simultaneously form the power semiconductor device. Current channel; the front first electrode metal is also in Schottky contact with the SiC substrate corresponding to the active area to form a number of Schottky contact areas for Schottky diode integration, and the Schottky contact area is located on the first In the second type conductive channel, the Schottky contact region is surrounded by the second conductive type doped region of the second type conductive channel in the second type conductive channel. The invention can effectively realize the integration of Schottky diodes, form good electric field protection, and reduce reverse leakage. When the integrated Schottky diode is used for freewheeling, the turn-on voltage is low and the freewheeling loss is low.

Description

SiC power semiconductor device with integrated Schottky diode

Technical field

The invention relates to a power semiconductor device, in particular to a SiC power semiconductor device integrating a Schottky diode.

Background technique

As a third-generation wide-bandgap material, silicon carbide (SiC) has the advantages of large bandgap width, high critical breakdown electric field, high thermal conductivity, and high carrier saturation velocity, so it is very popular in the field of power devices.

Silicon carbide metal oxide field effect transistors (MOSFETs) perform well in power devices. Due to the high critical breakdown electric field characteristics of silicon carbide materials, SiC MOSFET devices can achieve 10 times the withstand voltage of Si MOSFET devices, which is close to 1/ The drift area resistance of 300 has obvious application advantages. In addition, silicon carbide metal oxide field effect transistor (MOSFET) not only has the characteristics of SiC material such as high blocking voltage, high operating junction temperature, and strong radiation resistance, but also has the characteristics of easy driving, simple control, high operating frequency, and low switching loss. With such advantages, it is one of the ideal switching devices used in motor drives, high-end energy storage, power electronic transformers and other fields, and has broad development prospects.

During the manufacturing process of SiC MOSFET devices, more interface states will be formed at the bottom of the gate oxide layer, resulting in low channel mobility and high channel resistance. Therefore, one of the key factors to improve device performance is to reduce channel resistance. Common optimization methods are to increase channel mobility through process optimization, and to achieve higher density channels through structural design. The latter is more compatible and Universality. At the same time, when realizing high-density channels through structural design, problems of reduced reliability and short-circuit capability will be introduced. How to achieve SiCMOSFET devices with high conduction performance, high reliability, and strong short-circuit capability is what practitioners today need to think about. question.

In addition, the parasitic body diode in the SiC MOSFET device can generally serve as a freewheeling diode; however, the body diode, as a PIN diode of the SiC MOSFET device, has a high turn-on voltage, resulting in high losses in the SiC MOSFET device. How to reduce The losses in the freewheeling diode are worth exploring.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art and provide a SiC power semiconductor device integrating Schottky diodes, which can effectively realize the integration of Schottky diodes, form good electric field protection, and reduce reverse leakage. , when using the integrated Schottky diode for freewheeling, the turn-on voltage is low and the freewheeling loss is low.

According to the technical solution provided by the present invention, the SiC power semiconductor device with integrated Schottky diode includes a SiC substrate with a first conductivity type and an active area prepared in the central area of the SiC substrate; within the active area It includes several planar cells distributed side by side;

For any planar cell, include a first type conductive channel located in the active area;

In the active area, a second type of conductive channel is also included to increase the channel density, where,

Both the first type conductive channel and the second type conductive channel are in ohmic contact with the front first electrode metal above the SiC substrate, so that the first type conductive channel and the second type conductive channel are used to simultaneously form the current channel of the power semiconductor device ;

The front first electrode metal is also in Schottky contact with the SiC substrate corresponding to the active area to form a number of Schottky contact areas for Schottky diode integration. The Schottky contact areas are located in the second type of conductive area. in the channel, and the Schottky contact region is surrounded by a second conductive type doped region of the second conductive channel in the second conductive channel.

The channel length of the second type conductive channel is consistent with the channel length of the first type conductive channel;

The first type of conductive channel includes a first type of conductive channel and a second conductive type well region located in the SiC substrate. The second type of conductive channel includes a second type of conductive channel located in the SiC substrate. type well region, where,

In the cross section of the power semiconductor device, the lateral width of the second conductive type well region of the second conductive channel is smaller than the lateral width of the second conductive type well region of the first conductive channel.

The second type conductive channel also includes a second type conductive channel first conductive type source region disposed in the second conductive type well region of the second type conductive channel, wherein,

The second conductive type well region of the second type conductive channel is separated from the second conductive type well region of the first conductive type channel by the first conductive type lightly doped region in the SiC substrate;

The second conductive type doped region of the second type conductive channel is surrounded by the first conductive type source region of the second type conductive channel;

The front first electrode metal is in Schottky contact with the first conductivity type lightly doped area in the SiC substrate, and the front side first electrode metal is in Schottky contact with the first conductivity type source area of the second type conductive channel and the second type second conductive channel Conductive type doped area ohmic contact.

In the active area, all second-type conductive channels and first-conductivity-type source areas in all second-type conductive channels are connected to each other to form one body, or,

All the first conductivity type source regions of the second type conductive channel are connected to an equal potential state through the front first electrode metal.

In the active area, the arrangement shapes of planar cells include square, hexagonal or square-shaped, where,

On a top view of the power semiconductor device, for the Schottky contact areas in the same column, the Schottky contact areas and the first type conductive channels in the column are staggered.

In the longitudinal direction of the power semiconductor device, the doping concentration in the upper part of the first conductive type source region of the second conductive channel is greater than the doping concentration in the remaining regions of the first conductive type source region of the second conductive channel, and/or,

In the lateral direction of the power semiconductor device, the first conductive type source region of the second conductive channel includes a number of vacant regions, and/or the doping concentration of the first conductive type source region of the second conductive channel is Non-uniform changing state.

For planar cells, it also includes planar gate cells, where,

In the cross-section of the power semiconductor device, the planar gate unit includes a gate insulating layer disposed on the SiC substrate and gate conductive polysilicon disposed on the gate insulating layer. The ends of the gate conductive polysilicon are corresponding to The first type of conductive channels overlap;

The first type conductive channel also includes a first type conductive channel and a second conductive type heavily doped region located in the second conductive type well region of the first type conductive channel and a second conductive type heavily doped region distributed in the first type conductive channel. The first type conductive channel and the first conductive type source area on both sides of the second conductive type heavily doped area. The first type conductive channel, the first conductive type source area and the first type conductive channel are heavily doped with the second conductive type. Miscellaneous area contact;

For the first type conductive channel corresponding to the end of the gate conductive polysilicon, the first type conductive channel, the second conductive type well region and the first type conductive channel first conductive type source in the first type conductive channel The area is in contact with the gate insulating layer.

For the first type conductive channel second conductive type well region and the second type conductive channel second conductive type well region, a two-dimensional distribution state is formed in the active region, wherein the formed two-dimensional distribution state includes stripes Shape-adaptive distribution state.

The SiC substrate further includes a first conductive type substrate, a first conductive type buffer layer disposed on the first conductive type substrate, and a first conductive type drift region disposed on the first conductive type epitaxial layer, wherein ,

The first conductive type lightly doped region is located on the first conductive type drift region, and the first type conductive channel and the second type conductive channel are prepared in the first conductive type lightly doped region.

It also includes a back electrode structure on the back side of the SiC substrate, wherein the back electrode structure is disposed on the first conductive type substrate, and the back electrode structure cooperates with the first conductive type substrate so that the formed power semiconductor device is a MOSFET type. Power devices or IGBT type power devices.

Among the "first conductivity type" and "second conductivity type", for N-type SiC power semiconductor devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type SiC power semiconductor devices , the first conductivity type and the second conductivity type refer to the opposite types to N-type power semiconductor devices.

Advantages of the present invention: The channel density in the active area can be increased by utilizing the second type of conductive channels disposed in the active area, and the first type of conductive channels and the second type of conductive channels are simultaneously provided in the active area. After the channel, while maintaining the conduction efficiency of the power semiconductor device, the channel resistance can be effectively reduced, the electric field concentration efficiency can be reduced, and the reliability of the gate can be improved;

A Schottky contact area is provided in the second type conductive channel, and the Schottky contact between the front first electrode metal and the SiC substrate is used to realize the integration of the Schottky diode; the second conductive type doping is used in the second type conductive channel The surrounding area of the Schottky contact area can provide electric field protection and reduce reverse leakage current;

After the Schottky contact area is arranged in the second type of conductive channel, it can effectively utilize the area of the active area while increasing the channel density, and does not require the introduction of additional special processes. It is compatible with existing processes and will not increase power. Manufacturing costs of semiconductor devices.

Description of the drawings

Figure 1 is a cross-sectional view of an embodiment of the distribution of the first type of conductive channels and the second type of conductive channels in the active area of the present invention.

FIG. 2 is a cross-sectional view of the distribution of the Schottky contact area, the first type of conductive channel, and the second type of conductive channel in the active area according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of a Schottky contact area, a first type of conductive channel, and a second type of conductive channel distributed in an active area according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a third embodiment of the present invention in which the Schottky contact area, the first type of conductive channel, and the second type of conductive channel are distributed in the active area.

FIG. 5 is a top view of an embodiment of the distribution of the Schottky contact area, the first type of conductive channel, and the second type of conductive channel in the active area according to the present invention.

FIG. 6 is a top view of another embodiment of the present invention in which the Schottky contact area, the first type of conductive channel, and the second type of conductive channel are distributed in the active area.

FIG. 7 is a schematic diagram of the distribution of Schottky contact areas in the active area according to an embodiment of the present invention when the planar cells are arranged in a hexagonal manner.

FIG. 8 is a schematic diagram of the distribution of Schottky contact areas in the active area according to another embodiment of the present invention when the planar cells are arranged in a hexagonal manner.

FIG. 9 is a schematic diagram of the distribution of Schottky contact areas in the active area according to a third embodiment of the present invention when the planar cells are arranged in a hexagonal manner.

Figure 10 is a schematic diagram of an embodiment in which planar cells are arranged in a hexagonal shape.

Figure 11 is a schematic diagram of an embodiment in which planar cells are arranged in a Z-shaped arrangement.

Figure 12 is a schematic diagram of an embodiment in which planar cells are arranged in a square shape.

Explanation of reference signs: 1-N-type substrate, 2-N-type buffer layer, 3-N-type drift region, 4-N-type lightly doped region, 5-first type conductive channel P-type well region, 6- The first type of conductive channel N+ source area, 7-the first type of conductive channel P-type heavily doped area, 8-gate insulating layer, 9-gate conductive polysilicon, 10-insulating dielectric layer, 11-front-side first Electrode metal, 12-back electrode metal, 13-first type conductive channel, 14-second type conductive channel, 15-second type conductive channel P-type well region, 16-second type conductive channel N+ source area, 17-Schottky contact area, 18-second type conductive channel P-type doping area, 19-first type conductive channel contact hole, 20-second type conductive channel Schottky contact hole.

Detailed ways

The present invention will be further described below in conjunction with specific drawings and examples.

In order to effectively realize the integration of Schottky diodes, form good electric field protection, and reduce reverse leakage, for SiC power semiconductor devices integrating Schottky diodes, the first conductivity type is N type and the second conductivity type is P For example, one embodiment of the present invention includes an N-type SiC substrate and an active area prepared in the central area of the SiC substrate; the active area includes a number of planar cells distributed side by side;

For any planar cell, it includes a first type conductive channel 13 located in the active area;

In the active area, a second type of conductive channel 14 is also included for increasing the channel density, wherein,

Both the first type conductive channel 13 and the second type conductive channel 14 are in ohmic contact with the front first electrode metal 11 above the SiC substrate, so as to utilize the first type conductive channel 13 and the second type conductive channel 14 to simultaneously generate power. Current channels in semiconductor devices;

The front first electrode metal 11 is also in Schottky contact with the SiC substrate corresponding to the active area to form a number of Schottky contact areas 17 for Schottky diode integration. The Schottky contact areas 17 are located on the first In the second type conductive channel 14 , the Schottky contact region 17 is surrounded by the second type conductive channel P-type doped region 18 in the second type conductive channel 14 .

Specifically, the conductivity type of the SiC substrate is N-type, and the SiC substrate can adopt an existing commonly used form. An embodiment of the SiC substrate is shown in Figure 1, Figure 2, Figure 3 and Figure 4. In the figure, the SiC substrate It includes an N-type substrate 1, an N-type buffer layer 2 located on the N-type substrate 1, an N-type drift region 3 located on the N-type buffer layer 2, and an N-type light evaporator located on the N-type drift region 3. The corresponding doping concentration, thickness and other characteristics of the doped region 4, N-type substrate 1, N-type buffer layer 2, N-type drift region 3 and N-type lightly doped region 4 can be selected according to actual needs to meet the requirements of forming The required SiC substrate shall prevail. Of course, the SiC substrate can also adopt other implementation forms. When the SiC substrate adopts other implementation forms, it shall be subject to the SiC substrate that can meet the requirements for formation, and will not be listed one by one here.

For a SiC power semiconductor device, it at least includes an active area. The active area is generally located in the center area of the SiC substrate of the SiC power semiconductor device. Generally, the active area includes several unit cells distributed side by side. In one embodiment of the present invention, the unit cells are planar cells, that is, the active area includes several planar unit cells. The planar cell adopts the same structural form. Generally, the planar cell includes a first type of conductive channel 13, that is, the first type of conductive channel 13 can be used to form the conductive channel required for the operation of the existing planar cell. Channel, when the SiC substrate adopts the structural form shown in Figures 1 to 4, the first type conductive channel 13 is located in the N-type lightly doped region 4 corresponding to the active area. Therefore, the first type conductive channel 13 is in The distribution state in the N-type lightly doped region 4 and the principle of using the first type conductive channel 13 to form a current channel when the planar cell operates are consistent with the existing ones.

From the above description, it can be seen that for planar cells in the active area, there is a trade-off relationship between reducing the size of the planar cells and increasing the channel density, which may cause a decrease in short-circuit capability. In one embodiment of the present invention, a second type of conductive channel 14 is also prepared in the active area. Similar to the first type of conductive channel 13, the second type of conductive channel 14 can also form a current channel, but is different from the first type of conductive channel 13. The difference between the first type of conductive channels 13 is that the distribution of the second type of conductive channels 14 in the active area does not need to correspond to the planar cell, that is, the number of the second type of conductive channels 14 and the distribution of the second type of conductive channels 14 in the active area The distribution state can be selected according to needs, and has little correlation with the size of the planar cell.

For a power semiconductor device, the first type of conductive channel 13 generally needs to be in ohmic contact with the front first electrode metal 11, and the front first electrode metal 11 is in ohmic contact with the first type of conductive channel 13 and forms the front side of the power semiconductor device. Electrode, the type of the first electrode on the front side is related to the type of the power semiconductor device. If the power semiconductor device is a MOSFET type device, the first electrode on the front side is generally the source electrode. When the power semiconductor device is an IGBT type device, the first electrode on the front side is the source electrode. The electrode is generally the emitter. Therefore, according to the type of the power semiconductor device, after the front-side first electrode metal 11 is in ohmic contact with the first type conductive channel 13, the specific working principle of the power semiconductor device is consistent with the existing ones.

From the above description, it can be seen that the second type of conductive channel 14 needs to be distributed in the active area, that is, prepared in the N-type lightly doped region 4. Among them, the second type of conductive channel 14 also needs to be connected with the front first electrode metal. 11 ohm contact, so that when the power semiconductor device is in forward conduction, the first type of conductive channel 13 and the second type of conductive channel 14 are used to simultaneously form a current channel. The second type of conductive channel 14 increases the channel density, that is, With the same active area area, the channel density of the power semiconductor device can be increased, and when the channel density is increased, the channel resistance of the power semiconductor device can be reduced.

For power semiconductor devices, when conducting in the forward direction, the current density is generally small. When the smaller current flows through the second type conductive channel 14, the voltage difference generated is very small. Therefore, it has an impact on the gate control voltage of the power semiconductor device. Smaller, that is, adding the second type conductive channel 14 will not affect the conduction efficiency of the power semiconductor device, but can improve the conduction performance of the power semiconductor device.

For the gate control voltage of power semiconductor devices, for MOSFET type devices and IGBT type devices, the gate control voltage refers to the control voltage of the gate electrode.

From the above description, it can be seen that in order to meet the freewheeling requirements, it is generally necessary to integrate Schottky diodes in the active area. In one embodiment of the present invention, the front first electrode metal 11 is in Schottky contact with the N-type lightly doped region 4 in the SiC substrate, that is, the front-side first electrode metal 11 and the N-type lightly doped region 4 are in Schottky contact. The Schottky contact forms a Schottky contact area 17, and the Schottky contact area 17 is used to form an integration of Schottky diodes. During specific implementation, there are one or more Schottky contact regions 17 formed by Schottky contact between the front first electrode metal 11 and the N-type lightly doped region 4, and the Schottky contact regions 17 formed by the plurality of Schottky contact regions 17 are The base diodes are all electrically connected to the front first electrode metal 11. At this time, the front first electrode metal 11 is used to form the anode of the Schottky diode.

In order to form a good electric field protection for the Schottky contact area 17, the Schottky contact area 17 is surrounded by the second type conductive channel P-type doped area 18. At this time, through the second type conductive channel The P-type doped region 18 surrounds the Schottky contact region 17, which can reduce the electric field intensity of the Schottky contact region 17, thereby achieving electric field protection and at the same time, reducing reverse leakage. Specifically, the second type conductive channel P-type doped region 18 is annular, and the second type conductive channel P-type doped region 18 and the Schottky contact region 17 are both distributed in the second type conductive channel 14, such as As shown in Figure 5 and Figure 6.

In one embodiment of the present invention, the channel length of the second type conductive channel 14 is consistent with the channel length of the first type conductive channel 13;

The first type conductive channel 13 includes a first type conductive channel P-type well region 5 located in the SiC substrate, and the second type conductive channel 14 includes a second type conductive channel P-type located in the SiC substrate. Well region 15, where,

In the cross-section of the power semiconductor device, the lateral width of the second-type conductive channel P-type well region 15 is smaller than the lateral width of the first-type conductive channel P-type well region 5 .

Specifically, the channel length of the second type conductive channel 14 is consistent with the channel length of the first type conductive channel 13, which specifically means that the channel lengths are equal, or the difference between the two channel lengths is within an allowable range. Within the range, the allowable range of the difference can be selected according to the actual situation, whichever can meet the actual application requirements. When the channel length of the second type conductive channel 14 is consistent with the channel length of the first type conductive channel 13, when the power semiconductor device is normally conducting, the conduction performance of the second type conductive channel 14 is the same as that of the first type conductive channel 13. It is similar to the conductive channel 13, that is, it will not affect the conduction performance of the power semiconductor device.

The cross-sections of the SiC power semiconductor devices shown in FIGS. 1 to 4 show that the first type of conductive channel 13 includes the first type of conductive channel P-type well region 5 , and the second type of conductive channel 14 includes the second type of conductive channel. An embodiment of the conductive channel-like P-type well region 15. In the figure, the lateral width of the second-type conductive channel P-type well region 15 is smaller than the lateral width of the first-type conductive channel P-type well region 5, so The transverse width is the horizontal width in the illustration.

Since the lateral width of the second type conductive channel P-type well region 15 is smaller than the lateral width of the first type conductive channel P-type well region 5, when the second type conductive channel 14 is disposed in the active region, the second type conductive channel 14 The area occupied by the conductive channels 14 has a small impact on the planar cells prepared in the active area. At the same time, within the unit area, the channel density of the second type of conductive channels 14 is higher than that of the first type. The conductive channel 13 has a high channel density. Therefore, by arranging the second type conductive channel 14 in the active area, the channel density of the power semiconductor device can be significantly improved.

In one embodiment of the present invention, the planar cell further includes a planar gate unit, wherein:

In the cross-section of the power semiconductor device, the planar gate unit includes a gate insulating layer 8 disposed on the SiC substrate and a gate conductive polysilicon 9 disposed on the gate insulating layer 8. The terminals of the gate conductive polysilicon 9 All overlap with the corresponding first type conductive channel 13;

The first type conductive channel 13 also includes a first type conductive channel P-type heavily doped region 7 located in the first type conductive channel P-type well region 5 and a first type conductive channel P-type heavily doped region 7 distributed in the first type conductive channel P The first type conductive channel N+ source regions 6 on both sides of the type heavily doped region 7, the first type conductive channel N+ source regions 6 are in contact with the first type conductive channel P type heavily doped region 7;

For the first type conductive channel 13 corresponding to the end of the gate conductive polysilicon 9, the first type conductive channel P-type well region 5 and the first type conductive channel N+ source in the first type conductive channel 13 Region 6 is in contact with gate insulating layer 8 .

Figures 1 to 4 all show an embodiment of a planar cell. It can be seen from the illustration that in addition to the first type conductive channel 13, the planar cell also includes a planar gate unit. Specifically, a planar gate unit The unit includes a gate insulating layer 8 and a gate conductive polysilicon 9. The gate insulating layer 8 is generally a silicon dioxide layer. The gate insulating layer 8 covers the surface of the N-type lightly doped region 4. The gate conductive polysilicon 9 and the covering On the gate insulating layer 8 , the gate conductive polysilicon 9 is insulated and isolated from the N-type lightly doped region 4 through the gate insulating layer 8 .

In Figures 1 to 4, in the cross-section of the power semiconductor device, the end of each gate conductive polysilicon 9 corresponds to and overlaps with a first type conductive channel 13. The overlap specifically refers to the space between There is an intersection during projection.

In the cross-section of the power semiconductor device, the first type conductive channel 13 also includes the first type conductive channel P-type heavily doped region 7 and the first type conductive channel N+ source region 6. The first type conductive channel 13 is in ohmic contact with the front first electrode metal 11, specifically refers to the first type conductive channel N+ source region 6 and the first type conductive channel P-type heavily doped region 7 being in ohmic contact with the front first electrode metal 11.

The doping concentration of the P-type heavily doped region 7 of the first type conductive channel is greater than the doping concentration of the P-type well region 5 of the first type conductive channel. The use of the P-type heavily doped region 7 of the first type conductive channel can improve the Reliability of 11 ohm contact with the front first electrode metal. In the N-type lightly doped region 4, the height of the first-type conductive channel P-type heavily doped region 7 is generally consistent with the height of the first-type conductive channel P-type well region 5, but the first-type conductive channel The height of the N+ source region 6 is smaller than the height of the P-type well region 5 of the first type conductive channel.

For the first type conductive channel 13, parts of the P-type well region 5 of the first type conductive channel and the N+ source region 6 of the first type conductive channel are in contact with the gate insulating layer 8, and the gate conductive polysilicon 9 is in contact with the gate electrode. It can be seen from the corresponding relationship between the insulating layer 8 that at this time, the overlap between the gate conductive polysilicon 9 and the first type conductive channel 13 can be realized. The overlap between the gate conductive polysilicon 9 and the first type conductive channel 13 The situation can be consistent with the existing one.

In order to achieve ohmic contact between the first type conductive channel P-type heavily doped region 7 and the first type conductive channel N+ source region 6 and the front first electrode metal 11, it is generally necessary to provide a first type conductive channel contact hole 19 , both Figures 5 and 6 show the situation of the first type conductive channel contact hole 19. Generally, the first type conductive channel contact hole 19 and the first type conductive trench in the first type conductive channel 13 The P-type heavily doped region 7 corresponds to the first-type conductive channel N+ source region 6. When the front-side first electrode metal 11 is filled in the first-type conductive channel contact hole 19, the first-type conductive channel can be realized. The first type conductive channel P-type heavily doped region 7 in the channel 13 and the first type conductive channel N+ source region 6 have ohmic contacts.

Figures 5 and 6 show a top view of the first type conductive channel 13 in the active area. In Figures 5 and 6, the P-type well region 5 of the first type conductive channel is in a ring shape. The channel P-type heavily doped region 7 is located in the central region of the first-type conductive channel P-type well region 5, and the first-type conductive channel N+ source region 6 is located in the first-type conductive channel P-type heavily doped region 7 outer ring. The cross-sectional views of Figures 1 to 4 are generally taken along the dotted line direction in Figure 5 . Of course, during specific implementation, the distribution of the first type conductive channel P-type well region 5, the first type conductive channel P-type heavily doped region 7 and the first type conductive channel N+ source region 6 in the active area can be As needed, the specific cross-sectional distribution as shown in Figures 1 to 4 shall prevail.

The cross-sectional view of FIG. 1 shows a cross-sectional view of the first-type conductive channel 13 and the second-type conductive channel 14 in the active area. The cross-sectional view of FIG. 1 can be obtained along the dotted line on the left side in FIG. 5 . The cross-sectional view in Figure 2 also shows the Schottky contact area 17. The cross-sectional view in Figure 2 can be obtained along the dotted line on the right side in Figure 5. At this time, the cross-sectional position includes a first type Conductive channel 13 and two second type conductive channels 14. For the cross-sectional views in Figures 3 and 4, refer to the description of Figures 1 and 2, and mainly adjust the corresponding number and distribution position of the second type conductive channels 14 and Schottky contact areas 17.

In one embodiment of the present invention, the second type conductive channel 14 further includes a second type conductive channel N+ source region 16 disposed in the second type conductive channel P-type well region 15, wherein,

The second type conductive channel P-type well region 15 is separated from the first type conductive channel P-type well region 5 by the N-type lightly doped region 4 in the SiC substrate;

The second type conductive channel P-type doped region 18 is surrounded by the second type conductive channel N+ source region 16;

The front first electrode metal 11 is in Schottky contact with the N-type lightly doped region 4 in the SiC substrate, and the front first electrode metal 11 is in Schottky contact with the second type conductive channel N+ source region 16 and the second type conductive channel P-type Miscellaneous 18 ohm contacts.

Figures 1 to 4 show an embodiment of the second type conductive channel 14. In the figures, the second type conductive channel N+ source region 16 is in the P-type well region 15 of the second type conductive channel. Therefore, , the ohmic contact between the front first electrode metal 11 and the second type conductive channel 14 specifically refers to the ohmic contact between the front first electrode metal 11 and at least the N+ source region 16 of the second type conductive channel. In addition, the height of the N+ source region 16 of the second type conductive channel is smaller than the height of the P-type well region 15 of the second type conductive channel, and the lateral width of the N+ source region 16 of the second type conductive channel is also smaller than that of the second type conductive channel. The lateral width of the P-type well region 15. In the figure, the second type conductive channel P-type well region 15 is separated from the first type conductive channel P-type well region 5 by the N-type lightly doped region 4 . When there are adjacent second-type conductive channels 14 , the P-type well regions 15 of the second-type conductive channels in the adjacent second-type conductive channels 14 are also separated by the N-type lightly doped region 4 .

In an embodiment of the present invention, in the active area, all second-type conductive channels N+ source areas 16 in all second-type conductive channels 14 are connected to each other to form one body, or,

All the second type conductive channel N+ source regions 16 are connected to an equal potential state through the front first electrode metal 11 .

The top view of FIG. 5 and FIG. 6 shows an embodiment in which all the second type conductive channel N+ source regions 16 are interconnected and integrated. When the second type conductive channel 14 adopts the situation described in Figures 3 and 4, at this time, the N+ source region 16 of the second type conductive channel cannot be effectively directly physically connected into one body, but can be connected through the front first electrode metal 11 Connect to equipotential state. Of course, when all the second type conductive channels + source regions 16 are directly physically connected into one body, they also need to be in ohmic contact with the front first electrode metal 11 .

In order to achieve ohmic contact between the front first electrode metal 11 and the second type conductive channel N+ source region 16, optionally, a second type conductive channel N+ source region contact hole is prepared, and the second type conductive channel N+ source region is prepared There can be multiple contact holes. The number and location distribution of the second type conductive channel N+ source area contact holes can be selected according to needs. Therefore, the front first electrode metal 11 is filled behind the second type conductive channel N+ source area contact hole. , it is possible to connect all the second type conductive channel N+ source regions 16 through the front first electrode metal 11 into an equal potential state.

In Figures 5 and 6, when the front first electrode metal 11 is in Schottky contact with the N-type lightly doped region 4, it is generally necessary to provide a second type conductive channel Schottky contact hole 20. The second type conductive channel Schottky contact hole 20 is generally required. The special base contact hole 20 can generally be prepared using the same process as the second type conductive channel N+ source region contact hole. During specific implementation, only the second type conductive channel Schottky contact hole 20 may be provided, or the second type conductive channel N+ source area contact hole may be provided at the same time. The specific selection may be based on the actual process.

The second type conductive channel N+ source region contact hole is larger than the outer diameter of the second type conductive channel P-type doped region 18. At this time, the front first electrode metal 11 is filled in the second type conductive channel N+ source region contact hole. When, in addition to being in Schottky contact with the N-type lightly doped region 4, it is also possible to achieve contact with the P-type doped region 18 of the second type conductive channel and with the P-type doped region 18 of the second type conductive channel. Contact Type II conductive channel N+ source region 16 ohm contact.

It can be seen from FIG. 5 and FIG. 6 that when the current flows through the second type conductive channel 14, since the N+ source region 16 of the second type conductive channel has a long area in the lateral direction, the current flows through the front first electrode metal When 11 flows in the second type conductive channel N+ source region 16, the regional distribution of the second type conductive channel N+ source region 16 can be used to increase the voltage difference when the current flows, so that the front second electrode of the power semiconductor device and The voltage difference between the first electrodes on the front side decreases, so that the second type conductive channel 14 can be quickly saturated, that is, the saturation current of the second type conductive channel 14 is smaller than the saturation current of the first type conductive channel 13. At this time, the entire power semiconductor device can quickly reach the saturation current state, reducing the saturation current of the power semiconductor device, and improving the short-circuit capability of the power semiconductor device under short-circuit conditions.

The short-circuit condition of a power semiconductor device generally refers to a state in which the power semiconductor device is in a conductive state and is operating under high voltage and large current. Therefore, under short-circuit conditions, a large current will flow through the power semiconductor device. In one embodiment of the present invention, the saturation current of the second type conductive channel 14 is smaller than the saturation current of the first type conductive channel 13. Therefore, when a large current flows, the second type conductive channel 14 precedes the first type conductive channel 13. The conductive-like channel 13 reaches a saturation current state, and at this time, the saturation current of the entire power semiconductor device can be reduced. When the saturation current of the power semiconductor device is reduced/decreased, the short-circuit capability of the power semiconductor device can be improved.

During specific implementation, the source resistance of the second type conductive channel 14 can be configured to be greater than the channel resistance of the first type conductive channel 13, so that the saturation current of the second type conductive channel 14 can be smaller than that of the first type conductive channel. The channel resistance is 13; when a large current passes through a short circuit condition, the source resistance of the second type conductive channel 14 divides the gate voltage, so that the control voltage actually loaded to the second type conductive channel 14 is more Small, that is, the saturation current of the second type conductive channel 14 is smaller.

The source resistance of the second type conductive channel 14 specifically refers to the corresponding resistance when current flows through the front first electrode metal 11 and the second type conductive channel N+ source region 16 .

From the above description, it can be seen that for the second front electrode, when the power semiconductor device is a MOSFET type device, the second front electrode is generally a gate electrode; when the power semiconductor device is an IGBT type device, the second front electrode is generally a gate electrode. In FIGS. 1 to 6 , the front second electrode metal forming the front second electrode is not shown.

In one embodiment of the present invention, in the active area, the arrangement shape of the planar cells includes a square, a hexagonal or a square shape, wherein,

In a top view of the power semiconductor device, for the Schottky contact regions 17 in the same column, the Schottky contact regions 17 and the first type conductive channels 13 in the column are staggered.

Figure 9 shows an embodiment in which the existing planar cells are arranged in a hexagonal shape. Figure 12 shows an embodiment in which the existing planar cells are arranged in a square shape. Figure 11 shows The existing planar cells are arranged in a rectangular shape, but in the present invention, when the planar cells are arranged in a square, hexagonal or rectangular shape, please refer to the corresponding illustrations in Figures 10 to 12; in the figure , when the planar cells are arranged to form a square, hexagonal or rectangular shape, it specifically refers to the situation where multiple planar cells are combined and arranged; of course, in specific implementation, a single planar cell can also be distributed in a strip shape In terms of form, the specific arrangement of planar cells in the active area shall be subject to the required arrangement shape and the density of the planar cells shall be increased.

Figures 5 and 6 show that the N+ source regions 16 of the second type conductive channel are directly connected to each other and integrated. The Schottky contact region 17 is located in the second type conductive channel 14 and is located between two adjacent first A partial schematic diagram of the conductive-like channel 13. Figures 7, 8 and 9 show a schematic diagram of the distribution of the first type conductive channel 13 and the Schottky contact area 17 in the active area. Figures 7 to 9 show a planar cell with six In the case of angular distribution, and for an embodiment in which Schottky contact areas 17 in the same column are staggered with the first type conductive channels 13 in the same column, in Figure 7, two adjacent Schottky contact areas 17 are separated by a first-type conductive channel 13. In Figure 8, two adjacent Schottky contact areas 17 are separated by two first-type conductive channels 13. In Figure 9, there are two consecutive adjacent Schottky contact areas 17. Schottky contact area 17 , two consecutive adjacent Schottky contact areas 17 are separated by a first type conductive channel 13 .

During specific implementation, the number, distribution, and ratio of the second type conductive channels 14 and Schottky contact areas 17 to the first type conductive channels 13 can be selected according to actual needs, whichever can meet the actual application requirements. . Generally, when the proportion of the Schottky contact area 17 is increased, the turn-on voltage of the integrated Schottky diode can be further reduced, and the freewheeling loss can be reduced.

In one embodiment of the present invention, in the longitudinal direction of the power semiconductor device, the doping concentration in the upper part of the second type conductive channel N+ source region 16 is greater than the doping concentration in the remaining areas of the second type conductive channel N+ source region 16 ,and / or,

In the lateral direction of the power semiconductor device, the second type conductive channel N+ source region 16 includes a number of vacant regions, and/or the doping concentration of the second type conductive channel N+ source region 16 is in a non-uniform state. .

For the longitudinal direction of the power semiconductor device, it specifically refers to the direction along the N-type lightly doped region 4 pointing toward the N-type substrate 1. For the lateral direction of the power semiconductor device, it specifically refers to the direction perpendicular to the longitudinal direction. The upper part of the second type conductive channel N + source region 16 , specifically the end close to the front first electrode metal 11 , has a doping concentration of the upper part of the second type conductive channel N + source region 16 that is greater than the remaining regions in the longitudinal direction. The doping concentration can enhance the short-circuit capability of power semiconductor devices.

In the lateral direction, there is a vacancy area in the second type conductive channel N+ source region 16. The vacancy area specifically refers to the area where non-second type conductive channel N+ source region 16 exists, such as a P-type doped area. Or undoped N-type lightly doped region 4. When there is a vacancy area in the N+ source region 16 of the second type conductive channel, the source resistance of the second type conductive channel 14 can be increased under short circuit conditions.

In addition, the doping concentration of the second type conductive channel N+ source region 16 can also be set to vary non-uniformly. By utilizing the non-uniform doping concentration of the second type conductive channel N+ source region 16, the second type conductive channel N+ source region 16 can be further increased. The source resistance of the conductive-like channel 14 further enhances the short-circuit capability of the power semiconductor device. The doping concentration of the N+ source region 16 of the second type conductive channel is in a non-uniform changing state, which generally means that the doping concentration shows a low changing trend, that is, the non-uniform changing state refers to a normal doping-low doping trend state.

Optionally, in the longitudinal direction of the power semiconductor device, the doping concentration of the upper part of the first type conductive channel N+ source region 6 is greater than the doping concentration of the remaining areas of the first type conductive channel N+ source region 6, and/or,

In the lateral direction of the power semiconductor device, the first type conductive channel N+ source region 6 includes several vacant regions, and/or the doping concentration of the first type conductive channel N+ source region 6 changes non-uniformly. state.

Specifically, regarding the setting of the doping concentration of the first type conductive channel N+ source region 6, please refer to the above description of the second type conductive channel N+ source region 16, and will not be described again here.

In one embodiment of the present invention, a back electrode structure on the back side of the SiC substrate is also included, wherein the back electrode structure is disposed on the N-type substrate 1, and the back electrode structure cooperates with the N-type substrate 1 so that the formed The power semiconductor devices are MOSFET type power devices or IGBT type power devices.

Specifically, the back electrode structure will be different depending on the type of power semiconductor device. The back electrode structure is provided on the N-type substrate 1, that is, the N-type substrate 1 is generally the back side of the SiC substrate.

Figures 1 to 4 also show the case where the back electrode metal 12 is provided on the N-type substrate 1. By utilizing the ohmic contact between the back electrode metal 12 and the N-type substrate 1, a MOSFET type device can generally be formed at this time. , the specifics can be consistent with the existing ones. When it is necessary to form an IGBT type device, it is also necessary to set a collector area in the N-type substrate 1, and the conditions of the collector area can be consistent with the existing ones.

In one embodiment of the present invention, a two-dimensional distribution state is formed in the active region for the first type conductive channel P-type well region 5 and the second type conductive channel P-type well region 15, wherein the formed The two-dimensional distribution state includes a distribution state adapted to a bar shape.

In Figures 5 and 6, although the first type conductive channel P-type well region 5 and the second type conductive channel P-type well region 15 are annular, each side of the annular shape is distributed like a strip, that is, a The two-dimensional distribution of Gate reliability of semiconductor devices is improved. Specifically, the strip-shaped electric field is a constantly repeating two-dimensional arrangement, consisting of two P-type regions extending the electric field, which is a relatively ideal state.

In addition, after the second type conductive channel 14 is provided in the active area, the area of the JFET area in the active area is reduced. The Miller capacitance is positively related to the area of the JFET area below the gate. Therefore, when the area of the JFET area is reduced, the Miller capacitance becomes smaller and the charging and discharging speed is faster. In the switching process of the power semiconductor device, it can bring faster switching speed. and smaller losses.

For the power semiconductor devices shown in Figures 1 to 4, when the Schottky diode needs to be turned on, the front first electrode metal 11 needs to maintain a positive potential, and the current direction of freewheeling by the Schottky diode is the front first The electrode metal 11 points in the direction of the N-type substrate 1 . In the prior art, the freewheeling path of the Schottky diode generally needs to pass through the front first electrode metal 11 - the first type conductive channel P-type heavily doped region 7 - the N-type lightly doped region in the first type conductive channel 13 Hybrid region 4-N-type drift region 3-N-type buffer layer 2-N-type substrate 1-back electrode structure, and in the present invention, the freewheeling path of the Schottky diode is the front first electrode metal 11-N-type light Doping region 4-N-type drift region 3-N-type buffer layer 2-N-type substrate 1-back electrode structure. Therefore, from the path direction of the Schottky diode freewheeling, it can be seen that it is the same as the existing Schottky diode. Compared with current, the Schottky diode integrated in the present invention can quickly turn on and conduct, and can effectively reduce the freewheeling loss of the power semiconductor device.

Claims (10)

1. A SiC power semiconductor device with an integrated Schottky diode, comprising a SiC substrate with a first conductivity type and an active area prepared in the central area of the SiC substrate; the active area includes a number of planes distributed side by side type cell; its characteristics are: For any planar cell, include a first type conductive channel located in the active area; In the active area, a second type of conductive channel is also included to increase the channel density, where, Both the first type conductive channel and the second type conductive channel are in ohmic contact with the front first electrode metal above the SiC substrate, so that the first type conductive channel and the second type conductive channel are used to simultaneously form the current channel of the power semiconductor device ; The front first electrode metal is also in Schottky contact with the SiC substrate corresponding to the active area to form a number of Schottky contact areas for Schottky diode integration. The Schottky contact areas are located in the second type of conductive area. in the channel, and the Schottky contact region is surrounded by a second conductive type doped region of the second conductive channel in the second conductive channel. 2. The SiC power semiconductor device with integrated Schottky diode according to claim 1, characterized in that: the channel length of the second type of conductive channel is consistent with the channel length of the first type of conductive channel; The first type of conductive channel includes a first type of conductive channel and a second conductive type well region located in the SiC substrate. The second type of conductive channel includes a second type of conductive channel located in the SiC substrate. type well region, where, In the cross section of the power semiconductor device, the lateral width of the second conductive type well region of the second conductive channel is smaller than the lateral width of the second conductive type well region of the first conductive channel. 3. The SiC power semiconductor device with integrated Schottky diode according to claim 2, characterized in that: the second type conductive channel further includes a second type conductive channel disposed in the second conductive type well region of the second type conductive channel. The second type conductive channel first conductive type source region, where, The second conductive type well region of the second type conductive channel is separated from the second conductive type well region of the first conductive type channel by the first conductive type lightly doped region in the SiC substrate; The second conductive type doped region of the second type conductive channel is surrounded by the first conductive type source region of the second type conductive channel; The front first electrode metal is in Schottky contact with the first conductivity type lightly doped area in the SiC substrate, and the front side first electrode metal is in Schottky contact with the first conductivity type source area of the second type conductive channel and the second type second conductive channel Conductive type doped area ohmic contact. 4. The SiC power semiconductor device with integrated Schottky diode according to claim 3, characterized in that, in the active area, all the second type conductive channels in the first conductive type source area connected to each other, or, All the first conductivity type source regions of the second type conductive channel are connected to an equal potential state through the front first electrode metal. 5. The SiC power semiconductor device with integrated Schottky diode according to claim 2, characterized in that, in the active area, the arrangement shape of the planar cells includes square, hexagonal or square shape, wherein, On a top view of the power semiconductor device, for the Schottky contact areas in the same column, the Schottky contact areas and the first type conductive channels in the column are staggered. 6. The SiC power semiconductor device with integrated Schottky diode according to claim 3 or 4, characterized in that, in the longitudinal direction of the power semiconductor device, the second type conductive channel is doped in the upper part of the first conductive type source region. The impurity concentration is greater than the doping concentration in the remaining regions of the first conductivity type source region of the second type conductive channel, and/or, In the lateral direction of the power semiconductor device, the first conductive type source region of the second conductive channel includes a number of vacant regions, and/or the doping concentration of the first conductive type source region of the second conductive channel is Non-uniform changing state. 7. The SiC power semiconductor device with integrated Schottky diode according to any one of claims 2 to 5, characterized in that the planar cell further includes a planar gate unit, wherein, In the cross-section of the power semiconductor device, the planar gate unit includes a gate insulating layer disposed on the SiC substrate and gate conductive polysilicon disposed on the gate insulating layer. The ends of the gate conductive polysilicon are corresponding to The first type of conductive channels overlap; The first type conductive channel also includes a first type conductive channel and a second conductive type heavily doped region located in the second conductive type well region of the first type conductive channel and a second conductive type heavily doped region distributed in the first type conductive channel. The first type conductive channel and the first conductive type source area on both sides of the second conductive type heavily doped area. The first type conductive channel, the first conductive type source area and the first type conductive channel are heavily doped with the second conductive type. Miscellaneous area contact; For the first type conductive channel corresponding to the end of the gate conductive polysilicon, the first type conductive channel, the second conductive type well region and the first type conductive channel first conductive type source in the first type conductive channel The area is in contact with the gate insulating layer. 8. The SiC power semiconductor device with integrated Schottky diode according to claim 5, characterized in that: the first conductive channel, the second conductive type well region and the second conductive channel, the second conductive type well region , forming a two-dimensional distribution state in the active area, wherein the formed two-dimensional distribution state includes a distribution state adapted to the stripe shape. 9. The SiC power semiconductor device with integrated Schottky diode according to claim 3 or 4, wherein the SiC substrate further includes a first conductive type substrate disposed on the first conductive type substrate. a first conductivity type buffer layer and a first conductivity type drift region disposed on the first conductivity type epitaxial layer, wherein, The first conductive type lightly doped region is located on the first conductive type drift region, and the first type conductive channel and the second type conductive channel are prepared in the first conductive type lightly doped region. 10. The SiC power semiconductor device with integrated Schottky diode according to claim 9, further comprising a back electrode structure on the back side of the SiC substrate, wherein the back electrode structure is disposed on the first conductive type substrate , the back electrode structure cooperates with the first conductivity type substrate, so that the formed power semiconductor device is a MOSFET type power device or an IGBT type power device.