CN117525139A - Integrated strip-shaped groove source electrode control follow current channel plane SiC MOS and preparation method - Google Patents

Abstract

The invention provides an integrated strip trench source control freewheeling channel planar SiC MOS and a preparation method. The planar SiC MOS includes: at least one source trench and a planar gate; the source trench is along a first direction. Penetrating the N+ layer, P‑well layer and N‑drift layer; the source trench consists of a through hole located in the N+ layer and P‑well layer and a trench located in the upper layer of the N‑drift layer, and the through hole is connected to the The trenches are connected; a source oxide layer is attached to the inner wall of the source trench; source polysilicon is deposited in the source trench and covered by the oxide layer; the source polysilicon and the source connected; the planar gate is located above the N+ layer, the P-well layer and the N-drift layer, and is adjacent to the N+ layer, the P-well layer and the N-drift layer. The present invention opens a strip-shaped source trench below the source electrode, and deposits source polysilicon in the source trench. When the planar SiC MOS works in the reverse state, the P-well layer around the source trench induces The annular inversion layer realizes reverse freewheeling. The invention can reduce the device area and production cost.

Description

An integrated strip trench source controlled freewheeling channel planar SiC MOS and its preparation method

Technical field

The invention relates to the field of semiconductor technology, and specifically relates to an integrated strip trench source control freewheeling channel planar SiC MOS and a preparation method.

Background technique

The third generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturation electron migration rate, stable physical and chemical properties, etc., and can be applied to high temperature, high frequency, high power and extreme environments. Silicon carbide has a larger bandgap and higher critical breakdown field strength. Compared with silicon power devices under the same conditions, the voltage resistance of silicon carbide devices is about 10 times that of silicon materials. In addition, silicon carbide devices have high electron saturation rate, small forward conduction resistance, and low power loss. They are suitable for high-current and high-power applications and reduce the requirements for heat dissipation equipment. Compared with other third-generation semiconductors (such as GaN), silicon carbide can be more easily formed into silicon dioxide through thermal oxidation. SiC has unique physical, chemical and electrical properties and is a semiconductor material with great development potential in extreme application fields such as high temperature, high frequency, high power and radiation resistance. SiC power devices have a series of advantages such as high input impedance, fast switching speed, high operating frequency and high voltage resistance, and have been widely used in switching regulated power supplies, high frequencies and power amplifiers.

MOS field effect transistor power devices made of silicon carbide materials can withstand higher voltages and faster switching speeds than Si devices. For conventional Si MOS, its body diode turn-on voltage is only about 0.7V, so it is often used as a freewheeling channel under reverse bias of MOSFET. However, the SiC material has a wider bandgap, and the SiC MOSFET body diode turn-on voltage is too high (2.7-3.0V), making it difficult to play the role of freewheeling protection MOSFET under reverse bias. In the existing technology, SiC MOSFETs usually use anti-parallel Schottky diodes or JFET short-circuit body diodes to enhance the device's freewheeling capability, but both methods will occupy additional area and integrate the reverse leakage of the Schottky diode device. If the area occupied by the Schottky diode is too large during MOSFET design, it will affect the reverse breakdown voltage of the MOSFET. Moreover, the voltage drop of the Schottky diode is too large when the current is large, which will cause the voltage drop loss on the Schottky diode to be very large when the freewheeling current is large.

Contents of the invention

The object of the present invention is to provide an integrated strip-shaped trench source control freewheeling channel planar SiC MOS and a preparation method thereof. The planar SiC MOS has a strip-shaped source trench under the source electrode, and in the source trench Deposit source polysilicon. When the planar SiC MOS works in the reverse state, the source polysilicon is used to induce an annular inversion layer in the P-well layer around the source trench, allowing current to flow from the source to the drain. This method The reverse freewheeling channel set up in the invention can reduce the device area, reduce production costs, and improve the reliability of planar SiC MOS.

An integrated strip trench source control freewheeling channel planar SiC MOS, including: at least one source trench and a planar gate;

The source trench penetrates the N+ layer, the P-well layer and the N-drift layer along the first direction;

The source trench consists of a via hole located in the N+ layer and the P-well layer and a trench located in the upper layer of the N-drift layer, and the via hole is connected to the trench;

A source oxide layer is attached to the inner wall of the source trench;

Source polysilicon is deposited in the source trench and covered by the oxide layer;

The source polysilicon is connected to the source;

The planar gate is located above the N+ layer, the P-well layer and the N-drift layer, and is adjacent to the N+ layer, the P-well layer and the N-drift layer.

Preferably, the source trenches are arranged sequentially along the first direction.

Preferably, it also includes: P+ shielding layer;

The P+ shielding layer is in contact with the bottom surface of the source trench.

Preferably, the thickness of the source oxide layer is 50-100 nm.

Preferably, the doping concentration of the P-well layer is 10 ¹⁷ cm ^-3 .

Preferably, the thickness of the P-well layer is 0.25um greater than the thickness of the N+ layer.

Preferably, the thickness of the oxide layer of the planar gate is 30-40 nm.

Preferably, it also includes: gate, source, drain, substrate, N-drift layer, N+ layer and P-well layer;

The drain electrode is located under the substrate;

The substrate is located below the N-drift layer;

The N-drift layer is located below the P-well layer;

The P-well layer is located below the N+ layer;

The N+ layer is located under the source electrode;

The gate electrode is located on both sides of the N+ layer and the P-well layer.

An integrated strip trench source controlled freewheeling channel planar SiC MOS preparation method, including:

The P-well layer and N+ layer are epitaxially formed above the N-drift layer;

Etching via holes on the P-well layer and the N+ layer, etching trenches on the N-drift layer, and connecting the via holes with the trenches to form source trenches;

Deposit an oxide layer on the wall of the source trench, and deposit source polysilicon in the source trench;

Deposit gate, source and drain electrodes.

Preferably, depositing an oxide layer on the source trench wall, and before depositing source polysilicon in the source trench, further includes: forming a P+ shielding layer at the bottom of the source trench by ion implantation.

The present invention connects the polysilicon in the source trench to the source by opening a strip-shaped source trench. When the planar SiCMOS is forward-conducted, the source is connected to 0 potential or negative potential, and the source trench does not affect the planar SiC MOS works normally. When the planar SiC MOS works in the reverse state, the source trench can induce an annular inversion layer on the surrounding P-well layer, allowing current to flow from the source to the N+ layer, and from the N+ layer to the The P-well layer flows from the P-well layer to the N-drift layer and finally flows to the drain. Compared with the existing technology, the present invention adopts the freewheeling method of integrated SBD or JFET, which has a smaller area, lower cost and higher current density. Big advantages, and the reliability and stability of planar SiC MOS are also higher.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those of ordinary skill in the art, It is said that other drawings can be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic diagram of the planar SiC MOS structure of the present invention;

Figure 2 is a schematic cross-sectional structural diagram of the planar SiC MOS of the present invention along the first direction;

Figure 3 is a schematic diagram of the planar SiC MOS preparation process method of the present invention;

Figure 4 is a schematic structural diagram of the planar SiC MOS preparation process of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiment of the present invention are only used to explain the relationship between components in a specific posture (as shown in the drawings). Relative positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

In addition, descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor within the protection scope required by the present invention.

When the MOSFET is turned off, the parasitic body diode in the silicon carbide field effect transistor has a large turn-on voltage and cannot play the role of freewheeling protection for the MOSFET under reverse bias. In the existing technology, there are already anti-parallel Schottky diodes. Or the JFET method to enhance the freewheeling capability, but both methods will increase the device area. In addition, the reverse leakage of the Schottky diode is large. If the area occupied by the Schottky diode is too large during MOSFET design, it will affect the MOSFET. reverse breakdown voltage. Moreover, the voltage drop of the Schottky diode is too large when the current is large, which will cause the voltage drop loss on the Schottky diode to be very large when the freewheeling current is large.

The present invention connects the polysilicon in the source trench to the source by opening a source trench. When the planar SiC MOS is forward-conducted, the source is connected to 0 potential or negative potential, and the source trench does not affect the normal operation of the planar SiC MOS. When the planar SiCMOS works in the reverse state, the source trench can induce an annular inversion layer on the surrounding P-well layer, allowing the current to flow from the source to the N+ layer, and from the N+ layer to the P-well. layer, flows from the P-well layer to the N-drift layer and finally flows to the drain. Compared with the existing technology, the present invention adopts the freewheeling method of integrated SBD or JFET, which has the advantages of smaller area, lower cost and higher current density. , while the reliability and stability of planar SiC MOS are also higher.

Example 1

An integrated strip trench source controlled freewheeling channel planar SiC MOS, refer to Figures 1 and 2, including: at least one source trench and a planar gate;

The source trench penetrates the N+ layer, the P-well layer and the N-drift layer along the first direction;

The source trench is strip-shaped in SiC UMOS. The strip-shaped source trench can provide a larger reverse current than the columnar source trench and has better reverse performance.

The source trench consists of a via hole located in the N+ layer and the P-well layer and a trench located in the upper layer of the N-drift layer, and the via hole is connected to the trench;

A source oxide layer is attached to the inner wall of the source trench;

Source polysilicon is deposited in the source trench and covered by the oxide layer;

The source polysilicon is connected to the source;

The planar gate is located above the N+ layer, the P-well layer and the N-drift layer, and is adjacent to the N+ layer, the P-well layer and the N-drift layer.

Planar SiC MOS is a classic semiconductor device. It consists of three parts: an extremely thin metal film, an oxide film and a semiconductor crystal sheet. It is one of the most important basic structures in electronic devices. Moreover, the planar MOS structure is also one of the most important device manufacturing technologies at present, and it can be extended to the manufacturing of microelectronic devices and large-scale integrated circuits. Planar SiCMOS has small size and low power consumption: due to the use of metal oxide film as the insulating layer, the planar SiC MOS structure is very thin, small in size and low in power consumption. It reduces a lot of energy loss compared to other electronic devices and is conducive to improving the performance of the chip. Thermal performance. Strong anti-interference ability: Due to the characteristics of the metal oxide film, the planar SiC MOS structure is easy to form a composite insulating layer, giving electronic devices good anti-interference ability. Strong reliability: The metal oxide film can very effectively prevent short circuits inside electronic devices, making electronic devices very reliable.

Good operational stability: Due to the stability of the metal oxide film, electronic devices used in planar SiC MOS structures can still maintain good performance at high temperatures.

When planar SiC MOS operates in high-frequency circuits, a reverse freewheeling diode is often required due to oscillation or voltage spikes to avoid device degradation. Nowadays, there are mainly the following types of freewheeling diodes: connecting diodes in parallel in the circuit, but this will cause the circuit to increase the switching capacitance and gate charge degradation, increasing the energy loss of the entire circuit; while the device is packaged, the continuous current diode must be connected in parallel. The integration of flow diodes and planar SiC MOS into a set of facilities reduces the area usage of the chip. At the same time, the additional current leakage of the device caused by the integration of multiple systems reduces the reliability of the device. The second is to use the parasitic body diode of the switching element as a freewheeling diode during reverse voltage. However, for traditional SiC MOSFETs, the use of body diodes will bring some side effects: First, the silicon carbide material itself has a wide bandgap. , causing the SiC MOSFET's own body diode to have a higher threshold voltage, about 2.7V, which increases the circuit's additional energy consumption and decreases energy utilization; second, the conduction of the body diode will lead to bipolar degradation of the device, which is The recombination of electron-hole pairs will cause an increase in defects within the SiC material and the doping region will drift, which will lead to an increase in the leakage current of the permanent MOSFET, eventually causing permanent damage and failure.

The present invention creatively proposes a planar SiC MOS that uses a source trench to provide a reverse freewheeling channel. The wall surface of the source trench is attached with a source oxide layer. The material of the source oxide layer is usually silicon oxide. To isolate the source and drain and prevent current from flowing directly from the source to the drain, wet oxidation or dry oxidation is generally used to form the source oxide layer. After the source oxide layer is formed, the source trench is Polysilicon is deposited in the trench, and finally the polysilicon is connected to the source. When the planar SiC MOS is in the reverse state, that is, when the source is connected to a high potential and the drain is connected to a low potential, the source trench will induce in the nearby P-well layer After exiting the annular inversion layer, the current can flow from the source to the N+ layer, from the N+ layer through the inversion layer to the N-drift layer, from the N-drift layer to the substrate and finally to the drain, forming a reverse freewheeling channel. Compared with the power device using integrated SBD/JFET in the prior art, the chip area of the present invention is smaller, the production cost is lower, and the reliability is higher.

Preferably, the source trenches are arranged sequentially along the first direction.

As shown in Figure 1, the first reverse direction is the X-axis direction in the figure. Multiple source trenches are arranged in sequence along the X-axis direction. Each source trench is parallel to the gate electrode in the figure and is on the same plane. On the other hand, the greater the number of source trenches, the stronger the reverse freewheeling capability it can provide, and the greater the reverse current of SiC UMOS, but the chip area will also increase, reducing the number of source trenches. The number of source trenches can reduce the chip area, but the reverse current will also be reduced accordingly. As a preferred embodiment, the present invention sets the number of source trenches to 2, which can meet the requirements of SiC UMOS in most circuits. Reverse performance requirements.

Preferably, it also includes: P+ shielding layer;

The P+ shielding layer is in contact with the bottom surface of the source trench.

When the silicon carbide trench gate MOSFET works in reverse, it uses the depletion of the N-drift region to withstand a higher reverse bias voltage. Due to the high critical breakdown electric field of the silicon carbide material, the drift region at the bottom of the source trench is approaching breakdown will reach a very high electric field. The dielectric constant of the source oxide layer is smaller than the silicon carbide material, so the electric field intensity is about 2.8 times that of silicon carbide. Coupled with the curvature effect, the corners of the source oxide layer gather extremely high electric field intensity, making it possible to work under high electric fields for a long time. It will cause the source oxide layer to degrade and reduce reliability. In order to reduce the electric field intensity of the source oxide layer when the device works in reverse and improve the reliability of the source oxide layer, a P+ shielding layer is usually introduced at the bottom of the trench source oxide layer to shield the influence of high electric field intensity.

The present invention can also add a P+ shielding layer at the bottom of the gate trench to protect the bottom corners of the gate oxide layer from being broken down by high electric fields.

Preferably, the thickness of the source oxide layer is 50-100 nm.

The thickness of the source oxide layer directly affects the turn-on voltage of the reverse freewheeling channel. The thinner the source oxide layer, the easier it is to induce an inversion layer in the P-well layer, and the lower the turn-on voltage of the reverse freewheeling channel. The thicker the source oxide layer, the more difficult it is to induce the inversion layer in the P-well layer, and the higher the turn-on voltage of the reverse freewheeling channel. However, if the source oxide layer is too thin, the reliability of the source oxide layer will be reduced. , the source oxide layer is easily broken down, so the thickness of the source oxide layer cannot be less than 50nm. If the source oxide layer is too thick, the opening voltage of the reverse freewheeling channel will be too high, affecting the reverse performance of the planar SiC MOS, so The thickness of the source oxide layer cannot exceed 100 nm. As a preferred embodiment, the present invention sets the thickness of the source oxide layer to 70 nm, which can improve the reliability of SiC UMOS while having better reverse performance.

Preferably, the doping concentration of the P-well layer is 10 ¹⁷ cm ^-3 .

The doping concentration of the -well layer can also directly affect the turn-on voltage of the reverse freewheeling channel. The lower the doping concentration of the P-well layer, the easier it is to induce the inversion layer. However, if it is too low, it will affect the electrical properties of the planar SiC MOS. Performance, as a preferred embodiment, the present invention sets the doping concentration of the P-well layer to 10 ¹⁷ cm ^-3 .

Preferably, the thickness of the P-well layer is 0.25um greater than the thickness of the N+ layer.

After the P-well layer is pressurized, the channel will be inverted, that is, the majority of carriers (holes) in the channel will become electrons. This channel is called N-channel. The thickness and doping concentration of P-well directly determine the plane The electrical performance of SiC MOS. When planar SiCMOS is operating normally, the gate controls the P-well to form an inversion layer. When the planar SiC MOS is reversed, the polysilicon connected to the source controls the P-well layer to form an inversion layer. Therefore, The thickness and doping concentration of the P-well layer also determine the electrical performance of the reverse freewheeling channel.

The thickness of the P-well layer will also affect the turn-on voltage of the reverse freewheeling channel. The thinner the P-well layer, the smaller the turn-on voltage of the reverse freewheeling channel. As a preferred embodiment, the present invention combines the P-well layer with The thickness is set to 0.25um greater than the thickness of the N+ layer.

Preferably, the thickness of the oxide layer of the planar gate is 30-40 nm.

Because the MOSFET gate with a planar structure bears a smaller voltage than the MOSFET gate with a trench structure, the thickness of the oxide layer of the planar gate is smaller than the thickness of the oxide layer of the trench gate, as a preferred embodiment. , the present invention sets the thickness of the oxide layer of the planar gate to 50 nm.

Preferably, it also includes: gate, source, drain, substrate, N-drift layer, N+ layer and P-well layer;

The drain electrode is located under the substrate;

The drain is the charge sink in the MOSFET. It is connected to the channel and is the entrance to the charge. When the MOSFET is in the on state, a conductive path is formed between the drain and source, and electrons flow from the source to the drain to complete the transmission of current. The voltage change of the drain has little impact on the working state of the MOSFET, and mainly plays the role of current inflow.

The substrate is located below the N-drift layer;

The electric field distribution of the N-drift layer plays a key role in the conduction characteristics and current control of MOSFET. When a gate voltage is applied to a MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source and drain. When the MOSFET is working, the current between the source and the drain is mainly transmitted through the N-drift layer. The doping type and concentration of the N-drift layer determines the conduction type (N-type or P-type) and size of the current. The structure and characteristics of the N-drift layer directly affect the current control capability of the MOS tube. By adjusting the shape, size and doping concentration of the N-drift layer, precise control of the current can be achieved to meet the requirements of different applications.

The N-drift layer is located below the P-well layer;

The P-well layer is located below the N+ layer;

The N+ layer is located under the source electrode;

The source is the source of charge in the MOSFET and is the outlet of the charge. When the MOSFET is in the on state, a conductive path is formed between the source and drain, and electrons flow from the source to the drain to complete the transmission of current. At the same time, the source also plays the role of modulating the gate voltage. By controlling the change of the source voltage, the MOSFET is controlled.

The gate electrode is located on both sides of the N+ layer and the P-well layer.

The gate is the control electrode in the MOSFET. It is separated from the channel by an insulating layer and is a key part of the MOSFET. Changes in gate voltage can change the charge density in the channel, thereby controlling the amount of current between the drain and source.

Example 2

An integrated strip trench source control freewheeling channel planar SiC MOS preparation method, refer to Figures 2 and 3, including:

S100, epitaxially form the P-well layer and N+ layer above the N-drift layer;

The epitaxial process refers to the process of growing a fully ordered single crystal layer on a substrate. Generally speaking, the epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source-drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, etc. According to the different phase states of the growth source, epitaxial growth methods are divided into solid phase epitaxy, liquid phase epitaxy, and vapor phase epitaxy. In integrated circuit manufacturing, the commonly used epitaxy methods are solid-phase epitaxy and vapor-phase epitaxy.

Solid-phase epitaxy refers to the growth of a single crystal layer on a substrate by a solid source. For example, thermal annealing after ion implantation is actually a solid-phase epitaxy process. During the ion implantation process, the silicon atoms of the silicon wafer are bombarded by high-energy implanted ions, leaving the original lattice position and becoming amorphous, forming a surface amorphous silicon layer; after high-temperature thermal annealing, the amorphous atoms return to the original lattice position. to the crystal lattice position and consistent with the atomic orientation within the substrate.

The growth methods of vapor phase epitaxy include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE), etc. In the embodiment of the present invention, chemical vapor epitaxy (CVE) is used to form the N-drift layer. The principles of chemical vapor epitaxy and chemical vapor deposition (CVD) are basically the same. They are both processes that use gas mixture to react chemically on the surface of the wafer to deposit thin films. The difference is that because chemical vapor epitaxy grows a single crystal layer, it requires a lot of equipment. The impurity content in the silicon wafer and the cleanliness requirements on the silicon wafer surface are both higher. In integrated circuit manufacturing, CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source-drain epitaxial processes. The epitaxial silicon wafer process is to epitaxially extend a layer of single crystal silicon on the surface of the silicon wafer. Compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, thus improving the yield of semiconductor manufacturing. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to device design. For example, it can be used to reduce substrate resistance, enhance substrate isolation, etc. The embedded source-drain epitaxy process refers to the process of epitaxially growing doped silicon germanium or silicon in the source and drain regions of the transistor. The main advantages of introducing the embedded source-drain epitaxial process include: it can grow a pseudocrystalline layer that contains stress due to lattice adaptation, improving channel carrier mobility; it can dope the source and drain in situ, reducing the parasitic resistance of the source-drain junction , Reduce the defects of high-energy ion implantation.

S200, etching via holes on the P-well layer and the N+ layer, etching trenches on the N-drift layer, and connecting the via holes with the trenches to form source trenches;

The present invention forms the through hole connected to the trench through a one-time etching method, that is, etching starts from the uppermost N+ layer and stops etching to the upper layer of the CSL layer. Etching is the process of selectively removing unwanted materials from the surface of silicon wafers using chemical or physical methods. It is a general term for stripping and removing materials through solutions, reactive ions or other mechanical means. Etching technology is mainly divided into dry etching and wet etching. Dry etching mainly uses reactive gases and plasma for etching; wet etching mainly uses chemical reagents to react with the etched material for etching.

Ion beam etching is a physical dry etching process. Thereby, argon ions are radiated onto the surface in an ion beam of about 1 to 3 keV. Due to the energy of the ions, they hit the material on the surface. With the wafer vertical or tilted into the ion beam, the etching process is absolutely anisotropic. Selectivity is low as there is no difference between layers. The gases and ground material are removed by a vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched using this method, with very low wear on vertical walls due to vertical radiation.

Plasma etching is an absolute chemical etching process. The advantage is that the wafer surface will not be damaged by accelerated ions. Due to the movable particles of the etching gas, the etching profile is isotropic, so this method is used to remove the entire film layer (such as backside cleaning after thermal oxidation). One type of reactor used for plasma etching is the downstream reactor. Thus, plasma is ignited at a high frequency of 2.45GHz through impact ionization, and the location of impact ionization is separated from the wafer.

The etch rate depends on the pressure, power of the high frequency generator, process gas, actual gas flow and wafer temperature. Anisotropy increases with increasing high-frequency power, decreasing pressure, and decreasing temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes, and the material of the electrodes. If the distance is too small, the plasma cannot be dispersed unevenly, resulting in inhomogeneity. If the distance between the electrodes is increased, the etch rate decreases because the plasma is distributed in an enlarged volume. For electrodes, carbon has proven to be the material of choice. Because fluorine and chlorine gases also attack carbon, the electrodes create a uniformly strained plasma so the edges of the wafer are affected in the same way as the center of the wafer. Selectivity and etch rate are highly dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.

S300, deposit an oxide layer on the wall of the source trench, and deposit source polysilicon in the source trench;

The present invention adopts wet oxidation or dry oxidation to deposit an oxide layer on the wall surface of the source trench. According to the different oxidants in the oxidation reaction, the thermal oxidation process can be divided into dry oxidation and wet oxidation. The former uses pure oxygen to generate The silicon oxide layer is slow but the oxide layer is thin and dense. The latter requires the use of oxygen and highly soluble water vapor at the same time. It is characterized by a fast growth rate but a relatively thick protective layer and low density. Wet oxidation has two main steps: the mass transfer process of oxygen in the air from the gas phase to the liquid phase; and the chemical reaction between dissolved oxygen and the substrate. If the mass transfer process affects the overall reaction rate, it can be eliminated by strengthening stirring. In embodiments of the present invention, the rate at which the source oxide layer is formed by wet oxygen oxidation can be controlled by controlling the temperature, pressure, and concentration of the reaction gas during wet oxygen oxidation, thereby achieving the purpose of controlling the thickness of the source oxide layer.

Dry oxidation uses high-temperature pure oxygen to directly react with the wafer. Dry oxidation only uses pure oxygen (O ₂ ), so the growth rate of the oxide film is slow. It is mainly used to form thin films and can form oxides with good conductivity. The advantage of dry oxidation is that no by-product (H2) is produced, and the uniformity and density of the oxide film are high.

The gate electrode is deposited using the polysilicon deposition method. Polysilicon deposition is when silicide is stacked on the first layer of polysilicon (Poly1) to form the gate electrode and local connections, and the second layer of polysilicon (Poly2) forms the source/drain and cell connections. contact plug. The silicide is stacked on the third layer of polysilicon (Poly3) to form the unit connection. The fourth layer of polysilicon (Poly4) and the fifth layer of polysilicon (Poly5) form the two electrodes of the storage capacitor. Sandwiched between them is a high dielectric coefficient of dielectric. To maintain the desired capacitance value, the size of the capacitor can be reduced by using a high-k dielectric. Polysilicon deposition is a type of low-pressure chemical vapor deposition (LPCVD) by placing arsenic (AH ₃ ), phosphorus (PH ₃ ), or diborane (B ₂ H ₆ ) in a reaction chamber (i.e., a furnace tube). By directly inputting the doping gas into the silicon material gas of silane or DCS, the polysilicon doping process of on-site low-pressure chemical vapor deposition can be carried out. Polysilicon deposition is carried out under low pressure conditions of 0.2-1.0 Torr and deposition temperatures between 600 and 650°C, using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rates for both deposition processes are is mainly determined by the temperature during deposition.

S400, deposit gate, source and drain.

Metal electrode deposition processes are divided into chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD refers to the method of chemically depositing coatings on the surface of wafers, generally by applying energy to a mixed gas. Assuming that substance (A) is deposited on the wafer surface, two gases (B and C) that can generate substance (A) are first input to the deposition equipment, and then energy is applied to the gas to promote a chemical reaction between gases B and C.

PVD (physical vapor deposition) coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. The main methods of physical vapor deposition include: vacuum evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy, etc. Corresponding vacuum coating equipment includes vacuum evaporation coating machines, vacuum sputtering coating machines and vacuum ion coating machines.

Both chemical vapor deposition (CVD) and physical vapor deposition (PVD) can be used as technical means to deposit metal electrodes. In embodiments of the present invention, a chemical vapor deposition method is used to deposit metal electrodes. The chemical vapor deposition process is divided into three stages: diffusion of reaction gas to the surface of the substrate, adsorption of the reaction gas on the surface of the substrate, and chemical reaction on the surface of the substrate to form a solid deposition. The substances and the gas phase by-products produced are separated from the surface of the matrix. The most common chemical vapor deposition reactions are: thermal decomposition reactions, chemical synthesis reactions and chemical transport reactions. Usually, to deposit TiC or TiN, gases such as TiCl ₄ , H ₂ , and CH ₄ are introduced into a reaction chamber at 850-1100°C. After chemical reaction, a coating is formed on the surface of the substrate.

Preferably, depositing an oxide layer on the source trench wall, and before depositing source polysilicon in the source trench, further includes: forming a P+ shielding layer at the bottom of the source trench by ion implantation.

The present invention uses ion implantation to form a P+ shielding layer at the bottom of the source trench. Ion implantation is to emit an ion beam in a vacuum towards a solid material. After the ion beam hits the solid material, its speed slowly slows down due to the resistance of the solid material, and finally stays in the solid material. The ions of an element are accelerated into a solid target, thereby changing the physical, chemical or electrical properties of the target. Ion implantation is often used in the manufacturing of semiconductor devices, metal surface treatment, and materials science research. If the ions are stopped and remain in the target, the ions will change the elemental composition of the target (if the ions are of a different composition than the target). Ion implantation beamline designs all contain a common set of functional components. The main part of an ion beamline consists of a device called an ion source, which is used to generate ion species. The source is tightly coupled to a bias electrode to extract ions into the beamline, and most commonly to some means of selecting specific ion species for transport into the main accelerator section. The "mass" selection accompanies the extracted ion beam through the magnetic field region, with its exit path restricted by blocking holes or "slits" that only allow ions with mass and velocity/charge to continue along the beamline. If the target surface is larger than the ion beam diameter, and the implant dose is evenly distributed over the target surface, some combination of beam scanning and wafer motion can be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implant process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When injected into a semiconductor, each dopant atom can generate charge carriers in the semiconductor after annealing. A hole can be created for P-type dopants and an electron for N-type dopants. Changes the conductivity of the semiconductor near the doped region.

The present invention connects the polysilicon in the source trench to the source by opening a strip-shaped source trench. When the planar SiCMOS is forward-conducted, the source is connected to 0 potential or negative potential, and the source trench does not affect the planar SiC MOS works normally. When the planar SiC MOS works in the reverse state, the source trench can induce an annular inversion layer on the surrounding P-well layer, allowing the current to flow from the source to the N+ layer, and from the N+ layer to The P-well layer flows from the P-well layer to the N-drift layer and finally flows to the drain. Compared with the existing technology, the present invention adopts the freewheeling method of integrated SBD or JFET, which has a smaller area, lower cost and higher current density. Big advantages, and the reliability and stability of planar SiC MOS are also higher.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. An integrated striped trench source controlled freewheel channel planar SiC MOS comprising: at least one source trench and a planar gate;

the source electrode groove penetrates through the N+ layer, the P-well layer and the N-drift layer along a first direction;

the source electrode groove consists of a through hole positioned on the N+ layer and the P-well layer and a groove positioned on the upper layer of the N-drift layer, and the through hole is connected with the groove;

a source electrode oxide layer is attached to the inner wall of the source electrode groove;

source polycrystalline silicon is deposited in the source groove and is covered by the oxide layer;

the source polycrystalline silicon is connected with the source;

the planar gate is located above and adjacent to the n+ layer, the P-well layer, and the N-drift layer.

2. An integrated striped trench source controlled freewheel channel plane SiC MOS according to claim 1 characterized in that said source trenches are arranged in sequence along a first direction.

3. An integrated striped trench source controlled freewheel channel plane SiC MOS according to claim 1 characterized in that it further comprises: a P+ shielding layer;

the P+ shielding layer is abutted with the bottom surface of the source electrode groove.

4. An integrated striped trench source controlled freewheel channel planar SiC MOS according to claim 1 characterized in that said source oxide layer has a thickness of 50-100nm.

5. The SiC MOS integrated striped trench source controlled freewheel channel plane of claim 1 characterized in that the P-well layer has a doping concentration of 10 ¹⁷ cm ^-3 。

6. An integrated striped trench source controlled freewheel channel planar SiC MOS according to claim 1 characterized in that the thickness of said P-well layer is 0.25um larger than the thickness of the n+ layer.

7. An integrated striped trench source controlled freewheel channel planar SiC MOS according to claim 1 characterized in that the thickness of the oxide layer of said planar gate is 30-40nm.

8. An integrated striped trench source controlled freewheel channel plane SiC MOS according to claim 1 characterized in that it further comprises: the device comprises a grid electrode, a source electrode, a drain electrode, a substrate, an N-drift layer, an N+ layer and a P-well layer;

the drain electrode is positioned below the substrate;

the substrate is positioned below the N-drift layer;

the N-drift layer is positioned below the P-well layer;

the P-well layer is positioned below the N+ layer;

the N+ layer is positioned below the source electrode;

and the grid electrode is positioned at two sides of the N+ layer and the P-well layer.

9. The preparation method of the planar SiC MOS of the integrated strip-shaped groove source electrode control freewheel channel is characterized by comprising the following steps of:

epitaxially forming a P-well layer and an N+ layer above the N-drift layer;

etching through holes on the P-well layer and the N+ layer, etching grooves on the upper layer of the N-drift layer, and connecting the through holes with the grooves to form source grooves;

depositing an oxide layer on the wall surface of the source electrode groove, and depositing source electrode polysilicon in the source electrode groove;

a gate, a source and a drain are deposited.

10. The method for preparing the planar SiC MOS of the integrated striped trench source controlled freewheel channel of claim 9 further comprising, prior to depositing the source polysilicon in the source trench, depositing an oxide layer on a wall surface of the source trench: and forming a P+ shielding layer by ion implantation at the bottom of the source electrode groove.