CN115881797A - Silicon carbide device and preparation method thereof - Google Patents

Abstract

The invention discloses a silicon carbide device and a preparation method thereof. An N-type current expansion layer is arranged in the middle of the P-type body regions on the two sides, a P-type doped region is arranged on the surface of the source electrode of the unit cell, heterojunction diodes are arranged in the grid electrodes on the two sides and the P-type doped region, and a grid electrode oxide film is arranged on the surface of the grid electrode. Compared with the traditional MOSFET structure, the SiCMOS MOSFET structure provided by the invention has better static quality factor and dynamic quality factor, and is particularly characterized by having lower on-resistance and lower reverse transmission capacitance, the third quadrant on-characteristic and reverse recovery characteristic of the device are improved, the problems of bipolar degradation effect and overhigh electric field of a gate oxide are solved, and the SiCMOS MOSFET structure has better reliability.

Description

A silicon carbide device and its preparation method

technical field

The invention belongs to the technical field of semiconductors, in particular to a silicon carbide device and a preparation method thereof.

Background technique

Power semiconductor devices have the advantages of large drive current, high breakdown voltage, fast speed, low power consumption, and large output power, and can realize power control and conversion in different ranges. In recent years, with the continuous development of power electronic systems, higher requirements have been placed on the power devices in the system, but silicon (Si)-based power electronic devices can no longer meet the requirements of system applications due to the limitations of the material itself. The third-generation semiconductor SiC has the characteristics of wide band gap (about 3 times that of Si), high critical breakdown electric field (about 10 times that of Si), high saturation drift rate, etc., and is suitable for high temperature, high voltage and high frequency work. Significantly improve system energy conversion efficiency and improve system reliability, but due to its wide bandgap, SiC MOSFET has the problem of bipolar degradation during use. When the body diode is used as a freewheeling diode, the bipolar Degradation problems will be more severe, reducing device reliability. Therefore, in most power electronic systems, anti-parallel Schottky diodes are usually used as freewheeling diodes, but this method still increases the system cost, and due to the interconnection of components, additional stray inductance will be introduced in the circuit, reducing the The dynamic performance of the system.

Compared with trench MOSFET devices, planar MOSFET devices are more widely used in electronic power systems, and usually have lower reverse transfer capacitance, gate-to-drain charge and switching loss. The coupling between gate and drain can be further reduced by separating the gate The area is used to reduce the reverse transfer capacitance and gate-to-drain charge, but usually the on-resistance of the device increases due to the reduction of the current channel length, which reduces the static quality factor of the device. The usual solution is to use a higher concentration of the N-type current spreading layer to reduce the on-resistance, but the use of a high concentration of the current spreading layer usually makes the gate oxide layer be affected by a high electric field, so that the gate oxide layer may be in the body region It is broken down before the breakdown occurs, which greatly affects the reliability of the device. Therefore, researchers will use various gate oxide layer reinforcement structures to alleviate the electric field concentration phenomenon of the gate oxide layer, thereby improving device performance.

Contents of the invention

The object of the present invention is to provide a silicon carbide device and its preparation method, so as to solve the above-mentioned problems in the prior art. Compared with the traditional MOSFET structure, it has better static quality factor and dynamic quality factor, and the working performance of the third quadrant of the device has been improved, and the gate oxide electric field has also been effectively reduced.

In order to achieve the above object, the present invention provides a SiC MOSFET device with low power consumption and high reliability, including:

Metal drain, N+ substrate, N- epitaxial layer;

The N+ substrate is formed on the metal drain, and the metal drain is a bottom-up structure;

the N- epitaxial layer is formed on the N+ substrate;

The N-epitaxial layer includes an N-drift region, a P-type body region, an N-type current spreading layer, and a P-type doped region; the P-type body region is formed on both sides of the upper end of the N-type epitaxial layer, so The N-type current spreading layer is formed between the P-type body regions, and the P-type doped region is formed on the cell source surface;

The N-drift region is formed under the P-type body region, the N-type current spreading layer and the P-type doped region.

Optionally, the P-type body region is provided with an N+ source region, a metal source and a gate, P+ polysilicon is provided between the gate and the P-type doped region, and a gate is provided on the surface of the gate Oxide film.

Optionally, the P-type doped region has a thickness of 1.2 μm, a width of 0.8 μm˜1 μm, and a doping concentration of 1×10 ¹⁸ cm ⁻³ .

Optionally, the height of the bottom of the P-type doped region is between the height of the bottom of the P+ polysilicon and the height of the P-type body region.

Optionally, a limit value is set for the concentration of the N-type current spreading layer, and the limit value is higher than the concentration of the N-drift region.

Also provided is a method for preparing a silicon carbide device, characterized in that,

Step S1: preparing the N+ substrate of the semiconductor device, and sequentially forming the N-drift region and the N-type current spreading layer by epitaxy;

Step S2: forming a P-type doped region by ion implantation technology;

Step S3: using etching technology to form grooves on both sides of the cell, and forming a P-body region and an N+ source region in the grooves by ion implantation technology;

Step S4: using an etching technique to etch away the remaining N-type doped regions in the left and right parts of the P-type doped region;

Step S5: Depositing P+ polysilicon on both sides of the P-type doped region;

Step S6: etching back the P+ polysilicon to form polysilicon sidewalls;

Step S7: using a thermal oxidation process to form a gate oxide film under the gate, depositing polysilicon on the gate oxide film to form a gate, and depositing a thick oxide outside the gate;

Step S8: forming a source region on the surface of the N+ source region, the P-body region, the P-type doped region and the P+ polysilicon, and forming a drain region under the N+ substrate.

Technical effect of the present invention is:

The present invention proposes a SiC MOSFET device with low power consumption and high reliability. Its main features are that the traditional gate is changed to a separate gate, and a P-type doped region is formed on the inner surface of the cell by ion implantation, and the P-type Deposit P+ polysilicon and N-type SiC between the doped region and the gate to form a heterojunction diode, which improves the conduction characteristics and reverse recovery characteristics of the third quadrant. The bottom of the P+ polysilicon and the bottom of the gate oxide are at the same height to avoid The gate oxide electric field is too high due to the curvature in the off state. The static quality factor of the device is improved through the high-concentration current expansion layer, which is specifically manifested as a lower on-resistance, which effectively improves the forward conduction characteristics of the device. When the device is in the off state, introducing a peak electric field at the bottom of the P-type doped region can reduce the high electric field at the gate oxide and P+ polysilicon caused by the high-concentration current spreading layer, and avoid dynamic degradation. Due to the reduced drain coupling area, the dynamic quality factor of the device is improved, which is manifested in lower reverse transfer capacitance and gate-to-drain charge. The performance of the device has been effectively improved in all aspects, the bipolar degradation effect and the high electric field of the gate oxide have been effectively solved, and the reliability of the device has been effectively improved.

Description of drawings

The drawings constituting a part of the application are used to provide further understanding of the application, and the schematic embodiments and descriptions of the application are used to explain the application, and do not constitute an improper limitation to the application. In the attached picture:

Fig. 1 is the traditional planar MOSFET device structure schematic diagram in the embodiment of the present invention;

Fig. 2 is a schematic diagram of the cell structure of a SiC MOSFET device with low power consumption and high reliability in an embodiment of the present invention;

Fig. 3 is a schematic diagram of the manufacturing process of a SiC MOSFET device with low power consumption and high reliability in an embodiment of the present invention, wherein (a) is a formation diagram of an N+ substrate, an N-drift region and an N-type current spreading layer, and (b) is The formation diagram of the P-type doped region, (c) is the formation diagram of the P-body region and the N+ source region, (d) is the etching diagram of the remaining N-type doped region in the left and right parts of the P-type doped region, (e) It is a schematic diagram of depositing P+ polysilicon on both sides of the P-type doped region, (f) is the effect diagram of etching excess P+ polysilicon, (g) is the effect diagram of gate treatment, and (h) is the effect diagram of making the drain region;

4 is a comparison diagram of the forward conduction characteristic curve and the breakdown voltage curve of the SiC MOSFET device with low power consumption and high reliability in the embodiment of the present invention and the traditional planar MOSFET structure;

5 is a graph comparing the reverse transfer capacitance (gate-to-drain capacitance) curves of a SiC MOSFET device with low power consumption and high reliability in an embodiment of the present invention and a traditional planar MOSFET structure;

FIG. 6 is a comparison diagram of the gate charge characteristic curves of the SiC MOSFET device with low power consumption and high reliability and the traditional planar MOSFET structure in the embodiment of the present invention;

7 is a comparison diagram of the third quadrant I-V curve of the SiC MOSFET device with low power consumption and high reliability in the embodiment of the present invention and the traditional planar MOSFET structure;

FIG. 8 is a graph comparing the reverse recovery characteristic curves of the SiC MOSFET device with low power consumption and high reliability in the embodiment of the present invention and the traditional planar MOSFET structure.

Detailed ways

It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

Embodiment one

The present embodiment provides a silicon carbide device and a manufacturing method thereof, including a bottom-up metal drain, an N+ substrate, and an N- epitaxial layer. A P-type body region is arranged on the upper end of the N- epitaxial layer, an N-type current spreading layer is arranged in the middle of the P-type body regions on both sides, and an N+ source region, a metal source and a gate are arranged on the P-body region. The SiC MOSFET structure with low power consumption and high reliability also includes a P-type doped region on the surface of the cell source, P+ polysilicon is arranged on both side gates and the P-type doped region, and N-type SiC forms a heterojunction contact, and a gate oxide film is provided on the surface of the gate.

Preferably, the P-type doped region has a thickness of 1.2 μm, a width of 0.8 μm˜1 μm, and a doping concentration of 1×10 ¹⁸ cm ⁻³ .

Preferably, the bottom height of the P-type doped region is greater than the bottom of the P+ polysilicon, and the bottom height of the P-type doped region is smaller than the bottom of the P-type base region, so as to avoid premature breakdown of the device caused by electric field concentration.

Preferably, the bottom of the P+ polysilicon is at the same height as the bottom of the gate to improve the problem of excessively high electric field of the gate oxide caused by curvature.

Preferably, the concentration of the N-type current spreading layer needs to be greater than the concentration of the N-drift region, and in order to avoid the high electric field of the P-type doped region, the concentration of the N-type current spreading layer should not be too high, and the concentration of the N-type current spreading layer The preferred concentration is 6×10 ¹⁶ cm ^-3 .

Also provided is a method for manufacturing a SiC MOSFET device with low power consumption and high reliability, including:

Step S1: Prepare the N+ substrate region of the semiconductor device, and sequentially form an N-drift region and an N-type current spreading layer through epitaxy;

Step S2: forming a P-type doped region by ion implantation technology;

Step S3: using etching technology to form trenches on both sides of the cell, and forming a P- body region and an N+ source region in the trenches by ion implantation technology;

Step S4: Etching away the remaining N-type doped regions in the left and right parts of the P-type doped region by etching technology again. Since the width of the P-type doped region can be 0.8 μm to 1 μm, the process difficulty can be reduced;

Step S5: depositing P+ polysilicon;

Step S6: Etching away excess P+ polysilicon by etching back technology, the thickness of P+ polysilicon should be slightly greater than or equal to the thickness of the P-type doped region;

Step S7: using a thermal oxidation process to form a gate oxide film, depositing polysilicon on it to form a gate, and then depositing a thick oxide on its exterior;

Step S8: making a source region on the N+ source region, P-body region, P-type doped region and P+ polysilicon surface, and making a drain region under the N+ substrate.

Embodiment two

In this embodiment, a silicon carbide device and its preparation method are provided, including:

Referring to Figures 1 and 2, the present invention provides a SiC MOSFET device with low power consumption and high reliability, which is suitable for energy conversion in power electronic systems. N+ substrate, N-drift region, N-type current spreading layer, P-body region, N+ source region set in layers. The difference between Figure 2 and Figure 1 is that the gate region uses a separate gate and is at the same height as the integrated heterojunction, and is shielded by the electric field of the P-type doped region formed by ion implantation. A high-concentration current spreading layer is set in the side, and the P-type doped region avoids the high electric field under the action of the high-concentration current spreading layer on the surface of the gate oxide and the P+ polysilicon.

The manufacturing process of the SiC MOSFET device with low power consumption and high reliability is shown in Figure 3, including the following steps:

Step S1: Prepare the N+ substrate region of the semiconductor device, and form the N-drift region and the N-type current spreading layer through epitaxy in sequence. The concentrations of the N-drift region and the N-type current spreading layer are 8×1015cm-3 and 6× 1016cm-3, as shown in Figure 3(a);

Step S2: Form a P-type doped region by ion implantation technology, wherein the P-type doped region has a width of 0.8 μm to 1 μm, a thickness of 1.2 μm, and a concentration of 1×1018 cm-3, as shown in Figure 3(b);

Step S3: using etching technology to form grooves on both sides of the cell, and forming a P-body region and an N+ source region by ion implantation technology in the grooves, and the width of the single-side P-body region is 2.5 μm, such as As shown in Figure 3(c);

Step S4: Etch the remaining N-type doped region on the left and right of the P-type doped region again by etching technology. Since the width of the P-type doped region can be 0.8 μm to 1 μm, the process difficulty can be reduced, as shown in Figure 3 as shown in (d);

Step S5: Depositing P+ polysilicon, as shown in FIG. 3(e);

Step S6: Etching away excess P+ polysilicon by etching back technology, as shown in FIG. 3(f);

Step S7: using a thermal oxidation process to form a gate oxide film, and depositing polysilicon on it to form a gate, and then depositing a thick oxide outside it, as shown in FIG. 3(g);

Step S8: Fabricate a source region on the N+ source region, a P-body region, a P-type doped region, and a P+ polysilicon surface, and fabricate a drain region under the N+ substrate to complete the fabrication of an integrated heterojunction diode and a split gate MOSFET, As shown in Figure 3(h).

The embodiment of the present invention is based on Silvaco TCAD software, and the following is a simulation comparison analysis of the two device structures in Fig. 1-2.

As shown in Figure 4, the static conduction characteristics of the two device structures obtained by simulation. It can be seen from Fig. 4 that compared with the traditional planar MOSFET structure, the SiC MOSFET device with low power consumption and high reliability in the embodiment of the present invention can achieve smaller on-resistance and have a similar breakdown voltage, which can improve the device static quality factor.

As shown in Figure 5, the reverse transmission capacitance (gate-to-drain capacitance) of the two structures obtained by simulation varies with the drain voltage, and the smaller gate-to-drain capacitance can reduce the time of the Miller voltage during the switching process, thereby reducing the switching time and switching losses. It can be seen from the figure that the low power consumption and high reliability SiC MOSFET device of the present invention has lower reverse transmission capacitance, therefore, the structure of the embodiment of the present invention has greater advantages in high frequency applications.

As shown in Figure 6, the gate charge characteristics of the two device structures obtained by simulation, it can be seen that compared with the traditional planar MOSFET structure, the proposed SiC MOSFET device with low power consumption and high reliability has a lower Miller platform Time, the gate-to-drain charge Qgd is significantly reduced, indicating that the device has lower switching losses.

As shown in Figure 7, the comparison diagram of the third quadrant I-V curves of the two device structures obtained by simulation, it can be seen that compared with the traditional planar MOSFET structure, the third quadrant of the proposed SiC MOSFET device with low power consumption and high reliability The turn-on voltage is lower. Since the heterojunction is a multi-sub-device similar to a Schottky diode, the barrier height for electrons is much lower than that for holes, which can precede and suppress the conduction of the parasitic body diode in SiC MOSFET, avoiding The bipolar degradation of the device improves the reliability of the device.

As shown in Figure 8, the reverse recovery characteristic curves of the two device structures obtained by simulation are compared. It can be seen that compared with the traditional planar MOSFET structure, the proposed SiC MOSFET device with low power consumption and high reliability has a shorter Reverse recovery time, less reverse recovery charge and lower peak value of reverse recovery current mean that the embodiment proposed by the present invention has better reverse recovery characteristics and reduces energy loss during device switching.

In describing the present invention, it should be understood that the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "Horizontal", "top", "inner", "outer" and other indicator positions or positional relationships are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention, rather than indicating or implying No device or element must have a particular orientation, be constructed, and operate in a particular orientation and therefore should not be construed as limiting the invention.

The above is only a preferred embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person familiar with the technical field can easily conceive of changes or changes within the technical scope disclosed in this application Replacement should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (6)

1. A silicon carbide device, characterized in that, comprising: Metal drain, N+ substrate, N- epitaxial layer; The N+ substrate is formed on the metal drain, and the metal drain is a bottom-up structure; the N- epitaxial layer is formed on the N+ substrate; The N-epitaxial layer includes an N-drift region, a P-type body region, an N-type current spreading layer, and a P-type doped region; the P-type body region is formed on both sides of the upper end of the N-type epitaxial layer, so The N-type current spreading layer is formed between the P-type body regions, and the P-type doped region is formed on the cell source surface; The N-drift region is formed under the P-type body region, the N-type current spreading layer and the P-type doped region. 2. The silicon carbide device according to claim 1, characterized in that, The P-type body region is provided with an N+ source region, a metal source and a gate, P+ polysilicon is provided between the gate and the P-type doped region, and a gate oxide film is provided on the surface of the gate. 3. The silicon carbide device according to claim 1, characterized in that, The P-type doped region has a thickness of 1.2 μm, a width of 0.8 μm˜1 μm, and a doping concentration of 1×10 ¹⁸ cm ⁻³ . 4. The silicon carbide device according to claim 2, characterized in that, The height of the bottom of the P-type doped region is between the height of the bottom of the P+ polysilicon and the height of the P-type body region. 5. The silicon carbide device according to claim 1, characterized in that, The concentration of the N-type current spreading layer has a limit value, and the limit value is higher than the concentration of the N-drift region. 6. A method for preparing a silicon carbide device, characterized in that, Step S1: preparing the N+ substrate of the semiconductor device, and sequentially forming the N-drift region and the N-type current spreading layer by epitaxy; Step S2: forming a P-type doped region by ion implantation technology; Step S3: using etching technology to form grooves on both sides of the cell, and forming a P- body region and an N+ source region in the grooves by ion implantation technology; Step S4: using an etching technique to etch away the remaining N-type doped regions in the left and right parts of the P-type doped region; Step S5: depositing P+ polysilicon on both sides of the P-type doped region; Step S6: etching back the P+ polysilicon to form polysilicon sidewalls; Step S7: using a thermal oxidation process to form a gate oxide film under the gate, depositing polysilicon on the gate oxide film to form a gate, and depositing a thick oxide outside the gate; Step S8: forming a source region on the surface of the N+ source region, the P-body region, the P-type doped region and the P+ polysilicon, and forming a drain region under the N+ substrate.

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