CN118658881A - Deep source super junction MOSFET device and preparation method and chip thereof - Google Patents
Deep source super junction MOSFET device and preparation method and chip thereof Download PDFInfo
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Abstract
本申请属于功率器件技术领域，提供了一种深源极超结MOSFET器件及其制备方法、芯片，通过设置凸形结构的N型漂移层，在N型漂移层的两侧形成第一栅极多晶硅层和第二栅极多晶硅层，减小栅极面积，降低栅极电荷，并利用倒山字形结构的源极层控制第一栅极多晶硅层和第二栅极多晶硅层之间的第三P型基区的开启，增加电流导通通道，还可以通过控制绝缘介质层的厚度使得其导通电压低于体二极管的导通压降，减少P型源极的空穴注入，而且N型源极的存在增加了电子浓度，提高了正向导通电流，不会影响器件的正向导通特性，同时还降低了少子空穴的寿命，进一步改善了器件的反向恢复。
The present application belongs to the technical field of power devices, and provides a deep source super junction MOSFET device and a preparation method and chip thereof. By setting a convex N-type drift layer, a first gate polysilicon layer and a second gate polysilicon layer are formed on both sides of the N-type drift layer, the gate area is reduced, the gate charge is reduced, and the source layer with an inverted mountain structure is used to control the opening of the third P-type base region between the first gate polysilicon layer and the second gate polysilicon layer, thereby increasing the current conduction channel. The thickness of the insulating dielectric layer can also be controlled so that its conduction voltage is lower than the conduction voltage drop of the body diode, thereby reducing the hole injection of the P-type source. Moreover, the presence of the N-type source increases the electron concentration, improves the forward conduction current, and does not affect the forward conduction characteristics of the device. At the same time, the lifetime of minority holes is reduced, thereby further improving the reverse recovery of the device.
Description
Technical Field
The application belongs to the technical field of power devices, and particularly relates to a deep-source super-junction MOSFET device, a preparation method thereof and a chip.
Background
In recent years, super junction metal-Oxide-Semiconductor field effect transistors (Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor, SJMOSFET) gradually replace conventional Vertical Double-diffused metal-Oxide-Semiconductor field effect transistors (VDMOS) in many application fields with excellent performances of high voltage resistance, low internal resistance and the like, but during reverse conduction, P-type sources inject a large amount of minority carrier holes into drift regions, which affects the reverse recovery process of super junction MOSFET devices.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a deep source super-junction MOSFET device, a preparation method thereof and a chip, and can improve the reverse recovery process of the super-junction MOSFET device.
An embodiment of the present application provides, in a first aspect, a deep source superjunction MOSFET device, including:
An N-type substrate;
the first P column, the N-type drift layer and the second P column are formed on the N-type substrate; the first P column and the second P column are respectively positioned at two sides of the N-type drift layer, and the N-type drift layer is of a convex structure;
The first P-type base region is formed on the first horizontal part of the first P column and the N-type drift layer, the second P-type base region is formed on the second horizontal part of the second P column and the N-type drift layer, and the first P-type base region and the second P-type base region are of L-shaped structures;
The first P type source region and the first N type source region are formed on the horizontal part of the first P type base region;
the second P type source region and the second N type source region are formed on the horizontal part of the second P type base region;
The first gate dielectric layer is positioned on the vertical part of the first P-type base region, a partial region of the third horizontal part of the N-type drift layer and a partial region of the first N-type source region, and the first gate dielectric layer wraps the first gate polysilicon layer;
the second gate dielectric layer is positioned on the vertical part of the second P-type base region, the partial region of the N-type drift layer and the partial region of the second N-type source region, and the second gate dielectric layer wraps the second gate polysilicon layer;
The third P-type base region is formed on the N-type drift layer and is positioned between the first gate dielectric layer and the second gate dielectric layer;
the third N-type source region is formed on the third P-type base region and is positioned between the first grid dielectric layer and the second grid dielectric layer;
the source electrode layer is in an inverted-Chinese-character-shan-shaped structure, the source electrode layer is in contact with the first P-type source region, the first N-type source region, the second P-type source region and the second N-type source region, the middle protruding part of the inverted-Chinese-shan-shaped structure of the source electrode layer is embedded into the third P-type base region and the third N-type source region, and the source electrode layer embedded into the third P-type base region and the third N-type source region is isolated from the third P-type base region and the third N-type source region by an insulating medium layer;
and the drain electrode layer is formed on the back surface of the N-type substrate.
In some embodiments, the deep source superjunction MOSFET device further comprises:
The first N-type heavily doped region is formed between the N-type drift layer and the first gate dielectric layer, and is in contact with the vertical part of the first P-type base region and the first gate dielectric layer.
In some embodiments, the deep source superjunction MOSFET device further comprises:
The second N-type heavily doped region is formed between the N-type drift layer and the second gate dielectric layer, and is in contact with the vertical part of the second P-type base region and the second gate dielectric layer.
In some embodiments, a first schottky metal layer is disposed between the source layer and the first P-type source region.
In some embodiments, a second schottky metal layer is disposed between the source layer and the second P-type source region.
In some embodiments, the thickness of the insulating medium layer is a preset thickness; and when the thickness of the insulating medium layer is a preset thickness, the conduction voltage of the deep source super-junction MOSFET device is smaller than the body diode conduction voltage of the deep source super-junction MOSFET device.
The second aspect of the embodiment of the application also provides a preparation method of the deep source super junction MOSFET device, which comprises the following steps:
Epitaxially growing a silicon material on an N-type substrate and injecting N-type doping ions to form an N-type drift layer;
P-type doping ions are injected into the two side areas of the N-type drift layer to form a first P column and a second P column;
Forming a first P-type base region and a second P-type base region on a first P column, the N-type drift layer and a second P column, and enabling the N-type drift layer to be in a convex structure, wherein the first P-type base region is positioned on a first horizontal part of the first P column and the N-type drift layer, and the second P-type base region is formed on a second horizontal part of the second P column and the N-type drift layer;
N-type doping ions and P-type doping ions are sequentially injected into the first P-type base region and the second P-type base region to form a first P-type source region, a first N-type source region, a second P-type source region and a second N-type source region, so that the first P-type base region and the second P-type base region are of L-shaped structures; the first P type source region and the first N type source region are positioned on the horizontal part of the first P type base region, and the second P type source region and the second N type source region are positioned on the horizontal part of the second P type base region;
Epitaxially growing a silicon material on the N-type drift layer, injecting N-type doping ions to form an N-type layer, and sequentially injecting P-type doping ions and N-type doping ions into the central region of the N-type layer to form a third P-type base region and a third N-type source region; the third N-type source region is formed on the third P-type base region;
Respectively carrying out groove etching and oxide layer deposition on the N-type layers at two sides of the third P-type base region and the third N-type source region to form a first grid dielectric layer, a first grid polysilicon layer, a second grid dielectric layer and a second grid polysilicon layer; the first gate dielectric layer and the first gate polysilicon layer are positioned on the vertical part of the first P-type base region, a partial area of the third horizontal part of the N-type drift layer and a partial area of the first N-type source region, and the first gate dielectric layer wraps the first gate polysilicon layer; the second gate dielectric layer and the second gate polysilicon layer are positioned on the vertical part of the second P-type base region, the partial region of the N-type drift layer and the partial region of the second N-type source region, and the second gate dielectric layer wraps the second gate polysilicon layer;
etching the third P-type base region and the third N-type source region to form a deep groove, and forming an insulating medium layer in the deep groove;
Depositing a source metal material to form a source layer with an inverted-mountain-shaped structure; the source electrode layer is in contact with the first P-type source region, the first N-type source region, the second P-type source region and the second N-type source region, and the middle protruding part of the source electrode layer inverted-Chinese-character-shan-shaped structure is embedded into the insulating medium layer with the concave-shaped structure, so that the middle protruding part of the source electrode layer inverted-Chinese-shan-shaped structure is isolated from the third P-type base region and the third N-type source region by the insulating medium layer;
And forming a drain electrode layer on the back surface of the N-type substrate.
In some embodiments, the method of making further comprises:
Forming a first N-type heavily doped region and a second N-type heavily doped region on two sides of a third horizontal part of the N-type drift layer; the first N-type heavily doped region is in contact with the vertical part of the first P-type base region and the first gate dielectric layer, and the second N-type heavily doped region is in contact with the vertical part of the second P-type base region and the second gate dielectric layer.
In some embodiments, the method of making further comprises:
setting the thickness of the insulating medium layer to be a preset thickness; and when the thickness of the insulating medium layer is a preset thickness, the conduction voltage of the deep source super-junction MOSFET device is smaller than the body diode conduction voltage of the deep source super-junction MOSFET device.
The third aspect of the embodiment of the present application further provides a chip, which includes the deep source super junction MOSFET device according to any one of the embodiments above.
The embodiment of the application has the beneficial effects that: the first grid polycrystalline silicon layer and the second grid polycrystalline silicon layer are formed on two sides of the N-type drift layer through the arrangement of the N-type drift layer with the convex structure, the area of the grid is reduced, grid charges are reduced, the opening of a third P-type base region between the first grid polycrystalline silicon layer and the second grid polycrystalline silicon layer is controlled by utilizing a source layer with the inverted-mountain-shaped structure, a current conduction channel is increased, the middle protruding part of the source layer inverted-mountain-shaped structure is embedded into the third P-type base region and the third N-type source region, the source layer embedded into the third P-type base region, the source layer in the third N-type source region, the third P-type base region and the third N-type source region are isolated by an insulating medium layer, further, the thickness of the insulating medium layer is controlled, the conduction voltage of the insulating medium layer is lower than the conduction voltage drop of a body diode, hole injection of the first P-type source region and the second P-type source region is reduced, and reverse recovery of a device is improved.
Drawings
Fig. 1 is a schematic diagram of a first structure of a deep source super junction MOSFET device according to an embodiment of the present application;
fig. 2 is a schematic diagram of a second structure of a deep source super junction MOSFET device according to an embodiment of the present application;
Fig. 3 is a schematic diagram of a third structure of a deep source super junction MOSFET device according to an embodiment of the present application;
fig. 4 is a graph comparing simulation results of forward conduction current of a deep source super-junction MOSFET device provided by an embodiment of the present application with that of a conventional super-junction MOSFET device;
Fig. 5 is a comparison diagram of breakdown voltage simulation results of a deep source super-junction MOSFET device and a conventional super-junction MOSFET device according to an embodiment of the present application;
FIG. 6 is a graph comparing the reverse recovery speed simulation results of a deep source super-junction MOSFET device provided by an embodiment of the present application with a conventional super-junction MOSFET device;
Fig. 7 is a schematic flow chart of a method for manufacturing a deep source super junction MOSFET device according to an embodiment of the present application;
FIG. 8 is a schematic diagram of an N-type drift region formed on an N-type substrate layer according to an embodiment of the present application;
FIG. 9 is a schematic diagram of forming a first P column and a second P column according to an embodiment of the present application;
FIG. 10 is a schematic diagram of forming a first P-type base region, a second P-type base region, a first P-type source region, a second P-type source region, a first N-type source region, and a second N-type source region according to an embodiment of the present application;
FIG. 11 is a schematic diagram of forming an N-type layer, a third P-type source region, and a third N-type source region according to an embodiment of the present application;
Fig. 12 is a schematic diagram of forming a first gate dielectric layer, a first gate polysilicon layer, a second gate dielectric layer, and a second gate polysilicon layer according to an embodiment of the present application;
Fig. 13 is a schematic diagram of forming an insulating dielectric layer according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is one or more than one unless specifically defined otherwise.
The deep source super-junction MOSFET device (Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor, SJMOSFET) gradually replaces the conventional Vertical Double-diffused metal-Oxide-Semiconductor field effect transistor (VDMOS) with its excellent performances of high voltage resistance, low internal resistance, etc. in many application fields, but during the reverse conduction process, the P-type source will inject a large amount of minority carrier holes into the drift region, which affects the reverse recovery process of the super-junction MOSFET device.
In order to solve the above technical problems, an embodiment of the present application provides a deep source superjunction MOSFET device, referring to fig. 1, which includes an N-type substrate 110, a first P-pillar 121, an N-type drift layer 120, a second P-pillar 122, a first P-type base region 130, a second P-type base region 131, a first P-type source region 132, a first N-type source region 133, a second P-type source region 134, a second N-type source region 135, a first gate dielectric layer 151, a first gate polysilicon layer 152, a second gate dielectric layer 153, a second gate polysilicon layer 154, a third P-type base region 141, a third N-type source region 142, a source layer 160, and a drain layer 162.
In the embodiment of the present application, as shown in fig. 1, a first P-pillar 121, an N-type drift layer 120 and a second P-pillar 122 are formed on an N-type substrate 110, the first P-pillar 121 and the second P-pillar 122 are respectively located at two sides of the N-type drift layer 120, and the N-type drift layer 120 has a convex structure; the first P-type base region 130 and the second P-type base region 131, the first P-type base region 130 is formed on the first P column 121 and the first horizontal portion of the N-type drift layer, the second P-type base region 131 is formed on the second P column 122 and the second horizontal portion of the N-type drift layer, and the first P-type base region 130 and the second P-type base region 131 are of an L-shaped structure.
In the embodiment of the present application, as shown in fig. 1, a first P-type source region 132 and a first N-type source region 133 are formed on a horizontal portion of a first P-type base region 130; the second P-type source region 134 and the second N-type source region 135 are formed on the horizontal portion of the second P-type base region 131; the first gate dielectric layer 151 and the first gate polysilicon layer 152 are located on the vertical portion of the first P-type base region 130 and the partial region of the third horizontal portion of the N-type drift layer 120 and the partial region of the first N-type source region 133, and the first gate dielectric layer 151 wraps the first gate polysilicon layer 152; the second gate dielectric layer 153 and the second gate polysilicon layer 154 are located on the vertical portion of the second P-type base region 131 and the partial region of the N-type drift layer 120 and the partial region of the second N-type source region 135, and the second gate dielectric layer 153 wraps the second gate polysilicon layer 154.
In the embodiment of the present application, as shown in fig. 1, a third P-type base region 141 is formed on the N-type drift layer 120 and is located between the first gate dielectric layer 151 and the second gate dielectric layer 153; the third N-type source region 142 is formed on the third P-type base region 141 and is located between the first gate dielectric layer 151 and the second gate dielectric layer 153.
In the embodiment of the present application, as shown in fig. 1, the source layer 160 has an inverted-mountain structure, the source layer 160 contacts the first P-type source region 132, the first N-type source region 133, the second P-type source region 134, and the second N-type source region 135, and the middle protruding portion of the inverted-mountain structure of the source layer 160 is embedded into the third P-type base region 141 and the third N-type source region 142, and the source layer 160 embedded into the third P-type base region 141 and the third N-type source region 142 is isolated from the third P-type base region 141 and the third N-type source region 142 by an insulating medium layer; the drain layer 162 is formed on the back surface of the N-type substrate 110.
In the embodiment of the present application, in the first aspect, the first gate dielectric layer 151 and the first gate polysilicon layer 152 are disposed on the vertical portion of the first P-type base region 130, and on the partial region of the third horizontal portion of the N-type drift layer 120 and the partial region of the first N-type source region 133, and the second gate dielectric layer 153 and the second gate polysilicon layer 154 are disposed on the vertical portion of the second P-type base region 131, and on the partial region of the third horizontal portion of the N-type drift layer 120 and the second N-type source region 135, so as to reduce the gate area, and reduce the channel length to a certain extent based on the reduction of the gate area, so as to reduce the gate charge, and further improve the reverse recovery and the switching speed of the deep source superjunction MOSFET device; in the second aspect, by arranging the source layer 160 with an inverted-mountain-shaped structure, the opening of the first P-type base region 130 and the second P-type base region 131 at the top is controlled by using the source voltage, so as to increase the current conduction channel and compensate the adverse effect of the forward conduction characteristic of the deep source super-junction MOSFET device caused by the reduction of the gate area; in the third aspect, the middle protruding portion of the inverted-triangle structure of the source layer 160 is embedded into the third P-type base region 141 and the third N-type source region 142, and the source layer 160 embedded into the third P-type base region 141 and the third N-type source region 142 is isolated from the third P-type base region 141 and the third N-type source region 142 by the insulating medium layer, so that the turn-on voltage of the deep source superjunction MOSFET device is lower than the turn-on voltage of the body diode by controlling the thickness of the insulating medium layer, hole injection of the first P-type source region 132 and the second P-type source region 134 is reduced, and reverse recovery of the device is improved.
In some embodiments, as shown in connection with fig. 2, the deep source superjunction MOSFET device may further comprise: the first N-type heavily doped region 171, the first N-type heavily doped region 171 is formed between the N-type drift layer 120 and the first gate dielectric layer 151, and the first N-type heavily doped region 171 is in contact with the vertical portion of the first P-type base region 130 and the first gate dielectric layer 151.
In this embodiment, the presence of the first N-type heavily doped region 171 increases the electron concentration, increases the forward conduction current, does not affect the forward conduction characteristic of the device, and reduces the lifetime of minority carriers in the device, thereby further improving the reverse recovery characteristic of the device.
In some embodiments, as shown in connection with fig. 2, the deep source superjunction MOSFET device can further include a second N-type heavily doped region 172, the second N-type heavily doped region 172 being formed between the N-type drift layer 120 and the second gate dielectric layer 153, and the second N-type heavily doped region 172 being in contact with the second gate dielectric layer 153 and the vertical portion of the second P-type base region 131.
In this embodiment, the presence of the second N-type heavily doped region 172 increases the electron concentration, increases the forward conduction current, does not affect the forward conduction characteristic of the device, and also reduces the lifetime of minority carriers in the device, thereby further improving the reverse recovery characteristic of the device.
As shown in table 1 below, and fig. 4, 5, and 6, in the embodiment of the present application, by providing the first N-type heavily doped region 171 (n+) between the first gate dielectric layer 151 and the N-type drift layer 120, and providing the second N-type heavily doped region 172 (n+) between the second gate dielectric layer 153 and the N-type drift layer 120, the electron concentration of the device can be increased, the forward conduction current of the device can be increased, and the forward conduction characteristic of the device is not affected, and meanwhile, the lifetime of minority carrier holes is reduced, and the reverse recovery of the device is further improved.
Wherein V （BR）DSS in table 1 is drain-source breakdown voltage, R DS(ON) is on-resistance, I D is source-drain saturation current, V th is threshold voltage, t rr is body diode reverse recovery time, Q rr is body diode reverse recovery charge, I RRM reverse recovery current, V GS is on-voltage, I DS is drain current, V DD is supply voltage, di/dt is current.
Curve 1 in fig. 4 is a forward current-carrying curve of a deep source super-junction MOSFET device provided by the embodiment of the present application, and curve 2 is a forward current-carrying curve of a conventional super-junction MOSFET device; the abscissa in fig. 4 is the drain voltage Vd, and the ordinate is the saturation current Id of the superjunction device when it is turned on in the forward direction.
Curve 3 in fig. 5 is a breakdown voltage curve of a deep source super-junction MOSFET device provided by an embodiment of the present application, and curve 4 is a breakdown voltage curve of a conventional super-junction MOSFET device; vds is the voltage between drain and source and Ids is the current between drain and source.
Curve 5 in fig. 6 is a reverse recovery variation curve of a deep source super-junction MOSFET device provided in an embodiment of the present application without the first N-type heavily doped region 171 and the second N-type heavily doped region 172, curve 6 is a reverse recovery variation curve of a deep source super-junction MOSFET device provided in an embodiment of the present application with the first N-type heavily doped region 171 and the second N-type heavily doped region 172, curve 7 is a reverse recovery variation curve of a conventional super-junction MOSFET device, and the abscissa is time and the ordinate is current.
In the embodiment of the application, by arranging the N-type drift layer 120 with a convex structure, the first gate polysilicon layer 152 and the second gate polysilicon layer 154 are formed on two sides of the N-type drift layer 120, the gate area is reduced, the gate charge is reduced, the opening of the third P-type base region 141 between the first gate polysilicon layer 152 and the second gate polysilicon layer 154 is controlled by the source layer 160 with an inverted-mountain-shaped structure, the current conduction channel is increased, the conduction voltage of the current conduction channel is also enabled to be lower than the conduction voltage drop of the body diode by controlling the thickness of the insulating medium layer, the hole injection of the P-type source is reduced, the electron concentration is increased by the existence of the N-type source, the forward conduction current is improved, the forward conduction characteristic of the device is not affected, the service life of minority carrier holes is also reduced, and the reverse recovery of the device is further improved.
Table 1:
In some embodiments, the first N-type heavily doped region 171 and the second N-type heavily doped region 172 may be provided separately or simultaneously.
In some embodiments, as shown in connection with fig. 2, the first N-type heavily doped region 171 and the second N-type heavily doped region 172 are formed on both sides of the third horizontal portion of the N-type drift layer 120.
In some embodiments, referring to fig. 3, a first schottky metal layer 181 may be further disposed between the source layer 160 and the first P-type source region 132.
In some embodiments, referring to fig. 3, a second schottky metal layer 182 is further disposed between the source layer 160 and the second P-type source region 134.
In this embodiment, by forming schottky contact between the first P-type source region 132 and the first schottky metal layer 181 and forming schottky contact between the second P-type source region 134 and the second schottky metal layer 182, the device can enter the protruding portion of the N-type drift layer 120 only from the first N-type source region 133 and the second N-type source region 135 during reverse recovery, and the arrangement of the first N-type heavily doped region 171 and the second N-type heavily doped region 172 is overlapped, so that minority carrier injection is reduced, the purpose of further reducing hole injection is achieved, and reverse recovery of the device is improved.
In one embodiment, the thickness of the insulating dielectric layer is a predetermined thickness.
In the embodiment of the application, when the thickness of the insulating medium layer is a preset thickness, the on voltage of the deep source super-junction MOSFET device is smaller than the on voltage of the body diode of the deep source super-junction MOSFET device.
In the embodiment of the application, the thickness of the insulating medium layer is controlled to enable the on voltage of the deep source super junction MOSFET device to be lower than the on voltage of the body diode, so that the hole injection of the first P type source region 132 and the second P type source region 134 is reduced.
In one embodiment, the width of the first gate dielectric layer 151 is smaller than the width of the horizontal portion of the first P-type base region 130; the width of the second gate dielectric layer 153 is smaller than the width of the horizontal portion of the second P-type base region 131.
In the embodiment of the present application, the width of the first gate dielectric layer 151 is smaller than the width of the horizontal portion of the first P-type base region 130; the width of the second gate dielectric layer 153 is smaller than the width of the horizontal portion of the second P-type base region 131, so as to reduce the gate area, reduce the gate charge, and further improve the reverse recovery and switching speed of the deep source super junction MOSFET device.
In one embodiment, the thickness of the first gate dielectric layer 151 is less than the thickness of the vertical portion of the first P-type base region 130; the thickness of the second gate dielectric layer 153 is smaller than the thickness of the vertical portion of the second P-type base region 131.
In the embodiment of the present application, the thickness of the first gate dielectric layer 151 is smaller than the thickness of the vertical portion of the first P-type base region 130; the thickness of the second gate dielectric layer 153 is smaller than that of the vertical portion of the second P-type base region 131, so as to reduce the gate area, reduce the gate charge, and further improve the reverse recovery and the switching speed of the deep source super junction MOSFET device.
Referring to fig. 7, the embodiment also provides a method for manufacturing a deep source super junction MOSFET device, which includes steps S100 to S900.
In step S100, a silicon material is epitaxially grown on the N-type substrate 110 and N-type dopant ions are implanted to form an N-type drift layer 120.
In this embodiment, as shown in fig. 8, a silicon material may be epitaxially grown on a silicon substrate, and N-type doping ions may be implanted into the epitaxial silicon material to form an N-type substrate 110, and then an N-type drift layer 120 may be epitaxially grown on the front surface of the N-type substrate 110. The N-type drift layer 120 has a lower concentration of N-type dopant ions than the N-type substrate 110.
In one embodiment, the doping concentration of the N-type substrate 110 layer is at least 100 times the doping concentration of the N-type epitaxial layer.
In one embodiment, the N-type substrate 110 may have an N-type dopant ion concentration of 1e20cm-3 and the N-type drift layer 120 may have an N-type dopant ion concentration of 1e15cm-3-1e17cm-3. The thickness of the N-type substrate 110 may be 3um-10um. The thickness of the N-type drift layer 120 may be 20um-60um.
In step S200, P-type doped ions are implanted into the two side regions of the N-type drift layer 120 to form a first P-pillar 121 and a second P-pillar 122.
In this embodiment, as shown in fig. 9, the first P-pillar 121 and the second P-pillar 122 penetrating into the N-type substrate 110 can be formed by implanting P-type dopant ions at both sides of the N-type drift layer 120, and the N-type drift layer 120 is located between the first P-pillar 121 and the second P-pillar 122.
In one embodiment, the widths of the first P-pillars 121 and the second P-pillars 122 are the same, and the sum of the widths of the first P-pillars 121 and the second P-pillars 122 may be less than or equal to the width of the N-type drift layer 120.
In step S300, a first P-type base region 130 and a second P-type base region 131 are formed on the first P-pillar 121, the N-type drift layer 120, and the second P-pillar 122, and the N-type drift layer 120 is formed in a convex structure, the first P-type base region 130 is located on a first horizontal portion of the first P-pillar 121 and the N-type drift layer, and the second P-type base region 131 is formed on a second horizontal portion of the second P-pillar 122 and the N-type drift layer.
In step S400, N-type doping ions and P-type doping ions are sequentially implanted into the first P-type base region 130 and the second P-type base region 131 to form a first P-type source region 132, a first N-type source region 133, a second P-type source region 134, and a second N-type source region 135, so that the first P-type base region 130 and the second P-type base region 131 have an L-shaped structure.
In this embodiment, as shown in fig. 10, the first P-type source region 132 and the first N-type source region 133 are located on the horizontal portion of the first P-type base region 130, and the second P-type source region 134 and the second N-type source region 135 are located on the horizontal portion of the second P-type base region 131.
In step S500, a silicon material is epitaxially grown on the N-type drift layer 120 and N-type dopant ions are implanted to form an N-type layer, and P-type dopant ions and N-type dopant ions are sequentially implanted in the central region of the N-type layer to form a third P-type base region 141 and a third N-type source region 142.
In the present embodiment, as shown in fig. 11, the third N-type source region 142 is formed on the third P-type base region 141 in a stacked manner.
In one embodiment, the width of the third N-type source region 142 is the same as the width of the third P-type base region 141. The thickness of the third N-type source region 142 is the same as that of the third P-type base region 141.
In one embodiment, the ion doping concentration of the N-type layer is the same as the ion doping concentration of the N-type drift layer 120. And, the total thickness of the third N-type source region 142 and the third P-type base region 141 is smaller than the thickness of the N-type layer.
In one embodiment, the thickness of the N-type layer may be less than the thickness of the first P-type base region 130.
In step S600, trench etching is performed on the N-type layers on both sides of the third P-type base region 141 and the third N-type source region 142, and an oxide layer is deposited, so as to form a first gate dielectric layer 151, a first gate polysilicon layer 152, a second gate dielectric layer 153, and a second gate polysilicon layer 154.
In this embodiment, as shown in fig. 12, the first gate dielectric layer 151 and the first gate polysilicon layer 152 are located on the vertical portion of the first P-type base region 130 and the partial region of the third horizontal portion of the N-type drift layer 120 and the partial region of the first N-type source region 133, and the first gate dielectric layer 151 wraps the first gate polysilicon layer 152; the second gate dielectric layer 153 and the second gate polysilicon layer 154 are located on the vertical portion of the second P-type base region 131 and the partial region of the N-type drift layer 120 and the partial region of the second N-type source region 135, and the second gate dielectric layer 153 wraps the second gate polysilicon layer 154.
In step S700, the third P-type base region 141 and the third N-type source region 142 are etched to form deep trenches, and an insulating dielectric layer is formed in the deep trenches.
In one embodiment, as shown in fig. 13, an insulating dielectric layer may be formed by etching a dielectric material such as silicon oxide or silicon nitride at a predetermined depth in the middle of the third P-type base region 141 and the third N-type source region 142.
In one embodiment, the predetermined depth is less than or equal to the total thickness of the third P-type base region 141 and the third N-type source region 142.
In step S800, a source metal material is deposited to form a source layer 160 of an inverted-mountain structure; the source layer 160 is in contact with the first P-type source region 132, the first N-type source region 133, the second P-type source region 134, and the second N-type source region 135, and the middle protruding portion of the inverted-mountain-shaped structure of the source layer 160 is embedded into the insulating medium layer with the concave-shaped structure.
In this embodiment, as shown in fig. 1, the middle protruding portion of the inverted-mountain-shaped structure of the source layer 160 is isolated from the third P-type base region 141 and the third N-type source region 142 by an insulating dielectric layer; and, the middle convex portion of the inverted-mountain-shaped structure of the source layer 160 contacts the insulating dielectric layer.
In step S900, a drain layer 162 is formed on the back surface of the N-type substrate 110.
In the embodiment of the present application, in the first aspect, the first gate dielectric layer 151 and the first gate polysilicon layer 152 are disposed on the vertical portion of the first P-type base region 130, and on the partial region of the third horizontal portion of the N-type drift layer 120 and the partial region of the first N-type source region 133, and the second gate dielectric layer 153 and the second gate polysilicon layer 154 are disposed on the vertical portion of the second P-type base region 131, and on the partial region of the third horizontal portion of the N-type drift layer 120 and the second N-type source region 135, so as to reduce the gate area, and reduce the channel length to a certain extent based on the reduction of the gate area, so as to reduce the gate charge, and further improve the reverse recovery and the switching speed of the deep source superjunction MOSFET device; in the second aspect, by providing the source layer 160 with an inverted-mountain-shaped structure, the source voltage is used to control the opening of the first P-type base region 130 and the second P-type base region 131, so as to increase the current conduction channel, and compensate the adverse effect of the forward conduction characteristic of the deep source super-junction MOSFET device caused by the reduction of the gate area; in the third aspect, the middle protruding portion of the inverted-triangle structure of the source layer 160 is embedded into the third P-type base region 141 and the third N-type source region 142, and the source layer 160 embedded into the third P-type base region 141 and the third N-type source region 142 is isolated from the third P-type base region 141 and the third N-type source region 142 by the insulating medium layer, so that the turn-on voltage of the deep source superjunction MOSFET device is lower than the turn-on voltage of the body diode by controlling the thickness of the insulating medium layer, hole injection of the first P-type source region 132 and the second P-type source region 134 is reduced, and reverse recovery of the device is improved.
In one embodiment, before the above step S400, the first N-type heavily doped region 171 and the second N-type heavily doped region 172 may be further formed at both sides of the third horizontal portion of the N-type drift layer 120. Then, epitaxially growing silicon materials on the first P column 121, the N type drift layer 120 and the second P column 122, and injecting N type doping ions to form a new N type drift layer 120, injecting P type doping ions on two sides of the new N type drift layer 120 to form a first P type base region 130 and a second P type base region 131, and making the new N type drift layer 120 have a convex structure, wherein the first P type base region 130 is located on a first horizontal portion of the first P column 121 and the N type drift layer, and the second P type base region 131 is formed on a second horizontal portion of the second P column 122 and the N type drift layer.
In this embodiment, the first N-type heavily doped region 171 is in contact with the vertical portion of the first P-type base region 130 and the first gate dielectric layer 151, and the second N-type heavily doped region 172 is in contact with the vertical portion of the second P-type base region 131 and the second gate dielectric layer 153.
In this embodiment, the first N-type heavily doped region 171123 and the second N-type heavily doped region 172124 have the same thickness and the same width.
In some embodiments, referring to fig. 3, a first schottky metal layer 181 may be further disposed between the source layer 160 and the first P-type source region 132.
In some embodiments, referring to fig. 3, a second schottky metal layer 182 is further disposed between the source layer 160 and the second P-type source region 134.
In this embodiment, by forming schottky contact between the first P-type source region 132 and the first schottky metal layer 181 and forming schottky contact between the second P-type source region 134 and the second schottky metal layer 182, the device can enter the protruding portion of the N-type drift layer 120 only from the first N-type source region 133 and the second N-type source region 135 during reverse recovery, and the arrangement of the first N-type heavily doped region 171 and the second N-type heavily doped region 172 is overlapped, so that minority carrier injection is reduced, the purpose of further reducing hole injection is achieved, and reverse recovery of the device is improved.
In one embodiment, the method of making further comprises: the thickness of the insulating medium layer is set to be a preset thickness.
In this embodiment, when the thickness of the insulating dielectric layer is a preset thickness, the turn-on voltage of the deep source super junction MOSFET device is smaller than the body diode turn-on voltage of the deep source super junction MOSFET device.
In the embodiment of the application, the thickness of the insulating medium layer is controlled to enable the on voltage of the deep source super junction MOSFET device to be lower than the on voltage of the body diode, so that the hole injection of the first P type source region 132 and the second P type source region 134 is reduced.
The embodiment of the application also provides a chip which comprises the deep source super junction MOSFET device of any one of the embodiments.
In this embodiment, the chip includes a chip substrate, and one or more deep source superjunction MOSFET devices are disposed on the substrate, where the deep source superjunction MOSFET devices may be prepared by the preparation method in any of the foregoing embodiments, or the deep source superjunction MOSFET devices in any of the foregoing embodiments may be disposed on the chip substrate.
In one embodiment, other related semiconductor devices can be integrated on the chip substrate, and the deep source superjunction MOSFET devices form an integrated circuit.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of each doped region and device is illustrated, and in practical application, the above-described function allocation may be performed by different doped regions and devices according to needs, i.e. the internal structure of the device is divided into different doped regions, so as to perform all or part of the above-described functions. The doped regions and the devices in the embodiments can be integrated in one unit, or each unit can exist alone physically, or two or more units can be integrated in one unit.
In addition, the specific names of the doped regions and the devices are only used for distinguishing the doped regions and the devices from each other, and are not used for limiting the protection scope of the application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In addition, each doped region in the embodiments of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
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